3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/delay.h>
37 #include <linux/atomic.h>
38 #include <linux/jump_label.h>
39 #include "kvm_cache_regs.h"
46 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48 #define mod_64(x, y) ((x) % (y))
56 #define APIC_BUS_CYCLE_NS 1
58 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
59 #define apic_debug(fmt, arg...)
61 #define APIC_LVT_NUM 6
62 /* 14 is the version for Xeon and Pentium 8.4.8*/
63 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
64 #define LAPIC_MMIO_LENGTH (1 << 12)
65 /* followed define is not in apicdef.h */
66 #define APIC_SHORT_MASK 0xc0000
67 #define APIC_DEST_NOSHORT 0x0
68 #define APIC_DEST_MASK 0x800
69 #define MAX_APIC_VECTOR 256
70 #define APIC_VECTORS_PER_REG 32
72 #define APIC_BROADCAST 0xFF
73 #define X2APIC_BROADCAST 0xFFFFFFFFul
75 #define VEC_POS(v) ((v) & (32 - 1))
76 #define REG_POS(v) (((v) >> 5) << 4)
78 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
80 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
83 static inline int apic_test_vector(int vec
, void *bitmap
)
85 return test_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
88 bool kvm_apic_pending_eoi(struct kvm_vcpu
*vcpu
, int vector
)
90 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
92 return apic_test_vector(vector
, apic
->regs
+ APIC_ISR
) ||
93 apic_test_vector(vector
, apic
->regs
+ APIC_IRR
);
96 static inline void apic_set_vector(int vec
, void *bitmap
)
98 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
101 static inline void apic_clear_vector(int vec
, void *bitmap
)
103 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
106 static inline int __apic_test_and_set_vector(int vec
, void *bitmap
)
108 return __test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
111 static inline int __apic_test_and_clear_vector(int vec
, void *bitmap
)
113 return __test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
116 struct static_key_deferred apic_hw_disabled __read_mostly
;
117 struct static_key_deferred apic_sw_disabled __read_mostly
;
119 static inline int apic_enabled(struct kvm_lapic
*apic
)
121 return kvm_apic_sw_enabled(apic
) && kvm_apic_hw_enabled(apic
);
125 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
128 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
129 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
131 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
133 return (kvm_apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
136 static void recalculate_apic_map(struct kvm
*kvm
)
138 struct kvm_apic_map
*new, *old
= NULL
;
139 struct kvm_vcpu
*vcpu
;
142 new = kzalloc(sizeof(struct kvm_apic_map
), GFP_KERNEL
);
144 mutex_lock(&kvm
->arch
.apic_map_lock
);
150 /* flat mode is default */
153 new->lid_mask
= 0xff;
154 new->broadcast
= APIC_BROADCAST
;
156 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
157 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
159 if (!kvm_apic_present(vcpu
))
162 if (apic_x2apic_mode(apic
)) {
165 new->cid_mask
= new->lid_mask
= 0xffff;
166 new->broadcast
= X2APIC_BROADCAST
;
167 } else if (kvm_apic_get_reg(apic
, APIC_LDR
)) {
168 if (kvm_apic_get_reg(apic
, APIC_DFR
) ==
176 new->lid_mask
= 0xff;
181 * All APICs have to be configured in the same mode by an OS.
182 * We take advatage of this while building logical id loockup
183 * table. After reset APICs are in software disabled mode, so if
184 * we find apic with different setting we assume this is the mode
185 * OS wants all apics to be in; build lookup table accordingly.
187 if (kvm_apic_sw_enabled(apic
))
191 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
192 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
196 aid
= kvm_apic_id(apic
);
197 ldr
= kvm_apic_get_reg(apic
, APIC_LDR
);
198 cid
= apic_cluster_id(new, ldr
);
199 lid
= apic_logical_id(new, ldr
);
201 if (aid
< ARRAY_SIZE(new->phys_map
))
202 new->phys_map
[aid
] = apic
;
203 if (lid
&& cid
< ARRAY_SIZE(new->logical_map
))
204 new->logical_map
[cid
][ffs(lid
) - 1] = apic
;
207 old
= rcu_dereference_protected(kvm
->arch
.apic_map
,
208 lockdep_is_held(&kvm
->arch
.apic_map_lock
));
209 rcu_assign_pointer(kvm
->arch
.apic_map
, new);
210 mutex_unlock(&kvm
->arch
.apic_map_lock
);
215 kvm_vcpu_request_scan_ioapic(kvm
);
218 static inline void apic_set_spiv(struct kvm_lapic
*apic
, u32 val
)
220 bool enabled
= val
& APIC_SPIV_APIC_ENABLED
;
222 apic_set_reg(apic
, APIC_SPIV
, val
);
224 if (enabled
!= apic
->sw_enabled
) {
225 apic
->sw_enabled
= enabled
;
227 static_key_slow_dec_deferred(&apic_sw_disabled
);
228 recalculate_apic_map(apic
->vcpu
->kvm
);
230 static_key_slow_inc(&apic_sw_disabled
.key
);
234 static inline void kvm_apic_set_id(struct kvm_lapic
*apic
, u8 id
)
236 apic_set_reg(apic
, APIC_ID
, id
<< 24);
237 recalculate_apic_map(apic
->vcpu
->kvm
);
240 static inline void kvm_apic_set_ldr(struct kvm_lapic
*apic
, u32 id
)
242 apic_set_reg(apic
, APIC_LDR
, id
);
243 recalculate_apic_map(apic
->vcpu
->kvm
);
246 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
248 return !(kvm_apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
251 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
253 return kvm_apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
256 static inline int apic_lvtt_oneshot(struct kvm_lapic
*apic
)
258 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_ONESHOT
;
261 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
263 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_PERIODIC
;
266 static inline int apic_lvtt_tscdeadline(struct kvm_lapic
*apic
)
268 return apic
->lapic_timer
.timer_mode
== APIC_LVT_TIMER_TSCDEADLINE
;
271 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
273 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
276 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
278 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
279 struct kvm_cpuid_entry2
*feat
;
280 u32 v
= APIC_VERSION
;
282 if (!kvm_vcpu_has_lapic(vcpu
))
285 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
286 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
287 v
|= APIC_LVR_DIRECTED_EOI
;
288 apic_set_reg(apic
, APIC_LVR
, v
);
291 static const unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
292 LVT_MASK
, /* part LVTT mask, timer mode mask added at runtime */
293 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
294 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
295 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
296 LVT_MASK
/* LVTERR */
299 static int find_highest_vector(void *bitmap
)
304 for (vec
= MAX_APIC_VECTOR
- APIC_VECTORS_PER_REG
;
305 vec
>= 0; vec
-= APIC_VECTORS_PER_REG
) {
306 reg
= bitmap
+ REG_POS(vec
);
308 return fls(*reg
) - 1 + vec
;
314 static u8
count_vectors(void *bitmap
)
320 for (vec
= 0; vec
< MAX_APIC_VECTOR
; vec
+= APIC_VECTORS_PER_REG
) {
321 reg
= bitmap
+ REG_POS(vec
);
322 count
+= hweight32(*reg
);
328 void kvm_apic_update_irr(struct kvm_vcpu
*vcpu
, u32
*pir
)
331 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
333 for (i
= 0; i
<= 7; i
++) {
334 pir_val
= xchg(&pir
[i
], 0);
336 *((u32
*)(apic
->regs
+ APIC_IRR
+ i
* 0x10)) |= pir_val
;
339 EXPORT_SYMBOL_GPL(kvm_apic_update_irr
);
341 static inline void apic_set_irr(int vec
, struct kvm_lapic
*apic
)
343 apic_set_vector(vec
, apic
->regs
+ APIC_IRR
);
345 * irr_pending must be true if any interrupt is pending; set it after
346 * APIC_IRR to avoid race with apic_clear_irr
348 apic
->irr_pending
= true;
351 static inline int apic_search_irr(struct kvm_lapic
*apic
)
353 return find_highest_vector(apic
->regs
+ APIC_IRR
);
356 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
361 * Note that irr_pending is just a hint. It will be always
362 * true with virtual interrupt delivery enabled.
364 if (!apic
->irr_pending
)
367 kvm_x86_ops
->sync_pir_to_irr(apic
->vcpu
);
368 result
= apic_search_irr(apic
);
369 ASSERT(result
== -1 || result
>= 16);
374 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
376 struct kvm_vcpu
*vcpu
;
380 if (unlikely(kvm_apic_vid_enabled(vcpu
->kvm
))) {
381 /* try to update RVI */
382 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
383 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
385 apic
->irr_pending
= false;
386 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
387 if (apic_search_irr(apic
) != -1)
388 apic
->irr_pending
= true;
392 static inline void apic_set_isr(int vec
, struct kvm_lapic
*apic
)
394 struct kvm_vcpu
*vcpu
;
396 if (__apic_test_and_set_vector(vec
, apic
->regs
+ APIC_ISR
))
402 * With APIC virtualization enabled, all caching is disabled
403 * because the processor can modify ISR under the hood. Instead
406 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
407 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
, vec
);
410 BUG_ON(apic
->isr_count
> MAX_APIC_VECTOR
);
412 * ISR (in service register) bit is set when injecting an interrupt.
413 * The highest vector is injected. Thus the latest bit set matches
414 * the highest bit in ISR.
416 apic
->highest_isr_cache
= vec
;
420 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
425 * Note that isr_count is always 1, and highest_isr_cache
426 * is always -1, with APIC virtualization enabled.
428 if (!apic
->isr_count
)
430 if (likely(apic
->highest_isr_cache
!= -1))
431 return apic
->highest_isr_cache
;
433 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
434 ASSERT(result
== -1 || result
>= 16);
439 static inline void apic_clear_isr(int vec
, struct kvm_lapic
*apic
)
441 struct kvm_vcpu
*vcpu
;
442 if (!__apic_test_and_clear_vector(vec
, apic
->regs
+ APIC_ISR
))
448 * We do get here for APIC virtualization enabled if the guest
449 * uses the Hyper-V APIC enlightenment. In this case we may need
450 * to trigger a new interrupt delivery by writing the SVI field;
451 * on the other hand isr_count and highest_isr_cache are unused
452 * and must be left alone.
454 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
455 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
456 apic_find_highest_isr(apic
));
459 BUG_ON(apic
->isr_count
< 0);
460 apic
->highest_isr_cache
= -1;
464 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
468 /* This may race with setting of irr in __apic_accept_irq() and
469 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
470 * will cause vmexit immediately and the value will be recalculated
471 * on the next vmentry.
473 if (!kvm_vcpu_has_lapic(vcpu
))
475 highest_irr
= apic_find_highest_irr(vcpu
->arch
.apic
);
480 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
481 int vector
, int level
, int trig_mode
,
482 unsigned long *dest_map
);
484 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
,
485 unsigned long *dest_map
)
487 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
489 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
490 irq
->level
, irq
->trig_mode
, dest_map
);
493 static int pv_eoi_put_user(struct kvm_vcpu
*vcpu
, u8 val
)
496 return kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, &val
,
500 static int pv_eoi_get_user(struct kvm_vcpu
*vcpu
, u8
*val
)
503 return kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
, val
,
507 static inline bool pv_eoi_enabled(struct kvm_vcpu
*vcpu
)
509 return vcpu
->arch
.pv_eoi
.msr_val
& KVM_MSR_ENABLED
;
512 static bool pv_eoi_get_pending(struct kvm_vcpu
*vcpu
)
515 if (pv_eoi_get_user(vcpu
, &val
) < 0)
516 apic_debug("Can't read EOI MSR value: 0x%llx\n",
517 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
521 static void pv_eoi_set_pending(struct kvm_vcpu
*vcpu
)
523 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_ENABLED
) < 0) {
524 apic_debug("Can't set EOI MSR value: 0x%llx\n",
525 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
528 __set_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
531 static void pv_eoi_clr_pending(struct kvm_vcpu
*vcpu
)
533 if (pv_eoi_put_user(vcpu
, KVM_PV_EOI_DISABLED
) < 0) {
534 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
535 (unsigned long long)vcpu
->arch
.pv_eoi
.msr_val
);
538 __clear_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
);
541 void kvm_apic_update_tmr(struct kvm_vcpu
*vcpu
, u32
*tmr
)
543 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
546 for (i
= 0; i
< 8; i
++)
547 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, tmr
[i
]);
550 static void apic_update_ppr(struct kvm_lapic
*apic
)
552 u32 tpr
, isrv
, ppr
, old_ppr
;
555 old_ppr
= kvm_apic_get_reg(apic
, APIC_PROCPRI
);
556 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
);
557 isr
= apic_find_highest_isr(apic
);
558 isrv
= (isr
!= -1) ? isr
: 0;
560 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
565 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
566 apic
, ppr
, isr
, isrv
);
568 if (old_ppr
!= ppr
) {
569 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
571 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
575 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
577 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
578 apic_update_ppr(apic
);
581 static bool kvm_apic_broadcast(struct kvm_lapic
*apic
, u32 dest
)
583 return dest
== (apic_x2apic_mode(apic
) ?
584 X2APIC_BROADCAST
: APIC_BROADCAST
);
587 static bool kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u32 dest
)
589 return kvm_apic_id(apic
) == dest
|| kvm_apic_broadcast(apic
, dest
);
592 static bool kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u32 mda
)
596 if (kvm_apic_broadcast(apic
, mda
))
599 logical_id
= kvm_apic_get_reg(apic
, APIC_LDR
);
601 if (apic_x2apic_mode(apic
))
602 return ((logical_id
>> 16) == (mda
>> 16))
603 && (logical_id
& mda
& 0xffff) != 0;
605 logical_id
= GET_APIC_LOGICAL_ID(logical_id
);
607 switch (kvm_apic_get_reg(apic
, APIC_DFR
)) {
609 return (logical_id
& mda
) != 0;
610 case APIC_DFR_CLUSTER
:
611 return ((logical_id
>> 4) == (mda
>> 4))
612 && (logical_id
& mda
& 0xf) != 0;
614 apic_debug("Bad DFR vcpu %d: %08x\n",
615 apic
->vcpu
->vcpu_id
, kvm_apic_get_reg(apic
, APIC_DFR
));
620 bool kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
621 int short_hand
, unsigned int dest
, int dest_mode
)
623 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
625 apic_debug("target %p, source %p, dest 0x%x, "
626 "dest_mode 0x%x, short_hand 0x%x\n",
627 target
, source
, dest
, dest_mode
, short_hand
);
630 switch (short_hand
) {
631 case APIC_DEST_NOSHORT
:
632 if (dest_mode
== APIC_DEST_PHYSICAL
)
633 return kvm_apic_match_physical_addr(target
, dest
);
635 return kvm_apic_match_logical_addr(target
, dest
);
637 return target
== source
;
638 case APIC_DEST_ALLINC
:
640 case APIC_DEST_ALLBUT
:
641 return target
!= source
;
643 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
649 bool kvm_irq_delivery_to_apic_fast(struct kvm
*kvm
, struct kvm_lapic
*src
,
650 struct kvm_lapic_irq
*irq
, int *r
, unsigned long *dest_map
)
652 struct kvm_apic_map
*map
;
653 unsigned long bitmap
= 1;
654 struct kvm_lapic
**dst
;
660 if (irq
->shorthand
== APIC_DEST_SELF
) {
661 *r
= kvm_apic_set_irq(src
->vcpu
, irq
, dest_map
);
669 map
= rcu_dereference(kvm
->arch
.apic_map
);
674 if (irq
->dest_id
== map
->broadcast
)
679 if (irq
->dest_mode
== APIC_DEST_PHYSICAL
) {
680 if (irq
->dest_id
>= ARRAY_SIZE(map
->phys_map
))
683 dst
= &map
->phys_map
[irq
->dest_id
];
685 u32 mda
= irq
->dest_id
<< (32 - map
->ldr_bits
);
686 u16 cid
= apic_cluster_id(map
, mda
);
688 if (cid
>= ARRAY_SIZE(map
->logical_map
))
691 dst
= map
->logical_map
[cid
];
693 bitmap
= apic_logical_id(map
, mda
);
695 if (irq
->delivery_mode
== APIC_DM_LOWEST
) {
697 for_each_set_bit(i
, &bitmap
, 16) {
702 else if (kvm_apic_compare_prio(dst
[i
]->vcpu
, dst
[l
]->vcpu
) < 0)
706 bitmap
= (l
>= 0) ? 1 << l
: 0;
710 for_each_set_bit(i
, &bitmap
, 16) {
715 *r
+= kvm_apic_set_irq(dst
[i
]->vcpu
, irq
, dest_map
);
723 * Add a pending IRQ into lapic.
724 * Return 1 if successfully added and 0 if discarded.
726 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
727 int vector
, int level
, int trig_mode
,
728 unsigned long *dest_map
)
731 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
733 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
735 switch (delivery_mode
) {
737 vcpu
->arch
.apic_arb_prio
++;
739 /* FIXME add logic for vcpu on reset */
740 if (unlikely(!apic_enabled(apic
)))
746 __set_bit(vcpu
->vcpu_id
, dest_map
);
748 if (kvm_x86_ops
->deliver_posted_interrupt
)
749 kvm_x86_ops
->deliver_posted_interrupt(vcpu
, vector
);
751 apic_set_irr(vector
, apic
);
753 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
760 vcpu
->arch
.pv
.pv_unhalted
= 1;
761 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
766 apic_debug("Ignoring guest SMI\n");
771 kvm_inject_nmi(vcpu
);
776 if (!trig_mode
|| level
) {
778 /* assumes that there are only KVM_APIC_INIT/SIPI */
779 apic
->pending_events
= (1UL << KVM_APIC_INIT
);
780 /* make sure pending_events is visible before sending
783 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
786 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
791 case APIC_DM_STARTUP
:
792 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
793 vcpu
->vcpu_id
, vector
);
795 apic
->sipi_vector
= vector
;
796 /* make sure sipi_vector is visible for the receiver */
798 set_bit(KVM_APIC_SIPI
, &apic
->pending_events
);
799 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
805 * Should only be called by kvm_apic_local_deliver() with LVT0,
806 * before NMI watchdog was enabled. Already handled by
807 * kvm_apic_accept_pic_intr().
812 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
819 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
821 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
824 static void kvm_ioapic_send_eoi(struct kvm_lapic
*apic
, int vector
)
826 if (!(kvm_apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
) &&
827 kvm_ioapic_handles_vector(apic
->vcpu
->kvm
, vector
)) {
829 if (apic_test_vector(vector
, apic
->regs
+ APIC_TMR
))
830 trigger_mode
= IOAPIC_LEVEL_TRIG
;
832 trigger_mode
= IOAPIC_EDGE_TRIG
;
833 kvm_ioapic_update_eoi(apic
->vcpu
, vector
, trigger_mode
);
837 static int apic_set_eoi(struct kvm_lapic
*apic
)
839 int vector
= apic_find_highest_isr(apic
);
841 trace_kvm_eoi(apic
, vector
);
844 * Not every write EOI will has corresponding ISR,
845 * one example is when Kernel check timer on setup_IO_APIC
850 apic_clear_isr(vector
, apic
);
851 apic_update_ppr(apic
);
853 kvm_ioapic_send_eoi(apic
, vector
);
854 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
859 * this interface assumes a trap-like exit, which has already finished
860 * desired side effect including vISR and vPPR update.
862 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu
*vcpu
, int vector
)
864 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
866 trace_kvm_eoi(apic
, vector
);
868 kvm_ioapic_send_eoi(apic
, vector
);
869 kvm_make_request(KVM_REQ_EVENT
, apic
->vcpu
);
871 EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated
);
873 static void apic_send_ipi(struct kvm_lapic
*apic
)
875 u32 icr_low
= kvm_apic_get_reg(apic
, APIC_ICR
);
876 u32 icr_high
= kvm_apic_get_reg(apic
, APIC_ICR2
);
877 struct kvm_lapic_irq irq
;
879 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
880 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
881 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
882 irq
.level
= icr_low
& APIC_INT_ASSERT
;
883 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
884 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
885 if (apic_x2apic_mode(apic
))
886 irq
.dest_id
= icr_high
;
888 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
890 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
892 apic_debug("icr_high 0x%x, icr_low 0x%x, "
893 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
894 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
895 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
896 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
899 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
, NULL
);
902 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
908 ASSERT(apic
!= NULL
);
910 /* if initial count is 0, current count should also be 0 */
911 if (kvm_apic_get_reg(apic
, APIC_TMICT
) == 0 ||
912 apic
->lapic_timer
.period
== 0)
915 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
916 if (ktime_to_ns(remaining
) < 0)
917 remaining
= ktime_set(0, 0);
919 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
920 tmcct
= div64_u64(ns
,
921 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
926 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
928 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
929 struct kvm_run
*run
= vcpu
->run
;
931 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
932 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
933 run
->tpr_access
.is_write
= write
;
936 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
938 if (apic
->vcpu
->arch
.tpr_access_reporting
)
939 __report_tpr_access(apic
, write
);
942 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
946 if (offset
>= LAPIC_MMIO_LENGTH
)
951 if (apic_x2apic_mode(apic
))
952 val
= kvm_apic_id(apic
);
954 val
= kvm_apic_id(apic
) << 24;
957 apic_debug("Access APIC ARBPRI register which is for P6\n");
960 case APIC_TMCCT
: /* Timer CCR */
961 if (apic_lvtt_tscdeadline(apic
))
964 val
= apic_get_tmcct(apic
);
967 apic_update_ppr(apic
);
968 val
= kvm_apic_get_reg(apic
, offset
);
971 report_tpr_access(apic
, false);
974 val
= kvm_apic_get_reg(apic
, offset
);
981 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
983 return container_of(dev
, struct kvm_lapic
, dev
);
986 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
989 unsigned char alignment
= offset
& 0xf;
991 /* this bitmask has a bit cleared for each reserved register */
992 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
994 if ((alignment
+ len
) > 4) {
995 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1000 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
1001 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1006 result
= __apic_read(apic
, offset
& ~0xf);
1008 trace_kvm_apic_read(offset
, result
);
1014 memcpy(data
, (char *)&result
+ alignment
, len
);
1017 printk(KERN_ERR
"Local APIC read with len = %x, "
1018 "should be 1,2, or 4 instead\n", len
);
1024 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
1026 return kvm_apic_hw_enabled(apic
) &&
1027 addr
>= apic
->base_address
&&
1028 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
1031 static int apic_mmio_read(struct kvm_io_device
*this,
1032 gpa_t address
, int len
, void *data
)
1034 struct kvm_lapic
*apic
= to_lapic(this);
1035 u32 offset
= address
- apic
->base_address
;
1037 if (!apic_mmio_in_range(apic
, address
))
1040 apic_reg_read(apic
, offset
, len
, data
);
1045 static void update_divide_count(struct kvm_lapic
*apic
)
1047 u32 tmp1
, tmp2
, tdcr
;
1049 tdcr
= kvm_apic_get_reg(apic
, APIC_TDCR
);
1051 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
1052 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
1054 apic_debug("timer divide count is 0x%x\n",
1055 apic
->divide_count
);
1058 static void apic_timer_expired(struct kvm_lapic
*apic
)
1060 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1061 wait_queue_head_t
*q
= &vcpu
->wq
;
1062 struct kvm_timer
*ktimer
= &apic
->lapic_timer
;
1064 if (atomic_read(&apic
->lapic_timer
.pending
))
1067 atomic_inc(&apic
->lapic_timer
.pending
);
1068 kvm_set_pending_timer(vcpu
);
1070 if (waitqueue_active(q
))
1071 wake_up_interruptible(q
);
1073 if (apic_lvtt_tscdeadline(apic
))
1074 ktimer
->expired_tscdeadline
= ktimer
->tscdeadline
;
1078 * On APICv, this test will cause a busy wait
1079 * during a higher-priority task.
1082 static bool lapic_timer_int_injected(struct kvm_vcpu
*vcpu
)
1084 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1085 u32 reg
= kvm_apic_get_reg(apic
, APIC_LVTT
);
1087 if (kvm_apic_hw_enabled(apic
)) {
1088 int vec
= reg
& APIC_VECTOR_MASK
;
1090 if (kvm_x86_ops
->test_posted_interrupt
)
1091 return kvm_x86_ops
->test_posted_interrupt(vcpu
, vec
);
1093 if (apic_test_vector(vec
, apic
->regs
+ APIC_ISR
))
1100 void wait_lapic_expire(struct kvm_vcpu
*vcpu
)
1102 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1103 u64 guest_tsc
, tsc_deadline
;
1105 if (!kvm_vcpu_has_lapic(vcpu
))
1108 if (apic
->lapic_timer
.expired_tscdeadline
== 0)
1111 if (!lapic_timer_int_injected(vcpu
))
1114 tsc_deadline
= apic
->lapic_timer
.expired_tscdeadline
;
1115 apic
->lapic_timer
.expired_tscdeadline
= 0;
1116 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1117 trace_kvm_wait_lapic_expire(vcpu
->vcpu_id
, guest_tsc
- tsc_deadline
);
1119 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1120 if (guest_tsc
< tsc_deadline
)
1121 __delay(tsc_deadline
- guest_tsc
);
1124 static void start_apic_timer(struct kvm_lapic
*apic
)
1128 atomic_set(&apic
->lapic_timer
.pending
, 0);
1130 if (apic_lvtt_period(apic
) || apic_lvtt_oneshot(apic
)) {
1131 /* lapic timer in oneshot or periodic mode */
1132 now
= apic
->lapic_timer
.timer
.base
->get_time();
1133 apic
->lapic_timer
.period
= (u64
)kvm_apic_get_reg(apic
, APIC_TMICT
)
1134 * APIC_BUS_CYCLE_NS
* apic
->divide_count
;
1136 if (!apic
->lapic_timer
.period
)
1139 * Do not allow the guest to program periodic timers with small
1140 * interval, since the hrtimers are not throttled by the host
1143 if (apic_lvtt_period(apic
)) {
1144 s64 min_period
= min_timer_period_us
* 1000LL;
1146 if (apic
->lapic_timer
.period
< min_period
) {
1147 pr_info_ratelimited(
1148 "kvm: vcpu %i: requested %lld ns "
1149 "lapic timer period limited to %lld ns\n",
1150 apic
->vcpu
->vcpu_id
,
1151 apic
->lapic_timer
.period
, min_period
);
1152 apic
->lapic_timer
.period
= min_period
;
1156 hrtimer_start(&apic
->lapic_timer
.timer
,
1157 ktime_add_ns(now
, apic
->lapic_timer
.period
),
1160 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
1162 "timer initial count 0x%x, period %lldns, "
1163 "expire @ 0x%016" PRIx64
".\n", __func__
,
1164 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
1165 kvm_apic_get_reg(apic
, APIC_TMICT
),
1166 apic
->lapic_timer
.period
,
1167 ktime_to_ns(ktime_add_ns(now
,
1168 apic
->lapic_timer
.period
)));
1169 } else if (apic_lvtt_tscdeadline(apic
)) {
1170 /* lapic timer in tsc deadline mode */
1171 u64 guest_tsc
, tscdeadline
= apic
->lapic_timer
.tscdeadline
;
1174 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
1175 unsigned long this_tsc_khz
= vcpu
->arch
.virtual_tsc_khz
;
1176 unsigned long flags
;
1178 if (unlikely(!tscdeadline
|| !this_tsc_khz
))
1181 local_irq_save(flags
);
1183 now
= apic
->lapic_timer
.timer
.base
->get_time();
1184 guest_tsc
= kvm_x86_ops
->read_l1_tsc(vcpu
, native_read_tsc());
1185 if (likely(tscdeadline
> guest_tsc
)) {
1186 ns
= (tscdeadline
- guest_tsc
) * 1000000ULL;
1187 do_div(ns
, this_tsc_khz
);
1188 expire
= ktime_add_ns(now
, ns
);
1189 expire
= ktime_sub_ns(expire
, lapic_timer_advance_ns
);
1190 hrtimer_start(&apic
->lapic_timer
.timer
,
1191 expire
, HRTIMER_MODE_ABS
);
1193 apic_timer_expired(apic
);
1195 local_irq_restore(flags
);
1199 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
1201 int nmi_wd_enabled
= apic_lvt_nmi_mode(kvm_apic_get_reg(apic
, APIC_LVT0
));
1203 if (apic_lvt_nmi_mode(lvt0_val
)) {
1204 if (!nmi_wd_enabled
) {
1205 apic_debug("Receive NMI setting on APIC_LVT0 "
1206 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
1207 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
1209 } else if (nmi_wd_enabled
)
1210 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
1213 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
1217 trace_kvm_apic_write(reg
, val
);
1220 case APIC_ID
: /* Local APIC ID */
1221 if (!apic_x2apic_mode(apic
))
1222 kvm_apic_set_id(apic
, val
>> 24);
1228 report_tpr_access(apic
, true);
1229 apic_set_tpr(apic
, val
& 0xff);
1237 if (!apic_x2apic_mode(apic
))
1238 kvm_apic_set_ldr(apic
, val
& APIC_LDR_MASK
);
1244 if (!apic_x2apic_mode(apic
)) {
1245 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
1246 recalculate_apic_map(apic
->vcpu
->kvm
);
1253 if (kvm_apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
1254 mask
|= APIC_SPIV_DIRECTED_EOI
;
1255 apic_set_spiv(apic
, val
& mask
);
1256 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
1260 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
1261 lvt_val
= kvm_apic_get_reg(apic
,
1262 APIC_LVTT
+ 0x10 * i
);
1263 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
1264 lvt_val
| APIC_LVT_MASKED
);
1266 atomic_set(&apic
->lapic_timer
.pending
, 0);
1272 /* No delay here, so we always clear the pending bit */
1273 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
1274 apic_send_ipi(apic
);
1278 if (!apic_x2apic_mode(apic
))
1280 apic_set_reg(apic
, APIC_ICR2
, val
);
1284 apic_manage_nmi_watchdog(apic
, val
);
1289 /* TODO: Check vector */
1290 if (!kvm_apic_sw_enabled(apic
))
1291 val
|= APIC_LVT_MASKED
;
1293 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
1294 apic_set_reg(apic
, reg
, val
);
1299 u32 timer_mode
= val
& apic
->lapic_timer
.timer_mode_mask
;
1301 if (apic
->lapic_timer
.timer_mode
!= timer_mode
) {
1302 apic
->lapic_timer
.timer_mode
= timer_mode
;
1303 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1306 if (!kvm_apic_sw_enabled(apic
))
1307 val
|= APIC_LVT_MASKED
;
1308 val
&= (apic_lvt_mask
[0] | apic
->lapic_timer
.timer_mode_mask
);
1309 apic_set_reg(apic
, APIC_LVTT
, val
);
1314 if (apic_lvtt_tscdeadline(apic
))
1317 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1318 apic_set_reg(apic
, APIC_TMICT
, val
);
1319 start_apic_timer(apic
);
1324 apic_debug("KVM_WRITE:TDCR %x\n", val
);
1325 apic_set_reg(apic
, APIC_TDCR
, val
);
1326 update_divide_count(apic
);
1330 if (apic_x2apic_mode(apic
) && val
!= 0) {
1331 apic_debug("KVM_WRITE:ESR not zero %x\n", val
);
1337 if (apic_x2apic_mode(apic
)) {
1338 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
1347 apic_debug("Local APIC Write to read-only register %x\n", reg
);
1351 static int apic_mmio_write(struct kvm_io_device
*this,
1352 gpa_t address
, int len
, const void *data
)
1354 struct kvm_lapic
*apic
= to_lapic(this);
1355 unsigned int offset
= address
- apic
->base_address
;
1358 if (!apic_mmio_in_range(apic
, address
))
1362 * APIC register must be aligned on 128-bits boundary.
1363 * 32/64/128 bits registers must be accessed thru 32 bits.
1366 if (len
!= 4 || (offset
& 0xf)) {
1367 /* Don't shout loud, $infamous_os would cause only noise. */
1368 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
1374 /* too common printing */
1375 if (offset
!= APIC_EOI
)
1376 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1377 "0x%x\n", __func__
, offset
, len
, val
);
1379 apic_reg_write(apic
, offset
& 0xff0, val
);
1384 void kvm_lapic_set_eoi(struct kvm_vcpu
*vcpu
)
1386 if (kvm_vcpu_has_lapic(vcpu
))
1387 apic_reg_write(vcpu
->arch
.apic
, APIC_EOI
, 0);
1389 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi
);
1391 /* emulate APIC access in a trap manner */
1392 void kvm_apic_write_nodecode(struct kvm_vcpu
*vcpu
, u32 offset
)
1396 /* hw has done the conditional check and inst decode */
1399 apic_reg_read(vcpu
->arch
.apic
, offset
, 4, &val
);
1401 /* TODO: optimize to just emulate side effect w/o one more write */
1402 apic_reg_write(vcpu
->arch
.apic
, offset
, val
);
1404 EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode
);
1406 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
1408 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1410 if (!vcpu
->arch
.apic
)
1413 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1415 if (!(vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
))
1416 static_key_slow_dec_deferred(&apic_hw_disabled
);
1418 if (!apic
->sw_enabled
)
1419 static_key_slow_dec_deferred(&apic_sw_disabled
);
1422 free_page((unsigned long)apic
->regs
);
1428 *----------------------------------------------------------------------
1430 *----------------------------------------------------------------------
1433 u64
kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
)
1435 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1437 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1438 apic_lvtt_period(apic
))
1441 return apic
->lapic_timer
.tscdeadline
;
1444 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
*vcpu
, u64 data
)
1446 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1448 if (!kvm_vcpu_has_lapic(vcpu
) || apic_lvtt_oneshot(apic
) ||
1449 apic_lvtt_period(apic
))
1452 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1453 apic
->lapic_timer
.tscdeadline
= data
;
1454 start_apic_timer(apic
);
1457 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
1459 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1461 if (!kvm_vcpu_has_lapic(vcpu
))
1464 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
1465 | (kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 4));
1468 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
1472 if (!kvm_vcpu_has_lapic(vcpu
))
1475 tpr
= (u64
) kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_TASKPRI
);
1477 return (tpr
& 0xf0) >> 4;
1480 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
1482 u64 old_value
= vcpu
->arch
.apic_base
;
1483 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1486 value
|= MSR_IA32_APICBASE_BSP
;
1487 vcpu
->arch
.apic_base
= value
;
1491 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
1492 value
&= ~MSR_IA32_APICBASE_BSP
;
1493 vcpu
->arch
.apic_base
= value
;
1495 /* update jump label if enable bit changes */
1496 if ((old_value
^ value
) & MSR_IA32_APICBASE_ENABLE
) {
1497 if (value
& MSR_IA32_APICBASE_ENABLE
)
1498 static_key_slow_dec_deferred(&apic_hw_disabled
);
1500 static_key_slow_inc(&apic_hw_disabled
.key
);
1501 recalculate_apic_map(vcpu
->kvm
);
1504 if ((old_value
^ value
) & X2APIC_ENABLE
) {
1505 if (value
& X2APIC_ENABLE
) {
1506 u32 id
= kvm_apic_id(apic
);
1507 u32 ldr
= ((id
>> 4) << 16) | (1 << (id
& 0xf));
1508 kvm_apic_set_ldr(apic
, ldr
);
1509 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, true);
1511 kvm_x86_ops
->set_virtual_x2apic_mode(vcpu
, false);
1514 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
1515 MSR_IA32_APICBASE_BASE
;
1517 if ((value
& MSR_IA32_APICBASE_ENABLE
) &&
1518 apic
->base_address
!= APIC_DEFAULT_PHYS_BASE
)
1519 pr_warn_once("APIC base relocation is unsupported by KVM");
1521 /* with FSB delivery interrupt, we can restart APIC functionality */
1522 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
1523 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
1527 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
1529 struct kvm_lapic
*apic
;
1532 apic_debug("%s\n", __func__
);
1535 apic
= vcpu
->arch
.apic
;
1536 ASSERT(apic
!= NULL
);
1538 /* Stop the timer in case it's a reset to an active apic */
1539 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1541 kvm_apic_set_id(apic
, vcpu
->vcpu_id
);
1542 kvm_apic_set_version(apic
->vcpu
);
1544 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
1545 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
1546 apic
->lapic_timer
.timer_mode
= 0;
1547 apic_set_reg(apic
, APIC_LVT0
,
1548 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
1550 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
1551 apic_set_spiv(apic
, 0xff);
1552 apic_set_reg(apic
, APIC_TASKPRI
, 0);
1553 kvm_apic_set_ldr(apic
, 0);
1554 apic_set_reg(apic
, APIC_ESR
, 0);
1555 apic_set_reg(apic
, APIC_ICR
, 0);
1556 apic_set_reg(apic
, APIC_ICR2
, 0);
1557 apic_set_reg(apic
, APIC_TDCR
, 0);
1558 apic_set_reg(apic
, APIC_TMICT
, 0);
1559 for (i
= 0; i
< 8; i
++) {
1560 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
1561 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
1562 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
1564 apic
->irr_pending
= kvm_apic_vid_enabled(vcpu
->kvm
);
1565 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
);
1566 apic
->highest_isr_cache
= -1;
1567 update_divide_count(apic
);
1568 atomic_set(&apic
->lapic_timer
.pending
, 0);
1569 if (kvm_vcpu_is_bsp(vcpu
))
1570 kvm_lapic_set_base(vcpu
,
1571 vcpu
->arch
.apic_base
| MSR_IA32_APICBASE_BSP
);
1572 vcpu
->arch
.pv_eoi
.msr_val
= 0;
1573 apic_update_ppr(apic
);
1575 vcpu
->arch
.apic_arb_prio
= 0;
1576 vcpu
->arch
.apic_attention
= 0;
1578 apic_debug("%s: vcpu=%p, id=%d, base_msr="
1579 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
1580 vcpu
, kvm_apic_id(apic
),
1581 vcpu
->arch
.apic_base
, apic
->base_address
);
1585 *----------------------------------------------------------------------
1587 *----------------------------------------------------------------------
1590 static bool lapic_is_periodic(struct kvm_lapic
*apic
)
1592 return apic_lvtt_period(apic
);
1595 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1597 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1599 if (kvm_vcpu_has_lapic(vcpu
) && apic_enabled(apic
) &&
1600 apic_lvt_enabled(apic
, APIC_LVTT
))
1601 return atomic_read(&apic
->lapic_timer
.pending
);
1606 int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1608 u32 reg
= kvm_apic_get_reg(apic
, lvt_type
);
1609 int vector
, mode
, trig_mode
;
1611 if (kvm_apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1612 vector
= reg
& APIC_VECTOR_MASK
;
1613 mode
= reg
& APIC_MODE_MASK
;
1614 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1615 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
,
1621 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1623 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1626 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1629 static const struct kvm_io_device_ops apic_mmio_ops
= {
1630 .read
= apic_mmio_read
,
1631 .write
= apic_mmio_write
,
1634 static enum hrtimer_restart
apic_timer_fn(struct hrtimer
*data
)
1636 struct kvm_timer
*ktimer
= container_of(data
, struct kvm_timer
, timer
);
1637 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
, lapic_timer
);
1639 apic_timer_expired(apic
);
1641 if (lapic_is_periodic(apic
)) {
1642 hrtimer_add_expires_ns(&ktimer
->timer
, ktimer
->period
);
1643 return HRTIMER_RESTART
;
1645 return HRTIMER_NORESTART
;
1648 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1650 struct kvm_lapic
*apic
;
1652 ASSERT(vcpu
!= NULL
);
1653 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1655 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1659 vcpu
->arch
.apic
= apic
;
1661 apic
->regs
= (void *)get_zeroed_page(GFP_KERNEL
);
1663 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1665 goto nomem_free_apic
;
1669 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1671 apic
->lapic_timer
.timer
.function
= apic_timer_fn
;
1674 * APIC is created enabled. This will prevent kvm_lapic_set_base from
1675 * thinking that APIC satet has changed.
1677 vcpu
->arch
.apic_base
= MSR_IA32_APICBASE_ENABLE
;
1678 kvm_lapic_set_base(vcpu
,
1679 APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
);
1681 static_key_slow_inc(&apic_sw_disabled
.key
); /* sw disabled at reset */
1682 kvm_lapic_reset(vcpu
);
1683 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1692 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1694 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1697 if (!kvm_vcpu_has_lapic(vcpu
) || !apic_enabled(apic
))
1700 apic_update_ppr(apic
);
1701 highest_irr
= apic_find_highest_irr(apic
);
1702 if ((highest_irr
== -1) ||
1703 ((highest_irr
& 0xF0) <= kvm_apic_get_reg(apic
, APIC_PROCPRI
)))
1708 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1710 u32 lvt0
= kvm_apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1713 if (!kvm_apic_hw_enabled(vcpu
->arch
.apic
))
1715 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1716 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1721 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1723 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1725 if (!kvm_vcpu_has_lapic(vcpu
))
1728 if (atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1729 kvm_apic_local_deliver(apic
, APIC_LVTT
);
1730 if (apic_lvtt_tscdeadline(apic
))
1731 apic
->lapic_timer
.tscdeadline
= 0;
1732 atomic_set(&apic
->lapic_timer
.pending
, 0);
1736 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1738 int vector
= kvm_apic_has_interrupt(vcpu
);
1739 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1745 * We get here even with APIC virtualization enabled, if doing
1746 * nested virtualization and L1 runs with the "acknowledge interrupt
1747 * on exit" mode. Then we cannot inject the interrupt via RVI,
1748 * because the process would deliver it through the IDT.
1751 apic_set_isr(vector
, apic
);
1752 apic_update_ppr(apic
);
1753 apic_clear_irr(vector
, apic
);
1757 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
,
1758 struct kvm_lapic_state
*s
)
1760 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1762 kvm_lapic_set_base(vcpu
, vcpu
->arch
.apic_base
);
1763 /* set SPIV separately to get count of SW disabled APICs right */
1764 apic_set_spiv(apic
, *((u32
*)(s
->regs
+ APIC_SPIV
)));
1765 memcpy(vcpu
->arch
.apic
->regs
, s
->regs
, sizeof *s
);
1766 /* call kvm_apic_set_id() to put apic into apic_map */
1767 kvm_apic_set_id(apic
, kvm_apic_id(apic
));
1768 kvm_apic_set_version(vcpu
);
1770 apic_update_ppr(apic
);
1771 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1772 update_divide_count(apic
);
1773 start_apic_timer(apic
);
1774 apic
->irr_pending
= true;
1775 apic
->isr_count
= kvm_apic_vid_enabled(vcpu
->kvm
) ?
1776 1 : count_vectors(apic
->regs
+ APIC_ISR
);
1777 apic
->highest_isr_cache
= -1;
1778 if (kvm_x86_ops
->hwapic_irr_update
)
1779 kvm_x86_ops
->hwapic_irr_update(vcpu
,
1780 apic_find_highest_irr(apic
));
1781 if (unlikely(kvm_x86_ops
->hwapic_isr_update
))
1782 kvm_x86_ops
->hwapic_isr_update(vcpu
->kvm
,
1783 apic_find_highest_isr(apic
));
1784 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
1785 kvm_rtc_eoi_tracking_restore_one(vcpu
);
1788 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1790 struct hrtimer
*timer
;
1792 if (!kvm_vcpu_has_lapic(vcpu
))
1795 timer
= &vcpu
->arch
.apic
->lapic_timer
.timer
;
1796 if (hrtimer_cancel(timer
))
1797 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1801 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
1803 * Detect whether guest triggered PV EOI since the
1804 * last entry. If yes, set EOI on guests's behalf.
1805 * Clear PV EOI in guest memory in any case.
1807 static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu
*vcpu
,
1808 struct kvm_lapic
*apic
)
1813 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
1814 * and KVM_PV_EOI_ENABLED in guest memory as follows:
1816 * KVM_APIC_PV_EOI_PENDING is unset:
1817 * -> host disabled PV EOI.
1818 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
1819 * -> host enabled PV EOI, guest did not execute EOI yet.
1820 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
1821 * -> host enabled PV EOI, guest executed EOI.
1823 BUG_ON(!pv_eoi_enabled(vcpu
));
1824 pending
= pv_eoi_get_pending(vcpu
);
1826 * Clear pending bit in any case: it will be set again on vmentry.
1827 * While this might not be ideal from performance point of view,
1828 * this makes sure pv eoi is only enabled when we know it's safe.
1830 pv_eoi_clr_pending(vcpu
);
1833 vector
= apic_set_eoi(apic
);
1834 trace_kvm_pv_eoi(apic
, vector
);
1837 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1841 if (test_bit(KVM_APIC_PV_EOI_PENDING
, &vcpu
->arch
.apic_attention
))
1842 apic_sync_pv_eoi_from_guest(vcpu
, vcpu
->arch
.apic
);
1844 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1847 kvm_read_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1850 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1854 * apic_sync_pv_eoi_to_guest - called before vmentry
1856 * Detect whether it's safe to enable PV EOI and
1859 static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu
*vcpu
,
1860 struct kvm_lapic
*apic
)
1862 if (!pv_eoi_enabled(vcpu
) ||
1863 /* IRR set or many bits in ISR: could be nested. */
1864 apic
->irr_pending
||
1865 /* Cache not set: could be safe but we don't bother. */
1866 apic
->highest_isr_cache
== -1 ||
1867 /* Need EOI to update ioapic. */
1868 kvm_ioapic_handles_vector(vcpu
->kvm
, apic
->highest_isr_cache
)) {
1870 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
1871 * so we need not do anything here.
1876 pv_eoi_set_pending(apic
->vcpu
);
1879 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1882 int max_irr
, max_isr
;
1883 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1885 apic_sync_pv_eoi_to_guest(vcpu
, apic
);
1887 if (!test_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
))
1890 tpr
= kvm_apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1891 max_irr
= apic_find_highest_irr(apic
);
1894 max_isr
= apic_find_highest_isr(apic
);
1897 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1899 kvm_write_guest_cached(vcpu
->kvm
, &vcpu
->arch
.apic
->vapic_cache
, &data
,
1903 int kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1906 if (kvm_gfn_to_hva_cache_init(vcpu
->kvm
,
1907 &vcpu
->arch
.apic
->vapic_cache
,
1908 vapic_addr
, sizeof(u32
)))
1910 __set_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1912 __clear_bit(KVM_APIC_CHECK_VAPIC
, &vcpu
->arch
.apic_attention
);
1915 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1919 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1921 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1922 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1924 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1927 if (reg
== APIC_ICR2
)
1930 /* if this is ICR write vector before command */
1931 if (reg
== APIC_ICR
)
1932 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1933 return apic_reg_write(apic
, reg
, (u32
)data
);
1936 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1938 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1939 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1941 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1944 if (reg
== APIC_DFR
|| reg
== APIC_ICR2
) {
1945 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
1950 if (apic_reg_read(apic
, reg
, 4, &low
))
1952 if (reg
== APIC_ICR
)
1953 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1955 *data
= (((u64
)high
) << 32) | low
;
1960 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1962 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1964 if (!kvm_vcpu_has_lapic(vcpu
))
1967 /* if this is ICR write vector before command */
1968 if (reg
== APIC_ICR
)
1969 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1970 return apic_reg_write(apic
, reg
, (u32
)data
);
1973 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1975 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1978 if (!kvm_vcpu_has_lapic(vcpu
))
1981 if (apic_reg_read(apic
, reg
, 4, &low
))
1983 if (reg
== APIC_ICR
)
1984 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1986 *data
= (((u64
)high
) << 32) | low
;
1991 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu
*vcpu
, u64 data
)
1993 u64 addr
= data
& ~KVM_MSR_ENABLED
;
1994 if (!IS_ALIGNED(addr
, 4))
1997 vcpu
->arch
.pv_eoi
.msr_val
= data
;
1998 if (!pv_eoi_enabled(vcpu
))
2000 return kvm_gfn_to_hva_cache_init(vcpu
->kvm
, &vcpu
->arch
.pv_eoi
.data
,
2004 void kvm_apic_accept_events(struct kvm_vcpu
*vcpu
)
2006 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
2010 if (!kvm_vcpu_has_lapic(vcpu
) || !apic
->pending_events
)
2013 pe
= xchg(&apic
->pending_events
, 0);
2015 if (test_bit(KVM_APIC_INIT
, &pe
)) {
2016 kvm_lapic_reset(vcpu
);
2017 kvm_vcpu_reset(vcpu
);
2018 if (kvm_vcpu_is_bsp(apic
->vcpu
))
2019 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2021 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
2023 if (test_bit(KVM_APIC_SIPI
, &pe
) &&
2024 vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
2025 /* evaluate pending_events before reading the vector */
2027 sipi_vector
= apic
->sipi_vector
;
2028 apic_debug("vcpu %d received sipi with vector # %x\n",
2029 vcpu
->vcpu_id
, sipi_vector
);
2030 kvm_vcpu_deliver_sipi_vector(vcpu
, sipi_vector
);
2031 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
2035 void kvm_lapic_init(void)
2037 /* do not patch jump label more than once per second */
2038 jump_label_rate_limit(&apic_hw_disabled
, HZ
);
2039 jump_label_rate_limit(&apic_sw_disabled
, HZ
);