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KVM: SVM: Expect two more candiates for exit_int_info
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34
35 #include <asm/virtext.h>
36 #include "trace.h"
37
38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
39
40 MODULE_AUTHOR("Qumranet");
41 MODULE_LICENSE("GPL");
42
43 #define IOPM_ALLOC_ORDER 2
44 #define MSRPM_ALLOC_ORDER 1
45
46 #define SEG_TYPE_LDT 2
47 #define SEG_TYPE_BUSY_TSS16 3
48
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_FEATURE_SVML (1 << 2)
52 #define SVM_FEATURE_NRIP (1 << 3)
53 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
54
55 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
58
59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
60
61 static bool erratum_383_found __read_mostly;
62
63 static const u32 host_save_user_msrs[] = {
64 #ifdef CONFIG_X86_64
65 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
66 MSR_FS_BASE,
67 #endif
68 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
69 };
70
71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
72
73 struct kvm_vcpu;
74
75 struct nested_state {
76 struct vmcb *hsave;
77 u64 hsave_msr;
78 u64 vm_cr_msr;
79 u64 vmcb;
80
81 /* These are the merged vectors */
82 u32 *msrpm;
83
84 /* gpa pointers to the real vectors */
85 u64 vmcb_msrpm;
86 u64 vmcb_iopm;
87
88 /* A VMEXIT is required but not yet emulated */
89 bool exit_required;
90
91 /*
92 * If we vmexit during an instruction emulation we need this to restore
93 * the l1 guest rip after the emulation
94 */
95 unsigned long vmexit_rip;
96 unsigned long vmexit_rsp;
97 unsigned long vmexit_rax;
98
99 /* cache for intercepts of the guest */
100 u16 intercept_cr_read;
101 u16 intercept_cr_write;
102 u16 intercept_dr_read;
103 u16 intercept_dr_write;
104 u32 intercept_exceptions;
105 u64 intercept;
106
107 /* Nested Paging related state */
108 u64 nested_cr3;
109 };
110
111 #define MSRPM_OFFSETS 16
112 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
113
114 struct vcpu_svm {
115 struct kvm_vcpu vcpu;
116 struct vmcb *vmcb;
117 unsigned long vmcb_pa;
118 struct svm_cpu_data *svm_data;
119 uint64_t asid_generation;
120 uint64_t sysenter_esp;
121 uint64_t sysenter_eip;
122
123 u64 next_rip;
124
125 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
126 u64 host_gs_base;
127
128 u32 *msrpm;
129
130 struct nested_state nested;
131
132 bool nmi_singlestep;
133
134 unsigned int3_injected;
135 unsigned long int3_rip;
136 };
137
138 #define MSR_INVALID 0xffffffffU
139
140 static struct svm_direct_access_msrs {
141 u32 index; /* Index of the MSR */
142 bool always; /* True if intercept is always on */
143 } direct_access_msrs[] = {
144 { .index = MSR_STAR, .always = true },
145 { .index = MSR_IA32_SYSENTER_CS, .always = true },
146 #ifdef CONFIG_X86_64
147 { .index = MSR_GS_BASE, .always = true },
148 { .index = MSR_FS_BASE, .always = true },
149 { .index = MSR_KERNEL_GS_BASE, .always = true },
150 { .index = MSR_LSTAR, .always = true },
151 { .index = MSR_CSTAR, .always = true },
152 { .index = MSR_SYSCALL_MASK, .always = true },
153 #endif
154 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
155 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
156 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
157 { .index = MSR_IA32_LASTINTTOIP, .always = false },
158 { .index = MSR_INVALID, .always = false },
159 };
160
161 /* enable NPT for AMD64 and X86 with PAE */
162 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
163 static bool npt_enabled = true;
164 #else
165 static bool npt_enabled;
166 #endif
167 static int npt = 1;
168
169 module_param(npt, int, S_IRUGO);
170
171 static int nested = 1;
172 module_param(nested, int, S_IRUGO);
173
174 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
175 static void svm_complete_interrupts(struct vcpu_svm *svm);
176
177 static int nested_svm_exit_handled(struct vcpu_svm *svm);
178 static int nested_svm_intercept(struct vcpu_svm *svm);
179 static int nested_svm_vmexit(struct vcpu_svm *svm);
180 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
181 bool has_error_code, u32 error_code);
182
183 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
184 {
185 return container_of(vcpu, struct vcpu_svm, vcpu);
186 }
187
188 static inline bool is_nested(struct vcpu_svm *svm)
189 {
190 return svm->nested.vmcb;
191 }
192
193 static inline void enable_gif(struct vcpu_svm *svm)
194 {
195 svm->vcpu.arch.hflags |= HF_GIF_MASK;
196 }
197
198 static inline void disable_gif(struct vcpu_svm *svm)
199 {
200 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
201 }
202
203 static inline bool gif_set(struct vcpu_svm *svm)
204 {
205 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
206 }
207
208 static unsigned long iopm_base;
209
210 struct kvm_ldttss_desc {
211 u16 limit0;
212 u16 base0;
213 unsigned base1:8, type:5, dpl:2, p:1;
214 unsigned limit1:4, zero0:3, g:1, base2:8;
215 u32 base3;
216 u32 zero1;
217 } __attribute__((packed));
218
219 struct svm_cpu_data {
220 int cpu;
221
222 u64 asid_generation;
223 u32 max_asid;
224 u32 next_asid;
225 struct kvm_ldttss_desc *tss_desc;
226
227 struct page *save_area;
228 };
229
230 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
231 static uint32_t svm_features;
232
233 struct svm_init_data {
234 int cpu;
235 int r;
236 };
237
238 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
239
240 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
241 #define MSRS_RANGE_SIZE 2048
242 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
243
244 static u32 svm_msrpm_offset(u32 msr)
245 {
246 u32 offset;
247 int i;
248
249 for (i = 0; i < NUM_MSR_MAPS; i++) {
250 if (msr < msrpm_ranges[i] ||
251 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
252 continue;
253
254 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
255 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
256
257 /* Now we have the u8 offset - but need the u32 offset */
258 return offset / 4;
259 }
260
261 /* MSR not in any range */
262 return MSR_INVALID;
263 }
264
265 #define MAX_INST_SIZE 15
266
267 static inline u32 svm_has(u32 feat)
268 {
269 return svm_features & feat;
270 }
271
272 static inline void clgi(void)
273 {
274 asm volatile (__ex(SVM_CLGI));
275 }
276
277 static inline void stgi(void)
278 {
279 asm volatile (__ex(SVM_STGI));
280 }
281
282 static inline void invlpga(unsigned long addr, u32 asid)
283 {
284 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
285 }
286
287 static inline void force_new_asid(struct kvm_vcpu *vcpu)
288 {
289 to_svm(vcpu)->asid_generation--;
290 }
291
292 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
293 {
294 force_new_asid(vcpu);
295 }
296
297 static int get_npt_level(void)
298 {
299 #ifdef CONFIG_X86_64
300 return PT64_ROOT_LEVEL;
301 #else
302 return PT32E_ROOT_LEVEL;
303 #endif
304 }
305
306 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
307 {
308 vcpu->arch.efer = efer;
309 if (!npt_enabled && !(efer & EFER_LMA))
310 efer &= ~EFER_LME;
311
312 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
313 }
314
315 static int is_external_interrupt(u32 info)
316 {
317 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
318 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
319 }
320
321 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
322 {
323 struct vcpu_svm *svm = to_svm(vcpu);
324 u32 ret = 0;
325
326 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
327 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
328 return ret & mask;
329 }
330
331 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
332 {
333 struct vcpu_svm *svm = to_svm(vcpu);
334
335 if (mask == 0)
336 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
337 else
338 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
339
340 }
341
342 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
343 {
344 struct vcpu_svm *svm = to_svm(vcpu);
345
346 if (svm->vmcb->control.next_rip != 0)
347 svm->next_rip = svm->vmcb->control.next_rip;
348
349 if (!svm->next_rip) {
350 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
351 EMULATE_DONE)
352 printk(KERN_DEBUG "%s: NOP\n", __func__);
353 return;
354 }
355 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
356 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
357 __func__, kvm_rip_read(vcpu), svm->next_rip);
358
359 kvm_rip_write(vcpu, svm->next_rip);
360 svm_set_interrupt_shadow(vcpu, 0);
361 }
362
363 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
364 bool has_error_code, u32 error_code,
365 bool reinject)
366 {
367 struct vcpu_svm *svm = to_svm(vcpu);
368
369 /*
370 * If we are within a nested VM we'd better #VMEXIT and let the guest
371 * handle the exception
372 */
373 if (!reinject &&
374 nested_svm_check_exception(svm, nr, has_error_code, error_code))
375 return;
376
377 if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
378 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
379
380 /*
381 * For guest debugging where we have to reinject #BP if some
382 * INT3 is guest-owned:
383 * Emulate nRIP by moving RIP forward. Will fail if injection
384 * raises a fault that is not intercepted. Still better than
385 * failing in all cases.
386 */
387 skip_emulated_instruction(&svm->vcpu);
388 rip = kvm_rip_read(&svm->vcpu);
389 svm->int3_rip = rip + svm->vmcb->save.cs.base;
390 svm->int3_injected = rip - old_rip;
391 }
392
393 svm->vmcb->control.event_inj = nr
394 | SVM_EVTINJ_VALID
395 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
396 | SVM_EVTINJ_TYPE_EXEPT;
397 svm->vmcb->control.event_inj_err = error_code;
398 }
399
400 static void svm_init_erratum_383(void)
401 {
402 u32 low, high;
403 int err;
404 u64 val;
405
406 if (!cpu_has_amd_erratum(amd_erratum_383))
407 return;
408
409 /* Use _safe variants to not break nested virtualization */
410 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
411 if (err)
412 return;
413
414 val |= (1ULL << 47);
415
416 low = lower_32_bits(val);
417 high = upper_32_bits(val);
418
419 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
420
421 erratum_383_found = true;
422 }
423
424 static int has_svm(void)
425 {
426 const char *msg;
427
428 if (!cpu_has_svm(&msg)) {
429 printk(KERN_INFO "has_svm: %s\n", msg);
430 return 0;
431 }
432
433 return 1;
434 }
435
436 static void svm_hardware_disable(void *garbage)
437 {
438 cpu_svm_disable();
439 }
440
441 static int svm_hardware_enable(void *garbage)
442 {
443
444 struct svm_cpu_data *sd;
445 uint64_t efer;
446 struct desc_ptr gdt_descr;
447 struct desc_struct *gdt;
448 int me = raw_smp_processor_id();
449
450 rdmsrl(MSR_EFER, efer);
451 if (efer & EFER_SVME)
452 return -EBUSY;
453
454 if (!has_svm()) {
455 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
456 me);
457 return -EINVAL;
458 }
459 sd = per_cpu(svm_data, me);
460
461 if (!sd) {
462 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
463 me);
464 return -EINVAL;
465 }
466
467 sd->asid_generation = 1;
468 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
469 sd->next_asid = sd->max_asid + 1;
470
471 native_store_gdt(&gdt_descr);
472 gdt = (struct desc_struct *)gdt_descr.address;
473 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
474
475 wrmsrl(MSR_EFER, efer | EFER_SVME);
476
477 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
478
479 svm_init_erratum_383();
480
481 return 0;
482 }
483
484 static void svm_cpu_uninit(int cpu)
485 {
486 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
487
488 if (!sd)
489 return;
490
491 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
492 __free_page(sd->save_area);
493 kfree(sd);
494 }
495
496 static int svm_cpu_init(int cpu)
497 {
498 struct svm_cpu_data *sd;
499 int r;
500
501 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
502 if (!sd)
503 return -ENOMEM;
504 sd->cpu = cpu;
505 sd->save_area = alloc_page(GFP_KERNEL);
506 r = -ENOMEM;
507 if (!sd->save_area)
508 goto err_1;
509
510 per_cpu(svm_data, cpu) = sd;
511
512 return 0;
513
514 err_1:
515 kfree(sd);
516 return r;
517
518 }
519
520 static bool valid_msr_intercept(u32 index)
521 {
522 int i;
523
524 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
525 if (direct_access_msrs[i].index == index)
526 return true;
527
528 return false;
529 }
530
531 static void set_msr_interception(u32 *msrpm, unsigned msr,
532 int read, int write)
533 {
534 u8 bit_read, bit_write;
535 unsigned long tmp;
536 u32 offset;
537
538 /*
539 * If this warning triggers extend the direct_access_msrs list at the
540 * beginning of the file
541 */
542 WARN_ON(!valid_msr_intercept(msr));
543
544 offset = svm_msrpm_offset(msr);
545 bit_read = 2 * (msr & 0x0f);
546 bit_write = 2 * (msr & 0x0f) + 1;
547 tmp = msrpm[offset];
548
549 BUG_ON(offset == MSR_INVALID);
550
551 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
552 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
553
554 msrpm[offset] = tmp;
555 }
556
557 static void svm_vcpu_init_msrpm(u32 *msrpm)
558 {
559 int i;
560
561 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
562
563 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
564 if (!direct_access_msrs[i].always)
565 continue;
566
567 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
568 }
569 }
570
571 static void add_msr_offset(u32 offset)
572 {
573 int i;
574
575 for (i = 0; i < MSRPM_OFFSETS; ++i) {
576
577 /* Offset already in list? */
578 if (msrpm_offsets[i] == offset)
579 return;
580
581 /* Slot used by another offset? */
582 if (msrpm_offsets[i] != MSR_INVALID)
583 continue;
584
585 /* Add offset to list */
586 msrpm_offsets[i] = offset;
587
588 return;
589 }
590
591 /*
592 * If this BUG triggers the msrpm_offsets table has an overflow. Just
593 * increase MSRPM_OFFSETS in this case.
594 */
595 BUG();
596 }
597
598 static void init_msrpm_offsets(void)
599 {
600 int i;
601
602 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
603
604 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
605 u32 offset;
606
607 offset = svm_msrpm_offset(direct_access_msrs[i].index);
608 BUG_ON(offset == MSR_INVALID);
609
610 add_msr_offset(offset);
611 }
612 }
613
614 static void svm_enable_lbrv(struct vcpu_svm *svm)
615 {
616 u32 *msrpm = svm->msrpm;
617
618 svm->vmcb->control.lbr_ctl = 1;
619 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
620 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
621 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
622 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
623 }
624
625 static void svm_disable_lbrv(struct vcpu_svm *svm)
626 {
627 u32 *msrpm = svm->msrpm;
628
629 svm->vmcb->control.lbr_ctl = 0;
630 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
631 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
632 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
633 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
634 }
635
636 static __init int svm_hardware_setup(void)
637 {
638 int cpu;
639 struct page *iopm_pages;
640 void *iopm_va;
641 int r;
642
643 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
644
645 if (!iopm_pages)
646 return -ENOMEM;
647
648 iopm_va = page_address(iopm_pages);
649 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
650 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
651
652 init_msrpm_offsets();
653
654 if (boot_cpu_has(X86_FEATURE_NX))
655 kvm_enable_efer_bits(EFER_NX);
656
657 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
658 kvm_enable_efer_bits(EFER_FFXSR);
659
660 if (nested) {
661 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
662 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
663 }
664
665 for_each_possible_cpu(cpu) {
666 r = svm_cpu_init(cpu);
667 if (r)
668 goto err;
669 }
670
671 svm_features = cpuid_edx(SVM_CPUID_FUNC);
672
673 if (!svm_has(SVM_FEATURE_NPT))
674 npt_enabled = false;
675
676 if (npt_enabled && !npt) {
677 printk(KERN_INFO "kvm: Nested Paging disabled\n");
678 npt_enabled = false;
679 }
680
681 if (npt_enabled) {
682 printk(KERN_INFO "kvm: Nested Paging enabled\n");
683 kvm_enable_tdp();
684 } else
685 kvm_disable_tdp();
686
687 return 0;
688
689 err:
690 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
691 iopm_base = 0;
692 return r;
693 }
694
695 static __exit void svm_hardware_unsetup(void)
696 {
697 int cpu;
698
699 for_each_possible_cpu(cpu)
700 svm_cpu_uninit(cpu);
701
702 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
703 iopm_base = 0;
704 }
705
706 static void init_seg(struct vmcb_seg *seg)
707 {
708 seg->selector = 0;
709 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
710 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
711 seg->limit = 0xffff;
712 seg->base = 0;
713 }
714
715 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
716 {
717 seg->selector = 0;
718 seg->attrib = SVM_SELECTOR_P_MASK | type;
719 seg->limit = 0xffff;
720 seg->base = 0;
721 }
722
723 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
724 {
725 struct vcpu_svm *svm = to_svm(vcpu);
726 u64 g_tsc_offset = 0;
727
728 if (is_nested(svm)) {
729 g_tsc_offset = svm->vmcb->control.tsc_offset -
730 svm->nested.hsave->control.tsc_offset;
731 svm->nested.hsave->control.tsc_offset = offset;
732 }
733
734 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
735 }
736
737 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
738 {
739 struct vcpu_svm *svm = to_svm(vcpu);
740
741 svm->vmcb->control.tsc_offset += adjustment;
742 if (is_nested(svm))
743 svm->nested.hsave->control.tsc_offset += adjustment;
744 }
745
746 static void init_vmcb(struct vcpu_svm *svm)
747 {
748 struct vmcb_control_area *control = &svm->vmcb->control;
749 struct vmcb_save_area *save = &svm->vmcb->save;
750
751 svm->vcpu.fpu_active = 1;
752
753 control->intercept_cr_read = INTERCEPT_CR0_MASK |
754 INTERCEPT_CR3_MASK |
755 INTERCEPT_CR4_MASK;
756
757 control->intercept_cr_write = INTERCEPT_CR0_MASK |
758 INTERCEPT_CR3_MASK |
759 INTERCEPT_CR4_MASK |
760 INTERCEPT_CR8_MASK;
761
762 control->intercept_dr_read = INTERCEPT_DR0_MASK |
763 INTERCEPT_DR1_MASK |
764 INTERCEPT_DR2_MASK |
765 INTERCEPT_DR3_MASK |
766 INTERCEPT_DR4_MASK |
767 INTERCEPT_DR5_MASK |
768 INTERCEPT_DR6_MASK |
769 INTERCEPT_DR7_MASK;
770
771 control->intercept_dr_write = INTERCEPT_DR0_MASK |
772 INTERCEPT_DR1_MASK |
773 INTERCEPT_DR2_MASK |
774 INTERCEPT_DR3_MASK |
775 INTERCEPT_DR4_MASK |
776 INTERCEPT_DR5_MASK |
777 INTERCEPT_DR6_MASK |
778 INTERCEPT_DR7_MASK;
779
780 control->intercept_exceptions = (1 << PF_VECTOR) |
781 (1 << UD_VECTOR) |
782 (1 << MC_VECTOR);
783
784
785 control->intercept = (1ULL << INTERCEPT_INTR) |
786 (1ULL << INTERCEPT_NMI) |
787 (1ULL << INTERCEPT_SMI) |
788 (1ULL << INTERCEPT_SELECTIVE_CR0) |
789 (1ULL << INTERCEPT_CPUID) |
790 (1ULL << INTERCEPT_INVD) |
791 (1ULL << INTERCEPT_HLT) |
792 (1ULL << INTERCEPT_INVLPG) |
793 (1ULL << INTERCEPT_INVLPGA) |
794 (1ULL << INTERCEPT_IOIO_PROT) |
795 (1ULL << INTERCEPT_MSR_PROT) |
796 (1ULL << INTERCEPT_TASK_SWITCH) |
797 (1ULL << INTERCEPT_SHUTDOWN) |
798 (1ULL << INTERCEPT_VMRUN) |
799 (1ULL << INTERCEPT_VMMCALL) |
800 (1ULL << INTERCEPT_VMLOAD) |
801 (1ULL << INTERCEPT_VMSAVE) |
802 (1ULL << INTERCEPT_STGI) |
803 (1ULL << INTERCEPT_CLGI) |
804 (1ULL << INTERCEPT_SKINIT) |
805 (1ULL << INTERCEPT_WBINVD) |
806 (1ULL << INTERCEPT_MONITOR) |
807 (1ULL << INTERCEPT_MWAIT);
808
809 control->iopm_base_pa = iopm_base;
810 control->msrpm_base_pa = __pa(svm->msrpm);
811 control->int_ctl = V_INTR_MASKING_MASK;
812
813 init_seg(&save->es);
814 init_seg(&save->ss);
815 init_seg(&save->ds);
816 init_seg(&save->fs);
817 init_seg(&save->gs);
818
819 save->cs.selector = 0xf000;
820 /* Executable/Readable Code Segment */
821 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
822 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
823 save->cs.limit = 0xffff;
824 /*
825 * cs.base should really be 0xffff0000, but vmx can't handle that, so
826 * be consistent with it.
827 *
828 * Replace when we have real mode working for vmx.
829 */
830 save->cs.base = 0xf0000;
831
832 save->gdtr.limit = 0xffff;
833 save->idtr.limit = 0xffff;
834
835 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
836 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
837
838 svm_set_efer(&svm->vcpu, 0);
839 save->dr6 = 0xffff0ff0;
840 save->dr7 = 0x400;
841 save->rflags = 2;
842 save->rip = 0x0000fff0;
843 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
844
845 /*
846 * This is the guest-visible cr0 value.
847 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
848 */
849 svm->vcpu.arch.cr0 = 0;
850 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
851
852 save->cr4 = X86_CR4_PAE;
853 /* rdx = ?? */
854
855 if (npt_enabled) {
856 /* Setup VMCB for Nested Paging */
857 control->nested_ctl = 1;
858 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
859 (1ULL << INTERCEPT_INVLPG));
860 control->intercept_exceptions &= ~(1 << PF_VECTOR);
861 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
862 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
863 save->g_pat = 0x0007040600070406ULL;
864 save->cr3 = 0;
865 save->cr4 = 0;
866 }
867 force_new_asid(&svm->vcpu);
868
869 svm->nested.vmcb = 0;
870 svm->vcpu.arch.hflags = 0;
871
872 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
873 control->pause_filter_count = 3000;
874 control->intercept |= (1ULL << INTERCEPT_PAUSE);
875 }
876
877 enable_gif(svm);
878 }
879
880 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
881 {
882 struct vcpu_svm *svm = to_svm(vcpu);
883
884 init_vmcb(svm);
885
886 if (!kvm_vcpu_is_bsp(vcpu)) {
887 kvm_rip_write(vcpu, 0);
888 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
889 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
890 }
891 vcpu->arch.regs_avail = ~0;
892 vcpu->arch.regs_dirty = ~0;
893
894 return 0;
895 }
896
897 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
898 {
899 struct vcpu_svm *svm;
900 struct page *page;
901 struct page *msrpm_pages;
902 struct page *hsave_page;
903 struct page *nested_msrpm_pages;
904 int err;
905
906 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
907 if (!svm) {
908 err = -ENOMEM;
909 goto out;
910 }
911
912 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
913 if (err)
914 goto free_svm;
915
916 err = -ENOMEM;
917 page = alloc_page(GFP_KERNEL);
918 if (!page)
919 goto uninit;
920
921 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
922 if (!msrpm_pages)
923 goto free_page1;
924
925 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
926 if (!nested_msrpm_pages)
927 goto free_page2;
928
929 hsave_page = alloc_page(GFP_KERNEL);
930 if (!hsave_page)
931 goto free_page3;
932
933 svm->nested.hsave = page_address(hsave_page);
934
935 svm->msrpm = page_address(msrpm_pages);
936 svm_vcpu_init_msrpm(svm->msrpm);
937
938 svm->nested.msrpm = page_address(nested_msrpm_pages);
939 svm_vcpu_init_msrpm(svm->nested.msrpm);
940
941 svm->vmcb = page_address(page);
942 clear_page(svm->vmcb);
943 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
944 svm->asid_generation = 0;
945 init_vmcb(svm);
946 kvm_write_tsc(&svm->vcpu, 0);
947
948 err = fx_init(&svm->vcpu);
949 if (err)
950 goto free_page4;
951
952 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
953 if (kvm_vcpu_is_bsp(&svm->vcpu))
954 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
955
956 return &svm->vcpu;
957
958 free_page4:
959 __free_page(hsave_page);
960 free_page3:
961 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
962 free_page2:
963 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
964 free_page1:
965 __free_page(page);
966 uninit:
967 kvm_vcpu_uninit(&svm->vcpu);
968 free_svm:
969 kmem_cache_free(kvm_vcpu_cache, svm);
970 out:
971 return ERR_PTR(err);
972 }
973
974 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
975 {
976 struct vcpu_svm *svm = to_svm(vcpu);
977
978 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
979 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
980 __free_page(virt_to_page(svm->nested.hsave));
981 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
982 kvm_vcpu_uninit(vcpu);
983 kmem_cache_free(kvm_vcpu_cache, svm);
984 }
985
986 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
987 {
988 struct vcpu_svm *svm = to_svm(vcpu);
989 int i;
990
991 if (unlikely(cpu != vcpu->cpu)) {
992 svm->asid_generation = 0;
993 }
994
995 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
996 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
997 }
998
999 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1000 {
1001 struct vcpu_svm *svm = to_svm(vcpu);
1002 int i;
1003
1004 ++vcpu->stat.host_state_reload;
1005 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1006 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1007 }
1008
1009 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1010 {
1011 return to_svm(vcpu)->vmcb->save.rflags;
1012 }
1013
1014 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1015 {
1016 to_svm(vcpu)->vmcb->save.rflags = rflags;
1017 }
1018
1019 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1020 {
1021 switch (reg) {
1022 case VCPU_EXREG_PDPTR:
1023 BUG_ON(!npt_enabled);
1024 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
1025 break;
1026 default:
1027 BUG();
1028 }
1029 }
1030
1031 static void svm_set_vintr(struct vcpu_svm *svm)
1032 {
1033 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1034 }
1035
1036 static void svm_clear_vintr(struct vcpu_svm *svm)
1037 {
1038 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1039 }
1040
1041 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1042 {
1043 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1044
1045 switch (seg) {
1046 case VCPU_SREG_CS: return &save->cs;
1047 case VCPU_SREG_DS: return &save->ds;
1048 case VCPU_SREG_ES: return &save->es;
1049 case VCPU_SREG_FS: return &save->fs;
1050 case VCPU_SREG_GS: return &save->gs;
1051 case VCPU_SREG_SS: return &save->ss;
1052 case VCPU_SREG_TR: return &save->tr;
1053 case VCPU_SREG_LDTR: return &save->ldtr;
1054 }
1055 BUG();
1056 return NULL;
1057 }
1058
1059 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1060 {
1061 struct vmcb_seg *s = svm_seg(vcpu, seg);
1062
1063 return s->base;
1064 }
1065
1066 static void svm_get_segment(struct kvm_vcpu *vcpu,
1067 struct kvm_segment *var, int seg)
1068 {
1069 struct vmcb_seg *s = svm_seg(vcpu, seg);
1070
1071 var->base = s->base;
1072 var->limit = s->limit;
1073 var->selector = s->selector;
1074 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1075 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1076 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1077 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1078 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1079 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1080 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1081 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1082
1083 /*
1084 * AMD's VMCB does not have an explicit unusable field, so emulate it
1085 * for cross vendor migration purposes by "not present"
1086 */
1087 var->unusable = !var->present || (var->type == 0);
1088
1089 switch (seg) {
1090 case VCPU_SREG_CS:
1091 /*
1092 * SVM always stores 0 for the 'G' bit in the CS selector in
1093 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1094 * Intel's VMENTRY has a check on the 'G' bit.
1095 */
1096 var->g = s->limit > 0xfffff;
1097 break;
1098 case VCPU_SREG_TR:
1099 /*
1100 * Work around a bug where the busy flag in the tr selector
1101 * isn't exposed
1102 */
1103 var->type |= 0x2;
1104 break;
1105 case VCPU_SREG_DS:
1106 case VCPU_SREG_ES:
1107 case VCPU_SREG_FS:
1108 case VCPU_SREG_GS:
1109 /*
1110 * The accessed bit must always be set in the segment
1111 * descriptor cache, although it can be cleared in the
1112 * descriptor, the cached bit always remains at 1. Since
1113 * Intel has a check on this, set it here to support
1114 * cross-vendor migration.
1115 */
1116 if (!var->unusable)
1117 var->type |= 0x1;
1118 break;
1119 case VCPU_SREG_SS:
1120 /*
1121 * On AMD CPUs sometimes the DB bit in the segment
1122 * descriptor is left as 1, although the whole segment has
1123 * been made unusable. Clear it here to pass an Intel VMX
1124 * entry check when cross vendor migrating.
1125 */
1126 if (var->unusable)
1127 var->db = 0;
1128 break;
1129 }
1130 }
1131
1132 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1133 {
1134 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1135
1136 return save->cpl;
1137 }
1138
1139 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1140 {
1141 struct vcpu_svm *svm = to_svm(vcpu);
1142
1143 dt->size = svm->vmcb->save.idtr.limit;
1144 dt->address = svm->vmcb->save.idtr.base;
1145 }
1146
1147 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1148 {
1149 struct vcpu_svm *svm = to_svm(vcpu);
1150
1151 svm->vmcb->save.idtr.limit = dt->size;
1152 svm->vmcb->save.idtr.base = dt->address ;
1153 }
1154
1155 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1156 {
1157 struct vcpu_svm *svm = to_svm(vcpu);
1158
1159 dt->size = svm->vmcb->save.gdtr.limit;
1160 dt->address = svm->vmcb->save.gdtr.base;
1161 }
1162
1163 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1164 {
1165 struct vcpu_svm *svm = to_svm(vcpu);
1166
1167 svm->vmcb->save.gdtr.limit = dt->size;
1168 svm->vmcb->save.gdtr.base = dt->address ;
1169 }
1170
1171 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1172 {
1173 }
1174
1175 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1176 {
1177 }
1178
1179 static void update_cr0_intercept(struct vcpu_svm *svm)
1180 {
1181 struct vmcb *vmcb = svm->vmcb;
1182 ulong gcr0 = svm->vcpu.arch.cr0;
1183 u64 *hcr0 = &svm->vmcb->save.cr0;
1184
1185 if (!svm->vcpu.fpu_active)
1186 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1187 else
1188 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1189 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1190
1191
1192 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1193 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1194 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1195 if (is_nested(svm)) {
1196 struct vmcb *hsave = svm->nested.hsave;
1197
1198 hsave->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1199 hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1200 vmcb->control.intercept_cr_read |= svm->nested.intercept_cr_read;
1201 vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1202 }
1203 } else {
1204 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1205 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1206 if (is_nested(svm)) {
1207 struct vmcb *hsave = svm->nested.hsave;
1208
1209 hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1210 hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1211 }
1212 }
1213 }
1214
1215 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1216 {
1217 struct vcpu_svm *svm = to_svm(vcpu);
1218
1219 if (is_nested(svm)) {
1220 /*
1221 * We are here because we run in nested mode, the host kvm
1222 * intercepts cr0 writes but the l1 hypervisor does not.
1223 * But the L1 hypervisor may intercept selective cr0 writes.
1224 * This needs to be checked here.
1225 */
1226 unsigned long old, new;
1227
1228 /* Remove bits that would trigger a real cr0 write intercept */
1229 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1230 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1231
1232 if (old == new) {
1233 /* cr0 write with ts and mp unchanged */
1234 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1235 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1236 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1237 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1238 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1239 return;
1240 }
1241 }
1242 }
1243
1244 #ifdef CONFIG_X86_64
1245 if (vcpu->arch.efer & EFER_LME) {
1246 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1247 vcpu->arch.efer |= EFER_LMA;
1248 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1249 }
1250
1251 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1252 vcpu->arch.efer &= ~EFER_LMA;
1253 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1254 }
1255 }
1256 #endif
1257 vcpu->arch.cr0 = cr0;
1258
1259 if (!npt_enabled)
1260 cr0 |= X86_CR0_PG | X86_CR0_WP;
1261
1262 if (!vcpu->fpu_active)
1263 cr0 |= X86_CR0_TS;
1264 /*
1265 * re-enable caching here because the QEMU bios
1266 * does not do it - this results in some delay at
1267 * reboot
1268 */
1269 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1270 svm->vmcb->save.cr0 = cr0;
1271 update_cr0_intercept(svm);
1272 }
1273
1274 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1275 {
1276 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1277 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1278
1279 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1280 force_new_asid(vcpu);
1281
1282 vcpu->arch.cr4 = cr4;
1283 if (!npt_enabled)
1284 cr4 |= X86_CR4_PAE;
1285 cr4 |= host_cr4_mce;
1286 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1287 }
1288
1289 static void svm_set_segment(struct kvm_vcpu *vcpu,
1290 struct kvm_segment *var, int seg)
1291 {
1292 struct vcpu_svm *svm = to_svm(vcpu);
1293 struct vmcb_seg *s = svm_seg(vcpu, seg);
1294
1295 s->base = var->base;
1296 s->limit = var->limit;
1297 s->selector = var->selector;
1298 if (var->unusable)
1299 s->attrib = 0;
1300 else {
1301 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1302 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1303 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1304 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1305 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1306 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1307 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1308 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1309 }
1310 if (seg == VCPU_SREG_CS)
1311 svm->vmcb->save.cpl
1312 = (svm->vmcb->save.cs.attrib
1313 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1314
1315 }
1316
1317 static void update_db_intercept(struct kvm_vcpu *vcpu)
1318 {
1319 struct vcpu_svm *svm = to_svm(vcpu);
1320
1321 svm->vmcb->control.intercept_exceptions &=
1322 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1323
1324 if (svm->nmi_singlestep)
1325 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1326
1327 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1328 if (vcpu->guest_debug &
1329 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1330 svm->vmcb->control.intercept_exceptions |=
1331 1 << DB_VECTOR;
1332 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1333 svm->vmcb->control.intercept_exceptions |=
1334 1 << BP_VECTOR;
1335 } else
1336 vcpu->guest_debug = 0;
1337 }
1338
1339 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1340 {
1341 struct vcpu_svm *svm = to_svm(vcpu);
1342
1343 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1344 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1345 else
1346 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1347
1348 update_db_intercept(vcpu);
1349 }
1350
1351 static void load_host_msrs(struct kvm_vcpu *vcpu)
1352 {
1353 #ifdef CONFIG_X86_64
1354 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1355 #endif
1356 }
1357
1358 static void save_host_msrs(struct kvm_vcpu *vcpu)
1359 {
1360 #ifdef CONFIG_X86_64
1361 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1362 #endif
1363 }
1364
1365 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1366 {
1367 if (sd->next_asid > sd->max_asid) {
1368 ++sd->asid_generation;
1369 sd->next_asid = 1;
1370 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1371 }
1372
1373 svm->asid_generation = sd->asid_generation;
1374 svm->vmcb->control.asid = sd->next_asid++;
1375 }
1376
1377 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1378 {
1379 struct vcpu_svm *svm = to_svm(vcpu);
1380
1381 svm->vmcb->save.dr7 = value;
1382 }
1383
1384 static int pf_interception(struct vcpu_svm *svm)
1385 {
1386 u64 fault_address;
1387 u32 error_code;
1388
1389 fault_address = svm->vmcb->control.exit_info_2;
1390 error_code = svm->vmcb->control.exit_info_1;
1391
1392 trace_kvm_page_fault(fault_address, error_code);
1393 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1394 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1395 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1396 }
1397
1398 static int db_interception(struct vcpu_svm *svm)
1399 {
1400 struct kvm_run *kvm_run = svm->vcpu.run;
1401
1402 if (!(svm->vcpu.guest_debug &
1403 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1404 !svm->nmi_singlestep) {
1405 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1406 return 1;
1407 }
1408
1409 if (svm->nmi_singlestep) {
1410 svm->nmi_singlestep = false;
1411 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1412 svm->vmcb->save.rflags &=
1413 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1414 update_db_intercept(&svm->vcpu);
1415 }
1416
1417 if (svm->vcpu.guest_debug &
1418 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1419 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1420 kvm_run->debug.arch.pc =
1421 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1422 kvm_run->debug.arch.exception = DB_VECTOR;
1423 return 0;
1424 }
1425
1426 return 1;
1427 }
1428
1429 static int bp_interception(struct vcpu_svm *svm)
1430 {
1431 struct kvm_run *kvm_run = svm->vcpu.run;
1432
1433 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1434 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1435 kvm_run->debug.arch.exception = BP_VECTOR;
1436 return 0;
1437 }
1438
1439 static int ud_interception(struct vcpu_svm *svm)
1440 {
1441 int er;
1442
1443 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1444 if (er != EMULATE_DONE)
1445 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1446 return 1;
1447 }
1448
1449 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1450 {
1451 struct vcpu_svm *svm = to_svm(vcpu);
1452 u32 excp;
1453
1454 if (is_nested(svm)) {
1455 u32 h_excp, n_excp;
1456
1457 h_excp = svm->nested.hsave->control.intercept_exceptions;
1458 n_excp = svm->nested.intercept_exceptions;
1459 h_excp &= ~(1 << NM_VECTOR);
1460 excp = h_excp | n_excp;
1461 } else {
1462 excp = svm->vmcb->control.intercept_exceptions;
1463 excp &= ~(1 << NM_VECTOR);
1464 }
1465
1466 svm->vmcb->control.intercept_exceptions = excp;
1467
1468 svm->vcpu.fpu_active = 1;
1469 update_cr0_intercept(svm);
1470 }
1471
1472 static int nm_interception(struct vcpu_svm *svm)
1473 {
1474 svm_fpu_activate(&svm->vcpu);
1475 return 1;
1476 }
1477
1478 static bool is_erratum_383(void)
1479 {
1480 int err, i;
1481 u64 value;
1482
1483 if (!erratum_383_found)
1484 return false;
1485
1486 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1487 if (err)
1488 return false;
1489
1490 /* Bit 62 may or may not be set for this mce */
1491 value &= ~(1ULL << 62);
1492
1493 if (value != 0xb600000000010015ULL)
1494 return false;
1495
1496 /* Clear MCi_STATUS registers */
1497 for (i = 0; i < 6; ++i)
1498 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1499
1500 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1501 if (!err) {
1502 u32 low, high;
1503
1504 value &= ~(1ULL << 2);
1505 low = lower_32_bits(value);
1506 high = upper_32_bits(value);
1507
1508 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1509 }
1510
1511 /* Flush tlb to evict multi-match entries */
1512 __flush_tlb_all();
1513
1514 return true;
1515 }
1516
1517 static void svm_handle_mce(struct vcpu_svm *svm)
1518 {
1519 if (is_erratum_383()) {
1520 /*
1521 * Erratum 383 triggered. Guest state is corrupt so kill the
1522 * guest.
1523 */
1524 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1525
1526 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1527
1528 return;
1529 }
1530
1531 /*
1532 * On an #MC intercept the MCE handler is not called automatically in
1533 * the host. So do it by hand here.
1534 */
1535 asm volatile (
1536 "int $0x12\n");
1537 /* not sure if we ever come back to this point */
1538
1539 return;
1540 }
1541
1542 static int mc_interception(struct vcpu_svm *svm)
1543 {
1544 return 1;
1545 }
1546
1547 static int shutdown_interception(struct vcpu_svm *svm)
1548 {
1549 struct kvm_run *kvm_run = svm->vcpu.run;
1550
1551 /*
1552 * VMCB is undefined after a SHUTDOWN intercept
1553 * so reinitialize it.
1554 */
1555 clear_page(svm->vmcb);
1556 init_vmcb(svm);
1557
1558 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1559 return 0;
1560 }
1561
1562 static int io_interception(struct vcpu_svm *svm)
1563 {
1564 struct kvm_vcpu *vcpu = &svm->vcpu;
1565 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1566 int size, in, string;
1567 unsigned port;
1568
1569 ++svm->vcpu.stat.io_exits;
1570 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1571 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1572 if (string || in)
1573 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
1574
1575 port = io_info >> 16;
1576 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1577 svm->next_rip = svm->vmcb->control.exit_info_2;
1578 skip_emulated_instruction(&svm->vcpu);
1579
1580 return kvm_fast_pio_out(vcpu, size, port);
1581 }
1582
1583 static int nmi_interception(struct vcpu_svm *svm)
1584 {
1585 return 1;
1586 }
1587
1588 static int intr_interception(struct vcpu_svm *svm)
1589 {
1590 ++svm->vcpu.stat.irq_exits;
1591 return 1;
1592 }
1593
1594 static int nop_on_interception(struct vcpu_svm *svm)
1595 {
1596 return 1;
1597 }
1598
1599 static int halt_interception(struct vcpu_svm *svm)
1600 {
1601 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1602 skip_emulated_instruction(&svm->vcpu);
1603 return kvm_emulate_halt(&svm->vcpu);
1604 }
1605
1606 static int vmmcall_interception(struct vcpu_svm *svm)
1607 {
1608 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1609 skip_emulated_instruction(&svm->vcpu);
1610 kvm_emulate_hypercall(&svm->vcpu);
1611 return 1;
1612 }
1613
1614 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1615 {
1616 struct vcpu_svm *svm = to_svm(vcpu);
1617
1618 return svm->nested.nested_cr3;
1619 }
1620
1621 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1622 unsigned long root)
1623 {
1624 struct vcpu_svm *svm = to_svm(vcpu);
1625
1626 svm->vmcb->control.nested_cr3 = root;
1627 force_new_asid(vcpu);
1628 }
1629
1630 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu)
1631 {
1632 struct vcpu_svm *svm = to_svm(vcpu);
1633
1634 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1635 svm->vmcb->control.exit_code_hi = 0;
1636 svm->vmcb->control.exit_info_1 = vcpu->arch.fault.error_code;
1637 svm->vmcb->control.exit_info_2 = vcpu->arch.fault.address;
1638
1639 nested_svm_vmexit(svm);
1640 }
1641
1642 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1643 {
1644 int r;
1645
1646 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1647
1648 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1649 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1650 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1651 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1652 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1653
1654 return r;
1655 }
1656
1657 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1658 {
1659 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1660 }
1661
1662 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1663 {
1664 if (!(svm->vcpu.arch.efer & EFER_SVME)
1665 || !is_paging(&svm->vcpu)) {
1666 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1667 return 1;
1668 }
1669
1670 if (svm->vmcb->save.cpl) {
1671 kvm_inject_gp(&svm->vcpu, 0);
1672 return 1;
1673 }
1674
1675 return 0;
1676 }
1677
1678 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1679 bool has_error_code, u32 error_code)
1680 {
1681 int vmexit;
1682
1683 if (!is_nested(svm))
1684 return 0;
1685
1686 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1687 svm->vmcb->control.exit_code_hi = 0;
1688 svm->vmcb->control.exit_info_1 = error_code;
1689 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1690
1691 vmexit = nested_svm_intercept(svm);
1692 if (vmexit == NESTED_EXIT_DONE)
1693 svm->nested.exit_required = true;
1694
1695 return vmexit;
1696 }
1697
1698 /* This function returns true if it is save to enable the irq window */
1699 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1700 {
1701 if (!is_nested(svm))
1702 return true;
1703
1704 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1705 return true;
1706
1707 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1708 return false;
1709
1710 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1711 svm->vmcb->control.exit_info_1 = 0;
1712 svm->vmcb->control.exit_info_2 = 0;
1713
1714 if (svm->nested.intercept & 1ULL) {
1715 /*
1716 * The #vmexit can't be emulated here directly because this
1717 * code path runs with irqs and preemtion disabled. A
1718 * #vmexit emulation might sleep. Only signal request for
1719 * the #vmexit here.
1720 */
1721 svm->nested.exit_required = true;
1722 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1723 return false;
1724 }
1725
1726 return true;
1727 }
1728
1729 /* This function returns true if it is save to enable the nmi window */
1730 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1731 {
1732 if (!is_nested(svm))
1733 return true;
1734
1735 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1736 return true;
1737
1738 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1739 svm->nested.exit_required = true;
1740
1741 return false;
1742 }
1743
1744 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1745 {
1746 struct page *page;
1747
1748 might_sleep();
1749
1750 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1751 if (is_error_page(page))
1752 goto error;
1753
1754 *_page = page;
1755
1756 return kmap(page);
1757
1758 error:
1759 kvm_release_page_clean(page);
1760 kvm_inject_gp(&svm->vcpu, 0);
1761
1762 return NULL;
1763 }
1764
1765 static void nested_svm_unmap(struct page *page)
1766 {
1767 kunmap(page);
1768 kvm_release_page_dirty(page);
1769 }
1770
1771 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1772 {
1773 unsigned port;
1774 u8 val, bit;
1775 u64 gpa;
1776
1777 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1778 return NESTED_EXIT_HOST;
1779
1780 port = svm->vmcb->control.exit_info_1 >> 16;
1781 gpa = svm->nested.vmcb_iopm + (port / 8);
1782 bit = port % 8;
1783 val = 0;
1784
1785 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1786 val &= (1 << bit);
1787
1788 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1789 }
1790
1791 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1792 {
1793 u32 offset, msr, value;
1794 int write, mask;
1795
1796 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1797 return NESTED_EXIT_HOST;
1798
1799 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1800 offset = svm_msrpm_offset(msr);
1801 write = svm->vmcb->control.exit_info_1 & 1;
1802 mask = 1 << ((2 * (msr & 0xf)) + write);
1803
1804 if (offset == MSR_INVALID)
1805 return NESTED_EXIT_DONE;
1806
1807 /* Offset is in 32 bit units but need in 8 bit units */
1808 offset *= 4;
1809
1810 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1811 return NESTED_EXIT_DONE;
1812
1813 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1814 }
1815
1816 static int nested_svm_exit_special(struct vcpu_svm *svm)
1817 {
1818 u32 exit_code = svm->vmcb->control.exit_code;
1819
1820 switch (exit_code) {
1821 case SVM_EXIT_INTR:
1822 case SVM_EXIT_NMI:
1823 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1824 return NESTED_EXIT_HOST;
1825 case SVM_EXIT_NPF:
1826 /* For now we are always handling NPFs when using them */
1827 if (npt_enabled)
1828 return NESTED_EXIT_HOST;
1829 break;
1830 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1831 /* When we're shadowing, trap PFs */
1832 if (!npt_enabled)
1833 return NESTED_EXIT_HOST;
1834 break;
1835 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1836 nm_interception(svm);
1837 break;
1838 default:
1839 break;
1840 }
1841
1842 return NESTED_EXIT_CONTINUE;
1843 }
1844
1845 /*
1846 * If this function returns true, this #vmexit was already handled
1847 */
1848 static int nested_svm_intercept(struct vcpu_svm *svm)
1849 {
1850 u32 exit_code = svm->vmcb->control.exit_code;
1851 int vmexit = NESTED_EXIT_HOST;
1852
1853 switch (exit_code) {
1854 case SVM_EXIT_MSR:
1855 vmexit = nested_svm_exit_handled_msr(svm);
1856 break;
1857 case SVM_EXIT_IOIO:
1858 vmexit = nested_svm_intercept_ioio(svm);
1859 break;
1860 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1861 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1862 if (svm->nested.intercept_cr_read & cr_bits)
1863 vmexit = NESTED_EXIT_DONE;
1864 break;
1865 }
1866 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1867 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1868 if (svm->nested.intercept_cr_write & cr_bits)
1869 vmexit = NESTED_EXIT_DONE;
1870 break;
1871 }
1872 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1873 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1874 if (svm->nested.intercept_dr_read & dr_bits)
1875 vmexit = NESTED_EXIT_DONE;
1876 break;
1877 }
1878 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1879 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1880 if (svm->nested.intercept_dr_write & dr_bits)
1881 vmexit = NESTED_EXIT_DONE;
1882 break;
1883 }
1884 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1885 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1886 if (svm->nested.intercept_exceptions & excp_bits)
1887 vmexit = NESTED_EXIT_DONE;
1888 break;
1889 }
1890 case SVM_EXIT_ERR: {
1891 vmexit = NESTED_EXIT_DONE;
1892 break;
1893 }
1894 default: {
1895 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1896 if (svm->nested.intercept & exit_bits)
1897 vmexit = NESTED_EXIT_DONE;
1898 }
1899 }
1900
1901 return vmexit;
1902 }
1903
1904 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1905 {
1906 int vmexit;
1907
1908 vmexit = nested_svm_intercept(svm);
1909
1910 if (vmexit == NESTED_EXIT_DONE)
1911 nested_svm_vmexit(svm);
1912
1913 return vmexit;
1914 }
1915
1916 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1917 {
1918 struct vmcb_control_area *dst = &dst_vmcb->control;
1919 struct vmcb_control_area *from = &from_vmcb->control;
1920
1921 dst->intercept_cr_read = from->intercept_cr_read;
1922 dst->intercept_cr_write = from->intercept_cr_write;
1923 dst->intercept_dr_read = from->intercept_dr_read;
1924 dst->intercept_dr_write = from->intercept_dr_write;
1925 dst->intercept_exceptions = from->intercept_exceptions;
1926 dst->intercept = from->intercept;
1927 dst->iopm_base_pa = from->iopm_base_pa;
1928 dst->msrpm_base_pa = from->msrpm_base_pa;
1929 dst->tsc_offset = from->tsc_offset;
1930 dst->asid = from->asid;
1931 dst->tlb_ctl = from->tlb_ctl;
1932 dst->int_ctl = from->int_ctl;
1933 dst->int_vector = from->int_vector;
1934 dst->int_state = from->int_state;
1935 dst->exit_code = from->exit_code;
1936 dst->exit_code_hi = from->exit_code_hi;
1937 dst->exit_info_1 = from->exit_info_1;
1938 dst->exit_info_2 = from->exit_info_2;
1939 dst->exit_int_info = from->exit_int_info;
1940 dst->exit_int_info_err = from->exit_int_info_err;
1941 dst->nested_ctl = from->nested_ctl;
1942 dst->event_inj = from->event_inj;
1943 dst->event_inj_err = from->event_inj_err;
1944 dst->nested_cr3 = from->nested_cr3;
1945 dst->lbr_ctl = from->lbr_ctl;
1946 }
1947
1948 static int nested_svm_vmexit(struct vcpu_svm *svm)
1949 {
1950 struct vmcb *nested_vmcb;
1951 struct vmcb *hsave = svm->nested.hsave;
1952 struct vmcb *vmcb = svm->vmcb;
1953 struct page *page;
1954
1955 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1956 vmcb->control.exit_info_1,
1957 vmcb->control.exit_info_2,
1958 vmcb->control.exit_int_info,
1959 vmcb->control.exit_int_info_err);
1960
1961 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1962 if (!nested_vmcb)
1963 return 1;
1964
1965 /* Exit nested SVM mode */
1966 svm->nested.vmcb = 0;
1967
1968 /* Give the current vmcb to the guest */
1969 disable_gif(svm);
1970
1971 nested_vmcb->save.es = vmcb->save.es;
1972 nested_vmcb->save.cs = vmcb->save.cs;
1973 nested_vmcb->save.ss = vmcb->save.ss;
1974 nested_vmcb->save.ds = vmcb->save.ds;
1975 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1976 nested_vmcb->save.idtr = vmcb->save.idtr;
1977 nested_vmcb->save.efer = svm->vcpu.arch.efer;
1978 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
1979 nested_vmcb->save.cr3 = svm->vcpu.arch.cr3;
1980 nested_vmcb->save.cr2 = vmcb->save.cr2;
1981 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
1982 nested_vmcb->save.rflags = vmcb->save.rflags;
1983 nested_vmcb->save.rip = vmcb->save.rip;
1984 nested_vmcb->save.rsp = vmcb->save.rsp;
1985 nested_vmcb->save.rax = vmcb->save.rax;
1986 nested_vmcb->save.dr7 = vmcb->save.dr7;
1987 nested_vmcb->save.dr6 = vmcb->save.dr6;
1988 nested_vmcb->save.cpl = vmcb->save.cpl;
1989
1990 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1991 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1992 nested_vmcb->control.int_state = vmcb->control.int_state;
1993 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1994 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1995 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1996 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1997 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1998 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1999 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2000
2001 /*
2002 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2003 * to make sure that we do not lose injected events. So check event_inj
2004 * here and copy it to exit_int_info if it is valid.
2005 * Exit_int_info and event_inj can't be both valid because the case
2006 * below only happens on a VMRUN instruction intercept which has
2007 * no valid exit_int_info set.
2008 */
2009 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2010 struct vmcb_control_area *nc = &nested_vmcb->control;
2011
2012 nc->exit_int_info = vmcb->control.event_inj;
2013 nc->exit_int_info_err = vmcb->control.event_inj_err;
2014 }
2015
2016 nested_vmcb->control.tlb_ctl = 0;
2017 nested_vmcb->control.event_inj = 0;
2018 nested_vmcb->control.event_inj_err = 0;
2019
2020 /* We always set V_INTR_MASKING and remember the old value in hflags */
2021 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2022 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2023
2024 /* Restore the original control entries */
2025 copy_vmcb_control_area(vmcb, hsave);
2026
2027 kvm_clear_exception_queue(&svm->vcpu);
2028 kvm_clear_interrupt_queue(&svm->vcpu);
2029
2030 svm->nested.nested_cr3 = 0;
2031
2032 /* Restore selected save entries */
2033 svm->vmcb->save.es = hsave->save.es;
2034 svm->vmcb->save.cs = hsave->save.cs;
2035 svm->vmcb->save.ss = hsave->save.ss;
2036 svm->vmcb->save.ds = hsave->save.ds;
2037 svm->vmcb->save.gdtr = hsave->save.gdtr;
2038 svm->vmcb->save.idtr = hsave->save.idtr;
2039 svm->vmcb->save.rflags = hsave->save.rflags;
2040 svm_set_efer(&svm->vcpu, hsave->save.efer);
2041 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2042 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2043 if (npt_enabled) {
2044 svm->vmcb->save.cr3 = hsave->save.cr3;
2045 svm->vcpu.arch.cr3 = hsave->save.cr3;
2046 } else {
2047 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2048 }
2049 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2050 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2051 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2052 svm->vmcb->save.dr7 = 0;
2053 svm->vmcb->save.cpl = 0;
2054 svm->vmcb->control.exit_int_info = 0;
2055
2056 nested_svm_unmap(page);
2057
2058 nested_svm_uninit_mmu_context(&svm->vcpu);
2059 kvm_mmu_reset_context(&svm->vcpu);
2060 kvm_mmu_load(&svm->vcpu);
2061
2062 return 0;
2063 }
2064
2065 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2066 {
2067 /*
2068 * This function merges the msr permission bitmaps of kvm and the
2069 * nested vmcb. It is omptimized in that it only merges the parts where
2070 * the kvm msr permission bitmap may contain zero bits
2071 */
2072 int i;
2073
2074 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2075 return true;
2076
2077 for (i = 0; i < MSRPM_OFFSETS; i++) {
2078 u32 value, p;
2079 u64 offset;
2080
2081 if (msrpm_offsets[i] == 0xffffffff)
2082 break;
2083
2084 p = msrpm_offsets[i];
2085 offset = svm->nested.vmcb_msrpm + (p * 4);
2086
2087 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2088 return false;
2089
2090 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2091 }
2092
2093 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2094
2095 return true;
2096 }
2097
2098 static bool nested_vmcb_checks(struct vmcb *vmcb)
2099 {
2100 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2101 return false;
2102
2103 if (vmcb->control.asid == 0)
2104 return false;
2105
2106 if (vmcb->control.nested_ctl && !npt_enabled)
2107 return false;
2108
2109 return true;
2110 }
2111
2112 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2113 {
2114 struct vmcb *nested_vmcb;
2115 struct vmcb *hsave = svm->nested.hsave;
2116 struct vmcb *vmcb = svm->vmcb;
2117 struct page *page;
2118 u64 vmcb_gpa;
2119
2120 vmcb_gpa = svm->vmcb->save.rax;
2121
2122 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2123 if (!nested_vmcb)
2124 return false;
2125
2126 if (!nested_vmcb_checks(nested_vmcb)) {
2127 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2128 nested_vmcb->control.exit_code_hi = 0;
2129 nested_vmcb->control.exit_info_1 = 0;
2130 nested_vmcb->control.exit_info_2 = 0;
2131
2132 nested_svm_unmap(page);
2133
2134 return false;
2135 }
2136
2137 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2138 nested_vmcb->save.rip,
2139 nested_vmcb->control.int_ctl,
2140 nested_vmcb->control.event_inj,
2141 nested_vmcb->control.nested_ctl);
2142
2143 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
2144 nested_vmcb->control.intercept_cr_write,
2145 nested_vmcb->control.intercept_exceptions,
2146 nested_vmcb->control.intercept);
2147
2148 /* Clear internal status */
2149 kvm_clear_exception_queue(&svm->vcpu);
2150 kvm_clear_interrupt_queue(&svm->vcpu);
2151
2152 /*
2153 * Save the old vmcb, so we don't need to pick what we save, but can
2154 * restore everything when a VMEXIT occurs
2155 */
2156 hsave->save.es = vmcb->save.es;
2157 hsave->save.cs = vmcb->save.cs;
2158 hsave->save.ss = vmcb->save.ss;
2159 hsave->save.ds = vmcb->save.ds;
2160 hsave->save.gdtr = vmcb->save.gdtr;
2161 hsave->save.idtr = vmcb->save.idtr;
2162 hsave->save.efer = svm->vcpu.arch.efer;
2163 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2164 hsave->save.cr4 = svm->vcpu.arch.cr4;
2165 hsave->save.rflags = vmcb->save.rflags;
2166 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2167 hsave->save.rsp = vmcb->save.rsp;
2168 hsave->save.rax = vmcb->save.rax;
2169 if (npt_enabled)
2170 hsave->save.cr3 = vmcb->save.cr3;
2171 else
2172 hsave->save.cr3 = svm->vcpu.arch.cr3;
2173
2174 copy_vmcb_control_area(hsave, vmcb);
2175
2176 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2177 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2178 else
2179 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2180
2181 if (nested_vmcb->control.nested_ctl) {
2182 kvm_mmu_unload(&svm->vcpu);
2183 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2184 nested_svm_init_mmu_context(&svm->vcpu);
2185 }
2186
2187 /* Load the nested guest state */
2188 svm->vmcb->save.es = nested_vmcb->save.es;
2189 svm->vmcb->save.cs = nested_vmcb->save.cs;
2190 svm->vmcb->save.ss = nested_vmcb->save.ss;
2191 svm->vmcb->save.ds = nested_vmcb->save.ds;
2192 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2193 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2194 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2195 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2196 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2197 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2198 if (npt_enabled) {
2199 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2200 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2201 } else
2202 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2203
2204 /* Guest paging mode is active - reset mmu */
2205 kvm_mmu_reset_context(&svm->vcpu);
2206
2207 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2208 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2209 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2210 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2211
2212 /* In case we don't even reach vcpu_run, the fields are not updated */
2213 svm->vmcb->save.rax = nested_vmcb->save.rax;
2214 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2215 svm->vmcb->save.rip = nested_vmcb->save.rip;
2216 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2217 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2218 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2219
2220 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2221 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2222
2223 /* cache intercepts */
2224 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
2225 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
2226 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
2227 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
2228 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2229 svm->nested.intercept = nested_vmcb->control.intercept;
2230
2231 force_new_asid(&svm->vcpu);
2232 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2233 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2234 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2235 else
2236 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2237
2238 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2239 /* We only want the cr8 intercept bits of the guest */
2240 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2241 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2242 }
2243
2244 /* We don't want to see VMMCALLs from a nested guest */
2245 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2246
2247 /*
2248 * We don't want a nested guest to be more powerful than the guest, so
2249 * all intercepts are ORed
2250 */
2251 svm->vmcb->control.intercept_cr_read |=
2252 nested_vmcb->control.intercept_cr_read;
2253 svm->vmcb->control.intercept_cr_write |=
2254 nested_vmcb->control.intercept_cr_write;
2255 svm->vmcb->control.intercept_dr_read |=
2256 nested_vmcb->control.intercept_dr_read;
2257 svm->vmcb->control.intercept_dr_write |=
2258 nested_vmcb->control.intercept_dr_write;
2259 svm->vmcb->control.intercept_exceptions |=
2260 nested_vmcb->control.intercept_exceptions;
2261
2262 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2263
2264 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2265 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2266 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2267 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2268 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2269 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2270
2271 nested_svm_unmap(page);
2272
2273 /* nested_vmcb is our indicator if nested SVM is activated */
2274 svm->nested.vmcb = vmcb_gpa;
2275
2276 enable_gif(svm);
2277
2278 return true;
2279 }
2280
2281 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2282 {
2283 to_vmcb->save.fs = from_vmcb->save.fs;
2284 to_vmcb->save.gs = from_vmcb->save.gs;
2285 to_vmcb->save.tr = from_vmcb->save.tr;
2286 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2287 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2288 to_vmcb->save.star = from_vmcb->save.star;
2289 to_vmcb->save.lstar = from_vmcb->save.lstar;
2290 to_vmcb->save.cstar = from_vmcb->save.cstar;
2291 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2292 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2293 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2294 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2295 }
2296
2297 static int vmload_interception(struct vcpu_svm *svm)
2298 {
2299 struct vmcb *nested_vmcb;
2300 struct page *page;
2301
2302 if (nested_svm_check_permissions(svm))
2303 return 1;
2304
2305 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2306 skip_emulated_instruction(&svm->vcpu);
2307
2308 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2309 if (!nested_vmcb)
2310 return 1;
2311
2312 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2313 nested_svm_unmap(page);
2314
2315 return 1;
2316 }
2317
2318 static int vmsave_interception(struct vcpu_svm *svm)
2319 {
2320 struct vmcb *nested_vmcb;
2321 struct page *page;
2322
2323 if (nested_svm_check_permissions(svm))
2324 return 1;
2325
2326 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2327 skip_emulated_instruction(&svm->vcpu);
2328
2329 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2330 if (!nested_vmcb)
2331 return 1;
2332
2333 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2334 nested_svm_unmap(page);
2335
2336 return 1;
2337 }
2338
2339 static int vmrun_interception(struct vcpu_svm *svm)
2340 {
2341 if (nested_svm_check_permissions(svm))
2342 return 1;
2343
2344 /* Save rip after vmrun instruction */
2345 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2346
2347 if (!nested_svm_vmrun(svm))
2348 return 1;
2349
2350 if (!nested_svm_vmrun_msrpm(svm))
2351 goto failed;
2352
2353 return 1;
2354
2355 failed:
2356
2357 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2358 svm->vmcb->control.exit_code_hi = 0;
2359 svm->vmcb->control.exit_info_1 = 0;
2360 svm->vmcb->control.exit_info_2 = 0;
2361
2362 nested_svm_vmexit(svm);
2363
2364 return 1;
2365 }
2366
2367 static int stgi_interception(struct vcpu_svm *svm)
2368 {
2369 if (nested_svm_check_permissions(svm))
2370 return 1;
2371
2372 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2373 skip_emulated_instruction(&svm->vcpu);
2374
2375 enable_gif(svm);
2376
2377 return 1;
2378 }
2379
2380 static int clgi_interception(struct vcpu_svm *svm)
2381 {
2382 if (nested_svm_check_permissions(svm))
2383 return 1;
2384
2385 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2386 skip_emulated_instruction(&svm->vcpu);
2387
2388 disable_gif(svm);
2389
2390 /* After a CLGI no interrupts should come */
2391 svm_clear_vintr(svm);
2392 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2393
2394 return 1;
2395 }
2396
2397 static int invlpga_interception(struct vcpu_svm *svm)
2398 {
2399 struct kvm_vcpu *vcpu = &svm->vcpu;
2400
2401 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2402 vcpu->arch.regs[VCPU_REGS_RAX]);
2403
2404 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2405 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2406
2407 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2408 skip_emulated_instruction(&svm->vcpu);
2409 return 1;
2410 }
2411
2412 static int skinit_interception(struct vcpu_svm *svm)
2413 {
2414 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2415
2416 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2417 return 1;
2418 }
2419
2420 static int invalid_op_interception(struct vcpu_svm *svm)
2421 {
2422 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2423 return 1;
2424 }
2425
2426 static int task_switch_interception(struct vcpu_svm *svm)
2427 {
2428 u16 tss_selector;
2429 int reason;
2430 int int_type = svm->vmcb->control.exit_int_info &
2431 SVM_EXITINTINFO_TYPE_MASK;
2432 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2433 uint32_t type =
2434 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2435 uint32_t idt_v =
2436 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2437 bool has_error_code = false;
2438 u32 error_code = 0;
2439
2440 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2441
2442 if (svm->vmcb->control.exit_info_2 &
2443 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2444 reason = TASK_SWITCH_IRET;
2445 else if (svm->vmcb->control.exit_info_2 &
2446 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2447 reason = TASK_SWITCH_JMP;
2448 else if (idt_v)
2449 reason = TASK_SWITCH_GATE;
2450 else
2451 reason = TASK_SWITCH_CALL;
2452
2453 if (reason == TASK_SWITCH_GATE) {
2454 switch (type) {
2455 case SVM_EXITINTINFO_TYPE_NMI:
2456 svm->vcpu.arch.nmi_injected = false;
2457 break;
2458 case SVM_EXITINTINFO_TYPE_EXEPT:
2459 if (svm->vmcb->control.exit_info_2 &
2460 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2461 has_error_code = true;
2462 error_code =
2463 (u32)svm->vmcb->control.exit_info_2;
2464 }
2465 kvm_clear_exception_queue(&svm->vcpu);
2466 break;
2467 case SVM_EXITINTINFO_TYPE_INTR:
2468 kvm_clear_interrupt_queue(&svm->vcpu);
2469 break;
2470 default:
2471 break;
2472 }
2473 }
2474
2475 if (reason != TASK_SWITCH_GATE ||
2476 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2477 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2478 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2479 skip_emulated_instruction(&svm->vcpu);
2480
2481 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2482 has_error_code, error_code) == EMULATE_FAIL) {
2483 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2484 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2485 svm->vcpu.run->internal.ndata = 0;
2486 return 0;
2487 }
2488 return 1;
2489 }
2490
2491 static int cpuid_interception(struct vcpu_svm *svm)
2492 {
2493 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2494 kvm_emulate_cpuid(&svm->vcpu);
2495 return 1;
2496 }
2497
2498 static int iret_interception(struct vcpu_svm *svm)
2499 {
2500 ++svm->vcpu.stat.nmi_window_exits;
2501 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2502 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2503 return 1;
2504 }
2505
2506 static int invlpg_interception(struct vcpu_svm *svm)
2507 {
2508 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2509 }
2510
2511 static int emulate_on_interception(struct vcpu_svm *svm)
2512 {
2513 return emulate_instruction(&svm->vcpu, 0, 0, 0) == EMULATE_DONE;
2514 }
2515
2516 static int cr0_write_interception(struct vcpu_svm *svm)
2517 {
2518 struct kvm_vcpu *vcpu = &svm->vcpu;
2519 int r;
2520
2521 r = emulate_instruction(&svm->vcpu, 0, 0, 0);
2522
2523 if (svm->nested.vmexit_rip) {
2524 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2525 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2526 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2527 svm->nested.vmexit_rip = 0;
2528 }
2529
2530 return r == EMULATE_DONE;
2531 }
2532
2533 static int cr8_write_interception(struct vcpu_svm *svm)
2534 {
2535 struct kvm_run *kvm_run = svm->vcpu.run;
2536
2537 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2538 /* instruction emulation calls kvm_set_cr8() */
2539 emulate_instruction(&svm->vcpu, 0, 0, 0);
2540 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2541 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2542 return 1;
2543 }
2544 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2545 return 1;
2546 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2547 return 0;
2548 }
2549
2550 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2551 {
2552 struct vcpu_svm *svm = to_svm(vcpu);
2553
2554 switch (ecx) {
2555 case MSR_IA32_TSC: {
2556 u64 tsc_offset;
2557
2558 if (is_nested(svm))
2559 tsc_offset = svm->nested.hsave->control.tsc_offset;
2560 else
2561 tsc_offset = svm->vmcb->control.tsc_offset;
2562
2563 *data = tsc_offset + native_read_tsc();
2564 break;
2565 }
2566 case MSR_STAR:
2567 *data = svm->vmcb->save.star;
2568 break;
2569 #ifdef CONFIG_X86_64
2570 case MSR_LSTAR:
2571 *data = svm->vmcb->save.lstar;
2572 break;
2573 case MSR_CSTAR:
2574 *data = svm->vmcb->save.cstar;
2575 break;
2576 case MSR_KERNEL_GS_BASE:
2577 *data = svm->vmcb->save.kernel_gs_base;
2578 break;
2579 case MSR_SYSCALL_MASK:
2580 *data = svm->vmcb->save.sfmask;
2581 break;
2582 #endif
2583 case MSR_IA32_SYSENTER_CS:
2584 *data = svm->vmcb->save.sysenter_cs;
2585 break;
2586 case MSR_IA32_SYSENTER_EIP:
2587 *data = svm->sysenter_eip;
2588 break;
2589 case MSR_IA32_SYSENTER_ESP:
2590 *data = svm->sysenter_esp;
2591 break;
2592 /*
2593 * Nobody will change the following 5 values in the VMCB so we can
2594 * safely return them on rdmsr. They will always be 0 until LBRV is
2595 * implemented.
2596 */
2597 case MSR_IA32_DEBUGCTLMSR:
2598 *data = svm->vmcb->save.dbgctl;
2599 break;
2600 case MSR_IA32_LASTBRANCHFROMIP:
2601 *data = svm->vmcb->save.br_from;
2602 break;
2603 case MSR_IA32_LASTBRANCHTOIP:
2604 *data = svm->vmcb->save.br_to;
2605 break;
2606 case MSR_IA32_LASTINTFROMIP:
2607 *data = svm->vmcb->save.last_excp_from;
2608 break;
2609 case MSR_IA32_LASTINTTOIP:
2610 *data = svm->vmcb->save.last_excp_to;
2611 break;
2612 case MSR_VM_HSAVE_PA:
2613 *data = svm->nested.hsave_msr;
2614 break;
2615 case MSR_VM_CR:
2616 *data = svm->nested.vm_cr_msr;
2617 break;
2618 case MSR_IA32_UCODE_REV:
2619 *data = 0x01000065;
2620 break;
2621 default:
2622 return kvm_get_msr_common(vcpu, ecx, data);
2623 }
2624 return 0;
2625 }
2626
2627 static int rdmsr_interception(struct vcpu_svm *svm)
2628 {
2629 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2630 u64 data;
2631
2632 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2633 trace_kvm_msr_read_ex(ecx);
2634 kvm_inject_gp(&svm->vcpu, 0);
2635 } else {
2636 trace_kvm_msr_read(ecx, data);
2637
2638 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2639 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2640 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2641 skip_emulated_instruction(&svm->vcpu);
2642 }
2643 return 1;
2644 }
2645
2646 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2647 {
2648 struct vcpu_svm *svm = to_svm(vcpu);
2649 int svm_dis, chg_mask;
2650
2651 if (data & ~SVM_VM_CR_VALID_MASK)
2652 return 1;
2653
2654 chg_mask = SVM_VM_CR_VALID_MASK;
2655
2656 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2657 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2658
2659 svm->nested.vm_cr_msr &= ~chg_mask;
2660 svm->nested.vm_cr_msr |= (data & chg_mask);
2661
2662 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2663
2664 /* check for svm_disable while efer.svme is set */
2665 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2666 return 1;
2667
2668 return 0;
2669 }
2670
2671 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2672 {
2673 struct vcpu_svm *svm = to_svm(vcpu);
2674
2675 switch (ecx) {
2676 case MSR_IA32_TSC:
2677 kvm_write_tsc(vcpu, data);
2678 break;
2679 case MSR_STAR:
2680 svm->vmcb->save.star = data;
2681 break;
2682 #ifdef CONFIG_X86_64
2683 case MSR_LSTAR:
2684 svm->vmcb->save.lstar = data;
2685 break;
2686 case MSR_CSTAR:
2687 svm->vmcb->save.cstar = data;
2688 break;
2689 case MSR_KERNEL_GS_BASE:
2690 svm->vmcb->save.kernel_gs_base = data;
2691 break;
2692 case MSR_SYSCALL_MASK:
2693 svm->vmcb->save.sfmask = data;
2694 break;
2695 #endif
2696 case MSR_IA32_SYSENTER_CS:
2697 svm->vmcb->save.sysenter_cs = data;
2698 break;
2699 case MSR_IA32_SYSENTER_EIP:
2700 svm->sysenter_eip = data;
2701 svm->vmcb->save.sysenter_eip = data;
2702 break;
2703 case MSR_IA32_SYSENTER_ESP:
2704 svm->sysenter_esp = data;
2705 svm->vmcb->save.sysenter_esp = data;
2706 break;
2707 case MSR_IA32_DEBUGCTLMSR:
2708 if (!svm_has(SVM_FEATURE_LBRV)) {
2709 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2710 __func__, data);
2711 break;
2712 }
2713 if (data & DEBUGCTL_RESERVED_BITS)
2714 return 1;
2715
2716 svm->vmcb->save.dbgctl = data;
2717 if (data & (1ULL<<0))
2718 svm_enable_lbrv(svm);
2719 else
2720 svm_disable_lbrv(svm);
2721 break;
2722 case MSR_VM_HSAVE_PA:
2723 svm->nested.hsave_msr = data;
2724 break;
2725 case MSR_VM_CR:
2726 return svm_set_vm_cr(vcpu, data);
2727 case MSR_VM_IGNNE:
2728 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2729 break;
2730 default:
2731 return kvm_set_msr_common(vcpu, ecx, data);
2732 }
2733 return 0;
2734 }
2735
2736 static int wrmsr_interception(struct vcpu_svm *svm)
2737 {
2738 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2739 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2740 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2741
2742
2743 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2744 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2745 trace_kvm_msr_write_ex(ecx, data);
2746 kvm_inject_gp(&svm->vcpu, 0);
2747 } else {
2748 trace_kvm_msr_write(ecx, data);
2749 skip_emulated_instruction(&svm->vcpu);
2750 }
2751 return 1;
2752 }
2753
2754 static int msr_interception(struct vcpu_svm *svm)
2755 {
2756 if (svm->vmcb->control.exit_info_1)
2757 return wrmsr_interception(svm);
2758 else
2759 return rdmsr_interception(svm);
2760 }
2761
2762 static int interrupt_window_interception(struct vcpu_svm *svm)
2763 {
2764 struct kvm_run *kvm_run = svm->vcpu.run;
2765
2766 svm_clear_vintr(svm);
2767 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2768 /*
2769 * If the user space waits to inject interrupts, exit as soon as
2770 * possible
2771 */
2772 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2773 kvm_run->request_interrupt_window &&
2774 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2775 ++svm->vcpu.stat.irq_window_exits;
2776 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2777 return 0;
2778 }
2779
2780 return 1;
2781 }
2782
2783 static int pause_interception(struct vcpu_svm *svm)
2784 {
2785 kvm_vcpu_on_spin(&(svm->vcpu));
2786 return 1;
2787 }
2788
2789 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2790 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2791 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2792 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2793 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2794 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
2795 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
2796 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2797 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2798 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2799 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2800 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2801 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2802 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2803 [SVM_EXIT_READ_DR4] = emulate_on_interception,
2804 [SVM_EXIT_READ_DR5] = emulate_on_interception,
2805 [SVM_EXIT_READ_DR6] = emulate_on_interception,
2806 [SVM_EXIT_READ_DR7] = emulate_on_interception,
2807 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2808 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2809 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2810 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2811 [SVM_EXIT_WRITE_DR4] = emulate_on_interception,
2812 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2813 [SVM_EXIT_WRITE_DR6] = emulate_on_interception,
2814 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2815 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2816 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2817 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2818 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2819 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2820 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2821 [SVM_EXIT_INTR] = intr_interception,
2822 [SVM_EXIT_NMI] = nmi_interception,
2823 [SVM_EXIT_SMI] = nop_on_interception,
2824 [SVM_EXIT_INIT] = nop_on_interception,
2825 [SVM_EXIT_VINTR] = interrupt_window_interception,
2826 [SVM_EXIT_CPUID] = cpuid_interception,
2827 [SVM_EXIT_IRET] = iret_interception,
2828 [SVM_EXIT_INVD] = emulate_on_interception,
2829 [SVM_EXIT_PAUSE] = pause_interception,
2830 [SVM_EXIT_HLT] = halt_interception,
2831 [SVM_EXIT_INVLPG] = invlpg_interception,
2832 [SVM_EXIT_INVLPGA] = invlpga_interception,
2833 [SVM_EXIT_IOIO] = io_interception,
2834 [SVM_EXIT_MSR] = msr_interception,
2835 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2836 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2837 [SVM_EXIT_VMRUN] = vmrun_interception,
2838 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2839 [SVM_EXIT_VMLOAD] = vmload_interception,
2840 [SVM_EXIT_VMSAVE] = vmsave_interception,
2841 [SVM_EXIT_STGI] = stgi_interception,
2842 [SVM_EXIT_CLGI] = clgi_interception,
2843 [SVM_EXIT_SKINIT] = skinit_interception,
2844 [SVM_EXIT_WBINVD] = emulate_on_interception,
2845 [SVM_EXIT_MONITOR] = invalid_op_interception,
2846 [SVM_EXIT_MWAIT] = invalid_op_interception,
2847 [SVM_EXIT_NPF] = pf_interception,
2848 };
2849
2850 void dump_vmcb(struct kvm_vcpu *vcpu)
2851 {
2852 struct vcpu_svm *svm = to_svm(vcpu);
2853 struct vmcb_control_area *control = &svm->vmcb->control;
2854 struct vmcb_save_area *save = &svm->vmcb->save;
2855
2856 pr_err("VMCB Control Area:\n");
2857 pr_err("cr_read: %04x\n", control->intercept_cr_read);
2858 pr_err("cr_write: %04x\n", control->intercept_cr_write);
2859 pr_err("dr_read: %04x\n", control->intercept_dr_read);
2860 pr_err("dr_write: %04x\n", control->intercept_dr_write);
2861 pr_err("exceptions: %08x\n", control->intercept_exceptions);
2862 pr_err("intercepts: %016llx\n", control->intercept);
2863 pr_err("pause filter count: %d\n", control->pause_filter_count);
2864 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
2865 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
2866 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
2867 pr_err("asid: %d\n", control->asid);
2868 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
2869 pr_err("int_ctl: %08x\n", control->int_ctl);
2870 pr_err("int_vector: %08x\n", control->int_vector);
2871 pr_err("int_state: %08x\n", control->int_state);
2872 pr_err("exit_code: %08x\n", control->exit_code);
2873 pr_err("exit_info1: %016llx\n", control->exit_info_1);
2874 pr_err("exit_info2: %016llx\n", control->exit_info_2);
2875 pr_err("exit_int_info: %08x\n", control->exit_int_info);
2876 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
2877 pr_err("nested_ctl: %lld\n", control->nested_ctl);
2878 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
2879 pr_err("event_inj: %08x\n", control->event_inj);
2880 pr_err("event_inj_err: %08x\n", control->event_inj_err);
2881 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
2882 pr_err("next_rip: %016llx\n", control->next_rip);
2883 pr_err("VMCB State Save Area:\n");
2884 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2885 save->es.selector, save->es.attrib,
2886 save->es.limit, save->es.base);
2887 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2888 save->cs.selector, save->cs.attrib,
2889 save->cs.limit, save->cs.base);
2890 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2891 save->ss.selector, save->ss.attrib,
2892 save->ss.limit, save->ss.base);
2893 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2894 save->ds.selector, save->ds.attrib,
2895 save->ds.limit, save->ds.base);
2896 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2897 save->fs.selector, save->fs.attrib,
2898 save->fs.limit, save->fs.base);
2899 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2900 save->gs.selector, save->gs.attrib,
2901 save->gs.limit, save->gs.base);
2902 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2903 save->gdtr.selector, save->gdtr.attrib,
2904 save->gdtr.limit, save->gdtr.base);
2905 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2906 save->ldtr.selector, save->ldtr.attrib,
2907 save->ldtr.limit, save->ldtr.base);
2908 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2909 save->idtr.selector, save->idtr.attrib,
2910 save->idtr.limit, save->idtr.base);
2911 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2912 save->tr.selector, save->tr.attrib,
2913 save->tr.limit, save->tr.base);
2914 pr_err("cpl: %d efer: %016llx\n",
2915 save->cpl, save->efer);
2916 pr_err("cr0: %016llx cr2: %016llx\n",
2917 save->cr0, save->cr2);
2918 pr_err("cr3: %016llx cr4: %016llx\n",
2919 save->cr3, save->cr4);
2920 pr_err("dr6: %016llx dr7: %016llx\n",
2921 save->dr6, save->dr7);
2922 pr_err("rip: %016llx rflags: %016llx\n",
2923 save->rip, save->rflags);
2924 pr_err("rsp: %016llx rax: %016llx\n",
2925 save->rsp, save->rax);
2926 pr_err("star: %016llx lstar: %016llx\n",
2927 save->star, save->lstar);
2928 pr_err("cstar: %016llx sfmask: %016llx\n",
2929 save->cstar, save->sfmask);
2930 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2931 save->kernel_gs_base, save->sysenter_cs);
2932 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2933 save->sysenter_esp, save->sysenter_eip);
2934 pr_err("gpat: %016llx dbgctl: %016llx\n",
2935 save->g_pat, save->dbgctl);
2936 pr_err("br_from: %016llx br_to: %016llx\n",
2937 save->br_from, save->br_to);
2938 pr_err("excp_from: %016llx excp_to: %016llx\n",
2939 save->last_excp_from, save->last_excp_to);
2940
2941 }
2942
2943 static int handle_exit(struct kvm_vcpu *vcpu)
2944 {
2945 struct vcpu_svm *svm = to_svm(vcpu);
2946 struct kvm_run *kvm_run = vcpu->run;
2947 u32 exit_code = svm->vmcb->control.exit_code;
2948
2949 trace_kvm_exit(exit_code, vcpu);
2950
2951 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2952 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2953 if (npt_enabled)
2954 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2955
2956 if (unlikely(svm->nested.exit_required)) {
2957 nested_svm_vmexit(svm);
2958 svm->nested.exit_required = false;
2959
2960 return 1;
2961 }
2962
2963 if (is_nested(svm)) {
2964 int vmexit;
2965
2966 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2967 svm->vmcb->control.exit_info_1,
2968 svm->vmcb->control.exit_info_2,
2969 svm->vmcb->control.exit_int_info,
2970 svm->vmcb->control.exit_int_info_err);
2971
2972 vmexit = nested_svm_exit_special(svm);
2973
2974 if (vmexit == NESTED_EXIT_CONTINUE)
2975 vmexit = nested_svm_exit_handled(svm);
2976
2977 if (vmexit == NESTED_EXIT_DONE)
2978 return 1;
2979 }
2980
2981 svm_complete_interrupts(svm);
2982
2983 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2984 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2985 kvm_run->fail_entry.hardware_entry_failure_reason
2986 = svm->vmcb->control.exit_code;
2987 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2988 dump_vmcb(vcpu);
2989 return 0;
2990 }
2991
2992 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2993 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2994 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2995 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2996 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2997 "exit_code 0x%x\n",
2998 __func__, svm->vmcb->control.exit_int_info,
2999 exit_code);
3000
3001 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3002 || !svm_exit_handlers[exit_code]) {
3003 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3004 kvm_run->hw.hardware_exit_reason = exit_code;
3005 return 0;
3006 }
3007
3008 return svm_exit_handlers[exit_code](svm);
3009 }
3010
3011 static void reload_tss(struct kvm_vcpu *vcpu)
3012 {
3013 int cpu = raw_smp_processor_id();
3014
3015 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3016 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3017 load_TR_desc();
3018 }
3019
3020 static void pre_svm_run(struct vcpu_svm *svm)
3021 {
3022 int cpu = raw_smp_processor_id();
3023
3024 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3025
3026 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3027 /* FIXME: handle wraparound of asid_generation */
3028 if (svm->asid_generation != sd->asid_generation)
3029 new_asid(svm, sd);
3030 }
3031
3032 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3033 {
3034 struct vcpu_svm *svm = to_svm(vcpu);
3035
3036 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3037 vcpu->arch.hflags |= HF_NMI_MASK;
3038 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3039 ++vcpu->stat.nmi_injections;
3040 }
3041
3042 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3043 {
3044 struct vmcb_control_area *control;
3045
3046 control = &svm->vmcb->control;
3047 control->int_vector = irq;
3048 control->int_ctl &= ~V_INTR_PRIO_MASK;
3049 control->int_ctl |= V_IRQ_MASK |
3050 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3051 }
3052
3053 static void svm_set_irq(struct kvm_vcpu *vcpu)
3054 {
3055 struct vcpu_svm *svm = to_svm(vcpu);
3056
3057 BUG_ON(!(gif_set(svm)));
3058
3059 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3060 ++vcpu->stat.irq_injections;
3061
3062 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3063 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3064 }
3065
3066 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3067 {
3068 struct vcpu_svm *svm = to_svm(vcpu);
3069
3070 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3071 return;
3072
3073 if (irr == -1)
3074 return;
3075
3076 if (tpr >= irr)
3077 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
3078 }
3079
3080 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3081 {
3082 struct vcpu_svm *svm = to_svm(vcpu);
3083 struct vmcb *vmcb = svm->vmcb;
3084 int ret;
3085 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3086 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3087 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3088
3089 return ret;
3090 }
3091
3092 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3093 {
3094 struct vcpu_svm *svm = to_svm(vcpu);
3095
3096 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3097 }
3098
3099 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3100 {
3101 struct vcpu_svm *svm = to_svm(vcpu);
3102
3103 if (masked) {
3104 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3105 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3106 } else {
3107 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3108 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3109 }
3110 }
3111
3112 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3113 {
3114 struct vcpu_svm *svm = to_svm(vcpu);
3115 struct vmcb *vmcb = svm->vmcb;
3116 int ret;
3117
3118 if (!gif_set(svm) ||
3119 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3120 return 0;
3121
3122 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3123
3124 if (is_nested(svm))
3125 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3126
3127 return ret;
3128 }
3129
3130 static void enable_irq_window(struct kvm_vcpu *vcpu)
3131 {
3132 struct vcpu_svm *svm = to_svm(vcpu);
3133
3134 /*
3135 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3136 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3137 * get that intercept, this function will be called again though and
3138 * we'll get the vintr intercept.
3139 */
3140 if (gif_set(svm) && nested_svm_intr(svm)) {
3141 svm_set_vintr(svm);
3142 svm_inject_irq(svm, 0x0);
3143 }
3144 }
3145
3146 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3147 {
3148 struct vcpu_svm *svm = to_svm(vcpu);
3149
3150 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3151 == HF_NMI_MASK)
3152 return; /* IRET will cause a vm exit */
3153
3154 /*
3155 * Something prevents NMI from been injected. Single step over possible
3156 * problem (IRET or exception injection or interrupt shadow)
3157 */
3158 svm->nmi_singlestep = true;
3159 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3160 update_db_intercept(vcpu);
3161 }
3162
3163 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3164 {
3165 return 0;
3166 }
3167
3168 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3169 {
3170 force_new_asid(vcpu);
3171 }
3172
3173 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3174 {
3175 }
3176
3177 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3178 {
3179 struct vcpu_svm *svm = to_svm(vcpu);
3180
3181 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3182 return;
3183
3184 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
3185 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3186 kvm_set_cr8(vcpu, cr8);
3187 }
3188 }
3189
3190 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3191 {
3192 struct vcpu_svm *svm = to_svm(vcpu);
3193 u64 cr8;
3194
3195 if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
3196 return;
3197
3198 cr8 = kvm_get_cr8(vcpu);
3199 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3200 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3201 }
3202
3203 static void svm_complete_interrupts(struct vcpu_svm *svm)
3204 {
3205 u8 vector;
3206 int type;
3207 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3208 unsigned int3_injected = svm->int3_injected;
3209
3210 svm->int3_injected = 0;
3211
3212 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
3213 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3214
3215 svm->vcpu.arch.nmi_injected = false;
3216 kvm_clear_exception_queue(&svm->vcpu);
3217 kvm_clear_interrupt_queue(&svm->vcpu);
3218
3219 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3220 return;
3221
3222 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3223 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3224
3225 switch (type) {
3226 case SVM_EXITINTINFO_TYPE_NMI:
3227 svm->vcpu.arch.nmi_injected = true;
3228 break;
3229 case SVM_EXITINTINFO_TYPE_EXEPT:
3230 /*
3231 * In case of software exceptions, do not reinject the vector,
3232 * but re-execute the instruction instead. Rewind RIP first
3233 * if we emulated INT3 before.
3234 */
3235 if (kvm_exception_is_soft(vector)) {
3236 if (vector == BP_VECTOR && int3_injected &&
3237 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3238 kvm_rip_write(&svm->vcpu,
3239 kvm_rip_read(&svm->vcpu) -
3240 int3_injected);
3241 break;
3242 }
3243 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3244 u32 err = svm->vmcb->control.exit_int_info_err;
3245 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3246
3247 } else
3248 kvm_requeue_exception(&svm->vcpu, vector);
3249 break;
3250 case SVM_EXITINTINFO_TYPE_INTR:
3251 kvm_queue_interrupt(&svm->vcpu, vector, false);
3252 break;
3253 default:
3254 break;
3255 }
3256 }
3257
3258 #ifdef CONFIG_X86_64
3259 #define R "r"
3260 #else
3261 #define R "e"
3262 #endif
3263
3264 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3265 {
3266 struct vcpu_svm *svm = to_svm(vcpu);
3267 u16 fs_selector;
3268 u16 gs_selector;
3269 u16 ldt_selector;
3270
3271 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3272 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3273 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3274
3275 /*
3276 * A vmexit emulation is required before the vcpu can be executed
3277 * again.
3278 */
3279 if (unlikely(svm->nested.exit_required))
3280 return;
3281
3282 pre_svm_run(svm);
3283
3284 sync_lapic_to_cr8(vcpu);
3285
3286 save_host_msrs(vcpu);
3287 savesegment(fs, fs_selector);
3288 savesegment(gs, gs_selector);
3289 ldt_selector = kvm_read_ldt();
3290 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3291
3292 clgi();
3293
3294 local_irq_enable();
3295
3296 asm volatile (
3297 "push %%"R"bp; \n\t"
3298 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3299 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3300 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3301 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3302 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3303 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3304 #ifdef CONFIG_X86_64
3305 "mov %c[r8](%[svm]), %%r8 \n\t"
3306 "mov %c[r9](%[svm]), %%r9 \n\t"
3307 "mov %c[r10](%[svm]), %%r10 \n\t"
3308 "mov %c[r11](%[svm]), %%r11 \n\t"
3309 "mov %c[r12](%[svm]), %%r12 \n\t"
3310 "mov %c[r13](%[svm]), %%r13 \n\t"
3311 "mov %c[r14](%[svm]), %%r14 \n\t"
3312 "mov %c[r15](%[svm]), %%r15 \n\t"
3313 #endif
3314
3315 /* Enter guest mode */
3316 "push %%"R"ax \n\t"
3317 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3318 __ex(SVM_VMLOAD) "\n\t"
3319 __ex(SVM_VMRUN) "\n\t"
3320 __ex(SVM_VMSAVE) "\n\t"
3321 "pop %%"R"ax \n\t"
3322
3323 /* Save guest registers, load host registers */
3324 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3325 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3326 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3327 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3328 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3329 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3330 #ifdef CONFIG_X86_64
3331 "mov %%r8, %c[r8](%[svm]) \n\t"
3332 "mov %%r9, %c[r9](%[svm]) \n\t"
3333 "mov %%r10, %c[r10](%[svm]) \n\t"
3334 "mov %%r11, %c[r11](%[svm]) \n\t"
3335 "mov %%r12, %c[r12](%[svm]) \n\t"
3336 "mov %%r13, %c[r13](%[svm]) \n\t"
3337 "mov %%r14, %c[r14](%[svm]) \n\t"
3338 "mov %%r15, %c[r15](%[svm]) \n\t"
3339 #endif
3340 "pop %%"R"bp"
3341 :
3342 : [svm]"a"(svm),
3343 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3344 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3345 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3346 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3347 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3348 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3349 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3350 #ifdef CONFIG_X86_64
3351 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3352 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3353 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3354 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3355 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3356 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3357 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3358 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3359 #endif
3360 : "cc", "memory"
3361 , R"bx", R"cx", R"dx", R"si", R"di"
3362 #ifdef CONFIG_X86_64
3363 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3364 #endif
3365 );
3366
3367 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3368 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3369 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3370 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3371
3372 load_host_msrs(vcpu);
3373 loadsegment(fs, fs_selector);
3374 #ifdef CONFIG_X86_64
3375 load_gs_index(gs_selector);
3376 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
3377 #else
3378 loadsegment(gs, gs_selector);
3379 #endif
3380 kvm_load_ldt(ldt_selector);
3381
3382 reload_tss(vcpu);
3383
3384 local_irq_disable();
3385
3386 stgi();
3387
3388 sync_cr8_to_lapic(vcpu);
3389
3390 svm->next_rip = 0;
3391
3392 if (npt_enabled) {
3393 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3394 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3395 }
3396
3397 /*
3398 * We need to handle MC intercepts here before the vcpu has a chance to
3399 * change the physical cpu
3400 */
3401 if (unlikely(svm->vmcb->control.exit_code ==
3402 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3403 svm_handle_mce(svm);
3404 }
3405
3406 #undef R
3407
3408 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3409 {
3410 struct vcpu_svm *svm = to_svm(vcpu);
3411
3412 svm->vmcb->save.cr3 = root;
3413 force_new_asid(vcpu);
3414 }
3415
3416 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3417 {
3418 struct vcpu_svm *svm = to_svm(vcpu);
3419
3420 svm->vmcb->control.nested_cr3 = root;
3421
3422 /* Also sync guest cr3 here in case we live migrate */
3423 svm->vmcb->save.cr3 = vcpu->arch.cr3;
3424
3425 force_new_asid(vcpu);
3426 }
3427
3428 static int is_disabled(void)
3429 {
3430 u64 vm_cr;
3431
3432 rdmsrl(MSR_VM_CR, vm_cr);
3433 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3434 return 1;
3435
3436 return 0;
3437 }
3438
3439 static void
3440 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3441 {
3442 /*
3443 * Patch in the VMMCALL instruction:
3444 */
3445 hypercall[0] = 0x0f;
3446 hypercall[1] = 0x01;
3447 hypercall[2] = 0xd9;
3448 }
3449
3450 static void svm_check_processor_compat(void *rtn)
3451 {
3452 *(int *)rtn = 0;
3453 }
3454
3455 static bool svm_cpu_has_accelerated_tpr(void)
3456 {
3457 return false;
3458 }
3459
3460 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3461 {
3462 return 0;
3463 }
3464
3465 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3466 {
3467 }
3468
3469 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3470 {
3471 switch (func) {
3472 case 0x8000000A:
3473 entry->eax = 1; /* SVM revision 1 */
3474 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3475 ASID emulation to nested SVM */
3476 entry->ecx = 0; /* Reserved */
3477 entry->edx = 0; /* Per default do not support any
3478 additional features */
3479
3480 /* Support next_rip if host supports it */
3481 if (svm_has(SVM_FEATURE_NRIP))
3482 entry->edx |= SVM_FEATURE_NRIP;
3483
3484 break;
3485 }
3486 }
3487
3488 static const struct trace_print_flags svm_exit_reasons_str[] = {
3489 { SVM_EXIT_READ_CR0, "read_cr0" },
3490 { SVM_EXIT_READ_CR3, "read_cr3" },
3491 { SVM_EXIT_READ_CR4, "read_cr4" },
3492 { SVM_EXIT_READ_CR8, "read_cr8" },
3493 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3494 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3495 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3496 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3497 { SVM_EXIT_READ_DR0, "read_dr0" },
3498 { SVM_EXIT_READ_DR1, "read_dr1" },
3499 { SVM_EXIT_READ_DR2, "read_dr2" },
3500 { SVM_EXIT_READ_DR3, "read_dr3" },
3501 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3502 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3503 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3504 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3505 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3506 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3507 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3508 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3509 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3510 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3511 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3512 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3513 { SVM_EXIT_INTR, "interrupt" },
3514 { SVM_EXIT_NMI, "nmi" },
3515 { SVM_EXIT_SMI, "smi" },
3516 { SVM_EXIT_INIT, "init" },
3517 { SVM_EXIT_VINTR, "vintr" },
3518 { SVM_EXIT_CPUID, "cpuid" },
3519 { SVM_EXIT_INVD, "invd" },
3520 { SVM_EXIT_HLT, "hlt" },
3521 { SVM_EXIT_INVLPG, "invlpg" },
3522 { SVM_EXIT_INVLPGA, "invlpga" },
3523 { SVM_EXIT_IOIO, "io" },
3524 { SVM_EXIT_MSR, "msr" },
3525 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3526 { SVM_EXIT_SHUTDOWN, "shutdown" },
3527 { SVM_EXIT_VMRUN, "vmrun" },
3528 { SVM_EXIT_VMMCALL, "hypercall" },
3529 { SVM_EXIT_VMLOAD, "vmload" },
3530 { SVM_EXIT_VMSAVE, "vmsave" },
3531 { SVM_EXIT_STGI, "stgi" },
3532 { SVM_EXIT_CLGI, "clgi" },
3533 { SVM_EXIT_SKINIT, "skinit" },
3534 { SVM_EXIT_WBINVD, "wbinvd" },
3535 { SVM_EXIT_MONITOR, "monitor" },
3536 { SVM_EXIT_MWAIT, "mwait" },
3537 { SVM_EXIT_NPF, "npf" },
3538 { -1, NULL }
3539 };
3540
3541 static int svm_get_lpage_level(void)
3542 {
3543 return PT_PDPE_LEVEL;
3544 }
3545
3546 static bool svm_rdtscp_supported(void)
3547 {
3548 return false;
3549 }
3550
3551 static bool svm_has_wbinvd_exit(void)
3552 {
3553 return true;
3554 }
3555
3556 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3557 {
3558 struct vcpu_svm *svm = to_svm(vcpu);
3559
3560 svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3561 if (is_nested(svm))
3562 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3563 update_cr0_intercept(svm);
3564 }
3565
3566 static struct kvm_x86_ops svm_x86_ops = {
3567 .cpu_has_kvm_support = has_svm,
3568 .disabled_by_bios = is_disabled,
3569 .hardware_setup = svm_hardware_setup,
3570 .hardware_unsetup = svm_hardware_unsetup,
3571 .check_processor_compatibility = svm_check_processor_compat,
3572 .hardware_enable = svm_hardware_enable,
3573 .hardware_disable = svm_hardware_disable,
3574 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3575
3576 .vcpu_create = svm_create_vcpu,
3577 .vcpu_free = svm_free_vcpu,
3578 .vcpu_reset = svm_vcpu_reset,
3579
3580 .prepare_guest_switch = svm_prepare_guest_switch,
3581 .vcpu_load = svm_vcpu_load,
3582 .vcpu_put = svm_vcpu_put,
3583
3584 .set_guest_debug = svm_guest_debug,
3585 .get_msr = svm_get_msr,
3586 .set_msr = svm_set_msr,
3587 .get_segment_base = svm_get_segment_base,
3588 .get_segment = svm_get_segment,
3589 .set_segment = svm_set_segment,
3590 .get_cpl = svm_get_cpl,
3591 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3592 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3593 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3594 .set_cr0 = svm_set_cr0,
3595 .set_cr3 = svm_set_cr3,
3596 .set_cr4 = svm_set_cr4,
3597 .set_efer = svm_set_efer,
3598 .get_idt = svm_get_idt,
3599 .set_idt = svm_set_idt,
3600 .get_gdt = svm_get_gdt,
3601 .set_gdt = svm_set_gdt,
3602 .set_dr7 = svm_set_dr7,
3603 .cache_reg = svm_cache_reg,
3604 .get_rflags = svm_get_rflags,
3605 .set_rflags = svm_set_rflags,
3606 .fpu_activate = svm_fpu_activate,
3607 .fpu_deactivate = svm_fpu_deactivate,
3608
3609 .tlb_flush = svm_flush_tlb,
3610
3611 .run = svm_vcpu_run,
3612 .handle_exit = handle_exit,
3613 .skip_emulated_instruction = skip_emulated_instruction,
3614 .set_interrupt_shadow = svm_set_interrupt_shadow,
3615 .get_interrupt_shadow = svm_get_interrupt_shadow,
3616 .patch_hypercall = svm_patch_hypercall,
3617 .set_irq = svm_set_irq,
3618 .set_nmi = svm_inject_nmi,
3619 .queue_exception = svm_queue_exception,
3620 .interrupt_allowed = svm_interrupt_allowed,
3621 .nmi_allowed = svm_nmi_allowed,
3622 .get_nmi_mask = svm_get_nmi_mask,
3623 .set_nmi_mask = svm_set_nmi_mask,
3624 .enable_nmi_window = enable_nmi_window,
3625 .enable_irq_window = enable_irq_window,
3626 .update_cr8_intercept = update_cr8_intercept,
3627
3628 .set_tss_addr = svm_set_tss_addr,
3629 .get_tdp_level = get_npt_level,
3630 .get_mt_mask = svm_get_mt_mask,
3631
3632 .exit_reasons_str = svm_exit_reasons_str,
3633 .get_lpage_level = svm_get_lpage_level,
3634
3635 .cpuid_update = svm_cpuid_update,
3636
3637 .rdtscp_supported = svm_rdtscp_supported,
3638
3639 .set_supported_cpuid = svm_set_supported_cpuid,
3640
3641 .has_wbinvd_exit = svm_has_wbinvd_exit,
3642
3643 .write_tsc_offset = svm_write_tsc_offset,
3644 .adjust_tsc_offset = svm_adjust_tsc_offset,
3645
3646 .set_tdp_cr3 = set_tdp_cr3,
3647 };
3648
3649 static int __init svm_init(void)
3650 {
3651 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3652 __alignof__(struct vcpu_svm), THIS_MODULE);
3653 }
3654
3655 static void __exit svm_exit(void)
3656 {
3657 kvm_exit();
3658 }
3659
3660 module_init(svm_init)
3661 module_exit(svm_exit)
Linux kernel - Deliverables
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