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e4eb3fd91b9039710bc2295de7f66e4ecda4a526
[deliverable/linux.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28
29 #include <asm/desc.h>
30
31 #include <asm/virtext.h>
32
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
34
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
37
38 #define IOPM_ALLOC_ORDER 2
39 #define MSRPM_ALLOC_ORDER 1
40
41 #define DR7_GD_MASK (1 << 13)
42 #define DR6_BD_MASK (1 << 13)
43
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
46
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50
51 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
52
53 /* enable NPT for AMD64 and X86 with PAE */
54 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
55 static bool npt_enabled = true;
56 #else
57 static bool npt_enabled = false;
58 #endif
59 static int npt = 1;
60
61 module_param(npt, int, S_IRUGO);
62
63 static void kvm_reput_irq(struct vcpu_svm *svm);
64 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
65
66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
67 {
68 return container_of(vcpu, struct vcpu_svm, vcpu);
69 }
70
71 static unsigned long iopm_base;
72
73 struct kvm_ldttss_desc {
74 u16 limit0;
75 u16 base0;
76 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
77 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
78 u32 base3;
79 u32 zero1;
80 } __attribute__((packed));
81
82 struct svm_cpu_data {
83 int cpu;
84
85 u64 asid_generation;
86 u32 max_asid;
87 u32 next_asid;
88 struct kvm_ldttss_desc *tss_desc;
89
90 struct page *save_area;
91 };
92
93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
94 static uint32_t svm_features;
95
96 struct svm_init_data {
97 int cpu;
98 int r;
99 };
100
101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
102
103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
104 #define MSRS_RANGE_SIZE 2048
105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
106
107 #define MAX_INST_SIZE 15
108
109 static inline u32 svm_has(u32 feat)
110 {
111 return svm_features & feat;
112 }
113
114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
115 {
116 int word_index = __ffs(vcpu->arch.irq_summary);
117 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
118 int irq = word_index * BITS_PER_LONG + bit_index;
119
120 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
121 if (!vcpu->arch.irq_pending[word_index])
122 clear_bit(word_index, &vcpu->arch.irq_summary);
123 return irq;
124 }
125
126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
127 {
128 set_bit(irq, vcpu->arch.irq_pending);
129 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
130 }
131
132 static inline void clgi(void)
133 {
134 asm volatile (__ex(SVM_CLGI));
135 }
136
137 static inline void stgi(void)
138 {
139 asm volatile (__ex(SVM_STGI));
140 }
141
142 static inline void invlpga(unsigned long addr, u32 asid)
143 {
144 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
145 }
146
147 static inline unsigned long kvm_read_cr2(void)
148 {
149 unsigned long cr2;
150
151 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
152 return cr2;
153 }
154
155 static inline void kvm_write_cr2(unsigned long val)
156 {
157 asm volatile ("mov %0, %%cr2" :: "r" (val));
158 }
159
160 static inline unsigned long read_dr6(void)
161 {
162 unsigned long dr6;
163
164 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
165 return dr6;
166 }
167
168 static inline void write_dr6(unsigned long val)
169 {
170 asm volatile ("mov %0, %%dr6" :: "r" (val));
171 }
172
173 static inline unsigned long read_dr7(void)
174 {
175 unsigned long dr7;
176
177 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
178 return dr7;
179 }
180
181 static inline void write_dr7(unsigned long val)
182 {
183 asm volatile ("mov %0, %%dr7" :: "r" (val));
184 }
185
186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
187 {
188 to_svm(vcpu)->asid_generation--;
189 }
190
191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
192 {
193 force_new_asid(vcpu);
194 }
195
196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
197 {
198 if (!npt_enabled && !(efer & EFER_LMA))
199 efer &= ~EFER_LME;
200
201 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
202 vcpu->arch.shadow_efer = efer;
203 }
204
205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
206 bool has_error_code, u32 error_code)
207 {
208 struct vcpu_svm *svm = to_svm(vcpu);
209
210 svm->vmcb->control.event_inj = nr
211 | SVM_EVTINJ_VALID
212 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
213 | SVM_EVTINJ_TYPE_EXEPT;
214 svm->vmcb->control.event_inj_err = error_code;
215 }
216
217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
218 {
219 struct vcpu_svm *svm = to_svm(vcpu);
220
221 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
222 }
223
224 static int is_external_interrupt(u32 info)
225 {
226 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
228 }
229
230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
231 {
232 struct vcpu_svm *svm = to_svm(vcpu);
233
234 if (!svm->next_rip) {
235 printk(KERN_DEBUG "%s: NOP\n", __func__);
236 return;
237 }
238 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
239 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
240 __func__, kvm_rip_read(vcpu), svm->next_rip);
241
242 kvm_rip_write(vcpu, svm->next_rip);
243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
244
245 vcpu->arch.interrupt_window_open = 1;
246 }
247
248 static int has_svm(void)
249 {
250 const char *msg;
251
252 if (!cpu_has_svm(&msg)) {
253 printk(KERN_INFO "has_svn: %s\n", msg);
254 return 0;
255 }
256
257 return 1;
258 }
259
260 static void svm_hardware_disable(void *garbage)
261 {
262 cpu_svm_disable();
263 }
264
265 static void svm_hardware_enable(void *garbage)
266 {
267
268 struct svm_cpu_data *svm_data;
269 uint64_t efer;
270 struct desc_ptr gdt_descr;
271 struct desc_struct *gdt;
272 int me = raw_smp_processor_id();
273
274 if (!has_svm()) {
275 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
276 return;
277 }
278 svm_data = per_cpu(svm_data, me);
279
280 if (!svm_data) {
281 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
282 me);
283 return;
284 }
285
286 svm_data->asid_generation = 1;
287 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
288 svm_data->next_asid = svm_data->max_asid + 1;
289
290 asm volatile ("sgdt %0" : "=m"(gdt_descr));
291 gdt = (struct desc_struct *)gdt_descr.address;
292 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
293
294 rdmsrl(MSR_EFER, efer);
295 wrmsrl(MSR_EFER, efer | EFER_SVME);
296
297 wrmsrl(MSR_VM_HSAVE_PA,
298 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
299 }
300
301 static void svm_cpu_uninit(int cpu)
302 {
303 struct svm_cpu_data *svm_data
304 = per_cpu(svm_data, raw_smp_processor_id());
305
306 if (!svm_data)
307 return;
308
309 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
310 __free_page(svm_data->save_area);
311 kfree(svm_data);
312 }
313
314 static int svm_cpu_init(int cpu)
315 {
316 struct svm_cpu_data *svm_data;
317 int r;
318
319 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
320 if (!svm_data)
321 return -ENOMEM;
322 svm_data->cpu = cpu;
323 svm_data->save_area = alloc_page(GFP_KERNEL);
324 r = -ENOMEM;
325 if (!svm_data->save_area)
326 goto err_1;
327
328 per_cpu(svm_data, cpu) = svm_data;
329
330 return 0;
331
332 err_1:
333 kfree(svm_data);
334 return r;
335
336 }
337
338 static void set_msr_interception(u32 *msrpm, unsigned msr,
339 int read, int write)
340 {
341 int i;
342
343 for (i = 0; i < NUM_MSR_MAPS; i++) {
344 if (msr >= msrpm_ranges[i] &&
345 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
346 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
347 msrpm_ranges[i]) * 2;
348
349 u32 *base = msrpm + (msr_offset / 32);
350 u32 msr_shift = msr_offset % 32;
351 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
352 *base = (*base & ~(0x3 << msr_shift)) |
353 (mask << msr_shift);
354 return;
355 }
356 }
357 BUG();
358 }
359
360 static void svm_vcpu_init_msrpm(u32 *msrpm)
361 {
362 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
363
364 #ifdef CONFIG_X86_64
365 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
366 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
367 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
368 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
369 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
370 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
371 #endif
372 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
373 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
374 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
375 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
376 }
377
378 static void svm_enable_lbrv(struct vcpu_svm *svm)
379 {
380 u32 *msrpm = svm->msrpm;
381
382 svm->vmcb->control.lbr_ctl = 1;
383 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
386 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
387 }
388
389 static void svm_disable_lbrv(struct vcpu_svm *svm)
390 {
391 u32 *msrpm = svm->msrpm;
392
393 svm->vmcb->control.lbr_ctl = 0;
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
395 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
397 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
398 }
399
400 static __init int svm_hardware_setup(void)
401 {
402 int cpu;
403 struct page *iopm_pages;
404 void *iopm_va;
405 int r;
406
407 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
408
409 if (!iopm_pages)
410 return -ENOMEM;
411
412 iopm_va = page_address(iopm_pages);
413 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
414 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
415 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
416
417 if (boot_cpu_has(X86_FEATURE_NX))
418 kvm_enable_efer_bits(EFER_NX);
419
420 for_each_online_cpu(cpu) {
421 r = svm_cpu_init(cpu);
422 if (r)
423 goto err;
424 }
425
426 svm_features = cpuid_edx(SVM_CPUID_FUNC);
427
428 if (!svm_has(SVM_FEATURE_NPT))
429 npt_enabled = false;
430
431 if (npt_enabled && !npt) {
432 printk(KERN_INFO "kvm: Nested Paging disabled\n");
433 npt_enabled = false;
434 }
435
436 if (npt_enabled) {
437 printk(KERN_INFO "kvm: Nested Paging enabled\n");
438 kvm_enable_tdp();
439 } else
440 kvm_disable_tdp();
441
442 return 0;
443
444 err:
445 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
446 iopm_base = 0;
447 return r;
448 }
449
450 static __exit void svm_hardware_unsetup(void)
451 {
452 int cpu;
453
454 for_each_online_cpu(cpu)
455 svm_cpu_uninit(cpu);
456
457 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
458 iopm_base = 0;
459 }
460
461 static void init_seg(struct vmcb_seg *seg)
462 {
463 seg->selector = 0;
464 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
465 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
466 seg->limit = 0xffff;
467 seg->base = 0;
468 }
469
470 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
471 {
472 seg->selector = 0;
473 seg->attrib = SVM_SELECTOR_P_MASK | type;
474 seg->limit = 0xffff;
475 seg->base = 0;
476 }
477
478 static void init_vmcb(struct vcpu_svm *svm)
479 {
480 struct vmcb_control_area *control = &svm->vmcb->control;
481 struct vmcb_save_area *save = &svm->vmcb->save;
482
483 control->intercept_cr_read = INTERCEPT_CR0_MASK |
484 INTERCEPT_CR3_MASK |
485 INTERCEPT_CR4_MASK;
486
487 control->intercept_cr_write = INTERCEPT_CR0_MASK |
488 INTERCEPT_CR3_MASK |
489 INTERCEPT_CR4_MASK |
490 INTERCEPT_CR8_MASK;
491
492 control->intercept_dr_read = INTERCEPT_DR0_MASK |
493 INTERCEPT_DR1_MASK |
494 INTERCEPT_DR2_MASK |
495 INTERCEPT_DR3_MASK;
496
497 control->intercept_dr_write = INTERCEPT_DR0_MASK |
498 INTERCEPT_DR1_MASK |
499 INTERCEPT_DR2_MASK |
500 INTERCEPT_DR3_MASK |
501 INTERCEPT_DR5_MASK |
502 INTERCEPT_DR7_MASK;
503
504 control->intercept_exceptions = (1 << PF_VECTOR) |
505 (1 << UD_VECTOR) |
506 (1 << MC_VECTOR);
507
508
509 control->intercept = (1ULL << INTERCEPT_INTR) |
510 (1ULL << INTERCEPT_NMI) |
511 (1ULL << INTERCEPT_SMI) |
512 (1ULL << INTERCEPT_CPUID) |
513 (1ULL << INTERCEPT_INVD) |
514 (1ULL << INTERCEPT_HLT) |
515 (1ULL << INTERCEPT_INVLPG) |
516 (1ULL << INTERCEPT_INVLPGA) |
517 (1ULL << INTERCEPT_IOIO_PROT) |
518 (1ULL << INTERCEPT_MSR_PROT) |
519 (1ULL << INTERCEPT_TASK_SWITCH) |
520 (1ULL << INTERCEPT_SHUTDOWN) |
521 (1ULL << INTERCEPT_VMRUN) |
522 (1ULL << INTERCEPT_VMMCALL) |
523 (1ULL << INTERCEPT_VMLOAD) |
524 (1ULL << INTERCEPT_VMSAVE) |
525 (1ULL << INTERCEPT_STGI) |
526 (1ULL << INTERCEPT_CLGI) |
527 (1ULL << INTERCEPT_SKINIT) |
528 (1ULL << INTERCEPT_WBINVD) |
529 (1ULL << INTERCEPT_MONITOR) |
530 (1ULL << INTERCEPT_MWAIT);
531
532 control->iopm_base_pa = iopm_base;
533 control->msrpm_base_pa = __pa(svm->msrpm);
534 control->tsc_offset = 0;
535 control->int_ctl = V_INTR_MASKING_MASK;
536
537 init_seg(&save->es);
538 init_seg(&save->ss);
539 init_seg(&save->ds);
540 init_seg(&save->fs);
541 init_seg(&save->gs);
542
543 save->cs.selector = 0xf000;
544 /* Executable/Readable Code Segment */
545 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
546 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
547 save->cs.limit = 0xffff;
548 /*
549 * cs.base should really be 0xffff0000, but vmx can't handle that, so
550 * be consistent with it.
551 *
552 * Replace when we have real mode working for vmx.
553 */
554 save->cs.base = 0xf0000;
555
556 save->gdtr.limit = 0xffff;
557 save->idtr.limit = 0xffff;
558
559 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
560 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
561
562 save->efer = EFER_SVME;
563 save->dr6 = 0xffff0ff0;
564 save->dr7 = 0x400;
565 save->rflags = 2;
566 save->rip = 0x0000fff0;
567 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
568
569 /*
570 * cr0 val on cpu init should be 0x60000010, we enable cpu
571 * cache by default. the orderly way is to enable cache in bios.
572 */
573 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
574 save->cr4 = X86_CR4_PAE;
575 /* rdx = ?? */
576
577 if (npt_enabled) {
578 /* Setup VMCB for Nested Paging */
579 control->nested_ctl = 1;
580 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
581 (1ULL << INTERCEPT_INVLPG));
582 control->intercept_exceptions &= ~(1 << PF_VECTOR);
583 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
584 INTERCEPT_CR3_MASK);
585 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
586 INTERCEPT_CR3_MASK);
587 save->g_pat = 0x0007040600070406ULL;
588 /* enable caching because the QEMU Bios doesn't enable it */
589 save->cr0 = X86_CR0_ET;
590 save->cr3 = 0;
591 save->cr4 = 0;
592 }
593 force_new_asid(&svm->vcpu);
594 }
595
596 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
597 {
598 struct vcpu_svm *svm = to_svm(vcpu);
599
600 init_vmcb(svm);
601
602 if (vcpu->vcpu_id != 0) {
603 kvm_rip_write(vcpu, 0);
604 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
605 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
606 }
607 vcpu->arch.regs_avail = ~0;
608 vcpu->arch.regs_dirty = ~0;
609
610 return 0;
611 }
612
613 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
614 {
615 struct vcpu_svm *svm;
616 struct page *page;
617 struct page *msrpm_pages;
618 int err;
619
620 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
621 if (!svm) {
622 err = -ENOMEM;
623 goto out;
624 }
625
626 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
627 if (err)
628 goto free_svm;
629
630 page = alloc_page(GFP_KERNEL);
631 if (!page) {
632 err = -ENOMEM;
633 goto uninit;
634 }
635
636 err = -ENOMEM;
637 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
638 if (!msrpm_pages)
639 goto uninit;
640 svm->msrpm = page_address(msrpm_pages);
641 svm_vcpu_init_msrpm(svm->msrpm);
642
643 svm->vmcb = page_address(page);
644 clear_page(svm->vmcb);
645 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
646 svm->asid_generation = 0;
647 memset(svm->db_regs, 0, sizeof(svm->db_regs));
648 init_vmcb(svm);
649
650 fx_init(&svm->vcpu);
651 svm->vcpu.fpu_active = 1;
652 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
653 if (svm->vcpu.vcpu_id == 0)
654 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
655
656 return &svm->vcpu;
657
658 uninit:
659 kvm_vcpu_uninit(&svm->vcpu);
660 free_svm:
661 kmem_cache_free(kvm_vcpu_cache, svm);
662 out:
663 return ERR_PTR(err);
664 }
665
666 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
667 {
668 struct vcpu_svm *svm = to_svm(vcpu);
669
670 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
671 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
672 kvm_vcpu_uninit(vcpu);
673 kmem_cache_free(kvm_vcpu_cache, svm);
674 }
675
676 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
677 {
678 struct vcpu_svm *svm = to_svm(vcpu);
679 int i;
680
681 if (unlikely(cpu != vcpu->cpu)) {
682 u64 tsc_this, delta;
683
684 /*
685 * Make sure that the guest sees a monotonically
686 * increasing TSC.
687 */
688 rdtscll(tsc_this);
689 delta = vcpu->arch.host_tsc - tsc_this;
690 svm->vmcb->control.tsc_offset += delta;
691 vcpu->cpu = cpu;
692 kvm_migrate_timers(vcpu);
693 }
694
695 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
696 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
697 }
698
699 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
700 {
701 struct vcpu_svm *svm = to_svm(vcpu);
702 int i;
703
704 ++vcpu->stat.host_state_reload;
705 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
706 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
707
708 rdtscll(vcpu->arch.host_tsc);
709 }
710
711 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
712 {
713 return to_svm(vcpu)->vmcb->save.rflags;
714 }
715
716 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
717 {
718 to_svm(vcpu)->vmcb->save.rflags = rflags;
719 }
720
721 static void svm_set_vintr(struct vcpu_svm *svm)
722 {
723 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
724 }
725
726 static void svm_clear_vintr(struct vcpu_svm *svm)
727 {
728 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
729 }
730
731 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
732 {
733 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
734
735 switch (seg) {
736 case VCPU_SREG_CS: return &save->cs;
737 case VCPU_SREG_DS: return &save->ds;
738 case VCPU_SREG_ES: return &save->es;
739 case VCPU_SREG_FS: return &save->fs;
740 case VCPU_SREG_GS: return &save->gs;
741 case VCPU_SREG_SS: return &save->ss;
742 case VCPU_SREG_TR: return &save->tr;
743 case VCPU_SREG_LDTR: return &save->ldtr;
744 }
745 BUG();
746 return NULL;
747 }
748
749 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
750 {
751 struct vmcb_seg *s = svm_seg(vcpu, seg);
752
753 return s->base;
754 }
755
756 static void svm_get_segment(struct kvm_vcpu *vcpu,
757 struct kvm_segment *var, int seg)
758 {
759 struct vmcb_seg *s = svm_seg(vcpu, seg);
760
761 var->base = s->base;
762 var->limit = s->limit;
763 var->selector = s->selector;
764 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
765 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
766 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
767 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
768 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
769 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
770 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
771 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
772
773 /*
774 * SVM always stores 0 for the 'G' bit in the CS selector in
775 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
776 * Intel's VMENTRY has a check on the 'G' bit.
777 */
778 if (seg == VCPU_SREG_CS)
779 var->g = s->limit > 0xfffff;
780
781 /*
782 * Work around a bug where the busy flag in the tr selector
783 * isn't exposed
784 */
785 if (seg == VCPU_SREG_TR)
786 var->type |= 0x2;
787
788 var->unusable = !var->present;
789 }
790
791 static int svm_get_cpl(struct kvm_vcpu *vcpu)
792 {
793 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
794
795 return save->cpl;
796 }
797
798 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
799 {
800 struct vcpu_svm *svm = to_svm(vcpu);
801
802 dt->limit = svm->vmcb->save.idtr.limit;
803 dt->base = svm->vmcb->save.idtr.base;
804 }
805
806 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
807 {
808 struct vcpu_svm *svm = to_svm(vcpu);
809
810 svm->vmcb->save.idtr.limit = dt->limit;
811 svm->vmcb->save.idtr.base = dt->base ;
812 }
813
814 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
815 {
816 struct vcpu_svm *svm = to_svm(vcpu);
817
818 dt->limit = svm->vmcb->save.gdtr.limit;
819 dt->base = svm->vmcb->save.gdtr.base;
820 }
821
822 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
823 {
824 struct vcpu_svm *svm = to_svm(vcpu);
825
826 svm->vmcb->save.gdtr.limit = dt->limit;
827 svm->vmcb->save.gdtr.base = dt->base ;
828 }
829
830 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
831 {
832 }
833
834 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
835 {
836 struct vcpu_svm *svm = to_svm(vcpu);
837
838 #ifdef CONFIG_X86_64
839 if (vcpu->arch.shadow_efer & EFER_LME) {
840 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
841 vcpu->arch.shadow_efer |= EFER_LMA;
842 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
843 }
844
845 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
846 vcpu->arch.shadow_efer &= ~EFER_LMA;
847 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
848 }
849 }
850 #endif
851 if (npt_enabled)
852 goto set;
853
854 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
855 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
856 vcpu->fpu_active = 1;
857 }
858
859 vcpu->arch.cr0 = cr0;
860 cr0 |= X86_CR0_PG | X86_CR0_WP;
861 if (!vcpu->fpu_active) {
862 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
863 cr0 |= X86_CR0_TS;
864 }
865 set:
866 /*
867 * re-enable caching here because the QEMU bios
868 * does not do it - this results in some delay at
869 * reboot
870 */
871 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
872 svm->vmcb->save.cr0 = cr0;
873 }
874
875 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
876 {
877 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
878 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
879
880 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
881 force_new_asid(vcpu);
882
883 vcpu->arch.cr4 = cr4;
884 if (!npt_enabled)
885 cr4 |= X86_CR4_PAE;
886 cr4 |= host_cr4_mce;
887 to_svm(vcpu)->vmcb->save.cr4 = cr4;
888 }
889
890 static void svm_set_segment(struct kvm_vcpu *vcpu,
891 struct kvm_segment *var, int seg)
892 {
893 struct vcpu_svm *svm = to_svm(vcpu);
894 struct vmcb_seg *s = svm_seg(vcpu, seg);
895
896 s->base = var->base;
897 s->limit = var->limit;
898 s->selector = var->selector;
899 if (var->unusable)
900 s->attrib = 0;
901 else {
902 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
903 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
904 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
905 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
906 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
907 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
908 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
909 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
910 }
911 if (seg == VCPU_SREG_CS)
912 svm->vmcb->save.cpl
913 = (svm->vmcb->save.cs.attrib
914 >> SVM_SELECTOR_DPL_SHIFT) & 3;
915
916 }
917
918 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
919 {
920 return -EOPNOTSUPP;
921 }
922
923 static int svm_get_irq(struct kvm_vcpu *vcpu)
924 {
925 struct vcpu_svm *svm = to_svm(vcpu);
926 u32 exit_int_info = svm->vmcb->control.exit_int_info;
927
928 if (is_external_interrupt(exit_int_info))
929 return exit_int_info & SVM_EVTINJ_VEC_MASK;
930 return -1;
931 }
932
933 static void load_host_msrs(struct kvm_vcpu *vcpu)
934 {
935 #ifdef CONFIG_X86_64
936 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
937 #endif
938 }
939
940 static void save_host_msrs(struct kvm_vcpu *vcpu)
941 {
942 #ifdef CONFIG_X86_64
943 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
944 #endif
945 }
946
947 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
948 {
949 if (svm_data->next_asid > svm_data->max_asid) {
950 ++svm_data->asid_generation;
951 svm_data->next_asid = 1;
952 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
953 }
954
955 svm->vcpu.cpu = svm_data->cpu;
956 svm->asid_generation = svm_data->asid_generation;
957 svm->vmcb->control.asid = svm_data->next_asid++;
958 }
959
960 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
961 {
962 unsigned long val = to_svm(vcpu)->db_regs[dr];
963 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
964 return val;
965 }
966
967 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
968 int *exception)
969 {
970 struct vcpu_svm *svm = to_svm(vcpu);
971
972 *exception = 0;
973
974 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
975 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
976 svm->vmcb->save.dr6 |= DR6_BD_MASK;
977 *exception = DB_VECTOR;
978 return;
979 }
980
981 switch (dr) {
982 case 0 ... 3:
983 svm->db_regs[dr] = value;
984 return;
985 case 4 ... 5:
986 if (vcpu->arch.cr4 & X86_CR4_DE) {
987 *exception = UD_VECTOR;
988 return;
989 }
990 case 7: {
991 if (value & ~((1ULL << 32) - 1)) {
992 *exception = GP_VECTOR;
993 return;
994 }
995 svm->vmcb->save.dr7 = value;
996 return;
997 }
998 default:
999 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1000 __func__, dr);
1001 *exception = UD_VECTOR;
1002 return;
1003 }
1004 }
1005
1006 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1007 {
1008 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1009 struct kvm *kvm = svm->vcpu.kvm;
1010 u64 fault_address;
1011 u32 error_code;
1012 bool event_injection = false;
1013
1014 if (!irqchip_in_kernel(kvm) &&
1015 is_external_interrupt(exit_int_info)) {
1016 event_injection = true;
1017 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1018 }
1019
1020 fault_address = svm->vmcb->control.exit_info_2;
1021 error_code = svm->vmcb->control.exit_info_1;
1022
1023 if (!npt_enabled)
1024 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1025 (u32)fault_address, (u32)(fault_address >> 32),
1026 handler);
1027 else
1028 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1029 (u32)fault_address, (u32)(fault_address >> 32),
1030 handler);
1031 /*
1032 * FIXME: Tis shouldn't be necessary here, but there is a flush
1033 * missing in the MMU code. Until we find this bug, flush the
1034 * complete TLB here on an NPF
1035 */
1036 if (npt_enabled)
1037 svm_flush_tlb(&svm->vcpu);
1038
1039 if (!npt_enabled && event_injection)
1040 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1041 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1042 }
1043
1044 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046 int er;
1047
1048 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1049 if (er != EMULATE_DONE)
1050 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1051 return 1;
1052 }
1053
1054 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1055 {
1056 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1057 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1058 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1059 svm->vcpu.fpu_active = 1;
1060
1061 return 1;
1062 }
1063
1064 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1065 {
1066 /*
1067 * On an #MC intercept the MCE handler is not called automatically in
1068 * the host. So do it by hand here.
1069 */
1070 asm volatile (
1071 "int $0x12\n");
1072 /* not sure if we ever come back to this point */
1073
1074 return 1;
1075 }
1076
1077 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1078 {
1079 /*
1080 * VMCB is undefined after a SHUTDOWN intercept
1081 * so reinitialize it.
1082 */
1083 clear_page(svm->vmcb);
1084 init_vmcb(svm);
1085
1086 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1087 return 0;
1088 }
1089
1090 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1091 {
1092 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1093 int size, down, in, string, rep;
1094 unsigned port;
1095
1096 ++svm->vcpu.stat.io_exits;
1097
1098 svm->next_rip = svm->vmcb->control.exit_info_2;
1099
1100 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1101
1102 if (string) {
1103 if (emulate_instruction(&svm->vcpu,
1104 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1105 return 0;
1106 return 1;
1107 }
1108
1109 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1110 port = io_info >> 16;
1111 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1112 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1113 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1114
1115 skip_emulated_instruction(&svm->vcpu);
1116 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1117 }
1118
1119 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1120 {
1121 KVMTRACE_0D(NMI, &svm->vcpu, handler);
1122 return 1;
1123 }
1124
1125 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1126 {
1127 ++svm->vcpu.stat.irq_exits;
1128 KVMTRACE_0D(INTR, &svm->vcpu, handler);
1129 return 1;
1130 }
1131
1132 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1133 {
1134 return 1;
1135 }
1136
1137 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1138 {
1139 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1140 skip_emulated_instruction(&svm->vcpu);
1141 return kvm_emulate_halt(&svm->vcpu);
1142 }
1143
1144 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1145 {
1146 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1147 skip_emulated_instruction(&svm->vcpu);
1148 kvm_emulate_hypercall(&svm->vcpu);
1149 return 1;
1150 }
1151
1152 static int invalid_op_interception(struct vcpu_svm *svm,
1153 struct kvm_run *kvm_run)
1154 {
1155 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1156 return 1;
1157 }
1158
1159 static int task_switch_interception(struct vcpu_svm *svm,
1160 struct kvm_run *kvm_run)
1161 {
1162 u16 tss_selector;
1163
1164 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1165 if (svm->vmcb->control.exit_info_2 &
1166 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1167 return kvm_task_switch(&svm->vcpu, tss_selector,
1168 TASK_SWITCH_IRET);
1169 if (svm->vmcb->control.exit_info_2 &
1170 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1171 return kvm_task_switch(&svm->vcpu, tss_selector,
1172 TASK_SWITCH_JMP);
1173 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1174 }
1175
1176 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1177 {
1178 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1179 kvm_emulate_cpuid(&svm->vcpu);
1180 return 1;
1181 }
1182
1183 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 {
1185 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1186 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1187 return 1;
1188 }
1189
1190 static int emulate_on_interception(struct vcpu_svm *svm,
1191 struct kvm_run *kvm_run)
1192 {
1193 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1194 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1195 return 1;
1196 }
1197
1198 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1199 {
1200 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1201 if (irqchip_in_kernel(svm->vcpu.kvm))
1202 return 1;
1203 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1204 return 0;
1205 }
1206
1207 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1208 {
1209 struct vcpu_svm *svm = to_svm(vcpu);
1210
1211 switch (ecx) {
1212 case MSR_IA32_TIME_STAMP_COUNTER: {
1213 u64 tsc;
1214
1215 rdtscll(tsc);
1216 *data = svm->vmcb->control.tsc_offset + tsc;
1217 break;
1218 }
1219 case MSR_K6_STAR:
1220 *data = svm->vmcb->save.star;
1221 break;
1222 #ifdef CONFIG_X86_64
1223 case MSR_LSTAR:
1224 *data = svm->vmcb->save.lstar;
1225 break;
1226 case MSR_CSTAR:
1227 *data = svm->vmcb->save.cstar;
1228 break;
1229 case MSR_KERNEL_GS_BASE:
1230 *data = svm->vmcb->save.kernel_gs_base;
1231 break;
1232 case MSR_SYSCALL_MASK:
1233 *data = svm->vmcb->save.sfmask;
1234 break;
1235 #endif
1236 case MSR_IA32_SYSENTER_CS:
1237 *data = svm->vmcb->save.sysenter_cs;
1238 break;
1239 case MSR_IA32_SYSENTER_EIP:
1240 *data = svm->vmcb->save.sysenter_eip;
1241 break;
1242 case MSR_IA32_SYSENTER_ESP:
1243 *data = svm->vmcb->save.sysenter_esp;
1244 break;
1245 /* Nobody will change the following 5 values in the VMCB so
1246 we can safely return them on rdmsr. They will always be 0
1247 until LBRV is implemented. */
1248 case MSR_IA32_DEBUGCTLMSR:
1249 *data = svm->vmcb->save.dbgctl;
1250 break;
1251 case MSR_IA32_LASTBRANCHFROMIP:
1252 *data = svm->vmcb->save.br_from;
1253 break;
1254 case MSR_IA32_LASTBRANCHTOIP:
1255 *data = svm->vmcb->save.br_to;
1256 break;
1257 case MSR_IA32_LASTINTFROMIP:
1258 *data = svm->vmcb->save.last_excp_from;
1259 break;
1260 case MSR_IA32_LASTINTTOIP:
1261 *data = svm->vmcb->save.last_excp_to;
1262 break;
1263 default:
1264 return kvm_get_msr_common(vcpu, ecx, data);
1265 }
1266 return 0;
1267 }
1268
1269 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1270 {
1271 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1272 u64 data;
1273
1274 if (svm_get_msr(&svm->vcpu, ecx, &data))
1275 kvm_inject_gp(&svm->vcpu, 0);
1276 else {
1277 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1278 (u32)(data >> 32), handler);
1279
1280 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1281 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1282 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1283 skip_emulated_instruction(&svm->vcpu);
1284 }
1285 return 1;
1286 }
1287
1288 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1289 {
1290 struct vcpu_svm *svm = to_svm(vcpu);
1291
1292 switch (ecx) {
1293 case MSR_IA32_TIME_STAMP_COUNTER: {
1294 u64 tsc;
1295
1296 rdtscll(tsc);
1297 svm->vmcb->control.tsc_offset = data - tsc;
1298 break;
1299 }
1300 case MSR_K6_STAR:
1301 svm->vmcb->save.star = data;
1302 break;
1303 #ifdef CONFIG_X86_64
1304 case MSR_LSTAR:
1305 svm->vmcb->save.lstar = data;
1306 break;
1307 case MSR_CSTAR:
1308 svm->vmcb->save.cstar = data;
1309 break;
1310 case MSR_KERNEL_GS_BASE:
1311 svm->vmcb->save.kernel_gs_base = data;
1312 break;
1313 case MSR_SYSCALL_MASK:
1314 svm->vmcb->save.sfmask = data;
1315 break;
1316 #endif
1317 case MSR_IA32_SYSENTER_CS:
1318 svm->vmcb->save.sysenter_cs = data;
1319 break;
1320 case MSR_IA32_SYSENTER_EIP:
1321 svm->vmcb->save.sysenter_eip = data;
1322 break;
1323 case MSR_IA32_SYSENTER_ESP:
1324 svm->vmcb->save.sysenter_esp = data;
1325 break;
1326 case MSR_IA32_DEBUGCTLMSR:
1327 if (!svm_has(SVM_FEATURE_LBRV)) {
1328 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1329 __func__, data);
1330 break;
1331 }
1332 if (data & DEBUGCTL_RESERVED_BITS)
1333 return 1;
1334
1335 svm->vmcb->save.dbgctl = data;
1336 if (data & (1ULL<<0))
1337 svm_enable_lbrv(svm);
1338 else
1339 svm_disable_lbrv(svm);
1340 break;
1341 case MSR_K7_EVNTSEL0:
1342 case MSR_K7_EVNTSEL1:
1343 case MSR_K7_EVNTSEL2:
1344 case MSR_K7_EVNTSEL3:
1345 case MSR_K7_PERFCTR0:
1346 case MSR_K7_PERFCTR1:
1347 case MSR_K7_PERFCTR2:
1348 case MSR_K7_PERFCTR3:
1349 /*
1350 * Just discard all writes to the performance counters; this
1351 * should keep both older linux and windows 64-bit guests
1352 * happy
1353 */
1354 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1355
1356 break;
1357 default:
1358 return kvm_set_msr_common(vcpu, ecx, data);
1359 }
1360 return 0;
1361 }
1362
1363 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1364 {
1365 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1366 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1367 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1368
1369 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1370 handler);
1371
1372 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1373 if (svm_set_msr(&svm->vcpu, ecx, data))
1374 kvm_inject_gp(&svm->vcpu, 0);
1375 else
1376 skip_emulated_instruction(&svm->vcpu);
1377 return 1;
1378 }
1379
1380 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1381 {
1382 if (svm->vmcb->control.exit_info_1)
1383 return wrmsr_interception(svm, kvm_run);
1384 else
1385 return rdmsr_interception(svm, kvm_run);
1386 }
1387
1388 static int interrupt_window_interception(struct vcpu_svm *svm,
1389 struct kvm_run *kvm_run)
1390 {
1391 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1392
1393 svm_clear_vintr(svm);
1394 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1395 /*
1396 * If the user space waits to inject interrupts, exit as soon as
1397 * possible
1398 */
1399 if (kvm_run->request_interrupt_window &&
1400 !svm->vcpu.arch.irq_summary) {
1401 ++svm->vcpu.stat.irq_window_exits;
1402 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1403 return 0;
1404 }
1405
1406 return 1;
1407 }
1408
1409 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1410 struct kvm_run *kvm_run) = {
1411 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1412 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1413 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1414 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1415 /* for now: */
1416 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1417 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1418 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1419 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1420 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1421 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1422 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1423 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1424 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1425 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1426 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1427 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1428 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1429 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1430 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1431 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1432 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1433 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
1434 [SVM_EXIT_INTR] = intr_interception,
1435 [SVM_EXIT_NMI] = nmi_interception,
1436 [SVM_EXIT_SMI] = nop_on_interception,
1437 [SVM_EXIT_INIT] = nop_on_interception,
1438 [SVM_EXIT_VINTR] = interrupt_window_interception,
1439 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1440 [SVM_EXIT_CPUID] = cpuid_interception,
1441 [SVM_EXIT_INVD] = emulate_on_interception,
1442 [SVM_EXIT_HLT] = halt_interception,
1443 [SVM_EXIT_INVLPG] = invlpg_interception,
1444 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1445 [SVM_EXIT_IOIO] = io_interception,
1446 [SVM_EXIT_MSR] = msr_interception,
1447 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1448 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1449 [SVM_EXIT_VMRUN] = invalid_op_interception,
1450 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1451 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1452 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1453 [SVM_EXIT_STGI] = invalid_op_interception,
1454 [SVM_EXIT_CLGI] = invalid_op_interception,
1455 [SVM_EXIT_SKINIT] = invalid_op_interception,
1456 [SVM_EXIT_WBINVD] = emulate_on_interception,
1457 [SVM_EXIT_MONITOR] = invalid_op_interception,
1458 [SVM_EXIT_MWAIT] = invalid_op_interception,
1459 [SVM_EXIT_NPF] = pf_interception,
1460 };
1461
1462 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1463 {
1464 struct vcpu_svm *svm = to_svm(vcpu);
1465 u32 exit_code = svm->vmcb->control.exit_code;
1466
1467 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1468 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1469
1470 if (npt_enabled) {
1471 int mmu_reload = 0;
1472 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1473 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1474 mmu_reload = 1;
1475 }
1476 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1477 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1478 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1479 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1480 kvm_inject_gp(vcpu, 0);
1481 return 1;
1482 }
1483 }
1484 if (mmu_reload) {
1485 kvm_mmu_reset_context(vcpu);
1486 kvm_mmu_load(vcpu);
1487 }
1488 }
1489
1490 kvm_reput_irq(svm);
1491
1492 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1493 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1494 kvm_run->fail_entry.hardware_entry_failure_reason
1495 = svm->vmcb->control.exit_code;
1496 return 0;
1497 }
1498
1499 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1500 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1501 exit_code != SVM_EXIT_NPF)
1502 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1503 "exit_code 0x%x\n",
1504 __func__, svm->vmcb->control.exit_int_info,
1505 exit_code);
1506
1507 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1508 || !svm_exit_handlers[exit_code]) {
1509 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1510 kvm_run->hw.hardware_exit_reason = exit_code;
1511 return 0;
1512 }
1513
1514 return svm_exit_handlers[exit_code](svm, kvm_run);
1515 }
1516
1517 static void reload_tss(struct kvm_vcpu *vcpu)
1518 {
1519 int cpu = raw_smp_processor_id();
1520
1521 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1522 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1523 load_TR_desc();
1524 }
1525
1526 static void pre_svm_run(struct vcpu_svm *svm)
1527 {
1528 int cpu = raw_smp_processor_id();
1529
1530 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1531
1532 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1533 if (svm->vcpu.cpu != cpu ||
1534 svm->asid_generation != svm_data->asid_generation)
1535 new_asid(svm, svm_data);
1536 }
1537
1538
1539 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1540 {
1541 struct vmcb_control_area *control;
1542
1543 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1544
1545 ++svm->vcpu.stat.irq_injections;
1546 control = &svm->vmcb->control;
1547 control->int_vector = irq;
1548 control->int_ctl &= ~V_INTR_PRIO_MASK;
1549 control->int_ctl |= V_IRQ_MASK |
1550 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1551 }
1552
1553 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1554 {
1555 struct vcpu_svm *svm = to_svm(vcpu);
1556
1557 svm_inject_irq(svm, irq);
1558 }
1559
1560 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1561 {
1562 struct vcpu_svm *svm = to_svm(vcpu);
1563 struct vmcb *vmcb = svm->vmcb;
1564 int max_irr, tpr;
1565
1566 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1567 return;
1568
1569 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1570
1571 max_irr = kvm_lapic_find_highest_irr(vcpu);
1572 if (max_irr == -1)
1573 return;
1574
1575 tpr = kvm_lapic_get_cr8(vcpu) << 4;
1576
1577 if (tpr >= (max_irr & 0xf0))
1578 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1579 }
1580
1581 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1582 {
1583 struct vcpu_svm *svm = to_svm(vcpu);
1584 struct vmcb *vmcb = svm->vmcb;
1585 int intr_vector = -1;
1586
1587 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1588 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1589 intr_vector = vmcb->control.exit_int_info &
1590 SVM_EVTINJ_VEC_MASK;
1591 vmcb->control.exit_int_info = 0;
1592 svm_inject_irq(svm, intr_vector);
1593 goto out;
1594 }
1595
1596 if (vmcb->control.int_ctl & V_IRQ_MASK)
1597 goto out;
1598
1599 if (!kvm_cpu_has_interrupt(vcpu))
1600 goto out;
1601
1602 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1603 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1604 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1605 /* unable to deliver irq, set pending irq */
1606 svm_set_vintr(svm);
1607 svm_inject_irq(svm, 0x0);
1608 goto out;
1609 }
1610 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1611 intr_vector = kvm_cpu_get_interrupt(vcpu);
1612 svm_inject_irq(svm, intr_vector);
1613 out:
1614 update_cr8_intercept(vcpu);
1615 }
1616
1617 static void kvm_reput_irq(struct vcpu_svm *svm)
1618 {
1619 struct vmcb_control_area *control = &svm->vmcb->control;
1620
1621 if ((control->int_ctl & V_IRQ_MASK)
1622 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1623 control->int_ctl &= ~V_IRQ_MASK;
1624 push_irq(&svm->vcpu, control->int_vector);
1625 }
1626
1627 svm->vcpu.arch.interrupt_window_open =
1628 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1629 }
1630
1631 static void svm_do_inject_vector(struct vcpu_svm *svm)
1632 {
1633 struct kvm_vcpu *vcpu = &svm->vcpu;
1634 int word_index = __ffs(vcpu->arch.irq_summary);
1635 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1636 int irq = word_index * BITS_PER_LONG + bit_index;
1637
1638 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1639 if (!vcpu->arch.irq_pending[word_index])
1640 clear_bit(word_index, &vcpu->arch.irq_summary);
1641 svm_inject_irq(svm, irq);
1642 }
1643
1644 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1645 struct kvm_run *kvm_run)
1646 {
1647 struct vcpu_svm *svm = to_svm(vcpu);
1648 struct vmcb_control_area *control = &svm->vmcb->control;
1649
1650 svm->vcpu.arch.interrupt_window_open =
1651 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1652 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1653
1654 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1655 /*
1656 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1657 */
1658 svm_do_inject_vector(svm);
1659
1660 /*
1661 * Interrupts blocked. Wait for unblock.
1662 */
1663 if (!svm->vcpu.arch.interrupt_window_open &&
1664 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1665 svm_set_vintr(svm);
1666 else
1667 svm_clear_vintr(svm);
1668 }
1669
1670 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1671 {
1672 return 0;
1673 }
1674
1675 static void save_db_regs(unsigned long *db_regs)
1676 {
1677 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1678 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1679 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1680 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1681 }
1682
1683 static void load_db_regs(unsigned long *db_regs)
1684 {
1685 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1686 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1687 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1688 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1689 }
1690
1691 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1692 {
1693 force_new_asid(vcpu);
1694 }
1695
1696 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1697 {
1698 }
1699
1700 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1701 {
1702 struct vcpu_svm *svm = to_svm(vcpu);
1703
1704 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1705 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1706 kvm_lapic_set_tpr(vcpu, cr8);
1707 }
1708 }
1709
1710 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1711 {
1712 struct vcpu_svm *svm = to_svm(vcpu);
1713 u64 cr8;
1714
1715 if (!irqchip_in_kernel(vcpu->kvm))
1716 return;
1717
1718 cr8 = kvm_get_cr8(vcpu);
1719 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1720 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1721 }
1722
1723 #ifdef CONFIG_X86_64
1724 #define R "r"
1725 #else
1726 #define R "e"
1727 #endif
1728
1729 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1730 {
1731 struct vcpu_svm *svm = to_svm(vcpu);
1732 u16 fs_selector;
1733 u16 gs_selector;
1734 u16 ldt_selector;
1735
1736 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1737 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1738 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1739
1740 pre_svm_run(svm);
1741
1742 sync_lapic_to_cr8(vcpu);
1743
1744 save_host_msrs(vcpu);
1745 fs_selector = kvm_read_fs();
1746 gs_selector = kvm_read_gs();
1747 ldt_selector = kvm_read_ldt();
1748 svm->host_cr2 = kvm_read_cr2();
1749 svm->host_dr6 = read_dr6();
1750 svm->host_dr7 = read_dr7();
1751 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1752 /* required for live migration with NPT */
1753 if (npt_enabled)
1754 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1755
1756 if (svm->vmcb->save.dr7 & 0xff) {
1757 write_dr7(0);
1758 save_db_regs(svm->host_db_regs);
1759 load_db_regs(svm->db_regs);
1760 }
1761
1762 clgi();
1763
1764 local_irq_enable();
1765
1766 asm volatile (
1767 "push %%"R"bp; \n\t"
1768 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1769 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1770 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1771 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1772 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1773 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1774 #ifdef CONFIG_X86_64
1775 "mov %c[r8](%[svm]), %%r8 \n\t"
1776 "mov %c[r9](%[svm]), %%r9 \n\t"
1777 "mov %c[r10](%[svm]), %%r10 \n\t"
1778 "mov %c[r11](%[svm]), %%r11 \n\t"
1779 "mov %c[r12](%[svm]), %%r12 \n\t"
1780 "mov %c[r13](%[svm]), %%r13 \n\t"
1781 "mov %c[r14](%[svm]), %%r14 \n\t"
1782 "mov %c[r15](%[svm]), %%r15 \n\t"
1783 #endif
1784
1785 /* Enter guest mode */
1786 "push %%"R"ax \n\t"
1787 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1788 __ex(SVM_VMLOAD) "\n\t"
1789 __ex(SVM_VMRUN) "\n\t"
1790 __ex(SVM_VMSAVE) "\n\t"
1791 "pop %%"R"ax \n\t"
1792
1793 /* Save guest registers, load host registers */
1794 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1795 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1796 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1797 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1798 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1799 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1800 #ifdef CONFIG_X86_64
1801 "mov %%r8, %c[r8](%[svm]) \n\t"
1802 "mov %%r9, %c[r9](%[svm]) \n\t"
1803 "mov %%r10, %c[r10](%[svm]) \n\t"
1804 "mov %%r11, %c[r11](%[svm]) \n\t"
1805 "mov %%r12, %c[r12](%[svm]) \n\t"
1806 "mov %%r13, %c[r13](%[svm]) \n\t"
1807 "mov %%r14, %c[r14](%[svm]) \n\t"
1808 "mov %%r15, %c[r15](%[svm]) \n\t"
1809 #endif
1810 "pop %%"R"bp"
1811 :
1812 : [svm]"a"(svm),
1813 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1814 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1815 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1816 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1817 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1818 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1819 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1820 #ifdef CONFIG_X86_64
1821 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1822 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1823 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1824 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1825 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1826 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1827 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1828 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1829 #endif
1830 : "cc", "memory"
1831 , R"bx", R"cx", R"dx", R"si", R"di"
1832 #ifdef CONFIG_X86_64
1833 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1834 #endif
1835 );
1836
1837 if ((svm->vmcb->save.dr7 & 0xff))
1838 load_db_regs(svm->host_db_regs);
1839
1840 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1841 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1842 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1843 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1844
1845 write_dr6(svm->host_dr6);
1846 write_dr7(svm->host_dr7);
1847 kvm_write_cr2(svm->host_cr2);
1848
1849 kvm_load_fs(fs_selector);
1850 kvm_load_gs(gs_selector);
1851 kvm_load_ldt(ldt_selector);
1852 load_host_msrs(vcpu);
1853
1854 reload_tss(vcpu);
1855
1856 local_irq_disable();
1857
1858 stgi();
1859
1860 sync_cr8_to_lapic(vcpu);
1861
1862 svm->next_rip = 0;
1863 }
1864
1865 #undef R
1866
1867 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1868 {
1869 struct vcpu_svm *svm = to_svm(vcpu);
1870
1871 if (npt_enabled) {
1872 svm->vmcb->control.nested_cr3 = root;
1873 force_new_asid(vcpu);
1874 return;
1875 }
1876
1877 svm->vmcb->save.cr3 = root;
1878 force_new_asid(vcpu);
1879
1880 if (vcpu->fpu_active) {
1881 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1882 svm->vmcb->save.cr0 |= X86_CR0_TS;
1883 vcpu->fpu_active = 0;
1884 }
1885 }
1886
1887 static int is_disabled(void)
1888 {
1889 u64 vm_cr;
1890
1891 rdmsrl(MSR_VM_CR, vm_cr);
1892 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1893 return 1;
1894
1895 return 0;
1896 }
1897
1898 static void
1899 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1900 {
1901 /*
1902 * Patch in the VMMCALL instruction:
1903 */
1904 hypercall[0] = 0x0f;
1905 hypercall[1] = 0x01;
1906 hypercall[2] = 0xd9;
1907 }
1908
1909 static void svm_check_processor_compat(void *rtn)
1910 {
1911 *(int *)rtn = 0;
1912 }
1913
1914 static bool svm_cpu_has_accelerated_tpr(void)
1915 {
1916 return false;
1917 }
1918
1919 static int get_npt_level(void)
1920 {
1921 #ifdef CONFIG_X86_64
1922 return PT64_ROOT_LEVEL;
1923 #else
1924 return PT32E_ROOT_LEVEL;
1925 #endif
1926 }
1927
1928 static int svm_get_mt_mask_shift(void)
1929 {
1930 return 0;
1931 }
1932
1933 static struct kvm_x86_ops svm_x86_ops = {
1934 .cpu_has_kvm_support = has_svm,
1935 .disabled_by_bios = is_disabled,
1936 .hardware_setup = svm_hardware_setup,
1937 .hardware_unsetup = svm_hardware_unsetup,
1938 .check_processor_compatibility = svm_check_processor_compat,
1939 .hardware_enable = svm_hardware_enable,
1940 .hardware_disable = svm_hardware_disable,
1941 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1942
1943 .vcpu_create = svm_create_vcpu,
1944 .vcpu_free = svm_free_vcpu,
1945 .vcpu_reset = svm_vcpu_reset,
1946
1947 .prepare_guest_switch = svm_prepare_guest_switch,
1948 .vcpu_load = svm_vcpu_load,
1949 .vcpu_put = svm_vcpu_put,
1950
1951 .set_guest_debug = svm_guest_debug,
1952 .get_msr = svm_get_msr,
1953 .set_msr = svm_set_msr,
1954 .get_segment_base = svm_get_segment_base,
1955 .get_segment = svm_get_segment,
1956 .set_segment = svm_set_segment,
1957 .get_cpl = svm_get_cpl,
1958 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1959 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1960 .set_cr0 = svm_set_cr0,
1961 .set_cr3 = svm_set_cr3,
1962 .set_cr4 = svm_set_cr4,
1963 .set_efer = svm_set_efer,
1964 .get_idt = svm_get_idt,
1965 .set_idt = svm_set_idt,
1966 .get_gdt = svm_get_gdt,
1967 .set_gdt = svm_set_gdt,
1968 .get_dr = svm_get_dr,
1969 .set_dr = svm_set_dr,
1970 .get_rflags = svm_get_rflags,
1971 .set_rflags = svm_set_rflags,
1972
1973 .tlb_flush = svm_flush_tlb,
1974
1975 .run = svm_vcpu_run,
1976 .handle_exit = handle_exit,
1977 .skip_emulated_instruction = skip_emulated_instruction,
1978 .patch_hypercall = svm_patch_hypercall,
1979 .get_irq = svm_get_irq,
1980 .set_irq = svm_set_irq,
1981 .queue_exception = svm_queue_exception,
1982 .exception_injected = svm_exception_injected,
1983 .inject_pending_irq = svm_intr_assist,
1984 .inject_pending_vectors = do_interrupt_requests,
1985
1986 .set_tss_addr = svm_set_tss_addr,
1987 .get_tdp_level = get_npt_level,
1988 .get_mt_mask_shift = svm_get_mt_mask_shift,
1989 };
1990
1991 static int __init svm_init(void)
1992 {
1993 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1994 THIS_MODULE);
1995 }
1996
1997 static void __exit svm_exit(void)
1998 {
1999 kvm_exit();
2000 }
2001
2002 module_init(svm_init)
2003 module_exit(svm_exit)
Linux kernel - Deliverables
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