2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv_reg_vid
;
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
94 static bool __read_mostly nested
= 0;
95 module_param(nested
, bool, S_IRUGO
);
97 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
99 #define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
101 #define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
105 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
114 * According to test, this time is usually smaller than 128 cycles.
115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 #define KVM_VMX_DEFAULT_PLE_GAP 128
122 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
124 module_param(ple_gap
, int, S_IRUGO
);
126 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
127 module_param(ple_window
, int, S_IRUGO
);
129 extern const ulong vmx_return
;
131 #define NR_AUTOLOAD_MSRS 8
132 #define VMCS02_POOL_SIZE 1
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
149 struct list_head loaded_vmcss_on_cpu_link
;
152 struct shared_msr_entry
{
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 typedef u64 natural_width
;
172 struct __packed vmcs12
{
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
179 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding
[7]; /* room for future expansion */
185 u64 vm_exit_msr_store_addr
;
186 u64 vm_exit_msr_load_addr
;
187 u64 vm_entry_msr_load_addr
;
189 u64 virtual_apic_page_addr
;
190 u64 apic_access_addr
;
192 u64 guest_physical_address
;
193 u64 vmcs_link_pointer
;
194 u64 guest_ia32_debugctl
;
197 u64 guest_ia32_perf_global_ctrl
;
204 u64 host_ia32_perf_global_ctrl
;
205 u64 padding64
[8]; /* room for future expansion */
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
212 natural_width cr0_guest_host_mask
;
213 natural_width cr4_guest_host_mask
;
214 natural_width cr0_read_shadow
;
215 natural_width cr4_read_shadow
;
216 natural_width cr3_target_value0
;
217 natural_width cr3_target_value1
;
218 natural_width cr3_target_value2
;
219 natural_width cr3_target_value3
;
220 natural_width exit_qualification
;
221 natural_width guest_linear_address
;
222 natural_width guest_cr0
;
223 natural_width guest_cr3
;
224 natural_width guest_cr4
;
225 natural_width guest_es_base
;
226 natural_width guest_cs_base
;
227 natural_width guest_ss_base
;
228 natural_width guest_ds_base
;
229 natural_width guest_fs_base
;
230 natural_width guest_gs_base
;
231 natural_width guest_ldtr_base
;
232 natural_width guest_tr_base
;
233 natural_width guest_gdtr_base
;
234 natural_width guest_idtr_base
;
235 natural_width guest_dr7
;
236 natural_width guest_rsp
;
237 natural_width guest_rip
;
238 natural_width guest_rflags
;
239 natural_width guest_pending_dbg_exceptions
;
240 natural_width guest_sysenter_esp
;
241 natural_width guest_sysenter_eip
;
242 natural_width host_cr0
;
243 natural_width host_cr3
;
244 natural_width host_cr4
;
245 natural_width host_fs_base
;
246 natural_width host_gs_base
;
247 natural_width host_tr_base
;
248 natural_width host_gdtr_base
;
249 natural_width host_idtr_base
;
250 natural_width host_ia32_sysenter_esp
;
251 natural_width host_ia32_sysenter_eip
;
252 natural_width host_rsp
;
253 natural_width host_rip
;
254 natural_width paddingl
[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control
;
256 u32 cpu_based_vm_exec_control
;
257 u32 exception_bitmap
;
258 u32 page_fault_error_code_mask
;
259 u32 page_fault_error_code_match
;
260 u32 cr3_target_count
;
261 u32 vm_exit_controls
;
262 u32 vm_exit_msr_store_count
;
263 u32 vm_exit_msr_load_count
;
264 u32 vm_entry_controls
;
265 u32 vm_entry_msr_load_count
;
266 u32 vm_entry_intr_info_field
;
267 u32 vm_entry_exception_error_code
;
268 u32 vm_entry_instruction_len
;
270 u32 secondary_vm_exec_control
;
271 u32 vm_instruction_error
;
273 u32 vm_exit_intr_info
;
274 u32 vm_exit_intr_error_code
;
275 u32 idt_vectoring_info_field
;
276 u32 idt_vectoring_error_code
;
277 u32 vm_exit_instruction_len
;
278 u32 vmx_instruction_info
;
285 u32 guest_ldtr_limit
;
287 u32 guest_gdtr_limit
;
288 u32 guest_idtr_limit
;
289 u32 guest_es_ar_bytes
;
290 u32 guest_cs_ar_bytes
;
291 u32 guest_ss_ar_bytes
;
292 u32 guest_ds_ar_bytes
;
293 u32 guest_fs_ar_bytes
;
294 u32 guest_gs_ar_bytes
;
295 u32 guest_ldtr_ar_bytes
;
296 u32 guest_tr_ar_bytes
;
297 u32 guest_interruptibility_info
;
298 u32 guest_activity_state
;
299 u32 guest_sysenter_cs
;
300 u32 host_ia32_sysenter_cs
;
301 u32 padding32
[8]; /* room for future expansion */
302 u16 virtual_processor_id
;
303 u16 guest_es_selector
;
304 u16 guest_cs_selector
;
305 u16 guest_ss_selector
;
306 u16 guest_ds_selector
;
307 u16 guest_fs_selector
;
308 u16 guest_gs_selector
;
309 u16 guest_ldtr_selector
;
310 u16 guest_tr_selector
;
311 u16 host_es_selector
;
312 u16 host_cs_selector
;
313 u16 host_ss_selector
;
314 u16 host_ds_selector
;
315 u16 host_fs_selector
;
316 u16 host_gs_selector
;
317 u16 host_tr_selector
;
321 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
322 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
323 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 #define VMCS12_REVISION 0x11e57ed0
328 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
329 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
330 * current implementation, 4K are reserved to avoid future complications.
332 #define VMCS12_SIZE 0x1000
334 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
336 struct list_head list
;
338 struct loaded_vmcs vmcs02
;
342 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
343 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
346 /* Has the level1 guest done vmxon? */
349 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 /* The host-usable pointer to the above */
352 struct page
*current_vmcs12_page
;
353 struct vmcs12
*current_vmcs12
;
355 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
356 struct list_head vmcs02_pool
;
358 u64 vmcs01_tsc_offset
;
359 /* L2 must run next, and mustn't decide to exit to L1. */
360 bool nested_run_pending
;
362 * Guest pages referred to in vmcs02 with host-physical pointers, so
363 * we must keep them pinned while L2 runs.
365 struct page
*apic_access_page
;
369 struct kvm_vcpu vcpu
;
370 unsigned long host_rsp
;
373 bool nmi_known_unmasked
;
375 u32 idt_vectoring_info
;
377 struct shared_msr_entry
*guest_msrs
;
381 u64 msr_host_kernel_gs_base
;
382 u64 msr_guest_kernel_gs_base
;
385 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
386 * non-nested (L1) guest, it always points to vmcs01. For a nested
387 * guest (L2), it points to a different VMCS.
389 struct loaded_vmcs vmcs01
;
390 struct loaded_vmcs
*loaded_vmcs
;
391 bool __launched
; /* temporary, used in vmx_vcpu_run */
392 struct msr_autoload
{
394 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
395 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
399 u16 fs_sel
, gs_sel
, ldt_sel
;
403 int gs_ldt_reload_needed
;
404 int fs_reload_needed
;
409 struct kvm_segment segs
[8];
412 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
413 struct kvm_save_segment
{
421 bool emulation_required
;
423 /* Support for vnmi-less CPUs */
424 int soft_vnmi_blocked
;
426 s64 vnmi_blocked_time
;
431 /* Support for a guest hypervisor (nested VMX) */
432 struct nested_vmx nested
;
435 enum segment_cache_field
{
444 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
446 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
449 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
450 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
451 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
452 [number##_HIGH] = VMCS12_OFFSET(name)+4
454 static const unsigned short vmcs_field_to_offset_table
[] = {
455 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
456 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
457 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
458 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
459 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
460 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
461 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
462 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
463 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
464 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
465 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
466 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
467 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
468 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
469 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
470 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
471 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
472 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
473 FIELD64(MSR_BITMAP
, msr_bitmap
),
474 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
475 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
476 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
477 FIELD64(TSC_OFFSET
, tsc_offset
),
478 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
479 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
480 FIELD64(EPT_POINTER
, ept_pointer
),
481 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
482 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
483 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
484 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
485 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
486 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
487 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
488 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
489 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
490 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
491 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
492 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
493 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
494 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
495 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
496 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
497 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
498 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
499 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
500 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
501 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
502 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
503 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
504 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
505 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
506 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
507 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
508 FIELD(TPR_THRESHOLD
, tpr_threshold
),
509 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
510 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
511 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
512 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
513 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
514 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
515 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
516 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
517 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
518 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
519 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
520 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
521 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
522 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
523 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
524 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
525 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
526 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
527 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
528 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
529 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
530 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
531 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
532 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
533 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
534 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
535 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
536 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
537 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
538 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
539 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
540 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
541 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
542 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
543 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
544 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
545 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
546 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
547 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
548 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
549 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
550 FIELD(GUEST_CR0
, guest_cr0
),
551 FIELD(GUEST_CR3
, guest_cr3
),
552 FIELD(GUEST_CR4
, guest_cr4
),
553 FIELD(GUEST_ES_BASE
, guest_es_base
),
554 FIELD(GUEST_CS_BASE
, guest_cs_base
),
555 FIELD(GUEST_SS_BASE
, guest_ss_base
),
556 FIELD(GUEST_DS_BASE
, guest_ds_base
),
557 FIELD(GUEST_FS_BASE
, guest_fs_base
),
558 FIELD(GUEST_GS_BASE
, guest_gs_base
),
559 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
560 FIELD(GUEST_TR_BASE
, guest_tr_base
),
561 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
562 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
563 FIELD(GUEST_DR7
, guest_dr7
),
564 FIELD(GUEST_RSP
, guest_rsp
),
565 FIELD(GUEST_RIP
, guest_rip
),
566 FIELD(GUEST_RFLAGS
, guest_rflags
),
567 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
568 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
569 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
570 FIELD(HOST_CR0
, host_cr0
),
571 FIELD(HOST_CR3
, host_cr3
),
572 FIELD(HOST_CR4
, host_cr4
),
573 FIELD(HOST_FS_BASE
, host_fs_base
),
574 FIELD(HOST_GS_BASE
, host_gs_base
),
575 FIELD(HOST_TR_BASE
, host_tr_base
),
576 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
577 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
578 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
579 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
580 FIELD(HOST_RSP
, host_rsp
),
581 FIELD(HOST_RIP
, host_rip
),
583 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
585 static inline short vmcs_field_to_offset(unsigned long field
)
587 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
589 return vmcs_field_to_offset_table
[field
];
592 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
594 return to_vmx(vcpu
)->nested
.current_vmcs12
;
597 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
599 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
600 if (is_error_page(page
))
606 static void nested_release_page(struct page
*page
)
608 kvm_release_page_dirty(page
);
611 static void nested_release_page_clean(struct page
*page
)
613 kvm_release_page_clean(page
);
616 static u64
construct_eptp(unsigned long root_hpa
);
617 static void kvm_cpu_vmxon(u64 addr
);
618 static void kvm_cpu_vmxoff(void);
619 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
620 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
621 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
622 struct kvm_segment
*var
, int seg
);
623 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
624 struct kvm_segment
*var
, int seg
);
625 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
626 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
628 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
629 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
631 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
632 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
634 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
635 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
637 static unsigned long *vmx_io_bitmap_a
;
638 static unsigned long *vmx_io_bitmap_b
;
639 static unsigned long *vmx_msr_bitmap_legacy
;
640 static unsigned long *vmx_msr_bitmap_longmode
;
641 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
642 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
644 static bool cpu_has_load_ia32_efer
;
645 static bool cpu_has_load_perf_global_ctrl
;
647 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
648 static DEFINE_SPINLOCK(vmx_vpid_lock
);
650 static struct vmcs_config
{
654 u32 pin_based_exec_ctrl
;
655 u32 cpu_based_exec_ctrl
;
656 u32 cpu_based_2nd_exec_ctrl
;
661 static struct vmx_capability
{
666 #define VMX_SEGMENT_FIELD(seg) \
667 [VCPU_SREG_##seg] = { \
668 .selector = GUEST_##seg##_SELECTOR, \
669 .base = GUEST_##seg##_BASE, \
670 .limit = GUEST_##seg##_LIMIT, \
671 .ar_bytes = GUEST_##seg##_AR_BYTES, \
674 static const struct kvm_vmx_segment_field
{
679 } kvm_vmx_segment_fields
[] = {
680 VMX_SEGMENT_FIELD(CS
),
681 VMX_SEGMENT_FIELD(DS
),
682 VMX_SEGMENT_FIELD(ES
),
683 VMX_SEGMENT_FIELD(FS
),
684 VMX_SEGMENT_FIELD(GS
),
685 VMX_SEGMENT_FIELD(SS
),
686 VMX_SEGMENT_FIELD(TR
),
687 VMX_SEGMENT_FIELD(LDTR
),
690 static u64 host_efer
;
692 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
695 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
696 * away by decrementing the array size.
698 static const u32 vmx_msr_index
[] = {
700 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
702 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
704 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
706 static inline bool is_page_fault(u32 intr_info
)
708 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
709 INTR_INFO_VALID_MASK
)) ==
710 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
713 static inline bool is_no_device(u32 intr_info
)
715 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
716 INTR_INFO_VALID_MASK
)) ==
717 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
720 static inline bool is_invalid_opcode(u32 intr_info
)
722 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
723 INTR_INFO_VALID_MASK
)) ==
724 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
727 static inline bool is_external_interrupt(u32 intr_info
)
729 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
730 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
733 static inline bool is_machine_check(u32 intr_info
)
735 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
736 INTR_INFO_VALID_MASK
)) ==
737 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
740 static inline bool cpu_has_vmx_msr_bitmap(void)
742 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
745 static inline bool cpu_has_vmx_tpr_shadow(void)
747 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
750 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
752 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
755 static inline bool cpu_has_secondary_exec_ctrls(void)
757 return vmcs_config
.cpu_based_exec_ctrl
&
758 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
761 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
763 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
764 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
767 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
769 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
770 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
773 static inline bool cpu_has_vmx_apic_register_virt(void)
775 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
776 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
779 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
781 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
782 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
785 static inline bool cpu_has_vmx_flexpriority(void)
787 return cpu_has_vmx_tpr_shadow() &&
788 cpu_has_vmx_virtualize_apic_accesses();
791 static inline bool cpu_has_vmx_ept_execute_only(void)
793 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
796 static inline bool cpu_has_vmx_eptp_uncacheable(void)
798 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
801 static inline bool cpu_has_vmx_eptp_writeback(void)
803 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
806 static inline bool cpu_has_vmx_ept_2m_page(void)
808 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
811 static inline bool cpu_has_vmx_ept_1g_page(void)
813 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
816 static inline bool cpu_has_vmx_ept_4levels(void)
818 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
821 static inline bool cpu_has_vmx_ept_ad_bits(void)
823 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
826 static inline bool cpu_has_vmx_invept_context(void)
828 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
831 static inline bool cpu_has_vmx_invept_global(void)
833 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
836 static inline bool cpu_has_vmx_invvpid_single(void)
838 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
841 static inline bool cpu_has_vmx_invvpid_global(void)
843 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
846 static inline bool cpu_has_vmx_ept(void)
848 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
849 SECONDARY_EXEC_ENABLE_EPT
;
852 static inline bool cpu_has_vmx_unrestricted_guest(void)
854 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
855 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
858 static inline bool cpu_has_vmx_ple(void)
860 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
861 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
864 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
866 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
869 static inline bool cpu_has_vmx_vpid(void)
871 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
872 SECONDARY_EXEC_ENABLE_VPID
;
875 static inline bool cpu_has_vmx_rdtscp(void)
877 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
878 SECONDARY_EXEC_RDTSCP
;
881 static inline bool cpu_has_vmx_invpcid(void)
883 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
884 SECONDARY_EXEC_ENABLE_INVPCID
;
887 static inline bool cpu_has_virtual_nmis(void)
889 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
892 static inline bool cpu_has_vmx_wbinvd_exit(void)
894 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
895 SECONDARY_EXEC_WBINVD_EXITING
;
898 static inline bool report_flexpriority(void)
900 return flexpriority_enabled
;
903 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
905 return vmcs12
->cpu_based_vm_exec_control
& bit
;
908 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
910 return (vmcs12
->cpu_based_vm_exec_control
&
911 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
912 (vmcs12
->secondary_vm_exec_control
& bit
);
915 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
916 struct kvm_vcpu
*vcpu
)
918 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
921 static inline bool is_exception(u32 intr_info
)
923 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
924 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
927 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
928 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
929 struct vmcs12
*vmcs12
,
930 u32 reason
, unsigned long qualification
);
932 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
936 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
937 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
942 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
948 } operand
= { vpid
, 0, gva
};
950 asm volatile (__ex(ASM_VMX_INVVPID
)
951 /* CF==1 or ZF==1 --> rc = -1 */
953 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
956 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
960 } operand
= {eptp
, gpa
};
962 asm volatile (__ex(ASM_VMX_INVEPT
)
963 /* CF==1 or ZF==1 --> rc = -1 */
964 "; ja 1f ; ud2 ; 1:\n"
965 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
968 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
972 i
= __find_msr_index(vmx
, msr
);
974 return &vmx
->guest_msrs
[i
];
978 static void vmcs_clear(struct vmcs
*vmcs
)
980 u64 phys_addr
= __pa(vmcs
);
983 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
984 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
987 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
991 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
993 vmcs_clear(loaded_vmcs
->vmcs
);
994 loaded_vmcs
->cpu
= -1;
995 loaded_vmcs
->launched
= 0;
998 static void vmcs_load(struct vmcs
*vmcs
)
1000 u64 phys_addr
= __pa(vmcs
);
1003 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1004 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1007 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1013 * This bitmap is used to indicate whether the vmclear
1014 * operation is enabled on all cpus. All disabled by
1017 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1019 static inline void crash_enable_local_vmclear(int cpu
)
1021 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1024 static inline void crash_disable_local_vmclear(int cpu
)
1026 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1029 static inline int crash_local_vmclear_enabled(int cpu
)
1031 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1034 static void crash_vmclear_local_loaded_vmcss(void)
1036 int cpu
= raw_smp_processor_id();
1037 struct loaded_vmcs
*v
;
1039 if (!crash_local_vmclear_enabled(cpu
))
1042 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1043 loaded_vmcss_on_cpu_link
)
1044 vmcs_clear(v
->vmcs
);
1047 static inline void crash_enable_local_vmclear(int cpu
) { }
1048 static inline void crash_disable_local_vmclear(int cpu
) { }
1049 #endif /* CONFIG_KEXEC */
1051 static void __loaded_vmcs_clear(void *arg
)
1053 struct loaded_vmcs
*loaded_vmcs
= arg
;
1054 int cpu
= raw_smp_processor_id();
1056 if (loaded_vmcs
->cpu
!= cpu
)
1057 return; /* vcpu migration can race with cpu offline */
1058 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1059 per_cpu(current_vmcs
, cpu
) = NULL
;
1060 crash_disable_local_vmclear(cpu
);
1061 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1064 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1065 * is before setting loaded_vmcs->vcpu to -1 which is done in
1066 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1067 * then adds the vmcs into percpu list before it is deleted.
1071 loaded_vmcs_init(loaded_vmcs
);
1072 crash_enable_local_vmclear(cpu
);
1075 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1077 int cpu
= loaded_vmcs
->cpu
;
1080 smp_call_function_single(cpu
,
1081 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1084 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1089 if (cpu_has_vmx_invvpid_single())
1090 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1093 static inline void vpid_sync_vcpu_global(void)
1095 if (cpu_has_vmx_invvpid_global())
1096 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1099 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1101 if (cpu_has_vmx_invvpid_single())
1102 vpid_sync_vcpu_single(vmx
);
1104 vpid_sync_vcpu_global();
1107 static inline void ept_sync_global(void)
1109 if (cpu_has_vmx_invept_global())
1110 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1113 static inline void ept_sync_context(u64 eptp
)
1116 if (cpu_has_vmx_invept_context())
1117 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1123 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1125 unsigned long value
;
1127 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1128 : "=a"(value
) : "d"(field
) : "cc");
1132 static __always_inline u16
vmcs_read16(unsigned long field
)
1134 return vmcs_readl(field
);
1137 static __always_inline u32
vmcs_read32(unsigned long field
)
1139 return vmcs_readl(field
);
1142 static __always_inline u64
vmcs_read64(unsigned long field
)
1144 #ifdef CONFIG_X86_64
1145 return vmcs_readl(field
);
1147 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1151 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1153 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1154 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1158 static void vmcs_writel(unsigned long field
, unsigned long value
)
1162 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1163 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1164 if (unlikely(error
))
1165 vmwrite_error(field
, value
);
1168 static void vmcs_write16(unsigned long field
, u16 value
)
1170 vmcs_writel(field
, value
);
1173 static void vmcs_write32(unsigned long field
, u32 value
)
1175 vmcs_writel(field
, value
);
1178 static void vmcs_write64(unsigned long field
, u64 value
)
1180 vmcs_writel(field
, value
);
1181 #ifndef CONFIG_X86_64
1183 vmcs_writel(field
+1, value
>> 32);
1187 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1189 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1192 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1194 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1197 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1199 vmx
->segment_cache
.bitmask
= 0;
1202 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1206 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1208 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1209 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1210 vmx
->segment_cache
.bitmask
= 0;
1212 ret
= vmx
->segment_cache
.bitmask
& mask
;
1213 vmx
->segment_cache
.bitmask
|= mask
;
1217 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1219 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1221 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1222 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1226 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1228 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1230 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1231 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1235 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1237 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1239 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1240 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1244 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1246 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1248 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1249 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1253 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1257 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1258 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1259 if ((vcpu
->guest_debug
&
1260 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1261 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1262 eb
|= 1u << BP_VECTOR
;
1263 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1266 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1267 if (vcpu
->fpu_active
)
1268 eb
&= ~(1u << NM_VECTOR
);
1270 /* When we are running a nested L2 guest and L1 specified for it a
1271 * certain exception bitmap, we must trap the same exceptions and pass
1272 * them to L1. When running L2, we will only handle the exceptions
1273 * specified above if L1 did not want them.
1275 if (is_guest_mode(vcpu
))
1276 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1278 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1281 static void clear_atomic_switch_msr_special(unsigned long entry
,
1284 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1285 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1288 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1291 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1295 if (cpu_has_load_ia32_efer
) {
1296 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1297 VM_EXIT_LOAD_IA32_EFER
);
1301 case MSR_CORE_PERF_GLOBAL_CTRL
:
1302 if (cpu_has_load_perf_global_ctrl
) {
1303 clear_atomic_switch_msr_special(
1304 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1305 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1311 for (i
= 0; i
< m
->nr
; ++i
)
1312 if (m
->guest
[i
].index
== msr
)
1318 m
->guest
[i
] = m
->guest
[m
->nr
];
1319 m
->host
[i
] = m
->host
[m
->nr
];
1320 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1321 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1324 static void add_atomic_switch_msr_special(unsigned long entry
,
1325 unsigned long exit
, unsigned long guest_val_vmcs
,
1326 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1328 vmcs_write64(guest_val_vmcs
, guest_val
);
1329 vmcs_write64(host_val_vmcs
, host_val
);
1330 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1331 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1334 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1335 u64 guest_val
, u64 host_val
)
1338 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1342 if (cpu_has_load_ia32_efer
) {
1343 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1344 VM_EXIT_LOAD_IA32_EFER
,
1347 guest_val
, host_val
);
1351 case MSR_CORE_PERF_GLOBAL_CTRL
:
1352 if (cpu_has_load_perf_global_ctrl
) {
1353 add_atomic_switch_msr_special(
1354 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1355 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1356 GUEST_IA32_PERF_GLOBAL_CTRL
,
1357 HOST_IA32_PERF_GLOBAL_CTRL
,
1358 guest_val
, host_val
);
1364 for (i
= 0; i
< m
->nr
; ++i
)
1365 if (m
->guest
[i
].index
== msr
)
1368 if (i
== NR_AUTOLOAD_MSRS
) {
1369 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1370 "Can't add msr %x\n", msr
);
1372 } else if (i
== m
->nr
) {
1374 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1378 m
->guest
[i
].index
= msr
;
1379 m
->guest
[i
].value
= guest_val
;
1380 m
->host
[i
].index
= msr
;
1381 m
->host
[i
].value
= host_val
;
1384 static void reload_tss(void)
1387 * VT restores TR but not its size. Useless.
1389 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1390 struct desc_struct
*descs
;
1392 descs
= (void *)gdt
->address
;
1393 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1397 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1402 guest_efer
= vmx
->vcpu
.arch
.efer
;
1405 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1408 ignore_bits
= EFER_NX
| EFER_SCE
;
1409 #ifdef CONFIG_X86_64
1410 ignore_bits
|= EFER_LMA
| EFER_LME
;
1411 /* SCE is meaningful only in long mode on Intel */
1412 if (guest_efer
& EFER_LMA
)
1413 ignore_bits
&= ~(u64
)EFER_SCE
;
1415 guest_efer
&= ~ignore_bits
;
1416 guest_efer
|= host_efer
& ignore_bits
;
1417 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1418 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1420 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1421 /* On ept, can't emulate nx, and must switch nx atomically */
1422 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1423 guest_efer
= vmx
->vcpu
.arch
.efer
;
1424 if (!(guest_efer
& EFER_LMA
))
1425 guest_efer
&= ~EFER_LME
;
1426 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1433 static unsigned long segment_base(u16 selector
)
1435 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1436 struct desc_struct
*d
;
1437 unsigned long table_base
;
1440 if (!(selector
& ~3))
1443 table_base
= gdt
->address
;
1445 if (selector
& 4) { /* from ldt */
1446 u16 ldt_selector
= kvm_read_ldt();
1448 if (!(ldt_selector
& ~3))
1451 table_base
= segment_base(ldt_selector
);
1453 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1454 v
= get_desc_base(d
);
1455 #ifdef CONFIG_X86_64
1456 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1457 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1462 static inline unsigned long kvm_read_tr_base(void)
1465 asm("str %0" : "=g"(tr
));
1466 return segment_base(tr
);
1469 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1471 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1474 if (vmx
->host_state
.loaded
)
1477 vmx
->host_state
.loaded
= 1;
1479 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1480 * allow segment selectors with cpl > 0 or ti == 1.
1482 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1483 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1484 savesegment(fs
, vmx
->host_state
.fs_sel
);
1485 if (!(vmx
->host_state
.fs_sel
& 7)) {
1486 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1487 vmx
->host_state
.fs_reload_needed
= 0;
1489 vmcs_write16(HOST_FS_SELECTOR
, 0);
1490 vmx
->host_state
.fs_reload_needed
= 1;
1492 savesegment(gs
, vmx
->host_state
.gs_sel
);
1493 if (!(vmx
->host_state
.gs_sel
& 7))
1494 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1496 vmcs_write16(HOST_GS_SELECTOR
, 0);
1497 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1500 #ifdef CONFIG_X86_64
1501 savesegment(ds
, vmx
->host_state
.ds_sel
);
1502 savesegment(es
, vmx
->host_state
.es_sel
);
1505 #ifdef CONFIG_X86_64
1506 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1507 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1509 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1510 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1513 #ifdef CONFIG_X86_64
1514 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1515 if (is_long_mode(&vmx
->vcpu
))
1516 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1518 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1519 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1520 vmx
->guest_msrs
[i
].data
,
1521 vmx
->guest_msrs
[i
].mask
);
1524 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1526 if (!vmx
->host_state
.loaded
)
1529 ++vmx
->vcpu
.stat
.host_state_reload
;
1530 vmx
->host_state
.loaded
= 0;
1531 #ifdef CONFIG_X86_64
1532 if (is_long_mode(&vmx
->vcpu
))
1533 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1535 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1536 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1537 #ifdef CONFIG_X86_64
1538 load_gs_index(vmx
->host_state
.gs_sel
);
1540 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1543 if (vmx
->host_state
.fs_reload_needed
)
1544 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1545 #ifdef CONFIG_X86_64
1546 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1547 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1548 loadsegment(es
, vmx
->host_state
.es_sel
);
1552 #ifdef CONFIG_X86_64
1553 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1556 * If the FPU is not active (through the host task or
1557 * the guest vcpu), then restore the cr0.TS bit.
1559 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1561 load_gdt(&__get_cpu_var(host_gdt
));
1564 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1567 __vmx_load_host_state(vmx
);
1572 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1573 * vcpu mutex is already taken.
1575 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1577 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1578 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1581 kvm_cpu_vmxon(phys_addr
);
1582 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1583 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1585 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1586 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1587 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1590 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1591 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1592 unsigned long sysenter_esp
;
1594 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1595 local_irq_disable();
1596 crash_disable_local_vmclear(cpu
);
1599 * Read loaded_vmcs->cpu should be before fetching
1600 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1601 * See the comments in __loaded_vmcs_clear().
1605 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1606 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1607 crash_enable_local_vmclear(cpu
);
1611 * Linux uses per-cpu TSS and GDT, so set these when switching
1614 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1615 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1617 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1618 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1619 vmx
->loaded_vmcs
->cpu
= cpu
;
1623 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1625 __vmx_load_host_state(to_vmx(vcpu
));
1626 if (!vmm_exclusive
) {
1627 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1633 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1637 if (vcpu
->fpu_active
)
1639 vcpu
->fpu_active
= 1;
1640 cr0
= vmcs_readl(GUEST_CR0
);
1641 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1642 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1643 vmcs_writel(GUEST_CR0
, cr0
);
1644 update_exception_bitmap(vcpu
);
1645 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1646 if (is_guest_mode(vcpu
))
1647 vcpu
->arch
.cr0_guest_owned_bits
&=
1648 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1649 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1652 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1655 * Return the cr0 value that a nested guest would read. This is a combination
1656 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1657 * its hypervisor (cr0_read_shadow).
1659 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1661 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1662 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1664 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1666 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1667 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1670 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1672 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1673 * set this *before* calling this function.
1675 vmx_decache_cr0_guest_bits(vcpu
);
1676 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1677 update_exception_bitmap(vcpu
);
1678 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1679 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1680 if (is_guest_mode(vcpu
)) {
1682 * L1's specified read shadow might not contain the TS bit,
1683 * so now that we turned on shadowing of this bit, we need to
1684 * set this bit of the shadow. Like in nested_vmx_run we need
1685 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1686 * up-to-date here because we just decached cr0.TS (and we'll
1687 * only update vmcs12->guest_cr0 on nested exit).
1689 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1690 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1691 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1692 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1694 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1697 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1699 unsigned long rflags
, save_rflags
;
1701 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1702 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1703 rflags
= vmcs_readl(GUEST_RFLAGS
);
1704 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1705 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1706 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1707 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1709 to_vmx(vcpu
)->rflags
= rflags
;
1711 return to_vmx(vcpu
)->rflags
;
1714 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1716 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1717 to_vmx(vcpu
)->rflags
= rflags
;
1718 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1719 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1720 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1722 vmcs_writel(GUEST_RFLAGS
, rflags
);
1725 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1727 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1730 if (interruptibility
& GUEST_INTR_STATE_STI
)
1731 ret
|= KVM_X86_SHADOW_INT_STI
;
1732 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1733 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1738 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1740 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1741 u32 interruptibility
= interruptibility_old
;
1743 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1745 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1746 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1747 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1748 interruptibility
|= GUEST_INTR_STATE_STI
;
1750 if ((interruptibility
!= interruptibility_old
))
1751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1754 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1758 rip
= kvm_rip_read(vcpu
);
1759 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1760 kvm_rip_write(vcpu
, rip
);
1762 /* skipping an emulated instruction also counts */
1763 vmx_set_interrupt_shadow(vcpu
, 0);
1767 * KVM wants to inject page-faults which it got to the guest. This function
1768 * checks whether in a nested guest, we need to inject them to L1 or L2.
1769 * This function assumes it is called with the exit reason in vmcs02 being
1770 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1773 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1775 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1777 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1778 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1781 nested_vmx_vmexit(vcpu
);
1785 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1786 bool has_error_code
, u32 error_code
,
1789 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1790 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1792 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1793 nested_pf_handled(vcpu
))
1796 if (has_error_code
) {
1797 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1798 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1801 if (vmx
->rmode
.vm86_active
) {
1803 if (kvm_exception_is_soft(nr
))
1804 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1805 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1806 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1810 if (kvm_exception_is_soft(nr
)) {
1811 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1812 vmx
->vcpu
.arch
.event_exit_inst_len
);
1813 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1815 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1820 static bool vmx_rdtscp_supported(void)
1822 return cpu_has_vmx_rdtscp();
1825 static bool vmx_invpcid_supported(void)
1827 return cpu_has_vmx_invpcid() && enable_ept
;
1831 * Swap MSR entry in host/guest MSR entry array.
1833 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1835 struct shared_msr_entry tmp
;
1837 tmp
= vmx
->guest_msrs
[to
];
1838 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1839 vmx
->guest_msrs
[from
] = tmp
;
1842 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
1844 unsigned long *msr_bitmap
;
1846 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
1847 if (is_long_mode(vcpu
))
1848 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
1850 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
1852 if (is_long_mode(vcpu
))
1853 msr_bitmap
= vmx_msr_bitmap_longmode
;
1855 msr_bitmap
= vmx_msr_bitmap_legacy
;
1858 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1862 * Set up the vmcs to automatically save and restore system
1863 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1864 * mode, as fiddling with msrs is very expensive.
1866 static void setup_msrs(struct vcpu_vmx
*vmx
)
1868 int save_nmsrs
, index
;
1871 #ifdef CONFIG_X86_64
1872 if (is_long_mode(&vmx
->vcpu
)) {
1873 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1875 move_msr_up(vmx
, index
, save_nmsrs
++);
1876 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1878 move_msr_up(vmx
, index
, save_nmsrs
++);
1879 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1881 move_msr_up(vmx
, index
, save_nmsrs
++);
1882 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1883 if (index
>= 0 && vmx
->rdtscp_enabled
)
1884 move_msr_up(vmx
, index
, save_nmsrs
++);
1886 * MSR_STAR is only needed on long mode guests, and only
1887 * if efer.sce is enabled.
1889 index
= __find_msr_index(vmx
, MSR_STAR
);
1890 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1891 move_msr_up(vmx
, index
, save_nmsrs
++);
1894 index
= __find_msr_index(vmx
, MSR_EFER
);
1895 if (index
>= 0 && update_transition_efer(vmx
, index
))
1896 move_msr_up(vmx
, index
, save_nmsrs
++);
1898 vmx
->save_nmsrs
= save_nmsrs
;
1900 if (cpu_has_vmx_msr_bitmap())
1901 vmx_set_msr_bitmap(&vmx
->vcpu
);
1905 * reads and returns guest's timestamp counter "register"
1906 * guest_tsc = host_tsc + tsc_offset -- 21.3
1908 static u64
guest_read_tsc(void)
1910 u64 host_tsc
, tsc_offset
;
1913 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1914 return host_tsc
+ tsc_offset
;
1918 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1919 * counter, even if a nested guest (L2) is currently running.
1921 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
1925 tsc_offset
= is_guest_mode(vcpu
) ?
1926 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1927 vmcs_read64(TSC_OFFSET
);
1928 return host_tsc
+ tsc_offset
;
1932 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1933 * software catchup for faster rates on slower CPUs.
1935 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1940 if (user_tsc_khz
> tsc_khz
) {
1941 vcpu
->arch
.tsc_catchup
= 1;
1942 vcpu
->arch
.tsc_always_catchup
= 1;
1944 WARN(1, "user requested TSC rate below hardware speed\n");
1947 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
1949 return vmcs_read64(TSC_OFFSET
);
1953 * writes 'offset' into guest's timestamp counter offset register
1955 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1957 if (is_guest_mode(vcpu
)) {
1959 * We're here if L1 chose not to trap WRMSR to TSC. According
1960 * to the spec, this should set L1's TSC; The offset that L1
1961 * set for L2 remains unchanged, and still needs to be added
1962 * to the newly set TSC to get L2's TSC.
1964 struct vmcs12
*vmcs12
;
1965 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1966 /* recalculate vmcs02.TSC_OFFSET: */
1967 vmcs12
= get_vmcs12(vcpu
);
1968 vmcs_write64(TSC_OFFSET
, offset
+
1969 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1970 vmcs12
->tsc_offset
: 0));
1972 vmcs_write64(TSC_OFFSET
, offset
);
1976 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1978 u64 offset
= vmcs_read64(TSC_OFFSET
);
1979 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1980 if (is_guest_mode(vcpu
)) {
1981 /* Even when running L2, the adjustment needs to apply to L1 */
1982 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1986 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1988 return target_tsc
- native_read_tsc();
1991 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1993 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1994 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1998 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1999 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2000 * all guests if the "nested" module option is off, and can also be disabled
2001 * for a single guest by disabling its VMX cpuid bit.
2003 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2005 return nested
&& guest_cpuid_has_vmx(vcpu
);
2009 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2010 * returned for the various VMX controls MSRs when nested VMX is enabled.
2011 * The same values should also be used to verify that vmcs12 control fields are
2012 * valid during nested entry from L1 to L2.
2013 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2014 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2015 * bit in the high half is on if the corresponding bit in the control field
2016 * may be on. See also vmx_control_verify().
2017 * TODO: allow these variables to be modified (downgraded) by module options
2020 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2021 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2022 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2023 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2024 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2025 static __init
void nested_vmx_setup_ctls_msrs(void)
2028 * Note that as a general rule, the high half of the MSRs (bits in
2029 * the control fields which may be 1) should be initialized by the
2030 * intersection of the underlying hardware's MSR (i.e., features which
2031 * can be supported) and the list of features we want to expose -
2032 * because they are known to be properly supported in our code.
2033 * Also, usually, the low half of the MSRs (bits which must be 1) can
2034 * be set to 0, meaning that L1 may turn off any of these bits. The
2035 * reason is that if one of these bits is necessary, it will appear
2036 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2037 * fields of vmcs01 and vmcs02, will turn these bits off - and
2038 * nested_vmx_exit_handled() will not pass related exits to L1.
2039 * These rules have exceptions below.
2042 /* pin-based controls */
2044 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2045 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2047 nested_vmx_pinbased_ctls_low
= 0x16 ;
2048 nested_vmx_pinbased_ctls_high
= 0x16 |
2049 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
2050 PIN_BASED_VIRTUAL_NMIS
;
2053 nested_vmx_exit_ctls_low
= 0;
2054 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2055 #ifdef CONFIG_X86_64
2056 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2058 nested_vmx_exit_ctls_high
= 0;
2061 /* entry controls */
2062 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2063 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2064 nested_vmx_entry_ctls_low
= 0;
2065 nested_vmx_entry_ctls_high
&=
2066 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
2068 /* cpu-based controls */
2069 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2070 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2071 nested_vmx_procbased_ctls_low
= 0;
2072 nested_vmx_procbased_ctls_high
&=
2073 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2074 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2075 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2076 CPU_BASED_CR3_STORE_EXITING
|
2077 #ifdef CONFIG_X86_64
2078 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2080 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2081 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2082 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2083 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2085 * We can allow some features even when not supported by the
2086 * hardware. For example, L1 can specify an MSR bitmap - and we
2087 * can use it to avoid exits to L1 - even when L0 runs L2
2088 * without MSR bitmaps.
2090 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2092 /* secondary cpu-based controls */
2093 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2094 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2095 nested_vmx_secondary_ctls_low
= 0;
2096 nested_vmx_secondary_ctls_high
&=
2097 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2100 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2103 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2105 return ((control
& high
) | low
) == control
;
2108 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2110 return low
| ((u64
)high
<< 32);
2114 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2115 * also let it use VMX-specific MSRs.
2116 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2117 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2118 * like all other MSRs).
2120 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2122 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2123 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2125 * According to the spec, processors which do not support VMX
2126 * should throw a #GP(0) when VMX capability MSRs are read.
2128 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2132 switch (msr_index
) {
2133 case MSR_IA32_FEATURE_CONTROL
:
2136 case MSR_IA32_VMX_BASIC
:
2138 * This MSR reports some information about VMX support. We
2139 * should return information about the VMX we emulate for the
2140 * guest, and the VMCS structure we give it - not about the
2141 * VMX support of the underlying hardware.
2143 *pdata
= VMCS12_REVISION
|
2144 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2145 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2147 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2148 case MSR_IA32_VMX_PINBASED_CTLS
:
2149 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2150 nested_vmx_pinbased_ctls_high
);
2152 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2153 case MSR_IA32_VMX_PROCBASED_CTLS
:
2154 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2155 nested_vmx_procbased_ctls_high
);
2157 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2158 case MSR_IA32_VMX_EXIT_CTLS
:
2159 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2160 nested_vmx_exit_ctls_high
);
2162 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2163 case MSR_IA32_VMX_ENTRY_CTLS
:
2164 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2165 nested_vmx_entry_ctls_high
);
2167 case MSR_IA32_VMX_MISC
:
2171 * These MSRs specify bits which the guest must keep fixed (on or off)
2172 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2173 * We picked the standard core2 setting.
2175 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2176 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2177 case MSR_IA32_VMX_CR0_FIXED0
:
2178 *pdata
= VMXON_CR0_ALWAYSON
;
2180 case MSR_IA32_VMX_CR0_FIXED1
:
2183 case MSR_IA32_VMX_CR4_FIXED0
:
2184 *pdata
= VMXON_CR4_ALWAYSON
;
2186 case MSR_IA32_VMX_CR4_FIXED1
:
2189 case MSR_IA32_VMX_VMCS_ENUM
:
2192 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2193 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2194 nested_vmx_secondary_ctls_high
);
2196 case MSR_IA32_VMX_EPT_VPID_CAP
:
2197 /* Currently, no nested ept or nested vpid */
2207 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2209 if (!nested_vmx_allowed(vcpu
))
2212 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2213 /* TODO: the right thing. */
2216 * No need to treat VMX capability MSRs specially: If we don't handle
2217 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2223 * Reads an msr value (of 'msr_index') into 'pdata'.
2224 * Returns 0 on success, non-0 otherwise.
2225 * Assumes vcpu_load() was already called.
2227 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2230 struct shared_msr_entry
*msr
;
2233 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2237 switch (msr_index
) {
2238 #ifdef CONFIG_X86_64
2240 data
= vmcs_readl(GUEST_FS_BASE
);
2243 data
= vmcs_readl(GUEST_GS_BASE
);
2245 case MSR_KERNEL_GS_BASE
:
2246 vmx_load_host_state(to_vmx(vcpu
));
2247 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2251 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2253 data
= guest_read_tsc();
2255 case MSR_IA32_SYSENTER_CS
:
2256 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2258 case MSR_IA32_SYSENTER_EIP
:
2259 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2261 case MSR_IA32_SYSENTER_ESP
:
2262 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2265 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2267 /* Otherwise falls through */
2269 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2271 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2276 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2284 * Writes msr value into into the appropriate "register".
2285 * Returns 0 on success, non-0 otherwise.
2286 * Assumes vcpu_load() was already called.
2288 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2290 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2291 struct shared_msr_entry
*msr
;
2293 u32 msr_index
= msr_info
->index
;
2294 u64 data
= msr_info
->data
;
2296 switch (msr_index
) {
2298 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2300 #ifdef CONFIG_X86_64
2302 vmx_segment_cache_clear(vmx
);
2303 vmcs_writel(GUEST_FS_BASE
, data
);
2306 vmx_segment_cache_clear(vmx
);
2307 vmcs_writel(GUEST_GS_BASE
, data
);
2309 case MSR_KERNEL_GS_BASE
:
2310 vmx_load_host_state(vmx
);
2311 vmx
->msr_guest_kernel_gs_base
= data
;
2314 case MSR_IA32_SYSENTER_CS
:
2315 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2317 case MSR_IA32_SYSENTER_EIP
:
2318 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2320 case MSR_IA32_SYSENTER_ESP
:
2321 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2324 kvm_write_tsc(vcpu
, msr_info
);
2326 case MSR_IA32_CR_PAT
:
2327 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2328 vmcs_write64(GUEST_IA32_PAT
, data
);
2329 vcpu
->arch
.pat
= data
;
2332 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2334 case MSR_IA32_TSC_ADJUST
:
2335 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2338 if (!vmx
->rdtscp_enabled
)
2340 /* Check reserved bit, higher 32 bits should be zero */
2341 if ((data
>> 32) != 0)
2343 /* Otherwise falls through */
2345 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2347 msr
= find_msr_entry(vmx
, msr_index
);
2350 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2352 kvm_set_shared_msr(msr
->index
, msr
->data
,
2358 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2364 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2366 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2369 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2372 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2374 case VCPU_EXREG_PDPTR
:
2376 ept_save_pdptrs(vcpu
);
2383 static __init
int cpu_has_kvm_support(void)
2385 return cpu_has_vmx();
2388 static __init
int vmx_disabled_by_bios(void)
2392 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2393 if (msr
& FEATURE_CONTROL_LOCKED
) {
2394 /* launched w/ TXT and VMX disabled */
2395 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2398 /* launched w/o TXT and VMX only enabled w/ TXT */
2399 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2400 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2401 && !tboot_enabled()) {
2402 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2403 "activate TXT before enabling KVM\n");
2406 /* launched w/o TXT and VMX disabled */
2407 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2408 && !tboot_enabled())
2415 static void kvm_cpu_vmxon(u64 addr
)
2417 asm volatile (ASM_VMX_VMXON_RAX
2418 : : "a"(&addr
), "m"(addr
)
2422 static int hardware_enable(void *garbage
)
2424 int cpu
= raw_smp_processor_id();
2425 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2428 if (read_cr4() & X86_CR4_VMXE
)
2431 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2434 * Now we can enable the vmclear operation in kdump
2435 * since the loaded_vmcss_on_cpu list on this cpu
2436 * has been initialized.
2438 * Though the cpu is not in VMX operation now, there
2439 * is no problem to enable the vmclear operation
2440 * for the loaded_vmcss_on_cpu list is empty!
2442 crash_enable_local_vmclear(cpu
);
2444 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2446 test_bits
= FEATURE_CONTROL_LOCKED
;
2447 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2448 if (tboot_enabled())
2449 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2451 if ((old
& test_bits
) != test_bits
) {
2452 /* enable and lock */
2453 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2455 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2457 if (vmm_exclusive
) {
2458 kvm_cpu_vmxon(phys_addr
);
2462 store_gdt(&__get_cpu_var(host_gdt
));
2467 static void vmclear_local_loaded_vmcss(void)
2469 int cpu
= raw_smp_processor_id();
2470 struct loaded_vmcs
*v
, *n
;
2472 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2473 loaded_vmcss_on_cpu_link
)
2474 __loaded_vmcs_clear(v
);
2478 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2481 static void kvm_cpu_vmxoff(void)
2483 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2486 static void hardware_disable(void *garbage
)
2488 if (vmm_exclusive
) {
2489 vmclear_local_loaded_vmcss();
2492 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2495 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2496 u32 msr
, u32
*result
)
2498 u32 vmx_msr_low
, vmx_msr_high
;
2499 u32 ctl
= ctl_min
| ctl_opt
;
2501 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2503 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2504 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2506 /* Ensure minimum (required) set of control bits are supported. */
2514 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2516 u32 vmx_msr_low
, vmx_msr_high
;
2518 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2519 return vmx_msr_high
& ctl
;
2522 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2524 u32 vmx_msr_low
, vmx_msr_high
;
2525 u32 min
, opt
, min2
, opt2
;
2526 u32 _pin_based_exec_control
= 0;
2527 u32 _cpu_based_exec_control
= 0;
2528 u32 _cpu_based_2nd_exec_control
= 0;
2529 u32 _vmexit_control
= 0;
2530 u32 _vmentry_control
= 0;
2532 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2533 opt
= PIN_BASED_VIRTUAL_NMIS
;
2534 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2535 &_pin_based_exec_control
) < 0)
2538 min
= CPU_BASED_HLT_EXITING
|
2539 #ifdef CONFIG_X86_64
2540 CPU_BASED_CR8_LOAD_EXITING
|
2541 CPU_BASED_CR8_STORE_EXITING
|
2543 CPU_BASED_CR3_LOAD_EXITING
|
2544 CPU_BASED_CR3_STORE_EXITING
|
2545 CPU_BASED_USE_IO_BITMAPS
|
2546 CPU_BASED_MOV_DR_EXITING
|
2547 CPU_BASED_USE_TSC_OFFSETING
|
2548 CPU_BASED_MWAIT_EXITING
|
2549 CPU_BASED_MONITOR_EXITING
|
2550 CPU_BASED_INVLPG_EXITING
|
2551 CPU_BASED_RDPMC_EXITING
;
2553 opt
= CPU_BASED_TPR_SHADOW
|
2554 CPU_BASED_USE_MSR_BITMAPS
|
2555 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2556 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2557 &_cpu_based_exec_control
) < 0)
2559 #ifdef CONFIG_X86_64
2560 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2561 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2562 ~CPU_BASED_CR8_STORE_EXITING
;
2564 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2566 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2567 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2568 SECONDARY_EXEC_WBINVD_EXITING
|
2569 SECONDARY_EXEC_ENABLE_VPID
|
2570 SECONDARY_EXEC_ENABLE_EPT
|
2571 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2572 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2573 SECONDARY_EXEC_RDTSCP
|
2574 SECONDARY_EXEC_ENABLE_INVPCID
|
2575 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2576 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
2577 if (adjust_vmx_controls(min2
, opt2
,
2578 MSR_IA32_VMX_PROCBASED_CTLS2
,
2579 &_cpu_based_2nd_exec_control
) < 0)
2582 #ifndef CONFIG_X86_64
2583 if (!(_cpu_based_2nd_exec_control
&
2584 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2585 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2588 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2589 _cpu_based_2nd_exec_control
&= ~(
2590 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2591 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2592 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2594 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2595 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2597 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2598 CPU_BASED_CR3_STORE_EXITING
|
2599 CPU_BASED_INVLPG_EXITING
);
2600 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2601 vmx_capability
.ept
, vmx_capability
.vpid
);
2605 #ifdef CONFIG_X86_64
2606 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2608 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2609 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2610 &_vmexit_control
) < 0)
2614 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2615 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2616 &_vmentry_control
) < 0)
2619 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2621 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2622 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2625 #ifdef CONFIG_X86_64
2626 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2627 if (vmx_msr_high
& (1u<<16))
2631 /* Require Write-Back (WB) memory type for VMCS accesses. */
2632 if (((vmx_msr_high
>> 18) & 15) != 6)
2635 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2636 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2637 vmcs_conf
->revision_id
= vmx_msr_low
;
2639 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2640 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2641 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2642 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2643 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2645 cpu_has_load_ia32_efer
=
2646 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2647 VM_ENTRY_LOAD_IA32_EFER
)
2648 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2649 VM_EXIT_LOAD_IA32_EFER
);
2651 cpu_has_load_perf_global_ctrl
=
2652 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2653 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2654 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2655 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2658 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2659 * but due to arrata below it can't be used. Workaround is to use
2660 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2662 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2667 * BC86,AAY89,BD102 (model 44)
2671 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2672 switch (boot_cpu_data
.x86_model
) {
2678 cpu_has_load_perf_global_ctrl
= false;
2679 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2680 "does not work properly. Using workaround\n");
2690 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2692 int node
= cpu_to_node(cpu
);
2696 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2699 vmcs
= page_address(pages
);
2700 memset(vmcs
, 0, vmcs_config
.size
);
2701 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2705 static struct vmcs
*alloc_vmcs(void)
2707 return alloc_vmcs_cpu(raw_smp_processor_id());
2710 static void free_vmcs(struct vmcs
*vmcs
)
2712 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2716 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2718 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2720 if (!loaded_vmcs
->vmcs
)
2722 loaded_vmcs_clear(loaded_vmcs
);
2723 free_vmcs(loaded_vmcs
->vmcs
);
2724 loaded_vmcs
->vmcs
= NULL
;
2727 static void free_kvm_area(void)
2731 for_each_possible_cpu(cpu
) {
2732 free_vmcs(per_cpu(vmxarea
, cpu
));
2733 per_cpu(vmxarea
, cpu
) = NULL
;
2737 static __init
int alloc_kvm_area(void)
2741 for_each_possible_cpu(cpu
) {
2744 vmcs
= alloc_vmcs_cpu(cpu
);
2750 per_cpu(vmxarea
, cpu
) = vmcs
;
2755 static __init
int hardware_setup(void)
2757 if (setup_vmcs_config(&vmcs_config
) < 0)
2760 if (boot_cpu_has(X86_FEATURE_NX
))
2761 kvm_enable_efer_bits(EFER_NX
);
2763 if (!cpu_has_vmx_vpid())
2766 if (!cpu_has_vmx_ept() ||
2767 !cpu_has_vmx_ept_4levels()) {
2769 enable_unrestricted_guest
= 0;
2770 enable_ept_ad_bits
= 0;
2773 if (!cpu_has_vmx_ept_ad_bits())
2774 enable_ept_ad_bits
= 0;
2776 if (!cpu_has_vmx_unrestricted_guest())
2777 enable_unrestricted_guest
= 0;
2779 if (!cpu_has_vmx_flexpriority())
2780 flexpriority_enabled
= 0;
2782 if (!cpu_has_vmx_tpr_shadow())
2783 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2785 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2786 kvm_disable_largepages();
2788 if (!cpu_has_vmx_ple())
2791 if (!cpu_has_vmx_apic_register_virt() ||
2792 !cpu_has_vmx_virtual_intr_delivery())
2793 enable_apicv_reg_vid
= 0;
2795 if (enable_apicv_reg_vid
)
2796 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2798 kvm_x86_ops
->hwapic_irr_update
= NULL
;
2801 nested_vmx_setup_ctls_msrs();
2803 return alloc_kvm_area();
2806 static __exit
void hardware_unsetup(void)
2811 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2813 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2816 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
2817 struct kvm_segment
*save
)
2819 if (!emulate_invalid_guest_state
) {
2821 * CS and SS RPL should be equal during guest entry according
2822 * to VMX spec, but in reality it is not always so. Since vcpu
2823 * is in the middle of the transition from real mode to
2824 * protected mode it is safe to assume that RPL 0 is a good
2827 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
2828 save
->selector
&= ~SELECTOR_RPL_MASK
;
2829 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
2832 vmx_set_segment(vcpu
, save
, seg
);
2835 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2837 unsigned long flags
;
2838 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2841 * Update real mode segment cache. It may be not up-to-date if sement
2842 * register was written while vcpu was in a guest mode.
2844 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2845 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2846 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2847 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2848 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2849 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2851 vmx
->rmode
.vm86_active
= 0;
2853 vmx_segment_cache_clear(vmx
);
2855 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2857 flags
= vmcs_readl(GUEST_RFLAGS
);
2858 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2859 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2860 vmcs_writel(GUEST_RFLAGS
, flags
);
2862 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2863 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2865 update_exception_bitmap(vcpu
);
2867 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2868 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2869 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2870 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2871 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2872 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2874 /* CPL is always 0 when CPU enters protected mode */
2875 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2879 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2881 if (!kvm
->arch
.tss_addr
) {
2882 struct kvm_memslots
*slots
;
2883 struct kvm_memory_slot
*slot
;
2886 slots
= kvm_memslots(kvm
);
2887 slot
= id_to_memslot(slots
, 0);
2888 base_gfn
= slot
->base_gfn
+ slot
->npages
- 3;
2890 return base_gfn
<< PAGE_SHIFT
;
2892 return kvm
->arch
.tss_addr
;
2895 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
2897 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2898 struct kvm_segment var
= *save
;
2901 if (seg
== VCPU_SREG_CS
)
2904 if (!emulate_invalid_guest_state
) {
2905 var
.selector
= var
.base
>> 4;
2906 var
.base
= var
.base
& 0xffff0;
2916 if (save
->base
& 0xf)
2917 printk_once(KERN_WARNING
"kvm: segment base is not "
2918 "paragraph aligned when entering "
2919 "protected mode (seg=%d)", seg
);
2922 vmcs_write16(sf
->selector
, var
.selector
);
2923 vmcs_write32(sf
->base
, var
.base
);
2924 vmcs_write32(sf
->limit
, var
.limit
);
2925 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
2928 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2930 unsigned long flags
;
2931 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2933 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2934 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2935 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2936 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2937 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2938 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2939 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2941 vmx
->rmode
.vm86_active
= 1;
2944 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2945 * vcpu. Call it here with phys address pointing 16M below 4G.
2947 if (!vcpu
->kvm
->arch
.tss_addr
) {
2948 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2949 "called before entering vcpu\n");
2950 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2951 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2952 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2955 vmx_segment_cache_clear(vmx
);
2957 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2958 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2959 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2961 flags
= vmcs_readl(GUEST_RFLAGS
);
2962 vmx
->rmode
.save_rflags
= flags
;
2964 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2966 vmcs_writel(GUEST_RFLAGS
, flags
);
2967 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2968 update_exception_bitmap(vcpu
);
2970 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2971 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2972 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2973 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2974 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2975 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2977 kvm_mmu_reset_context(vcpu
);
2980 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2983 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2989 * Force kernel_gs_base reloading before EFER changes, as control
2990 * of this msr depends on is_long_mode().
2992 vmx_load_host_state(to_vmx(vcpu
));
2993 vcpu
->arch
.efer
= efer
;
2994 if (efer
& EFER_LMA
) {
2995 vmcs_write32(VM_ENTRY_CONTROLS
,
2996 vmcs_read32(VM_ENTRY_CONTROLS
) |
2997 VM_ENTRY_IA32E_MODE
);
3000 vmcs_write32(VM_ENTRY_CONTROLS
,
3001 vmcs_read32(VM_ENTRY_CONTROLS
) &
3002 ~VM_ENTRY_IA32E_MODE
);
3004 msr
->data
= efer
& ~EFER_LME
;
3009 #ifdef CONFIG_X86_64
3011 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3015 vmx_segment_cache_clear(to_vmx(vcpu
));
3017 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3018 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3019 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3021 vmcs_write32(GUEST_TR_AR_BYTES
,
3022 (guest_tr_ar
& ~AR_TYPE_MASK
)
3023 | AR_TYPE_BUSY_64_TSS
);
3025 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3028 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3030 vmcs_write32(VM_ENTRY_CONTROLS
,
3031 vmcs_read32(VM_ENTRY_CONTROLS
)
3032 & ~VM_ENTRY_IA32E_MODE
);
3033 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3038 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3040 vpid_sync_context(to_vmx(vcpu
));
3042 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3044 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3048 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3050 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3052 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3053 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3056 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3058 if (enable_ept
&& is_paging(vcpu
))
3059 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3060 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3063 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3065 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3067 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3068 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3071 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3073 if (!test_bit(VCPU_EXREG_PDPTR
,
3074 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3077 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3078 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
3079 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
3080 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
3081 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
3085 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3087 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3088 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3089 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3090 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3091 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3094 __set_bit(VCPU_EXREG_PDPTR
,
3095 (unsigned long *)&vcpu
->arch
.regs_avail
);
3096 __set_bit(VCPU_EXREG_PDPTR
,
3097 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3100 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3102 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3104 struct kvm_vcpu
*vcpu
)
3106 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3107 vmx_decache_cr3(vcpu
);
3108 if (!(cr0
& X86_CR0_PG
)) {
3109 /* From paging/starting to nonpaging */
3110 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3111 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3112 (CPU_BASED_CR3_LOAD_EXITING
|
3113 CPU_BASED_CR3_STORE_EXITING
));
3114 vcpu
->arch
.cr0
= cr0
;
3115 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3116 } else if (!is_paging(vcpu
)) {
3117 /* From nonpaging to paging */
3118 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3119 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3120 ~(CPU_BASED_CR3_LOAD_EXITING
|
3121 CPU_BASED_CR3_STORE_EXITING
));
3122 vcpu
->arch
.cr0
= cr0
;
3123 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3126 if (!(cr0
& X86_CR0_WP
))
3127 *hw_cr0
&= ~X86_CR0_WP
;
3130 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3132 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3133 unsigned long hw_cr0
;
3135 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3136 if (enable_unrestricted_guest
)
3137 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3139 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3141 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3144 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3148 #ifdef CONFIG_X86_64
3149 if (vcpu
->arch
.efer
& EFER_LME
) {
3150 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3152 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3158 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3160 if (!vcpu
->fpu_active
)
3161 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3163 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3164 vmcs_writel(GUEST_CR0
, hw_cr0
);
3165 vcpu
->arch
.cr0
= cr0
;
3167 /* depends on vcpu->arch.cr0 to be set to a new value */
3168 vmx
->emulation_required
= emulation_required(vcpu
);
3171 static u64
construct_eptp(unsigned long root_hpa
)
3175 /* TODO write the value reading from MSR */
3176 eptp
= VMX_EPT_DEFAULT_MT
|
3177 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3178 if (enable_ept_ad_bits
)
3179 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3180 eptp
|= (root_hpa
& PAGE_MASK
);
3185 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3187 unsigned long guest_cr3
;
3192 eptp
= construct_eptp(cr3
);
3193 vmcs_write64(EPT_POINTER
, eptp
);
3194 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3195 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3196 ept_load_pdptrs(vcpu
);
3199 vmx_flush_tlb(vcpu
);
3200 vmcs_writel(GUEST_CR3
, guest_cr3
);
3203 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3205 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3206 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3208 if (cr4
& X86_CR4_VMXE
) {
3210 * To use VMXON (and later other VMX instructions), a guest
3211 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3212 * So basically the check on whether to allow nested VMX
3215 if (!nested_vmx_allowed(vcpu
))
3217 } else if (to_vmx(vcpu
)->nested
.vmxon
)
3220 vcpu
->arch
.cr4
= cr4
;
3222 if (!is_paging(vcpu
)) {
3223 hw_cr4
&= ~X86_CR4_PAE
;
3224 hw_cr4
|= X86_CR4_PSE
;
3226 * SMEP is disabled if CPU is in non-paging mode in
3227 * hardware. However KVM always uses paging mode to
3228 * emulate guest non-paging mode with TDP.
3229 * To emulate this behavior, SMEP needs to be manually
3230 * disabled when guest switches to non-paging mode.
3232 hw_cr4
&= ~X86_CR4_SMEP
;
3233 } else if (!(cr4
& X86_CR4_PAE
)) {
3234 hw_cr4
&= ~X86_CR4_PAE
;
3238 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3239 vmcs_writel(GUEST_CR4
, hw_cr4
);
3243 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3244 struct kvm_segment
*var
, int seg
)
3246 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3249 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3250 *var
= vmx
->rmode
.segs
[seg
];
3251 if (seg
== VCPU_SREG_TR
3252 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3254 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3255 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3258 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3259 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3260 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3261 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3262 var
->type
= ar
& 15;
3263 var
->s
= (ar
>> 4) & 1;
3264 var
->dpl
= (ar
>> 5) & 3;
3265 var
->present
= (ar
>> 7) & 1;
3266 var
->avl
= (ar
>> 12) & 1;
3267 var
->l
= (ar
>> 13) & 1;
3268 var
->db
= (ar
>> 14) & 1;
3269 var
->g
= (ar
>> 15) & 1;
3270 var
->unusable
= (ar
>> 16) & 1;
3273 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3275 struct kvm_segment s
;
3277 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3278 vmx_get_segment(vcpu
, &s
, seg
);
3281 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3284 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3286 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3288 if (!is_protmode(vcpu
))
3291 if (!is_long_mode(vcpu
)
3292 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3295 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3296 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3297 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3304 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3308 if (var
->unusable
|| !var
->present
)
3311 ar
= var
->type
& 15;
3312 ar
|= (var
->s
& 1) << 4;
3313 ar
|= (var
->dpl
& 3) << 5;
3314 ar
|= (var
->present
& 1) << 7;
3315 ar
|= (var
->avl
& 1) << 12;
3316 ar
|= (var
->l
& 1) << 13;
3317 ar
|= (var
->db
& 1) << 14;
3318 ar
|= (var
->g
& 1) << 15;
3324 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3325 struct kvm_segment
*var
, int seg
)
3327 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3328 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3330 vmx_segment_cache_clear(vmx
);
3331 if (seg
== VCPU_SREG_CS
)
3332 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3334 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3335 vmx
->rmode
.segs
[seg
] = *var
;
3336 if (seg
== VCPU_SREG_TR
)
3337 vmcs_write16(sf
->selector
, var
->selector
);
3339 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3343 vmcs_writel(sf
->base
, var
->base
);
3344 vmcs_write32(sf
->limit
, var
->limit
);
3345 vmcs_write16(sf
->selector
, var
->selector
);
3348 * Fix the "Accessed" bit in AR field of segment registers for older
3350 * IA32 arch specifies that at the time of processor reset the
3351 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3352 * is setting it to 0 in the userland code. This causes invalid guest
3353 * state vmexit when "unrestricted guest" mode is turned on.
3354 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3355 * tree. Newer qemu binaries with that qemu fix would not need this
3358 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3359 var
->type
|= 0x1; /* Accessed */
3361 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3364 vmx
->emulation_required
|= emulation_required(vcpu
);
3367 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3369 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3371 *db
= (ar
>> 14) & 1;
3372 *l
= (ar
>> 13) & 1;
3375 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3377 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3378 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3381 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3383 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3384 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3387 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3389 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3390 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3393 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3395 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3396 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3399 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3401 struct kvm_segment var
;
3404 vmx_get_segment(vcpu
, &var
, seg
);
3406 if (seg
== VCPU_SREG_CS
)
3408 ar
= vmx_segment_access_rights(&var
);
3410 if (var
.base
!= (var
.selector
<< 4))
3412 if (var
.limit
!= 0xffff)
3420 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3422 struct kvm_segment cs
;
3423 unsigned int cs_rpl
;
3425 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3426 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3430 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3434 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3435 if (cs
.dpl
> cs_rpl
)
3438 if (cs
.dpl
!= cs_rpl
)
3444 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3448 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3450 struct kvm_segment ss
;
3451 unsigned int ss_rpl
;
3453 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3454 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3458 if (ss
.type
!= 3 && ss
.type
!= 7)
3462 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3470 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3472 struct kvm_segment var
;
3475 vmx_get_segment(vcpu
, &var
, seg
);
3476 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3484 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3485 if (var
.dpl
< rpl
) /* DPL < RPL */
3489 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3495 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3497 struct kvm_segment tr
;
3499 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3503 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3505 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3513 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3515 struct kvm_segment ldtr
;
3517 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3521 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3531 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3533 struct kvm_segment cs
, ss
;
3535 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3536 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3538 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3539 (ss
.selector
& SELECTOR_RPL_MASK
));
3543 * Check if guest state is valid. Returns true if valid, false if
3545 * We assume that registers are always usable
3547 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3549 if (enable_unrestricted_guest
)
3552 /* real mode guest state checks */
3553 if (!is_protmode(vcpu
)) {
3554 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3556 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3558 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3560 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3562 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3564 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3567 /* protected mode guest state checks */
3568 if (!cs_ss_rpl_check(vcpu
))
3570 if (!code_segment_valid(vcpu
))
3572 if (!stack_segment_valid(vcpu
))
3574 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3576 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3578 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3580 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3582 if (!tr_valid(vcpu
))
3584 if (!ldtr_valid(vcpu
))
3588 * - Add checks on RIP
3589 * - Add checks on RFLAGS
3595 static int init_rmode_tss(struct kvm
*kvm
)
3599 int r
, idx
, ret
= 0;
3601 idx
= srcu_read_lock(&kvm
->srcu
);
3602 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3603 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3606 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3607 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3608 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3611 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3614 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3618 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3619 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3626 srcu_read_unlock(&kvm
->srcu
, idx
);
3630 static int init_rmode_identity_map(struct kvm
*kvm
)
3633 pfn_t identity_map_pfn
;
3638 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3639 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3640 "haven't been allocated!\n");
3643 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3646 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3647 idx
= srcu_read_lock(&kvm
->srcu
);
3648 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3651 /* Set up identity-mapping pagetable for EPT in real mode */
3652 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3653 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3654 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3655 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3656 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3660 kvm
->arch
.ept_identity_pagetable_done
= true;
3663 srcu_read_unlock(&kvm
->srcu
, idx
);
3667 static void seg_setup(int seg
)
3669 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3672 vmcs_write16(sf
->selector
, 0);
3673 vmcs_writel(sf
->base
, 0);
3674 vmcs_write32(sf
->limit
, 0xffff);
3676 if (seg
== VCPU_SREG_CS
)
3677 ar
|= 0x08; /* code segment */
3679 vmcs_write32(sf
->ar_bytes
, ar
);
3682 static int alloc_apic_access_page(struct kvm
*kvm
)
3685 struct kvm_userspace_memory_region kvm_userspace_mem
;
3688 mutex_lock(&kvm
->slots_lock
);
3689 if (kvm
->arch
.apic_access_page
)
3691 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3692 kvm_userspace_mem
.flags
= 0;
3693 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3694 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3695 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, false);
3699 page
= gfn_to_page(kvm
, 0xfee00);
3700 if (is_error_page(page
)) {
3705 kvm
->arch
.apic_access_page
= page
;
3707 mutex_unlock(&kvm
->slots_lock
);
3711 static int alloc_identity_pagetable(struct kvm
*kvm
)
3714 struct kvm_userspace_memory_region kvm_userspace_mem
;
3717 mutex_lock(&kvm
->slots_lock
);
3718 if (kvm
->arch
.ept_identity_pagetable
)
3720 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3721 kvm_userspace_mem
.flags
= 0;
3722 kvm_userspace_mem
.guest_phys_addr
=
3723 kvm
->arch
.ept_identity_map_addr
;
3724 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3725 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, false);
3729 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3730 if (is_error_page(page
)) {
3735 kvm
->arch
.ept_identity_pagetable
= page
;
3737 mutex_unlock(&kvm
->slots_lock
);
3741 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3748 spin_lock(&vmx_vpid_lock
);
3749 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3750 if (vpid
< VMX_NR_VPIDS
) {
3752 __set_bit(vpid
, vmx_vpid_bitmap
);
3754 spin_unlock(&vmx_vpid_lock
);
3757 static void free_vpid(struct vcpu_vmx
*vmx
)
3761 spin_lock(&vmx_vpid_lock
);
3763 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3764 spin_unlock(&vmx_vpid_lock
);
3767 #define MSR_TYPE_R 1
3768 #define MSR_TYPE_W 2
3769 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
3772 int f
= sizeof(unsigned long);
3774 if (!cpu_has_vmx_msr_bitmap())
3778 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3779 * have the write-low and read-high bitmap offsets the wrong way round.
3780 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3782 if (msr
<= 0x1fff) {
3783 if (type
& MSR_TYPE_R
)
3785 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
3787 if (type
& MSR_TYPE_W
)
3789 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
3791 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3793 if (type
& MSR_TYPE_R
)
3795 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
3797 if (type
& MSR_TYPE_W
)
3799 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3804 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
3807 int f
= sizeof(unsigned long);
3809 if (!cpu_has_vmx_msr_bitmap())
3813 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3814 * have the write-low and read-high bitmap offsets the wrong way round.
3815 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3817 if (msr
<= 0x1fff) {
3818 if (type
& MSR_TYPE_R
)
3820 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
3822 if (type
& MSR_TYPE_W
)
3824 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
3826 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3828 if (type
& MSR_TYPE_R
)
3830 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
3832 if (type
& MSR_TYPE_W
)
3834 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3839 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3842 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
3843 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
3844 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
3845 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
3848 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
3850 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3852 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3856 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
3858 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3860 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3864 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
3866 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3868 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3873 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3874 * will not change in the lifetime of the guest.
3875 * Note that host-state that does change is set elsewhere. E.g., host-state
3876 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3878 static void vmx_set_constant_host_state(void)
3884 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
3885 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3886 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3888 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3889 #ifdef CONFIG_X86_64
3891 * Load null selectors, so we can avoid reloading them in
3892 * __vmx_load_host_state(), in case userspace uses the null selectors
3893 * too (the expected case).
3895 vmcs_write16(HOST_DS_SELECTOR
, 0);
3896 vmcs_write16(HOST_ES_SELECTOR
, 0);
3898 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3899 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3901 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3902 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3904 native_store_idt(&dt
);
3905 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3907 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
3909 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3910 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3911 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3912 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3914 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3915 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3916 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3920 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3922 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3924 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3925 if (is_guest_mode(&vmx
->vcpu
))
3926 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3927 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3928 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3931 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3933 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3934 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3935 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3936 #ifdef CONFIG_X86_64
3937 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3938 CPU_BASED_CR8_LOAD_EXITING
;
3942 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3943 CPU_BASED_CR3_LOAD_EXITING
|
3944 CPU_BASED_INVLPG_EXITING
;
3945 return exec_control
;
3948 static int vmx_vm_has_apicv(struct kvm
*kvm
)
3950 return enable_apicv_reg_vid
&& irqchip_in_kernel(kvm
);
3953 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3955 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3956 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3957 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3959 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3961 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3962 enable_unrestricted_guest
= 0;
3963 /* Enable INVPCID for non-ept guests may cause performance regression. */
3964 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
3966 if (!enable_unrestricted_guest
)
3967 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3969 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3970 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
3971 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3972 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3973 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
3974 return exec_control
;
3977 static void ept_set_mmio_spte_mask(void)
3980 * EPT Misconfigurations can be generated if the value of bits 2:0
3981 * of an EPT paging-structure entry is 110b (write/execute).
3982 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3985 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
3989 * Sets up the vmcs for emulated real mode.
3991 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3993 #ifdef CONFIG_X86_64
3999 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4000 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4002 if (cpu_has_vmx_msr_bitmap())
4003 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4005 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4008 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
4009 vmcs_config
.pin_based_exec_ctrl
);
4011 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4013 if (cpu_has_secondary_exec_ctrls()) {
4014 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4015 vmx_secondary_exec_control(vmx
));
4018 if (enable_apicv_reg_vid
) {
4019 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4020 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4021 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4022 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4024 vmcs_write16(GUEST_INTR_STATUS
, 0);
4028 vmcs_write32(PLE_GAP
, ple_gap
);
4029 vmcs_write32(PLE_WINDOW
, ple_window
);
4032 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4033 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4034 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4036 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4037 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4038 vmx_set_constant_host_state();
4039 #ifdef CONFIG_X86_64
4040 rdmsrl(MSR_FS_BASE
, a
);
4041 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4042 rdmsrl(MSR_GS_BASE
, a
);
4043 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4045 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4046 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4049 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4050 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4051 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4052 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4053 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4055 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4056 u32 msr_low
, msr_high
;
4058 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4059 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4060 /* Write the default value follow host pat */
4061 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4062 /* Keep arch.pat sync with GUEST_IA32_PAT */
4063 vmx
->vcpu
.arch
.pat
= host_pat
;
4066 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4067 u32 index
= vmx_msr_index
[i
];
4068 u32 data_low
, data_high
;
4071 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4073 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4075 vmx
->guest_msrs
[j
].index
= i
;
4076 vmx
->guest_msrs
[j
].data
= 0;
4077 vmx
->guest_msrs
[j
].mask
= -1ull;
4081 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
4083 /* 22.2.1, 20.8.1 */
4084 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
4086 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4087 set_cr4_guest_host_mask(vmx
);
4092 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4094 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4098 vmx
->rmode
.vm86_active
= 0;
4100 vmx
->soft_vnmi_blocked
= 0;
4102 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4103 kvm_set_cr8(&vmx
->vcpu
, 0);
4104 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4105 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4106 msr
|= MSR_IA32_APICBASE_BSP
;
4107 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4109 vmx_segment_cache_clear(vmx
);
4111 seg_setup(VCPU_SREG_CS
);
4112 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4113 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4115 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
4116 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
4119 seg_setup(VCPU_SREG_DS
);
4120 seg_setup(VCPU_SREG_ES
);
4121 seg_setup(VCPU_SREG_FS
);
4122 seg_setup(VCPU_SREG_GS
);
4123 seg_setup(VCPU_SREG_SS
);
4125 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4126 vmcs_writel(GUEST_TR_BASE
, 0);
4127 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4128 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4130 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4131 vmcs_writel(GUEST_LDTR_BASE
, 0);
4132 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4133 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4135 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4136 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4137 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4139 vmcs_writel(GUEST_RFLAGS
, 0x02);
4140 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4141 kvm_rip_write(vcpu
, 0xfff0);
4143 kvm_rip_write(vcpu
, 0);
4145 vmcs_writel(GUEST_GDTR_BASE
, 0);
4146 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4148 vmcs_writel(GUEST_IDTR_BASE
, 0);
4149 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4151 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4152 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4153 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4155 /* Special registers */
4156 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4160 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4162 if (cpu_has_vmx_tpr_shadow()) {
4163 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4164 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4165 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4166 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4167 vmcs_write32(TPR_THRESHOLD
, 0);
4170 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4171 vmcs_write64(APIC_ACCESS_ADDR
,
4172 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4175 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4177 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4178 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
4179 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4180 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
4181 vmx_set_cr4(&vmx
->vcpu
, 0);
4182 vmx_set_efer(&vmx
->vcpu
, 0);
4183 vmx_fpu_activate(&vmx
->vcpu
);
4184 update_exception_bitmap(&vmx
->vcpu
);
4186 vpid_sync_context(vmx
);
4194 * In nested virtualization, check if L1 asked to exit on external interrupts.
4195 * For most existing hypervisors, this will always return true.
4197 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4199 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4200 PIN_BASED_EXT_INTR_MASK
;
4203 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4205 u32 cpu_based_vm_exec_control
;
4206 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4208 * We get here if vmx_interrupt_allowed() said we can't
4209 * inject to L1 now because L2 must run. Ask L2 to exit
4210 * right after entry, so we can inject to L1 more promptly.
4212 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT
, vcpu
);
4216 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4217 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4218 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4221 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4223 u32 cpu_based_vm_exec_control
;
4225 if (!cpu_has_virtual_nmis()) {
4226 enable_irq_window(vcpu
);
4230 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4231 enable_irq_window(vcpu
);
4234 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4235 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4236 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4239 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4243 int irq
= vcpu
->arch
.interrupt
.nr
;
4245 trace_kvm_inj_virq(irq
);
4247 ++vcpu
->stat
.irq_injections
;
4248 if (vmx
->rmode
.vm86_active
) {
4250 if (vcpu
->arch
.interrupt
.soft
)
4251 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4252 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4253 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4256 intr
= irq
| INTR_INFO_VALID_MASK
;
4257 if (vcpu
->arch
.interrupt
.soft
) {
4258 intr
|= INTR_TYPE_SOFT_INTR
;
4259 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4260 vmx
->vcpu
.arch
.event_exit_inst_len
);
4262 intr
|= INTR_TYPE_EXT_INTR
;
4263 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4266 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4268 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4270 if (is_guest_mode(vcpu
))
4273 if (!cpu_has_virtual_nmis()) {
4275 * Tracking the NMI-blocked state in software is built upon
4276 * finding the next open IRQ window. This, in turn, depends on
4277 * well-behaving guests: They have to keep IRQs disabled at
4278 * least as long as the NMI handler runs. Otherwise we may
4279 * cause NMI nesting, maybe breaking the guest. But as this is
4280 * highly unlikely, we can live with the residual risk.
4282 vmx
->soft_vnmi_blocked
= 1;
4283 vmx
->vnmi_blocked_time
= 0;
4286 ++vcpu
->stat
.nmi_injections
;
4287 vmx
->nmi_known_unmasked
= false;
4288 if (vmx
->rmode
.vm86_active
) {
4289 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4290 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4293 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4294 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4297 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4299 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4302 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4303 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4304 | GUEST_INTR_STATE_NMI
));
4307 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4309 if (!cpu_has_virtual_nmis())
4310 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4311 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4313 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4316 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4318 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4320 if (!cpu_has_virtual_nmis()) {
4321 if (vmx
->soft_vnmi_blocked
!= masked
) {
4322 vmx
->soft_vnmi_blocked
= masked
;
4323 vmx
->vnmi_blocked_time
= 0;
4326 vmx
->nmi_known_unmasked
= !masked
;
4328 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4329 GUEST_INTR_STATE_NMI
);
4331 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4332 GUEST_INTR_STATE_NMI
);
4336 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4338 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4339 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4340 if (to_vmx(vcpu
)->nested
.nested_run_pending
||
4341 (vmcs12
->idt_vectoring_info_field
&
4342 VECTORING_INFO_VALID_MASK
))
4344 nested_vmx_vmexit(vcpu
);
4345 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
4346 vmcs12
->vm_exit_intr_info
= 0;
4347 /* fall through to normal code, but now in L1, not L2 */
4350 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4351 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4352 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4355 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4358 struct kvm_userspace_memory_region tss_mem
= {
4359 .slot
= TSS_PRIVATE_MEMSLOT
,
4360 .guest_phys_addr
= addr
,
4361 .memory_size
= PAGE_SIZE
* 3,
4365 ret
= kvm_set_memory_region(kvm
, &tss_mem
, false);
4368 kvm
->arch
.tss_addr
= addr
;
4369 if (!init_rmode_tss(kvm
))
4375 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4380 * Update instruction length as we may reinject the exception
4381 * from user space while in guest debugging mode.
4383 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4384 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4385 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4389 if (vcpu
->guest_debug
&
4390 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4407 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4408 int vec
, u32 err_code
)
4411 * Instruction with address size override prefix opcode 0x67
4412 * Cause the #SS fault with 0 error code in VM86 mode.
4414 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4415 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4416 if (vcpu
->arch
.halt_request
) {
4417 vcpu
->arch
.halt_request
= 0;
4418 return kvm_emulate_halt(vcpu
);
4426 * Forward all other exceptions that are valid in real mode.
4427 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4428 * the required debugging infrastructure rework.
4430 kvm_queue_exception(vcpu
, vec
);
4435 * Trigger machine check on the host. We assume all the MSRs are already set up
4436 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4437 * We pass a fake environment to the machine check handler because we want
4438 * the guest to be always treated like user space, no matter what context
4439 * it used internally.
4441 static void kvm_machine_check(void)
4443 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4444 struct pt_regs regs
= {
4445 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4446 .flags
= X86_EFLAGS_IF
,
4449 do_machine_check(®s
, 0);
4453 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4455 /* already handled by vcpu_run */
4459 static int handle_exception(struct kvm_vcpu
*vcpu
)
4461 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4462 struct kvm_run
*kvm_run
= vcpu
->run
;
4463 u32 intr_info
, ex_no
, error_code
;
4464 unsigned long cr2
, rip
, dr6
;
4466 enum emulation_result er
;
4468 vect_info
= vmx
->idt_vectoring_info
;
4469 intr_info
= vmx
->exit_intr_info
;
4471 if (is_machine_check(intr_info
))
4472 return handle_machine_check(vcpu
);
4474 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4475 return 1; /* already handled by vmx_vcpu_run() */
4477 if (is_no_device(intr_info
)) {
4478 vmx_fpu_activate(vcpu
);
4482 if (is_invalid_opcode(intr_info
)) {
4483 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4484 if (er
!= EMULATE_DONE
)
4485 kvm_queue_exception(vcpu
, UD_VECTOR
);
4490 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4491 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4494 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4495 * MMIO, it is better to report an internal error.
4496 * See the comments in vmx_handle_exit.
4498 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4499 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4500 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4501 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4502 vcpu
->run
->internal
.ndata
= 2;
4503 vcpu
->run
->internal
.data
[0] = vect_info
;
4504 vcpu
->run
->internal
.data
[1] = intr_info
;
4508 if (is_page_fault(intr_info
)) {
4509 /* EPT won't cause page fault directly */
4511 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4512 trace_kvm_page_fault(cr2
, error_code
);
4514 if (kvm_event_needs_reinjection(vcpu
))
4515 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4516 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4519 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4521 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4522 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4526 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4527 if (!(vcpu
->guest_debug
&
4528 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4529 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4530 kvm_queue_exception(vcpu
, DB_VECTOR
);
4533 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4534 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4538 * Update instruction length as we may reinject #BP from
4539 * user space while in guest debugging mode. Reading it for
4540 * #DB as well causes no harm, it is not used in that case.
4542 vmx
->vcpu
.arch
.event_exit_inst_len
=
4543 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4544 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4545 rip
= kvm_rip_read(vcpu
);
4546 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4547 kvm_run
->debug
.arch
.exception
= ex_no
;
4550 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4551 kvm_run
->ex
.exception
= ex_no
;
4552 kvm_run
->ex
.error_code
= error_code
;
4558 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4560 ++vcpu
->stat
.irq_exits
;
4564 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4566 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4570 static int handle_io(struct kvm_vcpu
*vcpu
)
4572 unsigned long exit_qualification
;
4573 int size
, in
, string
;
4576 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4577 string
= (exit_qualification
& 16) != 0;
4578 in
= (exit_qualification
& 8) != 0;
4580 ++vcpu
->stat
.io_exits
;
4583 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4585 port
= exit_qualification
>> 16;
4586 size
= (exit_qualification
& 7) + 1;
4587 skip_emulated_instruction(vcpu
);
4589 return kvm_fast_pio_out(vcpu
, size
, port
);
4593 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4596 * Patch in the VMCALL instruction:
4598 hypercall
[0] = 0x0f;
4599 hypercall
[1] = 0x01;
4600 hypercall
[2] = 0xc1;
4603 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4604 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4606 if (to_vmx(vcpu
)->nested
.vmxon
&&
4607 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4610 if (is_guest_mode(vcpu
)) {
4612 * We get here when L2 changed cr0 in a way that did not change
4613 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4614 * but did change L0 shadowed bits. This can currently happen
4615 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4616 * loading) while pretending to allow the guest to change it.
4618 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4619 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4621 vmcs_writel(CR0_READ_SHADOW
, val
);
4624 return kvm_set_cr0(vcpu
, val
);
4627 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4629 if (is_guest_mode(vcpu
)) {
4630 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4631 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4633 vmcs_writel(CR4_READ_SHADOW
, val
);
4636 return kvm_set_cr4(vcpu
, val
);
4639 /* called to set cr0 as approriate for clts instruction exit. */
4640 static void handle_clts(struct kvm_vcpu
*vcpu
)
4642 if (is_guest_mode(vcpu
)) {
4644 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4645 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4646 * just pretend it's off (also in arch.cr0 for fpu_activate).
4648 vmcs_writel(CR0_READ_SHADOW
,
4649 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4650 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4652 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4655 static int handle_cr(struct kvm_vcpu
*vcpu
)
4657 unsigned long exit_qualification
, val
;
4662 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4663 cr
= exit_qualification
& 15;
4664 reg
= (exit_qualification
>> 8) & 15;
4665 switch ((exit_qualification
>> 4) & 3) {
4666 case 0: /* mov to cr */
4667 val
= kvm_register_read(vcpu
, reg
);
4668 trace_kvm_cr_write(cr
, val
);
4671 err
= handle_set_cr0(vcpu
, val
);
4672 kvm_complete_insn_gp(vcpu
, err
);
4675 err
= kvm_set_cr3(vcpu
, val
);
4676 kvm_complete_insn_gp(vcpu
, err
);
4679 err
= handle_set_cr4(vcpu
, val
);
4680 kvm_complete_insn_gp(vcpu
, err
);
4683 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4684 u8 cr8
= kvm_register_read(vcpu
, reg
);
4685 err
= kvm_set_cr8(vcpu
, cr8
);
4686 kvm_complete_insn_gp(vcpu
, err
);
4687 if (irqchip_in_kernel(vcpu
->kvm
))
4689 if (cr8_prev
<= cr8
)
4691 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4698 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4699 skip_emulated_instruction(vcpu
);
4700 vmx_fpu_activate(vcpu
);
4702 case 1: /*mov from cr*/
4705 val
= kvm_read_cr3(vcpu
);
4706 kvm_register_write(vcpu
, reg
, val
);
4707 trace_kvm_cr_read(cr
, val
);
4708 skip_emulated_instruction(vcpu
);
4711 val
= kvm_get_cr8(vcpu
);
4712 kvm_register_write(vcpu
, reg
, val
);
4713 trace_kvm_cr_read(cr
, val
);
4714 skip_emulated_instruction(vcpu
);
4719 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4720 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4721 kvm_lmsw(vcpu
, val
);
4723 skip_emulated_instruction(vcpu
);
4728 vcpu
->run
->exit_reason
= 0;
4729 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4730 (int)(exit_qualification
>> 4) & 3, cr
);
4734 static int handle_dr(struct kvm_vcpu
*vcpu
)
4736 unsigned long exit_qualification
;
4739 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4740 if (!kvm_require_cpl(vcpu
, 0))
4742 dr
= vmcs_readl(GUEST_DR7
);
4745 * As the vm-exit takes precedence over the debug trap, we
4746 * need to emulate the latter, either for the host or the
4747 * guest debugging itself.
4749 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4750 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4751 vcpu
->run
->debug
.arch
.dr7
= dr
;
4752 vcpu
->run
->debug
.arch
.pc
=
4753 vmcs_readl(GUEST_CS_BASE
) +
4754 vmcs_readl(GUEST_RIP
);
4755 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4756 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4759 vcpu
->arch
.dr7
&= ~DR7_GD
;
4760 vcpu
->arch
.dr6
|= DR6_BD
;
4761 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4762 kvm_queue_exception(vcpu
, DB_VECTOR
);
4767 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4768 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4769 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4770 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4772 if (!kvm_get_dr(vcpu
, dr
, &val
))
4773 kvm_register_write(vcpu
, reg
, val
);
4775 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4776 skip_emulated_instruction(vcpu
);
4780 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4782 vmcs_writel(GUEST_DR7
, val
);
4785 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4787 kvm_emulate_cpuid(vcpu
);
4791 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4793 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4796 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4797 trace_kvm_msr_read_ex(ecx
);
4798 kvm_inject_gp(vcpu
, 0);
4802 trace_kvm_msr_read(ecx
, data
);
4804 /* FIXME: handling of bits 32:63 of rax, rdx */
4805 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4806 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4807 skip_emulated_instruction(vcpu
);
4811 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4813 struct msr_data msr
;
4814 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4815 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4816 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4820 msr
.host_initiated
= false;
4821 if (vmx_set_msr(vcpu
, &msr
) != 0) {
4822 trace_kvm_msr_write_ex(ecx
, data
);
4823 kvm_inject_gp(vcpu
, 0);
4827 trace_kvm_msr_write(ecx
, data
);
4828 skip_emulated_instruction(vcpu
);
4832 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4834 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4838 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4840 u32 cpu_based_vm_exec_control
;
4842 /* clear pending irq */
4843 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4844 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4845 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4847 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4849 ++vcpu
->stat
.irq_window_exits
;
4852 * If the user space waits to inject interrupts, exit as soon as
4855 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4856 vcpu
->run
->request_interrupt_window
&&
4857 !kvm_cpu_has_interrupt(vcpu
)) {
4858 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4864 static int handle_halt(struct kvm_vcpu
*vcpu
)
4866 skip_emulated_instruction(vcpu
);
4867 return kvm_emulate_halt(vcpu
);
4870 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4872 skip_emulated_instruction(vcpu
);
4873 kvm_emulate_hypercall(vcpu
);
4877 static int handle_invd(struct kvm_vcpu
*vcpu
)
4879 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4882 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4884 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4886 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4887 skip_emulated_instruction(vcpu
);
4891 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
4895 err
= kvm_rdpmc(vcpu
);
4896 kvm_complete_insn_gp(vcpu
, err
);
4901 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4903 skip_emulated_instruction(vcpu
);
4904 kvm_emulate_wbinvd(vcpu
);
4908 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4910 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4911 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4913 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4914 skip_emulated_instruction(vcpu
);
4918 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4920 if (likely(fasteoi
)) {
4921 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4922 int access_type
, offset
;
4924 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4925 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4927 * Sane guest uses MOV to write EOI, with written value
4928 * not cared. So make a short-circuit here by avoiding
4929 * heavy instruction emulation.
4931 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4932 (offset
== APIC_EOI
)) {
4933 kvm_lapic_set_eoi(vcpu
);
4934 skip_emulated_instruction(vcpu
);
4938 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4941 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
4943 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4944 int vector
= exit_qualification
& 0xff;
4946 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4947 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
4951 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
4953 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4954 u32 offset
= exit_qualification
& 0xfff;
4956 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4957 kvm_apic_write_nodecode(vcpu
, offset
);
4961 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4963 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4964 unsigned long exit_qualification
;
4965 bool has_error_code
= false;
4968 int reason
, type
, idt_v
, idt_index
;
4970 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4971 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
4972 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4974 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4976 reason
= (u32
)exit_qualification
>> 30;
4977 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4979 case INTR_TYPE_NMI_INTR
:
4980 vcpu
->arch
.nmi_injected
= false;
4981 vmx_set_nmi_mask(vcpu
, true);
4983 case INTR_TYPE_EXT_INTR
:
4984 case INTR_TYPE_SOFT_INTR
:
4985 kvm_clear_interrupt_queue(vcpu
);
4987 case INTR_TYPE_HARD_EXCEPTION
:
4988 if (vmx
->idt_vectoring_info
&
4989 VECTORING_INFO_DELIVER_CODE_MASK
) {
4990 has_error_code
= true;
4992 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4995 case INTR_TYPE_SOFT_EXCEPTION
:
4996 kvm_clear_exception_queue(vcpu
);
5002 tss_selector
= exit_qualification
;
5004 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5005 type
!= INTR_TYPE_EXT_INTR
&&
5006 type
!= INTR_TYPE_NMI_INTR
))
5007 skip_emulated_instruction(vcpu
);
5009 if (kvm_task_switch(vcpu
, tss_selector
,
5010 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5011 has_error_code
, error_code
) == EMULATE_FAIL
) {
5012 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5013 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5014 vcpu
->run
->internal
.ndata
= 0;
5018 /* clear all local breakpoint enable flags */
5019 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5022 * TODO: What about debug traps on tss switch?
5023 * Are we supposed to inject them and update dr6?
5029 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5031 unsigned long exit_qualification
;
5036 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5038 gla_validity
= (exit_qualification
>> 7) & 0x3;
5039 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5040 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5041 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5042 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5043 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5044 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5045 (long unsigned int)exit_qualification
);
5046 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5047 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5051 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5052 trace_kvm_page_fault(gpa
, exit_qualification
);
5054 /* It is a write fault? */
5055 error_code
= exit_qualification
& (1U << 1);
5056 /* ept page table is present? */
5057 error_code
|= (exit_qualification
>> 3) & 0x1;
5059 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5062 static u64
ept_rsvd_mask(u64 spte
, int level
)
5067 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5068 mask
|= (1ULL << i
);
5071 /* bits 7:3 reserved */
5073 else if (level
== 2) {
5074 if (spte
& (1ULL << 7))
5075 /* 2MB ref, bits 20:12 reserved */
5078 /* bits 6:3 reserved */
5085 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5088 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5090 /* 010b (write-only) */
5091 WARN_ON((spte
& 0x7) == 0x2);
5093 /* 110b (write/execute) */
5094 WARN_ON((spte
& 0x7) == 0x6);
5096 /* 100b (execute-only) and value not supported by logical processor */
5097 if (!cpu_has_vmx_ept_execute_only())
5098 WARN_ON((spte
& 0x7) == 0x4);
5102 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5104 if (rsvd_bits
!= 0) {
5105 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5106 __func__
, rsvd_bits
);
5110 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5111 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5113 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5114 ept_mem_type
== 7) {
5115 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5116 __func__
, ept_mem_type
);
5123 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5126 int nr_sptes
, i
, ret
;
5129 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5131 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5132 if (likely(ret
== 1))
5133 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5138 /* It is the real ept misconfig */
5139 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5140 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5142 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5144 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5145 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5147 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5148 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5153 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5155 u32 cpu_based_vm_exec_control
;
5157 /* clear pending NMI */
5158 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5159 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5160 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5161 ++vcpu
->stat
.nmi_window_exits
;
5162 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5167 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5169 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5170 enum emulation_result err
= EMULATE_DONE
;
5173 bool intr_window_requested
;
5174 unsigned count
= 130;
5176 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5177 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5179 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5180 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5181 return handle_interrupt_window(&vmx
->vcpu
);
5183 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5186 err
= emulate_instruction(vcpu
, 0);
5188 if (err
== EMULATE_DO_MMIO
) {
5193 if (err
!= EMULATE_DONE
) {
5194 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5195 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5196 vcpu
->run
->internal
.ndata
= 0;
5200 if (signal_pending(current
))
5206 vmx
->emulation_required
= emulation_required(vcpu
);
5212 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5213 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5215 static int handle_pause(struct kvm_vcpu
*vcpu
)
5217 skip_emulated_instruction(vcpu
);
5218 kvm_vcpu_on_spin(vcpu
);
5223 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5225 kvm_queue_exception(vcpu
, UD_VECTOR
);
5230 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5231 * We could reuse a single VMCS for all the L2 guests, but we also want the
5232 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5233 * allows keeping them loaded on the processor, and in the future will allow
5234 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5235 * every entry if they never change.
5236 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5237 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5239 * The following functions allocate and free a vmcs02 in this pool.
5242 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5243 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5245 struct vmcs02_list
*item
;
5246 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5247 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5248 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5249 return &item
->vmcs02
;
5252 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5253 /* Recycle the least recently used VMCS. */
5254 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5255 struct vmcs02_list
, list
);
5256 item
->vmptr
= vmx
->nested
.current_vmptr
;
5257 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5258 return &item
->vmcs02
;
5261 /* Create a new VMCS */
5262 item
= (struct vmcs02_list
*)
5263 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5266 item
->vmcs02
.vmcs
= alloc_vmcs();
5267 if (!item
->vmcs02
.vmcs
) {
5271 loaded_vmcs_init(&item
->vmcs02
);
5272 item
->vmptr
= vmx
->nested
.current_vmptr
;
5273 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5274 vmx
->nested
.vmcs02_num
++;
5275 return &item
->vmcs02
;
5278 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5279 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5281 struct vmcs02_list
*item
;
5282 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5283 if (item
->vmptr
== vmptr
) {
5284 free_loaded_vmcs(&item
->vmcs02
);
5285 list_del(&item
->list
);
5287 vmx
->nested
.vmcs02_num
--;
5293 * Free all VMCSs saved for this vcpu, except the one pointed by
5294 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5295 * currently used, if running L2), and vmcs01 when running L2.
5297 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5299 struct vmcs02_list
*item
, *n
;
5300 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5301 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5302 free_loaded_vmcs(&item
->vmcs02
);
5303 list_del(&item
->list
);
5306 vmx
->nested
.vmcs02_num
= 0;
5308 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5309 free_loaded_vmcs(&vmx
->vmcs01
);
5313 * Emulate the VMXON instruction.
5314 * Currently, we just remember that VMX is active, and do not save or even
5315 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5316 * do not currently need to store anything in that guest-allocated memory
5317 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5318 * argument is different from the VMXON pointer (which the spec says they do).
5320 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5322 struct kvm_segment cs
;
5323 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5325 /* The Intel VMX Instruction Reference lists a bunch of bits that
5326 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5327 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5328 * Otherwise, we should fail with #UD. We test these now:
5330 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5331 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5332 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5333 kvm_queue_exception(vcpu
, UD_VECTOR
);
5337 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5338 if (is_long_mode(vcpu
) && !cs
.l
) {
5339 kvm_queue_exception(vcpu
, UD_VECTOR
);
5343 if (vmx_get_cpl(vcpu
)) {
5344 kvm_inject_gp(vcpu
, 0);
5348 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5349 vmx
->nested
.vmcs02_num
= 0;
5351 vmx
->nested
.vmxon
= true;
5353 skip_emulated_instruction(vcpu
);
5358 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5359 * for running VMX instructions (except VMXON, whose prerequisites are
5360 * slightly different). It also specifies what exception to inject otherwise.
5362 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5364 struct kvm_segment cs
;
5365 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5367 if (!vmx
->nested
.vmxon
) {
5368 kvm_queue_exception(vcpu
, UD_VECTOR
);
5372 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5373 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5374 (is_long_mode(vcpu
) && !cs
.l
)) {
5375 kvm_queue_exception(vcpu
, UD_VECTOR
);
5379 if (vmx_get_cpl(vcpu
)) {
5380 kvm_inject_gp(vcpu
, 0);
5388 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5389 * just stops using VMX.
5391 static void free_nested(struct vcpu_vmx
*vmx
)
5393 if (!vmx
->nested
.vmxon
)
5395 vmx
->nested
.vmxon
= false;
5396 if (vmx
->nested
.current_vmptr
!= -1ull) {
5397 kunmap(vmx
->nested
.current_vmcs12_page
);
5398 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5399 vmx
->nested
.current_vmptr
= -1ull;
5400 vmx
->nested
.current_vmcs12
= NULL
;
5402 /* Unpin physical memory we referred to in current vmcs02 */
5403 if (vmx
->nested
.apic_access_page
) {
5404 nested_release_page(vmx
->nested
.apic_access_page
);
5405 vmx
->nested
.apic_access_page
= 0;
5408 nested_free_all_saved_vmcss(vmx
);
5411 /* Emulate the VMXOFF instruction */
5412 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5414 if (!nested_vmx_check_permission(vcpu
))
5416 free_nested(to_vmx(vcpu
));
5417 skip_emulated_instruction(vcpu
);
5422 * Decode the memory-address operand of a vmx instruction, as recorded on an
5423 * exit caused by such an instruction (run by a guest hypervisor).
5424 * On success, returns 0. When the operand is invalid, returns 1 and throws
5427 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5428 unsigned long exit_qualification
,
5429 u32 vmx_instruction_info
, gva_t
*ret
)
5432 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5433 * Execution", on an exit, vmx_instruction_info holds most of the
5434 * addressing components of the operand. Only the displacement part
5435 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5436 * For how an actual address is calculated from all these components,
5437 * refer to Vol. 1, "Operand Addressing".
5439 int scaling
= vmx_instruction_info
& 3;
5440 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5441 bool is_reg
= vmx_instruction_info
& (1u << 10);
5442 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5443 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5444 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5445 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5446 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5449 kvm_queue_exception(vcpu
, UD_VECTOR
);
5453 /* Addr = segment_base + offset */
5454 /* offset = base + [index * scale] + displacement */
5455 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5457 *ret
+= kvm_register_read(vcpu
, base_reg
);
5459 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5460 *ret
+= exit_qualification
; /* holds the displacement */
5462 if (addr_size
== 1) /* 32 bit */
5466 * TODO: throw #GP (and return 1) in various cases that the VM*
5467 * instructions require it - e.g., offset beyond segment limit,
5468 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5469 * address, and so on. Currently these are not checked.
5475 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5476 * set the success or error code of an emulated VMX instruction, as specified
5477 * by Vol 2B, VMX Instruction Reference, "Conventions".
5479 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5481 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5482 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5483 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5486 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5488 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5489 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5490 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5494 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5495 u32 vm_instruction_error
)
5497 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5499 * failValid writes the error number to the current VMCS, which
5500 * can't be done there isn't a current VMCS.
5502 nested_vmx_failInvalid(vcpu
);
5505 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5506 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5507 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5509 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5512 /* Emulate the VMCLEAR instruction */
5513 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5515 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5518 struct vmcs12
*vmcs12
;
5520 struct x86_exception e
;
5522 if (!nested_vmx_check_permission(vcpu
))
5525 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5526 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5529 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5530 sizeof(vmptr
), &e
)) {
5531 kvm_inject_page_fault(vcpu
, &e
);
5535 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5536 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5537 skip_emulated_instruction(vcpu
);
5541 if (vmptr
== vmx
->nested
.current_vmptr
) {
5542 kunmap(vmx
->nested
.current_vmcs12_page
);
5543 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5544 vmx
->nested
.current_vmptr
= -1ull;
5545 vmx
->nested
.current_vmcs12
= NULL
;
5548 page
= nested_get_page(vcpu
, vmptr
);
5551 * For accurate processor emulation, VMCLEAR beyond available
5552 * physical memory should do nothing at all. However, it is
5553 * possible that a nested vmx bug, not a guest hypervisor bug,
5554 * resulted in this case, so let's shut down before doing any
5557 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5560 vmcs12
= kmap(page
);
5561 vmcs12
->launch_state
= 0;
5563 nested_release_page(page
);
5565 nested_free_vmcs02(vmx
, vmptr
);
5567 skip_emulated_instruction(vcpu
);
5568 nested_vmx_succeed(vcpu
);
5572 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5574 /* Emulate the VMLAUNCH instruction */
5575 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5577 return nested_vmx_run(vcpu
, true);
5580 /* Emulate the VMRESUME instruction */
5581 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5584 return nested_vmx_run(vcpu
, false);
5587 enum vmcs_field_type
{
5588 VMCS_FIELD_TYPE_U16
= 0,
5589 VMCS_FIELD_TYPE_U64
= 1,
5590 VMCS_FIELD_TYPE_U32
= 2,
5591 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5594 static inline int vmcs_field_type(unsigned long field
)
5596 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5597 return VMCS_FIELD_TYPE_U32
;
5598 return (field
>> 13) & 0x3 ;
5601 static inline int vmcs_field_readonly(unsigned long field
)
5603 return (((field
>> 10) & 0x3) == 1);
5607 * Read a vmcs12 field. Since these can have varying lengths and we return
5608 * one type, we chose the biggest type (u64) and zero-extend the return value
5609 * to that size. Note that the caller, handle_vmread, might need to use only
5610 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5611 * 64-bit fields are to be returned).
5613 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5614 unsigned long field
, u64
*ret
)
5616 short offset
= vmcs_field_to_offset(field
);
5622 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5624 switch (vmcs_field_type(field
)) {
5625 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5626 *ret
= *((natural_width
*)p
);
5628 case VMCS_FIELD_TYPE_U16
:
5631 case VMCS_FIELD_TYPE_U32
:
5634 case VMCS_FIELD_TYPE_U64
:
5638 return 0; /* can never happen. */
5643 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5644 * used before) all generate the same failure when it is missing.
5646 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5648 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5649 if (vmx
->nested
.current_vmptr
== -1ull) {
5650 nested_vmx_failInvalid(vcpu
);
5651 skip_emulated_instruction(vcpu
);
5657 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5659 unsigned long field
;
5661 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5662 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5665 if (!nested_vmx_check_permission(vcpu
) ||
5666 !nested_vmx_check_vmcs12(vcpu
))
5669 /* Decode instruction info and find the field to read */
5670 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5671 /* Read the field, zero-extended to a u64 field_value */
5672 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5673 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5674 skip_emulated_instruction(vcpu
);
5678 * Now copy part of this value to register or memory, as requested.
5679 * Note that the number of bits actually copied is 32 or 64 depending
5680 * on the guest's mode (32 or 64 bit), not on the given field's length.
5682 if (vmx_instruction_info
& (1u << 10)) {
5683 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5686 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5687 vmx_instruction_info
, &gva
))
5689 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5690 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5691 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5694 nested_vmx_succeed(vcpu
);
5695 skip_emulated_instruction(vcpu
);
5700 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5702 unsigned long field
;
5704 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5705 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5708 /* The value to write might be 32 or 64 bits, depending on L1's long
5709 * mode, and eventually we need to write that into a field of several
5710 * possible lengths. The code below first zero-extends the value to 64
5711 * bit (field_value), and then copies only the approriate number of
5712 * bits into the vmcs12 field.
5714 u64 field_value
= 0;
5715 struct x86_exception e
;
5717 if (!nested_vmx_check_permission(vcpu
) ||
5718 !nested_vmx_check_vmcs12(vcpu
))
5721 if (vmx_instruction_info
& (1u << 10))
5722 field_value
= kvm_register_read(vcpu
,
5723 (((vmx_instruction_info
) >> 3) & 0xf));
5725 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5726 vmx_instruction_info
, &gva
))
5728 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5729 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5730 kvm_inject_page_fault(vcpu
, &e
);
5736 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5737 if (vmcs_field_readonly(field
)) {
5738 nested_vmx_failValid(vcpu
,
5739 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5740 skip_emulated_instruction(vcpu
);
5744 offset
= vmcs_field_to_offset(field
);
5746 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5747 skip_emulated_instruction(vcpu
);
5750 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5752 switch (vmcs_field_type(field
)) {
5753 case VMCS_FIELD_TYPE_U16
:
5754 *(u16
*)p
= field_value
;
5756 case VMCS_FIELD_TYPE_U32
:
5757 *(u32
*)p
= field_value
;
5759 case VMCS_FIELD_TYPE_U64
:
5760 *(u64
*)p
= field_value
;
5762 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5763 *(natural_width
*)p
= field_value
;
5766 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5767 skip_emulated_instruction(vcpu
);
5771 nested_vmx_succeed(vcpu
);
5772 skip_emulated_instruction(vcpu
);
5776 /* Emulate the VMPTRLD instruction */
5777 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5779 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5782 struct x86_exception e
;
5784 if (!nested_vmx_check_permission(vcpu
))
5787 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5788 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5791 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5792 sizeof(vmptr
), &e
)) {
5793 kvm_inject_page_fault(vcpu
, &e
);
5797 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5798 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5799 skip_emulated_instruction(vcpu
);
5803 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5804 struct vmcs12
*new_vmcs12
;
5806 page
= nested_get_page(vcpu
, vmptr
);
5808 nested_vmx_failInvalid(vcpu
);
5809 skip_emulated_instruction(vcpu
);
5812 new_vmcs12
= kmap(page
);
5813 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5815 nested_release_page_clean(page
);
5816 nested_vmx_failValid(vcpu
,
5817 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5818 skip_emulated_instruction(vcpu
);
5821 if (vmx
->nested
.current_vmptr
!= -1ull) {
5822 kunmap(vmx
->nested
.current_vmcs12_page
);
5823 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5826 vmx
->nested
.current_vmptr
= vmptr
;
5827 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5828 vmx
->nested
.current_vmcs12_page
= page
;
5831 nested_vmx_succeed(vcpu
);
5832 skip_emulated_instruction(vcpu
);
5836 /* Emulate the VMPTRST instruction */
5837 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5839 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5840 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5842 struct x86_exception e
;
5844 if (!nested_vmx_check_permission(vcpu
))
5847 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5848 vmx_instruction_info
, &vmcs_gva
))
5850 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5851 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5852 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5854 kvm_inject_page_fault(vcpu
, &e
);
5857 nested_vmx_succeed(vcpu
);
5858 skip_emulated_instruction(vcpu
);
5863 * The exit handlers return 1 if the exit was handled fully and guest execution
5864 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5865 * to be done to userspace and return 0.
5867 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5868 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5869 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5870 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5871 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5872 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5873 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5874 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5875 [EXIT_REASON_CPUID
] = handle_cpuid
,
5876 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5877 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5878 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5879 [EXIT_REASON_HLT
] = handle_halt
,
5880 [EXIT_REASON_INVD
] = handle_invd
,
5881 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5882 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
5883 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5884 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5885 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5886 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5887 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5888 [EXIT_REASON_VMREAD
] = handle_vmread
,
5889 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5890 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5891 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5892 [EXIT_REASON_VMON
] = handle_vmon
,
5893 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5894 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5895 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
5896 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
5897 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5898 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5899 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5900 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5901 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5902 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5903 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5904 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5905 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5908 static const int kvm_vmx_max_exit_handlers
=
5909 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5912 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5913 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5914 * disinterest in the current event (read or write a specific MSR) by using an
5915 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5917 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5918 struct vmcs12
*vmcs12
, u32 exit_reason
)
5920 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5923 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
5927 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5928 * for the four combinations of read/write and low/high MSR numbers.
5929 * First we need to figure out which of the four to use:
5931 bitmap
= vmcs12
->msr_bitmap
;
5932 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5934 if (msr_index
>= 0xc0000000) {
5935 msr_index
-= 0xc0000000;
5939 /* Then read the msr_index'th bit from this bitmap: */
5940 if (msr_index
< 1024*8) {
5942 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5943 return 1 & (b
>> (msr_index
& 7));
5945 return 1; /* let L1 handle the wrong parameter */
5949 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5950 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5951 * intercept (via guest_host_mask etc.) the current event.
5953 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5954 struct vmcs12
*vmcs12
)
5956 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5957 int cr
= exit_qualification
& 15;
5958 int reg
= (exit_qualification
>> 8) & 15;
5959 unsigned long val
= kvm_register_read(vcpu
, reg
);
5961 switch ((exit_qualification
>> 4) & 3) {
5962 case 0: /* mov to cr */
5965 if (vmcs12
->cr0_guest_host_mask
&
5966 (val
^ vmcs12
->cr0_read_shadow
))
5970 if ((vmcs12
->cr3_target_count
>= 1 &&
5971 vmcs12
->cr3_target_value0
== val
) ||
5972 (vmcs12
->cr3_target_count
>= 2 &&
5973 vmcs12
->cr3_target_value1
== val
) ||
5974 (vmcs12
->cr3_target_count
>= 3 &&
5975 vmcs12
->cr3_target_value2
== val
) ||
5976 (vmcs12
->cr3_target_count
>= 4 &&
5977 vmcs12
->cr3_target_value3
== val
))
5979 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5983 if (vmcs12
->cr4_guest_host_mask
&
5984 (vmcs12
->cr4_read_shadow
^ val
))
5988 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5994 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5995 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5998 case 1: /* mov from cr */
6001 if (vmcs12
->cpu_based_vm_exec_control
&
6002 CPU_BASED_CR3_STORE_EXITING
)
6006 if (vmcs12
->cpu_based_vm_exec_control
&
6007 CPU_BASED_CR8_STORE_EXITING
)
6014 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6015 * cr0. Other attempted changes are ignored, with no exit.
6017 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6018 (val
^ vmcs12
->cr0_read_shadow
))
6020 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6021 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6030 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6031 * should handle it ourselves in L0 (and then continue L2). Only call this
6032 * when in is_guest_mode (L2).
6034 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6036 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6037 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6039 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6041 if (vmx
->nested
.nested_run_pending
)
6044 if (unlikely(vmx
->fail
)) {
6045 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6046 vmcs_read32(VM_INSTRUCTION_ERROR
));
6050 switch (exit_reason
) {
6051 case EXIT_REASON_EXCEPTION_NMI
:
6052 if (!is_exception(intr_info
))
6054 else if (is_page_fault(intr_info
))
6056 return vmcs12
->exception_bitmap
&
6057 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6058 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6060 case EXIT_REASON_TRIPLE_FAULT
:
6062 case EXIT_REASON_PENDING_INTERRUPT
:
6063 case EXIT_REASON_NMI_WINDOW
:
6065 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6066 * (aka Interrupt Window Exiting) only when L1 turned it on,
6067 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6068 * Same for NMI Window Exiting.
6071 case EXIT_REASON_TASK_SWITCH
:
6073 case EXIT_REASON_CPUID
:
6075 case EXIT_REASON_HLT
:
6076 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6077 case EXIT_REASON_INVD
:
6079 case EXIT_REASON_INVLPG
:
6080 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6081 case EXIT_REASON_RDPMC
:
6082 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6083 case EXIT_REASON_RDTSC
:
6084 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6085 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6086 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6087 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6088 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6089 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6091 * VMX instructions trap unconditionally. This allows L1 to
6092 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6095 case EXIT_REASON_CR_ACCESS
:
6096 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6097 case EXIT_REASON_DR_ACCESS
:
6098 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6099 case EXIT_REASON_IO_INSTRUCTION
:
6100 /* TODO: support IO bitmaps */
6102 case EXIT_REASON_MSR_READ
:
6103 case EXIT_REASON_MSR_WRITE
:
6104 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6105 case EXIT_REASON_INVALID_STATE
:
6107 case EXIT_REASON_MWAIT_INSTRUCTION
:
6108 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6109 case EXIT_REASON_MONITOR_INSTRUCTION
:
6110 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6111 case EXIT_REASON_PAUSE_INSTRUCTION
:
6112 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6113 nested_cpu_has2(vmcs12
,
6114 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6115 case EXIT_REASON_MCE_DURING_VMENTRY
:
6117 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6119 case EXIT_REASON_APIC_ACCESS
:
6120 return nested_cpu_has2(vmcs12
,
6121 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6122 case EXIT_REASON_EPT_VIOLATION
:
6123 case EXIT_REASON_EPT_MISCONFIG
:
6125 case EXIT_REASON_WBINVD
:
6126 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6127 case EXIT_REASON_XSETBV
:
6134 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6136 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6137 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6141 * The guest has exited. See if we can fix it or if we need userspace
6144 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6146 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6147 u32 exit_reason
= vmx
->exit_reason
;
6148 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6150 /* If guest state is invalid, start emulating */
6151 if (vmx
->emulation_required
)
6152 return handle_invalid_guest_state(vcpu
);
6155 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6156 * we did not inject a still-pending event to L1 now because of
6157 * nested_run_pending, we need to re-enable this bit.
6159 if (vmx
->nested
.nested_run_pending
)
6160 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6162 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
6163 exit_reason
== EXIT_REASON_VMRESUME
))
6164 vmx
->nested
.nested_run_pending
= 1;
6166 vmx
->nested
.nested_run_pending
= 0;
6168 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6169 nested_vmx_vmexit(vcpu
);
6173 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6174 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6175 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6180 if (unlikely(vmx
->fail
)) {
6181 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6182 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6183 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6189 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6190 * delivery event since it indicates guest is accessing MMIO.
6191 * The vm-exit can be triggered again after return to guest that
6192 * will cause infinite loop.
6194 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6195 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6196 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6197 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6198 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6199 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6200 vcpu
->run
->internal
.ndata
= 2;
6201 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6202 vcpu
->run
->internal
.data
[1] = exit_reason
;
6206 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6207 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6208 get_vmcs12(vcpu
), vcpu
)))) {
6209 if (vmx_interrupt_allowed(vcpu
)) {
6210 vmx
->soft_vnmi_blocked
= 0;
6211 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6212 vcpu
->arch
.nmi_pending
) {
6214 * This CPU don't support us in finding the end of an
6215 * NMI-blocked window if the guest runs with IRQs
6216 * disabled. So we pull the trigger after 1 s of
6217 * futile waiting, but inform the user about this.
6219 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6220 "state on VCPU %d after 1 s timeout\n",
6221 __func__
, vcpu
->vcpu_id
);
6222 vmx
->soft_vnmi_blocked
= 0;
6226 if (exit_reason
< kvm_vmx_max_exit_handlers
6227 && kvm_vmx_exit_handlers
[exit_reason
])
6228 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6230 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6231 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6236 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6238 if (irr
== -1 || tpr
< irr
) {
6239 vmcs_write32(TPR_THRESHOLD
, 0);
6243 vmcs_write32(TPR_THRESHOLD
, irr
);
6246 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6248 u32 sec_exec_control
;
6251 * There is not point to enable virtualize x2apic without enable
6254 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6255 !vmx_vm_has_apicv(vcpu
->kvm
))
6258 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6261 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6264 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6265 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6267 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6268 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6270 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6272 vmx_set_msr_bitmap(vcpu
);
6275 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6280 if (!vmx_vm_has_apicv(kvm
))
6286 status
= vmcs_read16(GUEST_INTR_STATUS
);
6291 vmcs_write16(GUEST_INTR_STATUS
, status
);
6295 static void vmx_set_rvi(int vector
)
6300 status
= vmcs_read16(GUEST_INTR_STATUS
);
6301 old
= (u8
)status
& 0xff;
6302 if ((u8
)vector
!= old
) {
6304 status
|= (u8
)vector
;
6305 vmcs_write16(GUEST_INTR_STATUS
, status
);
6309 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6314 vmx_set_rvi(max_irr
);
6317 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6319 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6320 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6321 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6322 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6325 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6329 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6330 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6333 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6334 exit_intr_info
= vmx
->exit_intr_info
;
6336 /* Handle machine checks before interrupts are enabled */
6337 if (is_machine_check(exit_intr_info
))
6338 kvm_machine_check();
6340 /* We need to handle NMIs before interrupts are enabled */
6341 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6342 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6343 kvm_before_handle_nmi(&vmx
->vcpu
);
6345 kvm_after_handle_nmi(&vmx
->vcpu
);
6349 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6354 bool idtv_info_valid
;
6356 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6358 if (cpu_has_virtual_nmis()) {
6359 if (vmx
->nmi_known_unmasked
)
6362 * Can't use vmx->exit_intr_info since we're not sure what
6363 * the exit reason is.
6365 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6366 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6367 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6369 * SDM 3: 27.7.1.2 (September 2008)
6370 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6371 * a guest IRET fault.
6372 * SDM 3: 23.2.2 (September 2008)
6373 * Bit 12 is undefined in any of the following cases:
6374 * If the VM exit sets the valid bit in the IDT-vectoring
6375 * information field.
6376 * If the VM exit is due to a double fault.
6378 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6379 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6380 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6381 GUEST_INTR_STATE_NMI
);
6383 vmx
->nmi_known_unmasked
=
6384 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6385 & GUEST_INTR_STATE_NMI
);
6386 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6387 vmx
->vnmi_blocked_time
+=
6388 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6391 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
6392 u32 idt_vectoring_info
,
6393 int instr_len_field
,
6394 int error_code_field
)
6398 bool idtv_info_valid
;
6400 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6402 vmx
->vcpu
.arch
.nmi_injected
= false;
6403 kvm_clear_exception_queue(&vmx
->vcpu
);
6404 kvm_clear_interrupt_queue(&vmx
->vcpu
);
6406 if (!idtv_info_valid
)
6409 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6411 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6412 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6415 case INTR_TYPE_NMI_INTR
:
6416 vmx
->vcpu
.arch
.nmi_injected
= true;
6418 * SDM 3: 27.7.1.2 (September 2008)
6419 * Clear bit "block by NMI" before VM entry if a NMI
6422 vmx_set_nmi_mask(&vmx
->vcpu
, false);
6424 case INTR_TYPE_SOFT_EXCEPTION
:
6425 vmx
->vcpu
.arch
.event_exit_inst_len
=
6426 vmcs_read32(instr_len_field
);
6428 case INTR_TYPE_HARD_EXCEPTION
:
6429 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6430 u32 err
= vmcs_read32(error_code_field
);
6431 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
6433 kvm_queue_exception(&vmx
->vcpu
, vector
);
6435 case INTR_TYPE_SOFT_INTR
:
6436 vmx
->vcpu
.arch
.event_exit_inst_len
=
6437 vmcs_read32(instr_len_field
);
6439 case INTR_TYPE_EXT_INTR
:
6440 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
6441 type
== INTR_TYPE_SOFT_INTR
);
6448 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6450 if (is_guest_mode(&vmx
->vcpu
))
6452 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
6453 VM_EXIT_INSTRUCTION_LEN
,
6454 IDT_VECTORING_ERROR_CODE
);
6457 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6459 if (is_guest_mode(vcpu
))
6461 __vmx_complete_interrupts(to_vmx(vcpu
),
6462 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6463 VM_ENTRY_INSTRUCTION_LEN
,
6464 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6466 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6469 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6472 struct perf_guest_switch_msr
*msrs
;
6474 msrs
= perf_guest_get_msrs(&nr_msrs
);
6479 for (i
= 0; i
< nr_msrs
; i
++)
6480 if (msrs
[i
].host
== msrs
[i
].guest
)
6481 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6483 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6487 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6490 unsigned long debugctlmsr
;
6492 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
6493 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6494 if (vmcs12
->idt_vectoring_info_field
&
6495 VECTORING_INFO_VALID_MASK
) {
6496 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6497 vmcs12
->idt_vectoring_info_field
);
6498 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6499 vmcs12
->vm_exit_instruction_len
);
6500 if (vmcs12
->idt_vectoring_info_field
&
6501 VECTORING_INFO_DELIVER_CODE_MASK
)
6502 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6503 vmcs12
->idt_vectoring_error_code
);
6507 /* Record the guest's net vcpu time for enforced NMI injections. */
6508 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6509 vmx
->entry_time
= ktime_get();
6511 /* Don't enter VMX if guest state is invalid, let the exit handler
6512 start emulation until we arrive back to a valid state */
6513 if (vmx
->emulation_required
)
6516 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6517 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6518 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6519 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6521 /* When single-stepping over STI and MOV SS, we must clear the
6522 * corresponding interruptibility bits in the guest state. Otherwise
6523 * vmentry fails as it then expects bit 14 (BS) in pending debug
6524 * exceptions being set, but that's not correct for the guest debugging
6526 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6527 vmx_set_interrupt_shadow(vcpu
, 0);
6529 atomic_switch_perf_msrs(vmx
);
6530 debugctlmsr
= get_debugctlmsr();
6532 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6534 /* Store host registers */
6535 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
6536 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
6537 "push %%" _ASM_CX
" \n\t"
6538 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6540 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6541 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6543 /* Reload cr2 if changed */
6544 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
6545 "mov %%cr2, %%" _ASM_DX
" \n\t"
6546 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
6548 "mov %%" _ASM_AX
", %%cr2 \n\t"
6550 /* Check if vmlaunch of vmresume is needed */
6551 "cmpl $0, %c[launched](%0) \n\t"
6552 /* Load guest registers. Don't clobber flags. */
6553 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
6554 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
6555 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
6556 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
6557 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
6558 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
6559 #ifdef CONFIG_X86_64
6560 "mov %c[r8](%0), %%r8 \n\t"
6561 "mov %c[r9](%0), %%r9 \n\t"
6562 "mov %c[r10](%0), %%r10 \n\t"
6563 "mov %c[r11](%0), %%r11 \n\t"
6564 "mov %c[r12](%0), %%r12 \n\t"
6565 "mov %c[r13](%0), %%r13 \n\t"
6566 "mov %c[r14](%0), %%r14 \n\t"
6567 "mov %c[r15](%0), %%r15 \n\t"
6569 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
6571 /* Enter guest mode */
6573 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6575 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6577 /* Save guest registers, load host registers, keep flags */
6578 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
6580 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
6581 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
6582 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
6583 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
6584 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
6585 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
6586 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
6587 #ifdef CONFIG_X86_64
6588 "mov %%r8, %c[r8](%0) \n\t"
6589 "mov %%r9, %c[r9](%0) \n\t"
6590 "mov %%r10, %c[r10](%0) \n\t"
6591 "mov %%r11, %c[r11](%0) \n\t"
6592 "mov %%r12, %c[r12](%0) \n\t"
6593 "mov %%r13, %c[r13](%0) \n\t"
6594 "mov %%r14, %c[r14](%0) \n\t"
6595 "mov %%r15, %c[r15](%0) \n\t"
6597 "mov %%cr2, %%" _ASM_AX
" \n\t"
6598 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
6600 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
6601 "setbe %c[fail](%0) \n\t"
6602 ".pushsection .rodata \n\t"
6603 ".global vmx_return \n\t"
6604 "vmx_return: " _ASM_PTR
" 2b \n\t"
6606 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6607 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6608 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6609 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6610 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6611 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6612 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6613 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6614 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6615 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6616 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6617 #ifdef CONFIG_X86_64
6618 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6619 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6620 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6621 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6622 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6623 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6624 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6625 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6627 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6628 [wordsize
]"i"(sizeof(ulong
))
6630 #ifdef CONFIG_X86_64
6631 , "rax", "rbx", "rdi", "rsi"
6632 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6634 , "eax", "ebx", "edi", "esi"
6638 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6640 update_debugctlmsr(debugctlmsr
);
6642 #ifndef CONFIG_X86_64
6644 * The sysexit path does not restore ds/es, so we must set them to
6645 * a reasonable value ourselves.
6647 * We can't defer this to vmx_load_host_state() since that function
6648 * may be executed in interrupt context, which saves and restore segments
6649 * around it, nullifying its effect.
6651 loadsegment(ds
, __USER_DS
);
6652 loadsegment(es
, __USER_DS
);
6655 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6656 | (1 << VCPU_EXREG_RFLAGS
)
6657 | (1 << VCPU_EXREG_CPL
)
6658 | (1 << VCPU_EXREG_PDPTR
)
6659 | (1 << VCPU_EXREG_SEGMENTS
)
6660 | (1 << VCPU_EXREG_CR3
));
6661 vcpu
->arch
.regs_dirty
= 0;
6663 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6665 if (is_guest_mode(vcpu
)) {
6666 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6667 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6668 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6669 vmcs12
->idt_vectoring_error_code
=
6670 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6671 vmcs12
->vm_exit_instruction_len
=
6672 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6676 vmx
->loaded_vmcs
->launched
= 1;
6678 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6679 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6681 vmx_complete_atomic_exit(vmx
);
6682 vmx_recover_nmi_blocking(vmx
);
6683 vmx_complete_interrupts(vmx
);
6686 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6688 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6692 free_loaded_vmcs(vmx
->loaded_vmcs
);
6693 kfree(vmx
->guest_msrs
);
6694 kvm_vcpu_uninit(vcpu
);
6695 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6698 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6701 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6705 return ERR_PTR(-ENOMEM
);
6709 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6713 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6715 if (!vmx
->guest_msrs
) {
6719 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6720 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6721 if (!vmx
->loaded_vmcs
->vmcs
)
6724 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6725 loaded_vmcs_init(vmx
->loaded_vmcs
);
6730 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6731 vmx
->vcpu
.cpu
= cpu
;
6732 err
= vmx_vcpu_setup(vmx
);
6733 vmx_vcpu_put(&vmx
->vcpu
);
6737 if (vm_need_virtualize_apic_accesses(kvm
))
6738 err
= alloc_apic_access_page(kvm
);
6743 if (!kvm
->arch
.ept_identity_map_addr
)
6744 kvm
->arch
.ept_identity_map_addr
=
6745 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6747 if (alloc_identity_pagetable(kvm
) != 0)
6749 if (!init_rmode_identity_map(kvm
))
6753 vmx
->nested
.current_vmptr
= -1ull;
6754 vmx
->nested
.current_vmcs12
= NULL
;
6759 free_loaded_vmcs(vmx
->loaded_vmcs
);
6761 kfree(vmx
->guest_msrs
);
6763 kvm_vcpu_uninit(&vmx
->vcpu
);
6766 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6767 return ERR_PTR(err
);
6770 static void __init
vmx_check_processor_compat(void *rtn
)
6772 struct vmcs_config vmcs_conf
;
6775 if (setup_vmcs_config(&vmcs_conf
) < 0)
6777 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6778 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6779 smp_processor_id());
6784 static int get_ept_level(void)
6786 return VMX_EPT_DEFAULT_GAW
+ 1;
6789 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6793 /* For VT-d and EPT combination
6794 * 1. MMIO: always map as UC
6796 * a. VT-d without snooping control feature: can't guarantee the
6797 * result, try to trust guest.
6798 * b. VT-d with snooping control feature: snooping control feature of
6799 * VT-d engine can guarantee the cache correctness. Just set it
6800 * to WB to keep consistent with host. So the same as item 3.
6801 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6802 * consistent with host MTRR
6805 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6806 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6807 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6808 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6809 VMX_EPT_MT_EPTE_SHIFT
;
6811 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6817 static int vmx_get_lpage_level(void)
6819 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6820 return PT_DIRECTORY_LEVEL
;
6822 /* For shadow and EPT supported 1GB page */
6823 return PT_PDPE_LEVEL
;
6826 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6828 struct kvm_cpuid_entry2
*best
;
6829 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6832 vmx
->rdtscp_enabled
= false;
6833 if (vmx_rdtscp_supported()) {
6834 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6835 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6836 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6837 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6838 vmx
->rdtscp_enabled
= true;
6840 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6841 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6847 /* Exposing INVPCID only when PCID is exposed */
6848 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
6849 if (vmx_invpcid_supported() &&
6850 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
6851 guest_cpuid_has_pcid(vcpu
)) {
6852 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6853 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
6854 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6857 if (cpu_has_secondary_exec_ctrls()) {
6858 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6859 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
6860 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6864 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
6868 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6870 if (func
== 1 && nested
)
6871 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6875 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6876 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6877 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6878 * guest in a way that will both be appropriate to L1's requests, and our
6879 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6880 * function also has additional necessary side-effects, like setting various
6881 * vcpu->arch fields.
6883 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6888 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6889 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6890 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6891 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6892 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6893 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6894 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6895 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6896 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6897 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6898 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6899 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6900 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6901 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6902 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6903 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6904 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6905 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6906 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6907 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6908 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6909 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6910 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6911 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6912 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6913 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6914 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6915 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6916 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6917 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6918 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6919 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6920 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6921 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6922 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6923 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6925 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6926 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6927 vmcs12
->vm_entry_intr_info_field
);
6928 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6929 vmcs12
->vm_entry_exception_error_code
);
6930 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6931 vmcs12
->vm_entry_instruction_len
);
6932 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6933 vmcs12
->guest_interruptibility_info
);
6934 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6935 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6936 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6937 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6938 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6939 vmcs12
->guest_pending_dbg_exceptions
);
6940 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6941 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6943 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6945 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6946 (vmcs_config
.pin_based_exec_ctrl
|
6947 vmcs12
->pin_based_vm_exec_control
));
6950 * Whether page-faults are trapped is determined by a combination of
6951 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6952 * If enable_ept, L0 doesn't care about page faults and we should
6953 * set all of these to L1's desires. However, if !enable_ept, L0 does
6954 * care about (at least some) page faults, and because it is not easy
6955 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6956 * to exit on each and every L2 page fault. This is done by setting
6957 * MASK=MATCH=0 and (see below) EB.PF=1.
6958 * Note that below we don't need special code to set EB.PF beyond the
6959 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6960 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6961 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6963 * A problem with this approach (when !enable_ept) is that L1 may be
6964 * injected with more page faults than it asked for. This could have
6965 * caused problems, but in practice existing hypervisors don't care.
6966 * To fix this, we will need to emulate the PFEC checking (on the L1
6967 * page tables), using walk_addr(), when injecting PFs to L1.
6969 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6970 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6971 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6972 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6974 if (cpu_has_secondary_exec_ctrls()) {
6975 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6976 if (!vmx
->rdtscp_enabled
)
6977 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6978 /* Take the following fields only from vmcs12 */
6979 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6980 if (nested_cpu_has(vmcs12
,
6981 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6982 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6984 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6986 * Translate L1 physical address to host physical
6987 * address for vmcs02. Keep the page pinned, so this
6988 * physical address remains valid. We keep a reference
6989 * to it so we can release it later.
6991 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6992 nested_release_page(vmx
->nested
.apic_access_page
);
6993 vmx
->nested
.apic_access_page
=
6994 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6996 * If translation failed, no matter: This feature asks
6997 * to exit when accessing the given address, and if it
6998 * can never be accessed, this feature won't do
7001 if (!vmx
->nested
.apic_access_page
)
7003 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7005 vmcs_write64(APIC_ACCESS_ADDR
,
7006 page_to_phys(vmx
->nested
.apic_access_page
));
7009 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7014 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7015 * Some constant fields are set here by vmx_set_constant_host_state().
7016 * Other fields are different per CPU, and will be set later when
7017 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7019 vmx_set_constant_host_state();
7022 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7023 * entry, but only if the current (host) sp changed from the value
7024 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7025 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7026 * here we just force the write to happen on entry.
7030 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7031 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7032 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7033 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7034 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7036 * Merging of IO and MSR bitmaps not currently supported.
7037 * Rather, exit every time.
7039 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7040 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7041 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7043 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7045 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7046 * bitwise-or of what L1 wants to trap for L2, and what we want to
7047 * trap. Note that CR0.TS also needs updating - we do this later.
7049 update_exception_bitmap(vcpu
);
7050 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7051 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7053 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7054 vmcs_write32(VM_EXIT_CONTROLS
,
7055 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
7056 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
7057 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7059 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
7060 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7061 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7062 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7065 set_cr4_guest_host_mask(vmx
);
7067 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7068 vmcs_write64(TSC_OFFSET
,
7069 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7071 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7075 * Trivially support vpid by letting L2s share their parent
7076 * L1's vpid. TODO: move to a more elaborate solution, giving
7077 * each L2 its own vpid and exposing the vpid feature to L1.
7079 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7080 vmx_flush_tlb(vcpu
);
7083 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7084 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7085 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7086 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7088 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7089 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7090 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7093 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7094 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7095 * The CR0_READ_SHADOW is what L2 should have expected to read given
7096 * the specifications by L1; It's not enough to take
7097 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7098 * have more bits than L1 expected.
7100 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7101 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7103 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7104 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7106 /* shadow page tables on either EPT or shadow page tables */
7107 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7108 kvm_mmu_reset_context(vcpu
);
7110 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7111 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7115 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7116 * for running an L2 nested guest.
7118 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7120 struct vmcs12
*vmcs12
;
7121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7123 struct loaded_vmcs
*vmcs02
;
7125 if (!nested_vmx_check_permission(vcpu
) ||
7126 !nested_vmx_check_vmcs12(vcpu
))
7129 skip_emulated_instruction(vcpu
);
7130 vmcs12
= get_vmcs12(vcpu
);
7133 * The nested entry process starts with enforcing various prerequisites
7134 * on vmcs12 as required by the Intel SDM, and act appropriately when
7135 * they fail: As the SDM explains, some conditions should cause the
7136 * instruction to fail, while others will cause the instruction to seem
7137 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7138 * To speed up the normal (success) code path, we should avoid checking
7139 * for misconfigurations which will anyway be caught by the processor
7140 * when using the merged vmcs02.
7142 if (vmcs12
->launch_state
== launch
) {
7143 nested_vmx_failValid(vcpu
,
7144 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7145 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7149 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7150 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7151 /*TODO: Also verify bits beyond physical address width are 0*/
7152 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7156 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7157 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7158 /*TODO: Also verify bits beyond physical address width are 0*/
7159 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7163 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7164 vmcs12
->vm_exit_msr_load_count
> 0 ||
7165 vmcs12
->vm_exit_msr_store_count
> 0) {
7166 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7168 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7172 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7173 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7174 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7175 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7176 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7177 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7178 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7179 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7180 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7181 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7183 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7187 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7188 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7189 nested_vmx_failValid(vcpu
,
7190 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7194 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7195 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7196 nested_vmx_entry_failure(vcpu
, vmcs12
,
7197 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7200 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7201 nested_vmx_entry_failure(vcpu
, vmcs12
,
7202 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
7207 * We're finally done with prerequisite checking, and can start with
7211 vmcs02
= nested_get_current_vmcs02(vmx
);
7215 enter_guest_mode(vcpu
);
7217 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
7220 vmx
->loaded_vmcs
= vmcs02
;
7222 vmx_vcpu_load(vcpu
, cpu
);
7226 vmcs12
->launch_state
= 1;
7228 prepare_vmcs02(vcpu
, vmcs12
);
7231 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7232 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7233 * returned as far as L1 is concerned. It will only return (and set
7234 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7240 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7241 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7242 * This function returns the new value we should put in vmcs12.guest_cr0.
7243 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7244 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7245 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7246 * didn't trap the bit, because if L1 did, so would L0).
7247 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7248 * been modified by L2, and L1 knows it. So just leave the old value of
7249 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7250 * isn't relevant, because if L0 traps this bit it can set it to anything.
7251 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7252 * changed these bits, and therefore they need to be updated, but L0
7253 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7254 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7256 static inline unsigned long
7257 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7260 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
7261 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
7262 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
7263 vcpu
->arch
.cr0_guest_owned_bits
));
7266 static inline unsigned long
7267 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7270 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
7271 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
7272 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
7273 vcpu
->arch
.cr4_guest_owned_bits
));
7277 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7278 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7279 * and this function updates it to reflect the changes to the guest state while
7280 * L2 was running (and perhaps made some exits which were handled directly by L0
7281 * without going back to L1), and to reflect the exit reason.
7282 * Note that we do not have to copy here all VMCS fields, just those that
7283 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7284 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7285 * which already writes to vmcs12 directly.
7287 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7289 /* update guest state fields: */
7290 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
7291 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
7293 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
7294 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
7295 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
7296 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
7298 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
7299 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
7300 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
7301 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
7302 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
7303 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
7304 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
7305 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
7306 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
7307 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
7308 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
7309 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
7310 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
7311 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
7312 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
7313 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
7314 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
7315 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
7316 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
7317 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
7318 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
7319 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
7320 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
7321 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
7322 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
7323 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
7324 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
7325 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
7326 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
7327 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
7328 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
7329 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
7330 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
7331 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
7332 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
7333 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
7335 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
7336 vmcs12
->guest_interruptibility_info
=
7337 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
7338 vmcs12
->guest_pending_dbg_exceptions
=
7339 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
7341 /* TODO: These cannot have changed unless we have MSR bitmaps and
7342 * the relevant bit asks not to trap the change */
7343 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
7344 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
7345 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
7346 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
7347 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
7348 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
7350 /* update exit information fields: */
7352 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7353 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7355 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7356 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7357 vmcs12
->idt_vectoring_info_field
=
7358 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7359 vmcs12
->idt_vectoring_error_code
=
7360 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
7361 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7362 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7364 /* clear vm-entry fields which are to be cleared on exit */
7365 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
7366 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
7370 * A part of what we need to when the nested L2 guest exits and we want to
7371 * run its L1 parent, is to reset L1's guest state to the host state specified
7373 * This function is to be called not only on normal nested exit, but also on
7374 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7375 * Failures During or After Loading Guest State").
7376 * This function should be called when the active VMCS is L1's (vmcs01).
7378 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7380 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
7381 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7382 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7383 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7385 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7386 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7388 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7389 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7391 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7392 * actually changed, because it depends on the current state of
7393 * fpu_active (which may have changed).
7394 * Note that vmx_set_cr0 refers to efer set above.
7396 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
7398 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7399 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7400 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7402 update_exception_bitmap(vcpu
);
7403 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
7404 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7407 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7408 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7410 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
7411 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
7413 /* shadow page tables on either EPT or shadow page tables */
7414 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
7415 kvm_mmu_reset_context(vcpu
);
7419 * Trivially support vpid by letting L2s share their parent
7420 * L1's vpid. TODO: move to a more elaborate solution, giving
7421 * each L2 its own vpid and exposing the vpid feature to L1.
7423 vmx_flush_tlb(vcpu
);
7427 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
7428 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
7429 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
7430 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
7431 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
7432 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
7433 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
7434 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
7435 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
7436 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
7437 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
7438 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
7439 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
7440 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
7441 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
7443 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
7444 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
7445 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7446 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
7447 vmcs12
->host_ia32_perf_global_ctrl
);
7451 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7452 * and modify vmcs12 to make it see what it would expect to see there if
7453 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7455 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
7457 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7459 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7461 leave_guest_mode(vcpu
);
7462 prepare_vmcs12(vcpu
, vmcs12
);
7465 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7467 vmx_vcpu_load(vcpu
, cpu
);
7471 /* if no vmcs02 cache requested, remove the one we used */
7472 if (VMCS02_POOL_SIZE
== 0)
7473 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
7475 load_vmcs12_host_state(vcpu
, vmcs12
);
7477 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7478 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7480 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7483 /* Unpin physical memory we referred to in vmcs02 */
7484 if (vmx
->nested
.apic_access_page
) {
7485 nested_release_page(vmx
->nested
.apic_access_page
);
7486 vmx
->nested
.apic_access_page
= 0;
7490 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7491 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7492 * success or failure flag accordingly.
7494 if (unlikely(vmx
->fail
)) {
7496 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
7498 nested_vmx_succeed(vcpu
);
7502 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7503 * 23.7 "VM-entry failures during or after loading guest state" (this also
7504 * lists the acceptable exit-reason and exit-qualification parameters).
7505 * It should only be called before L2 actually succeeded to run, and when
7506 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7508 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
7509 struct vmcs12
*vmcs12
,
7510 u32 reason
, unsigned long qualification
)
7512 load_vmcs12_host_state(vcpu
, vmcs12
);
7513 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
7514 vmcs12
->exit_qualification
= qualification
;
7515 nested_vmx_succeed(vcpu
);
7518 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7519 struct x86_instruction_info
*info
,
7520 enum x86_intercept_stage stage
)
7522 return X86EMUL_CONTINUE
;
7525 static struct kvm_x86_ops vmx_x86_ops
= {
7526 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7527 .disabled_by_bios
= vmx_disabled_by_bios
,
7528 .hardware_setup
= hardware_setup
,
7529 .hardware_unsetup
= hardware_unsetup
,
7530 .check_processor_compatibility
= vmx_check_processor_compat
,
7531 .hardware_enable
= hardware_enable
,
7532 .hardware_disable
= hardware_disable
,
7533 .cpu_has_accelerated_tpr
= report_flexpriority
,
7535 .vcpu_create
= vmx_create_vcpu
,
7536 .vcpu_free
= vmx_free_vcpu
,
7537 .vcpu_reset
= vmx_vcpu_reset
,
7539 .prepare_guest_switch
= vmx_save_host_state
,
7540 .vcpu_load
= vmx_vcpu_load
,
7541 .vcpu_put
= vmx_vcpu_put
,
7543 .update_db_bp_intercept
= update_exception_bitmap
,
7544 .get_msr
= vmx_get_msr
,
7545 .set_msr
= vmx_set_msr
,
7546 .get_segment_base
= vmx_get_segment_base
,
7547 .get_segment
= vmx_get_segment
,
7548 .set_segment
= vmx_set_segment
,
7549 .get_cpl
= vmx_get_cpl
,
7550 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7551 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7552 .decache_cr3
= vmx_decache_cr3
,
7553 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7554 .set_cr0
= vmx_set_cr0
,
7555 .set_cr3
= vmx_set_cr3
,
7556 .set_cr4
= vmx_set_cr4
,
7557 .set_efer
= vmx_set_efer
,
7558 .get_idt
= vmx_get_idt
,
7559 .set_idt
= vmx_set_idt
,
7560 .get_gdt
= vmx_get_gdt
,
7561 .set_gdt
= vmx_set_gdt
,
7562 .set_dr7
= vmx_set_dr7
,
7563 .cache_reg
= vmx_cache_reg
,
7564 .get_rflags
= vmx_get_rflags
,
7565 .set_rflags
= vmx_set_rflags
,
7566 .fpu_activate
= vmx_fpu_activate
,
7567 .fpu_deactivate
= vmx_fpu_deactivate
,
7569 .tlb_flush
= vmx_flush_tlb
,
7571 .run
= vmx_vcpu_run
,
7572 .handle_exit
= vmx_handle_exit
,
7573 .skip_emulated_instruction
= skip_emulated_instruction
,
7574 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7575 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7576 .patch_hypercall
= vmx_patch_hypercall
,
7577 .set_irq
= vmx_inject_irq
,
7578 .set_nmi
= vmx_inject_nmi
,
7579 .queue_exception
= vmx_queue_exception
,
7580 .cancel_injection
= vmx_cancel_injection
,
7581 .interrupt_allowed
= vmx_interrupt_allowed
,
7582 .nmi_allowed
= vmx_nmi_allowed
,
7583 .get_nmi_mask
= vmx_get_nmi_mask
,
7584 .set_nmi_mask
= vmx_set_nmi_mask
,
7585 .enable_nmi_window
= enable_nmi_window
,
7586 .enable_irq_window
= enable_irq_window
,
7587 .update_cr8_intercept
= update_cr8_intercept
,
7588 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
7589 .vm_has_apicv
= vmx_vm_has_apicv
,
7590 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
7591 .hwapic_irr_update
= vmx_hwapic_irr_update
,
7592 .hwapic_isr_update
= vmx_hwapic_isr_update
,
7594 .set_tss_addr
= vmx_set_tss_addr
,
7595 .get_tdp_level
= get_ept_level
,
7596 .get_mt_mask
= vmx_get_mt_mask
,
7598 .get_exit_info
= vmx_get_exit_info
,
7600 .get_lpage_level
= vmx_get_lpage_level
,
7602 .cpuid_update
= vmx_cpuid_update
,
7604 .rdtscp_supported
= vmx_rdtscp_supported
,
7605 .invpcid_supported
= vmx_invpcid_supported
,
7607 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7609 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7611 .set_tsc_khz
= vmx_set_tsc_khz
,
7612 .read_tsc_offset
= vmx_read_tsc_offset
,
7613 .write_tsc_offset
= vmx_write_tsc_offset
,
7614 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7615 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7616 .read_l1_tsc
= vmx_read_l1_tsc
,
7618 .set_tdp_cr3
= vmx_set_cr3
,
7620 .check_intercept
= vmx_check_intercept
,
7623 static int __init
vmx_init(void)
7627 rdmsrl_safe(MSR_EFER
, &host_efer
);
7629 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7630 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7632 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7633 if (!vmx_io_bitmap_a
)
7638 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7639 if (!vmx_io_bitmap_b
)
7642 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7643 if (!vmx_msr_bitmap_legacy
)
7646 vmx_msr_bitmap_legacy_x2apic
=
7647 (unsigned long *)__get_free_page(GFP_KERNEL
);
7648 if (!vmx_msr_bitmap_legacy_x2apic
)
7651 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7652 if (!vmx_msr_bitmap_longmode
)
7655 vmx_msr_bitmap_longmode_x2apic
=
7656 (unsigned long *)__get_free_page(GFP_KERNEL
);
7657 if (!vmx_msr_bitmap_longmode_x2apic
)
7661 * Allow direct access to the PC debug port (it is often used for I/O
7662 * delays, but the vmexits simply slow things down).
7664 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7665 clear_bit(0x80, vmx_io_bitmap_a
);
7667 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7669 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7670 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7672 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7674 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7675 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7680 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
7681 crash_vmclear_local_loaded_vmcss
);
7684 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7685 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7686 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7687 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7688 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7689 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7690 memcpy(vmx_msr_bitmap_legacy_x2apic
,
7691 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
7692 memcpy(vmx_msr_bitmap_longmode_x2apic
,
7693 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
7695 if (enable_apicv_reg_vid
) {
7696 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
7697 vmx_disable_intercept_msr_read_x2apic(msr
);
7699 /* According SDM, in x2apic mode, the whole id reg is used.
7700 * But in KVM, it only use the highest eight bits. Need to
7702 vmx_enable_intercept_msr_read_x2apic(0x802);
7704 vmx_enable_intercept_msr_read_x2apic(0x839);
7706 vmx_disable_intercept_msr_write_x2apic(0x808);
7708 vmx_disable_intercept_msr_write_x2apic(0x80b);
7710 vmx_disable_intercept_msr_write_x2apic(0x83f);
7714 kvm_mmu_set_mask_ptes(0ull,
7715 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
7716 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
7717 0ull, VMX_EPT_EXECUTABLE_MASK
);
7718 ept_set_mmio_spte_mask();
7726 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7728 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
7730 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7732 free_page((unsigned long)vmx_io_bitmap_b
);
7734 free_page((unsigned long)vmx_io_bitmap_a
);
7738 static void __exit
vmx_exit(void)
7740 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
7741 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
7742 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7743 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7744 free_page((unsigned long)vmx_io_bitmap_b
);
7745 free_page((unsigned long)vmx_io_bitmap_a
);
7748 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
7755 module_init(vmx_init
)
7756 module_exit(vmx_exit
)