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Merge branch 'nfs-for-2.6.37' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6
[deliverable/linux.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
89 /*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
104
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
107
108 #define NR_AUTOLOAD_MSRS 1
109
110 struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114 };
115
116 struct shared_msr_entry {
117 unsigned index;
118 u64 data;
119 u64 mask;
120 };
121
122 struct vcpu_vmx {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
126 int launched;
127 u8 fail;
128 u32 exit_intr_info;
129 u32 idt_vectoring_info;
130 struct shared_msr_entry *guest_msrs;
131 int nmsrs;
132 int save_nmsrs;
133 #ifdef CONFIG_X86_64
134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
136 #endif
137 struct vmcs *vmcs;
138 struct msr_autoload {
139 unsigned nr;
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 } msr_autoload;
143 struct {
144 int loaded;
145 u16 fs_sel, gs_sel, ldt_sel;
146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
148 } host_state;
149 struct {
150 int vm86_active;
151 ulong save_rflags;
152 struct kvm_save_segment {
153 u16 selector;
154 unsigned long base;
155 u32 limit;
156 u32 ar;
157 } tr, es, ds, fs, gs;
158 } rmode;
159 int vpid;
160 bool emulation_required;
161
162 /* Support for vnmi-less CPUs */
163 int soft_vnmi_blocked;
164 ktime_t entry_time;
165 s64 vnmi_blocked_time;
166 u32 exit_reason;
167
168 bool rdtscp_enabled;
169 };
170
171 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
172 {
173 return container_of(vcpu, struct vcpu_vmx, vcpu);
174 }
175
176 static int init_rmode(struct kvm *kvm);
177 static u64 construct_eptp(unsigned long root_hpa);
178 static void kvm_cpu_vmxon(u64 addr);
179 static void kvm_cpu_vmxoff(void);
180
181 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
182 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
183 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
184 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
185
186 static unsigned long *vmx_io_bitmap_a;
187 static unsigned long *vmx_io_bitmap_b;
188 static unsigned long *vmx_msr_bitmap_legacy;
189 static unsigned long *vmx_msr_bitmap_longmode;
190
191 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
192 static DEFINE_SPINLOCK(vmx_vpid_lock);
193
194 static struct vmcs_config {
195 int size;
196 int order;
197 u32 revision_id;
198 u32 pin_based_exec_ctrl;
199 u32 cpu_based_exec_ctrl;
200 u32 cpu_based_2nd_exec_ctrl;
201 u32 vmexit_ctrl;
202 u32 vmentry_ctrl;
203 } vmcs_config;
204
205 static struct vmx_capability {
206 u32 ept;
207 u32 vpid;
208 } vmx_capability;
209
210 #define VMX_SEGMENT_FIELD(seg) \
211 [VCPU_SREG_##seg] = { \
212 .selector = GUEST_##seg##_SELECTOR, \
213 .base = GUEST_##seg##_BASE, \
214 .limit = GUEST_##seg##_LIMIT, \
215 .ar_bytes = GUEST_##seg##_AR_BYTES, \
216 }
217
218 static struct kvm_vmx_segment_field {
219 unsigned selector;
220 unsigned base;
221 unsigned limit;
222 unsigned ar_bytes;
223 } kvm_vmx_segment_fields[] = {
224 VMX_SEGMENT_FIELD(CS),
225 VMX_SEGMENT_FIELD(DS),
226 VMX_SEGMENT_FIELD(ES),
227 VMX_SEGMENT_FIELD(FS),
228 VMX_SEGMENT_FIELD(GS),
229 VMX_SEGMENT_FIELD(SS),
230 VMX_SEGMENT_FIELD(TR),
231 VMX_SEGMENT_FIELD(LDTR),
232 };
233
234 static u64 host_efer;
235
236 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
237
238 /*
239 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
240 * away by decrementing the array size.
241 */
242 static const u32 vmx_msr_index[] = {
243 #ifdef CONFIG_X86_64
244 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
245 #endif
246 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
247 };
248 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
249
250 static inline bool is_page_fault(u32 intr_info)
251 {
252 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
253 INTR_INFO_VALID_MASK)) ==
254 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
255 }
256
257 static inline bool is_no_device(u32 intr_info)
258 {
259 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
260 INTR_INFO_VALID_MASK)) ==
261 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
262 }
263
264 static inline bool is_invalid_opcode(u32 intr_info)
265 {
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
269 }
270
271 static inline bool is_external_interrupt(u32 intr_info)
272 {
273 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
274 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
275 }
276
277 static inline bool is_machine_check(u32 intr_info)
278 {
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
280 INTR_INFO_VALID_MASK)) ==
281 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
282 }
283
284 static inline bool cpu_has_vmx_msr_bitmap(void)
285 {
286 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
287 }
288
289 static inline bool cpu_has_vmx_tpr_shadow(void)
290 {
291 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
292 }
293
294 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
295 {
296 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
297 }
298
299 static inline bool cpu_has_secondary_exec_ctrls(void)
300 {
301 return vmcs_config.cpu_based_exec_ctrl &
302 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
303 }
304
305 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
306 {
307 return vmcs_config.cpu_based_2nd_exec_ctrl &
308 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
309 }
310
311 static inline bool cpu_has_vmx_flexpriority(void)
312 {
313 return cpu_has_vmx_tpr_shadow() &&
314 cpu_has_vmx_virtualize_apic_accesses();
315 }
316
317 static inline bool cpu_has_vmx_ept_execute_only(void)
318 {
319 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
320 }
321
322 static inline bool cpu_has_vmx_eptp_uncacheable(void)
323 {
324 return vmx_capability.ept & VMX_EPTP_UC_BIT;
325 }
326
327 static inline bool cpu_has_vmx_eptp_writeback(void)
328 {
329 return vmx_capability.ept & VMX_EPTP_WB_BIT;
330 }
331
332 static inline bool cpu_has_vmx_ept_2m_page(void)
333 {
334 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
335 }
336
337 static inline bool cpu_has_vmx_ept_1g_page(void)
338 {
339 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
340 }
341
342 static inline bool cpu_has_vmx_ept_4levels(void)
343 {
344 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
345 }
346
347 static inline bool cpu_has_vmx_invept_individual_addr(void)
348 {
349 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
350 }
351
352 static inline bool cpu_has_vmx_invept_context(void)
353 {
354 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
355 }
356
357 static inline bool cpu_has_vmx_invept_global(void)
358 {
359 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
360 }
361
362 static inline bool cpu_has_vmx_invvpid_single(void)
363 {
364 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
365 }
366
367 static inline bool cpu_has_vmx_invvpid_global(void)
368 {
369 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
370 }
371
372 static inline bool cpu_has_vmx_ept(void)
373 {
374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_ENABLE_EPT;
376 }
377
378 static inline bool cpu_has_vmx_unrestricted_guest(void)
379 {
380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_UNRESTRICTED_GUEST;
382 }
383
384 static inline bool cpu_has_vmx_ple(void)
385 {
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
388 }
389
390 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
391 {
392 return flexpriority_enabled && irqchip_in_kernel(kvm);
393 }
394
395 static inline bool cpu_has_vmx_vpid(void)
396 {
397 return vmcs_config.cpu_based_2nd_exec_ctrl &
398 SECONDARY_EXEC_ENABLE_VPID;
399 }
400
401 static inline bool cpu_has_vmx_rdtscp(void)
402 {
403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_RDTSCP;
405 }
406
407 static inline bool cpu_has_virtual_nmis(void)
408 {
409 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
410 }
411
412 static inline bool cpu_has_vmx_wbinvd_exit(void)
413 {
414 return vmcs_config.cpu_based_2nd_exec_ctrl &
415 SECONDARY_EXEC_WBINVD_EXITING;
416 }
417
418 static inline bool report_flexpriority(void)
419 {
420 return flexpriority_enabled;
421 }
422
423 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
424 {
425 int i;
426
427 for (i = 0; i < vmx->nmsrs; ++i)
428 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
429 return i;
430 return -1;
431 }
432
433 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
434 {
435 struct {
436 u64 vpid : 16;
437 u64 rsvd : 48;
438 u64 gva;
439 } operand = { vpid, 0, gva };
440
441 asm volatile (__ex(ASM_VMX_INVVPID)
442 /* CF==1 or ZF==1 --> rc = -1 */
443 "; ja 1f ; ud2 ; 1:"
444 : : "a"(&operand), "c"(ext) : "cc", "memory");
445 }
446
447 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
448 {
449 struct {
450 u64 eptp, gpa;
451 } operand = {eptp, gpa};
452
453 asm volatile (__ex(ASM_VMX_INVEPT)
454 /* CF==1 or ZF==1 --> rc = -1 */
455 "; ja 1f ; ud2 ; 1:\n"
456 : : "a" (&operand), "c" (ext) : "cc", "memory");
457 }
458
459 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
460 {
461 int i;
462
463 i = __find_msr_index(vmx, msr);
464 if (i >= 0)
465 return &vmx->guest_msrs[i];
466 return NULL;
467 }
468
469 static void vmcs_clear(struct vmcs *vmcs)
470 {
471 u64 phys_addr = __pa(vmcs);
472 u8 error;
473
474 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
475 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
476 : "cc", "memory");
477 if (error)
478 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
479 vmcs, phys_addr);
480 }
481
482 static void vmcs_load(struct vmcs *vmcs)
483 {
484 u64 phys_addr = __pa(vmcs);
485 u8 error;
486
487 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
488 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
489 : "cc", "memory");
490 if (error)
491 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
492 vmcs, phys_addr);
493 }
494
495 static void __vcpu_clear(void *arg)
496 {
497 struct vcpu_vmx *vmx = arg;
498 int cpu = raw_smp_processor_id();
499
500 if (vmx->vcpu.cpu == cpu)
501 vmcs_clear(vmx->vmcs);
502 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
503 per_cpu(current_vmcs, cpu) = NULL;
504 list_del(&vmx->local_vcpus_link);
505 vmx->vcpu.cpu = -1;
506 vmx->launched = 0;
507 }
508
509 static void vcpu_clear(struct vcpu_vmx *vmx)
510 {
511 if (vmx->vcpu.cpu == -1)
512 return;
513 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
514 }
515
516 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
517 {
518 if (vmx->vpid == 0)
519 return;
520
521 if (cpu_has_vmx_invvpid_single())
522 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
523 }
524
525 static inline void vpid_sync_vcpu_global(void)
526 {
527 if (cpu_has_vmx_invvpid_global())
528 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
529 }
530
531 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
532 {
533 if (cpu_has_vmx_invvpid_single())
534 vpid_sync_vcpu_single(vmx);
535 else
536 vpid_sync_vcpu_global();
537 }
538
539 static inline void ept_sync_global(void)
540 {
541 if (cpu_has_vmx_invept_global())
542 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
543 }
544
545 static inline void ept_sync_context(u64 eptp)
546 {
547 if (enable_ept) {
548 if (cpu_has_vmx_invept_context())
549 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
550 else
551 ept_sync_global();
552 }
553 }
554
555 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
556 {
557 if (enable_ept) {
558 if (cpu_has_vmx_invept_individual_addr())
559 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
560 eptp, gpa);
561 else
562 ept_sync_context(eptp);
563 }
564 }
565
566 static unsigned long vmcs_readl(unsigned long field)
567 {
568 unsigned long value;
569
570 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
571 : "=a"(value) : "d"(field) : "cc");
572 return value;
573 }
574
575 static u16 vmcs_read16(unsigned long field)
576 {
577 return vmcs_readl(field);
578 }
579
580 static u32 vmcs_read32(unsigned long field)
581 {
582 return vmcs_readl(field);
583 }
584
585 static u64 vmcs_read64(unsigned long field)
586 {
587 #ifdef CONFIG_X86_64
588 return vmcs_readl(field);
589 #else
590 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
591 #endif
592 }
593
594 static noinline void vmwrite_error(unsigned long field, unsigned long value)
595 {
596 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
597 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
598 dump_stack();
599 }
600
601 static void vmcs_writel(unsigned long field, unsigned long value)
602 {
603 u8 error;
604
605 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
606 : "=q"(error) : "a"(value), "d"(field) : "cc");
607 if (unlikely(error))
608 vmwrite_error(field, value);
609 }
610
611 static void vmcs_write16(unsigned long field, u16 value)
612 {
613 vmcs_writel(field, value);
614 }
615
616 static void vmcs_write32(unsigned long field, u32 value)
617 {
618 vmcs_writel(field, value);
619 }
620
621 static void vmcs_write64(unsigned long field, u64 value)
622 {
623 vmcs_writel(field, value);
624 #ifndef CONFIG_X86_64
625 asm volatile ("");
626 vmcs_writel(field+1, value >> 32);
627 #endif
628 }
629
630 static void vmcs_clear_bits(unsigned long field, u32 mask)
631 {
632 vmcs_writel(field, vmcs_readl(field) & ~mask);
633 }
634
635 static void vmcs_set_bits(unsigned long field, u32 mask)
636 {
637 vmcs_writel(field, vmcs_readl(field) | mask);
638 }
639
640 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
641 {
642 u32 eb;
643
644 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
645 (1u << NM_VECTOR) | (1u << DB_VECTOR);
646 if ((vcpu->guest_debug &
647 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
648 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
649 eb |= 1u << BP_VECTOR;
650 if (to_vmx(vcpu)->rmode.vm86_active)
651 eb = ~0;
652 if (enable_ept)
653 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
654 if (vcpu->fpu_active)
655 eb &= ~(1u << NM_VECTOR);
656 vmcs_write32(EXCEPTION_BITMAP, eb);
657 }
658
659 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
660 {
661 unsigned i;
662 struct msr_autoload *m = &vmx->msr_autoload;
663
664 for (i = 0; i < m->nr; ++i)
665 if (m->guest[i].index == msr)
666 break;
667
668 if (i == m->nr)
669 return;
670 --m->nr;
671 m->guest[i] = m->guest[m->nr];
672 m->host[i] = m->host[m->nr];
673 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
674 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
675 }
676
677 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
678 u64 guest_val, u64 host_val)
679 {
680 unsigned i;
681 struct msr_autoload *m = &vmx->msr_autoload;
682
683 for (i = 0; i < m->nr; ++i)
684 if (m->guest[i].index == msr)
685 break;
686
687 if (i == m->nr) {
688 ++m->nr;
689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
691 }
692
693 m->guest[i].index = msr;
694 m->guest[i].value = guest_val;
695 m->host[i].index = msr;
696 m->host[i].value = host_val;
697 }
698
699 static void reload_tss(void)
700 {
701 /*
702 * VT restores TR but not its size. Useless.
703 */
704 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
705 struct desc_struct *descs;
706
707 descs = (void *)gdt->address;
708 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
709 load_TR_desc();
710 }
711
712 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
713 {
714 u64 guest_efer;
715 u64 ignore_bits;
716
717 guest_efer = vmx->vcpu.arch.efer;
718
719 /*
720 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
721 * outside long mode
722 */
723 ignore_bits = EFER_NX | EFER_SCE;
724 #ifdef CONFIG_X86_64
725 ignore_bits |= EFER_LMA | EFER_LME;
726 /* SCE is meaningful only in long mode on Intel */
727 if (guest_efer & EFER_LMA)
728 ignore_bits &= ~(u64)EFER_SCE;
729 #endif
730 guest_efer &= ~ignore_bits;
731 guest_efer |= host_efer & ignore_bits;
732 vmx->guest_msrs[efer_offset].data = guest_efer;
733 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
734
735 clear_atomic_switch_msr(vmx, MSR_EFER);
736 /* On ept, can't emulate nx, and must switch nx atomically */
737 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
738 guest_efer = vmx->vcpu.arch.efer;
739 if (!(guest_efer & EFER_LMA))
740 guest_efer &= ~EFER_LME;
741 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
742 return false;
743 }
744
745 return true;
746 }
747
748 static unsigned long segment_base(u16 selector)
749 {
750 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
751 struct desc_struct *d;
752 unsigned long table_base;
753 unsigned long v;
754
755 if (!(selector & ~3))
756 return 0;
757
758 table_base = gdt->address;
759
760 if (selector & 4) { /* from ldt */
761 u16 ldt_selector = kvm_read_ldt();
762
763 if (!(ldt_selector & ~3))
764 return 0;
765
766 table_base = segment_base(ldt_selector);
767 }
768 d = (struct desc_struct *)(table_base + (selector & ~7));
769 v = get_desc_base(d);
770 #ifdef CONFIG_X86_64
771 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
772 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
773 #endif
774 return v;
775 }
776
777 static inline unsigned long kvm_read_tr_base(void)
778 {
779 u16 tr;
780 asm("str %0" : "=g"(tr));
781 return segment_base(tr);
782 }
783
784 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
785 {
786 struct vcpu_vmx *vmx = to_vmx(vcpu);
787 int i;
788
789 if (vmx->host_state.loaded)
790 return;
791
792 vmx->host_state.loaded = 1;
793 /*
794 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
795 * allow segment selectors with cpl > 0 or ti == 1.
796 */
797 vmx->host_state.ldt_sel = kvm_read_ldt();
798 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
799 savesegment(fs, vmx->host_state.fs_sel);
800 if (!(vmx->host_state.fs_sel & 7)) {
801 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
802 vmx->host_state.fs_reload_needed = 0;
803 } else {
804 vmcs_write16(HOST_FS_SELECTOR, 0);
805 vmx->host_state.fs_reload_needed = 1;
806 }
807 savesegment(gs, vmx->host_state.gs_sel);
808 if (!(vmx->host_state.gs_sel & 7))
809 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
810 else {
811 vmcs_write16(HOST_GS_SELECTOR, 0);
812 vmx->host_state.gs_ldt_reload_needed = 1;
813 }
814
815 #ifdef CONFIG_X86_64
816 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
817 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
818 #else
819 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
820 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
821 #endif
822
823 #ifdef CONFIG_X86_64
824 if (is_long_mode(&vmx->vcpu)) {
825 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
826 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
827 }
828 #endif
829 for (i = 0; i < vmx->save_nmsrs; ++i)
830 kvm_set_shared_msr(vmx->guest_msrs[i].index,
831 vmx->guest_msrs[i].data,
832 vmx->guest_msrs[i].mask);
833 }
834
835 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
836 {
837 if (!vmx->host_state.loaded)
838 return;
839
840 ++vmx->vcpu.stat.host_state_reload;
841 vmx->host_state.loaded = 0;
842 if (vmx->host_state.fs_reload_needed)
843 loadsegment(fs, vmx->host_state.fs_sel);
844 if (vmx->host_state.gs_ldt_reload_needed) {
845 kvm_load_ldt(vmx->host_state.ldt_sel);
846 #ifdef CONFIG_X86_64
847 load_gs_index(vmx->host_state.gs_sel);
848 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
849 #else
850 loadsegment(gs, vmx->host_state.gs_sel);
851 #endif
852 }
853 reload_tss();
854 #ifdef CONFIG_X86_64
855 if (is_long_mode(&vmx->vcpu)) {
856 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
857 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
858 }
859 #endif
860 if (current_thread_info()->status & TS_USEDFPU)
861 clts();
862 load_gdt(&__get_cpu_var(host_gdt));
863 }
864
865 static void vmx_load_host_state(struct vcpu_vmx *vmx)
866 {
867 preempt_disable();
868 __vmx_load_host_state(vmx);
869 preempt_enable();
870 }
871
872 /*
873 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
874 * vcpu mutex is already taken.
875 */
876 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
877 {
878 struct vcpu_vmx *vmx = to_vmx(vcpu);
879 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
880
881 if (!vmm_exclusive)
882 kvm_cpu_vmxon(phys_addr);
883 else if (vcpu->cpu != cpu)
884 vcpu_clear(vmx);
885
886 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
887 per_cpu(current_vmcs, cpu) = vmx->vmcs;
888 vmcs_load(vmx->vmcs);
889 }
890
891 if (vcpu->cpu != cpu) {
892 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
893 unsigned long sysenter_esp;
894
895 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
896 local_irq_disable();
897 list_add(&vmx->local_vcpus_link,
898 &per_cpu(vcpus_on_cpu, cpu));
899 local_irq_enable();
900
901 /*
902 * Linux uses per-cpu TSS and GDT, so set these when switching
903 * processors.
904 */
905 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
906 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
907
908 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
909 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
910 }
911 }
912
913 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
914 {
915 __vmx_load_host_state(to_vmx(vcpu));
916 if (!vmm_exclusive) {
917 __vcpu_clear(to_vmx(vcpu));
918 kvm_cpu_vmxoff();
919 }
920 }
921
922 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
923 {
924 ulong cr0;
925
926 if (vcpu->fpu_active)
927 return;
928 vcpu->fpu_active = 1;
929 cr0 = vmcs_readl(GUEST_CR0);
930 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
931 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
932 vmcs_writel(GUEST_CR0, cr0);
933 update_exception_bitmap(vcpu);
934 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
935 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
936 }
937
938 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
939
940 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
941 {
942 vmx_decache_cr0_guest_bits(vcpu);
943 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
944 update_exception_bitmap(vcpu);
945 vcpu->arch.cr0_guest_owned_bits = 0;
946 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
947 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
948 }
949
950 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
951 {
952 unsigned long rflags, save_rflags;
953
954 rflags = vmcs_readl(GUEST_RFLAGS);
955 if (to_vmx(vcpu)->rmode.vm86_active) {
956 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
957 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
958 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
959 }
960 return rflags;
961 }
962
963 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
964 {
965 if (to_vmx(vcpu)->rmode.vm86_active) {
966 to_vmx(vcpu)->rmode.save_rflags = rflags;
967 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
968 }
969 vmcs_writel(GUEST_RFLAGS, rflags);
970 }
971
972 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
973 {
974 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
975 int ret = 0;
976
977 if (interruptibility & GUEST_INTR_STATE_STI)
978 ret |= KVM_X86_SHADOW_INT_STI;
979 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
980 ret |= KVM_X86_SHADOW_INT_MOV_SS;
981
982 return ret & mask;
983 }
984
985 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
986 {
987 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
988 u32 interruptibility = interruptibility_old;
989
990 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
991
992 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
993 interruptibility |= GUEST_INTR_STATE_MOV_SS;
994 else if (mask & KVM_X86_SHADOW_INT_STI)
995 interruptibility |= GUEST_INTR_STATE_STI;
996
997 if ((interruptibility != interruptibility_old))
998 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
999 }
1000
1001 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1002 {
1003 unsigned long rip;
1004
1005 rip = kvm_rip_read(vcpu);
1006 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1007 kvm_rip_write(vcpu, rip);
1008
1009 /* skipping an emulated instruction also counts */
1010 vmx_set_interrupt_shadow(vcpu, 0);
1011 }
1012
1013 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1014 bool has_error_code, u32 error_code,
1015 bool reinject)
1016 {
1017 struct vcpu_vmx *vmx = to_vmx(vcpu);
1018 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1019
1020 if (has_error_code) {
1021 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1022 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1023 }
1024
1025 if (vmx->rmode.vm86_active) {
1026 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1027 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1028 return;
1029 }
1030
1031 if (kvm_exception_is_soft(nr)) {
1032 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1033 vmx->vcpu.arch.event_exit_inst_len);
1034 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1035 } else
1036 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1037
1038 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1039 }
1040
1041 static bool vmx_rdtscp_supported(void)
1042 {
1043 return cpu_has_vmx_rdtscp();
1044 }
1045
1046 /*
1047 * Swap MSR entry in host/guest MSR entry array.
1048 */
1049 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1050 {
1051 struct shared_msr_entry tmp;
1052
1053 tmp = vmx->guest_msrs[to];
1054 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1055 vmx->guest_msrs[from] = tmp;
1056 }
1057
1058 /*
1059 * Set up the vmcs to automatically save and restore system
1060 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1061 * mode, as fiddling with msrs is very expensive.
1062 */
1063 static void setup_msrs(struct vcpu_vmx *vmx)
1064 {
1065 int save_nmsrs, index;
1066 unsigned long *msr_bitmap;
1067
1068 vmx_load_host_state(vmx);
1069 save_nmsrs = 0;
1070 #ifdef CONFIG_X86_64
1071 if (is_long_mode(&vmx->vcpu)) {
1072 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1073 if (index >= 0)
1074 move_msr_up(vmx, index, save_nmsrs++);
1075 index = __find_msr_index(vmx, MSR_LSTAR);
1076 if (index >= 0)
1077 move_msr_up(vmx, index, save_nmsrs++);
1078 index = __find_msr_index(vmx, MSR_CSTAR);
1079 if (index >= 0)
1080 move_msr_up(vmx, index, save_nmsrs++);
1081 index = __find_msr_index(vmx, MSR_TSC_AUX);
1082 if (index >= 0 && vmx->rdtscp_enabled)
1083 move_msr_up(vmx, index, save_nmsrs++);
1084 /*
1085 * MSR_STAR is only needed on long mode guests, and only
1086 * if efer.sce is enabled.
1087 */
1088 index = __find_msr_index(vmx, MSR_STAR);
1089 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1090 move_msr_up(vmx, index, save_nmsrs++);
1091 }
1092 #endif
1093 index = __find_msr_index(vmx, MSR_EFER);
1094 if (index >= 0 && update_transition_efer(vmx, index))
1095 move_msr_up(vmx, index, save_nmsrs++);
1096
1097 vmx->save_nmsrs = save_nmsrs;
1098
1099 if (cpu_has_vmx_msr_bitmap()) {
1100 if (is_long_mode(&vmx->vcpu))
1101 msr_bitmap = vmx_msr_bitmap_longmode;
1102 else
1103 msr_bitmap = vmx_msr_bitmap_legacy;
1104
1105 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1106 }
1107 }
1108
1109 /*
1110 * reads and returns guest's timestamp counter "register"
1111 * guest_tsc = host_tsc + tsc_offset -- 21.3
1112 */
1113 static u64 guest_read_tsc(void)
1114 {
1115 u64 host_tsc, tsc_offset;
1116
1117 rdtscll(host_tsc);
1118 tsc_offset = vmcs_read64(TSC_OFFSET);
1119 return host_tsc + tsc_offset;
1120 }
1121
1122 /*
1123 * writes 'offset' into guest's timestamp counter offset register
1124 */
1125 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1126 {
1127 vmcs_write64(TSC_OFFSET, offset);
1128 }
1129
1130 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1131 {
1132 u64 offset = vmcs_read64(TSC_OFFSET);
1133 vmcs_write64(TSC_OFFSET, offset + adjustment);
1134 }
1135
1136 /*
1137 * Reads an msr value (of 'msr_index') into 'pdata'.
1138 * Returns 0 on success, non-0 otherwise.
1139 * Assumes vcpu_load() was already called.
1140 */
1141 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1142 {
1143 u64 data;
1144 struct shared_msr_entry *msr;
1145
1146 if (!pdata) {
1147 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1148 return -EINVAL;
1149 }
1150
1151 switch (msr_index) {
1152 #ifdef CONFIG_X86_64
1153 case MSR_FS_BASE:
1154 data = vmcs_readl(GUEST_FS_BASE);
1155 break;
1156 case MSR_GS_BASE:
1157 data = vmcs_readl(GUEST_GS_BASE);
1158 break;
1159 case MSR_KERNEL_GS_BASE:
1160 vmx_load_host_state(to_vmx(vcpu));
1161 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1162 break;
1163 #endif
1164 case MSR_EFER:
1165 return kvm_get_msr_common(vcpu, msr_index, pdata);
1166 case MSR_IA32_TSC:
1167 data = guest_read_tsc();
1168 break;
1169 case MSR_IA32_SYSENTER_CS:
1170 data = vmcs_read32(GUEST_SYSENTER_CS);
1171 break;
1172 case MSR_IA32_SYSENTER_EIP:
1173 data = vmcs_readl(GUEST_SYSENTER_EIP);
1174 break;
1175 case MSR_IA32_SYSENTER_ESP:
1176 data = vmcs_readl(GUEST_SYSENTER_ESP);
1177 break;
1178 case MSR_TSC_AUX:
1179 if (!to_vmx(vcpu)->rdtscp_enabled)
1180 return 1;
1181 /* Otherwise falls through */
1182 default:
1183 vmx_load_host_state(to_vmx(vcpu));
1184 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1185 if (msr) {
1186 vmx_load_host_state(to_vmx(vcpu));
1187 data = msr->data;
1188 break;
1189 }
1190 return kvm_get_msr_common(vcpu, msr_index, pdata);
1191 }
1192
1193 *pdata = data;
1194 return 0;
1195 }
1196
1197 /*
1198 * Writes msr value into into the appropriate "register".
1199 * Returns 0 on success, non-0 otherwise.
1200 * Assumes vcpu_load() was already called.
1201 */
1202 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1203 {
1204 struct vcpu_vmx *vmx = to_vmx(vcpu);
1205 struct shared_msr_entry *msr;
1206 int ret = 0;
1207
1208 switch (msr_index) {
1209 case MSR_EFER:
1210 vmx_load_host_state(vmx);
1211 ret = kvm_set_msr_common(vcpu, msr_index, data);
1212 break;
1213 #ifdef CONFIG_X86_64
1214 case MSR_FS_BASE:
1215 vmcs_writel(GUEST_FS_BASE, data);
1216 break;
1217 case MSR_GS_BASE:
1218 vmcs_writel(GUEST_GS_BASE, data);
1219 break;
1220 case MSR_KERNEL_GS_BASE:
1221 vmx_load_host_state(vmx);
1222 vmx->msr_guest_kernel_gs_base = data;
1223 break;
1224 #endif
1225 case MSR_IA32_SYSENTER_CS:
1226 vmcs_write32(GUEST_SYSENTER_CS, data);
1227 break;
1228 case MSR_IA32_SYSENTER_EIP:
1229 vmcs_writel(GUEST_SYSENTER_EIP, data);
1230 break;
1231 case MSR_IA32_SYSENTER_ESP:
1232 vmcs_writel(GUEST_SYSENTER_ESP, data);
1233 break;
1234 case MSR_IA32_TSC:
1235 kvm_write_tsc(vcpu, data);
1236 break;
1237 case MSR_IA32_CR_PAT:
1238 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1239 vmcs_write64(GUEST_IA32_PAT, data);
1240 vcpu->arch.pat = data;
1241 break;
1242 }
1243 ret = kvm_set_msr_common(vcpu, msr_index, data);
1244 break;
1245 case MSR_TSC_AUX:
1246 if (!vmx->rdtscp_enabled)
1247 return 1;
1248 /* Check reserved bit, higher 32 bits should be zero */
1249 if ((data >> 32) != 0)
1250 return 1;
1251 /* Otherwise falls through */
1252 default:
1253 msr = find_msr_entry(vmx, msr_index);
1254 if (msr) {
1255 vmx_load_host_state(vmx);
1256 msr->data = data;
1257 break;
1258 }
1259 ret = kvm_set_msr_common(vcpu, msr_index, data);
1260 }
1261
1262 return ret;
1263 }
1264
1265 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1266 {
1267 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1268 switch (reg) {
1269 case VCPU_REGS_RSP:
1270 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1271 break;
1272 case VCPU_REGS_RIP:
1273 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1274 break;
1275 case VCPU_EXREG_PDPTR:
1276 if (enable_ept)
1277 ept_save_pdptrs(vcpu);
1278 break;
1279 default:
1280 break;
1281 }
1282 }
1283
1284 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1285 {
1286 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1287 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1288 else
1289 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1290
1291 update_exception_bitmap(vcpu);
1292 }
1293
1294 static __init int cpu_has_kvm_support(void)
1295 {
1296 return cpu_has_vmx();
1297 }
1298
1299 static __init int vmx_disabled_by_bios(void)
1300 {
1301 u64 msr;
1302
1303 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1304 if (msr & FEATURE_CONTROL_LOCKED) {
1305 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1306 && tboot_enabled())
1307 return 1;
1308 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1309 && !tboot_enabled())
1310 return 1;
1311 }
1312
1313 return 0;
1314 /* locked but not enabled */
1315 }
1316
1317 static void kvm_cpu_vmxon(u64 addr)
1318 {
1319 asm volatile (ASM_VMX_VMXON_RAX
1320 : : "a"(&addr), "m"(addr)
1321 : "memory", "cc");
1322 }
1323
1324 static int hardware_enable(void *garbage)
1325 {
1326 int cpu = raw_smp_processor_id();
1327 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1328 u64 old, test_bits;
1329
1330 if (read_cr4() & X86_CR4_VMXE)
1331 return -EBUSY;
1332
1333 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1334 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1335
1336 test_bits = FEATURE_CONTROL_LOCKED;
1337 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1338 if (tboot_enabled())
1339 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1340
1341 if ((old & test_bits) != test_bits) {
1342 /* enable and lock */
1343 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1344 }
1345 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1346
1347 if (vmm_exclusive) {
1348 kvm_cpu_vmxon(phys_addr);
1349 ept_sync_global();
1350 }
1351
1352 store_gdt(&__get_cpu_var(host_gdt));
1353
1354 return 0;
1355 }
1356
1357 static void vmclear_local_vcpus(void)
1358 {
1359 int cpu = raw_smp_processor_id();
1360 struct vcpu_vmx *vmx, *n;
1361
1362 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1363 local_vcpus_link)
1364 __vcpu_clear(vmx);
1365 }
1366
1367
1368 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1369 * tricks.
1370 */
1371 static void kvm_cpu_vmxoff(void)
1372 {
1373 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1374 }
1375
1376 static void hardware_disable(void *garbage)
1377 {
1378 if (vmm_exclusive) {
1379 vmclear_local_vcpus();
1380 kvm_cpu_vmxoff();
1381 }
1382 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1383 }
1384
1385 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1386 u32 msr, u32 *result)
1387 {
1388 u32 vmx_msr_low, vmx_msr_high;
1389 u32 ctl = ctl_min | ctl_opt;
1390
1391 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1392
1393 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1394 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1395
1396 /* Ensure minimum (required) set of control bits are supported. */
1397 if (ctl_min & ~ctl)
1398 return -EIO;
1399
1400 *result = ctl;
1401 return 0;
1402 }
1403
1404 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1405 {
1406 u32 vmx_msr_low, vmx_msr_high;
1407 u32 min, opt, min2, opt2;
1408 u32 _pin_based_exec_control = 0;
1409 u32 _cpu_based_exec_control = 0;
1410 u32 _cpu_based_2nd_exec_control = 0;
1411 u32 _vmexit_control = 0;
1412 u32 _vmentry_control = 0;
1413
1414 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1415 opt = PIN_BASED_VIRTUAL_NMIS;
1416 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1417 &_pin_based_exec_control) < 0)
1418 return -EIO;
1419
1420 min = CPU_BASED_HLT_EXITING |
1421 #ifdef CONFIG_X86_64
1422 CPU_BASED_CR8_LOAD_EXITING |
1423 CPU_BASED_CR8_STORE_EXITING |
1424 #endif
1425 CPU_BASED_CR3_LOAD_EXITING |
1426 CPU_BASED_CR3_STORE_EXITING |
1427 CPU_BASED_USE_IO_BITMAPS |
1428 CPU_BASED_MOV_DR_EXITING |
1429 CPU_BASED_USE_TSC_OFFSETING |
1430 CPU_BASED_MWAIT_EXITING |
1431 CPU_BASED_MONITOR_EXITING |
1432 CPU_BASED_INVLPG_EXITING;
1433 opt = CPU_BASED_TPR_SHADOW |
1434 CPU_BASED_USE_MSR_BITMAPS |
1435 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1436 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1437 &_cpu_based_exec_control) < 0)
1438 return -EIO;
1439 #ifdef CONFIG_X86_64
1440 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1441 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1442 ~CPU_BASED_CR8_STORE_EXITING;
1443 #endif
1444 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1445 min2 = 0;
1446 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1447 SECONDARY_EXEC_WBINVD_EXITING |
1448 SECONDARY_EXEC_ENABLE_VPID |
1449 SECONDARY_EXEC_ENABLE_EPT |
1450 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1451 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1452 SECONDARY_EXEC_RDTSCP;
1453 if (adjust_vmx_controls(min2, opt2,
1454 MSR_IA32_VMX_PROCBASED_CTLS2,
1455 &_cpu_based_2nd_exec_control) < 0)
1456 return -EIO;
1457 }
1458 #ifndef CONFIG_X86_64
1459 if (!(_cpu_based_2nd_exec_control &
1460 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1461 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1462 #endif
1463 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1464 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1465 enabled */
1466 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1467 CPU_BASED_CR3_STORE_EXITING |
1468 CPU_BASED_INVLPG_EXITING);
1469 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1470 vmx_capability.ept, vmx_capability.vpid);
1471 }
1472
1473 min = 0;
1474 #ifdef CONFIG_X86_64
1475 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1476 #endif
1477 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1478 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1479 &_vmexit_control) < 0)
1480 return -EIO;
1481
1482 min = 0;
1483 opt = VM_ENTRY_LOAD_IA32_PAT;
1484 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1485 &_vmentry_control) < 0)
1486 return -EIO;
1487
1488 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1489
1490 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1491 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1492 return -EIO;
1493
1494 #ifdef CONFIG_X86_64
1495 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1496 if (vmx_msr_high & (1u<<16))
1497 return -EIO;
1498 #endif
1499
1500 /* Require Write-Back (WB) memory type for VMCS accesses. */
1501 if (((vmx_msr_high >> 18) & 15) != 6)
1502 return -EIO;
1503
1504 vmcs_conf->size = vmx_msr_high & 0x1fff;
1505 vmcs_conf->order = get_order(vmcs_config.size);
1506 vmcs_conf->revision_id = vmx_msr_low;
1507
1508 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1509 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1510 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1511 vmcs_conf->vmexit_ctrl = _vmexit_control;
1512 vmcs_conf->vmentry_ctrl = _vmentry_control;
1513
1514 return 0;
1515 }
1516
1517 static struct vmcs *alloc_vmcs_cpu(int cpu)
1518 {
1519 int node = cpu_to_node(cpu);
1520 struct page *pages;
1521 struct vmcs *vmcs;
1522
1523 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1524 if (!pages)
1525 return NULL;
1526 vmcs = page_address(pages);
1527 memset(vmcs, 0, vmcs_config.size);
1528 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1529 return vmcs;
1530 }
1531
1532 static struct vmcs *alloc_vmcs(void)
1533 {
1534 return alloc_vmcs_cpu(raw_smp_processor_id());
1535 }
1536
1537 static void free_vmcs(struct vmcs *vmcs)
1538 {
1539 free_pages((unsigned long)vmcs, vmcs_config.order);
1540 }
1541
1542 static void free_kvm_area(void)
1543 {
1544 int cpu;
1545
1546 for_each_possible_cpu(cpu) {
1547 free_vmcs(per_cpu(vmxarea, cpu));
1548 per_cpu(vmxarea, cpu) = NULL;
1549 }
1550 }
1551
1552 static __init int alloc_kvm_area(void)
1553 {
1554 int cpu;
1555
1556 for_each_possible_cpu(cpu) {
1557 struct vmcs *vmcs;
1558
1559 vmcs = alloc_vmcs_cpu(cpu);
1560 if (!vmcs) {
1561 free_kvm_area();
1562 return -ENOMEM;
1563 }
1564
1565 per_cpu(vmxarea, cpu) = vmcs;
1566 }
1567 return 0;
1568 }
1569
1570 static __init int hardware_setup(void)
1571 {
1572 if (setup_vmcs_config(&vmcs_config) < 0)
1573 return -EIO;
1574
1575 if (boot_cpu_has(X86_FEATURE_NX))
1576 kvm_enable_efer_bits(EFER_NX);
1577
1578 if (!cpu_has_vmx_vpid())
1579 enable_vpid = 0;
1580
1581 if (!cpu_has_vmx_ept() ||
1582 !cpu_has_vmx_ept_4levels()) {
1583 enable_ept = 0;
1584 enable_unrestricted_guest = 0;
1585 }
1586
1587 if (!cpu_has_vmx_unrestricted_guest())
1588 enable_unrestricted_guest = 0;
1589
1590 if (!cpu_has_vmx_flexpriority())
1591 flexpriority_enabled = 0;
1592
1593 if (!cpu_has_vmx_tpr_shadow())
1594 kvm_x86_ops->update_cr8_intercept = NULL;
1595
1596 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1597 kvm_disable_largepages();
1598
1599 if (!cpu_has_vmx_ple())
1600 ple_gap = 0;
1601
1602 return alloc_kvm_area();
1603 }
1604
1605 static __exit void hardware_unsetup(void)
1606 {
1607 free_kvm_area();
1608 }
1609
1610 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1611 {
1612 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1613
1614 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1615 vmcs_write16(sf->selector, save->selector);
1616 vmcs_writel(sf->base, save->base);
1617 vmcs_write32(sf->limit, save->limit);
1618 vmcs_write32(sf->ar_bytes, save->ar);
1619 } else {
1620 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1621 << AR_DPL_SHIFT;
1622 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1623 }
1624 }
1625
1626 static void enter_pmode(struct kvm_vcpu *vcpu)
1627 {
1628 unsigned long flags;
1629 struct vcpu_vmx *vmx = to_vmx(vcpu);
1630
1631 vmx->emulation_required = 1;
1632 vmx->rmode.vm86_active = 0;
1633
1634 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1635 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1636 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1637
1638 flags = vmcs_readl(GUEST_RFLAGS);
1639 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1640 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1641 vmcs_writel(GUEST_RFLAGS, flags);
1642
1643 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1644 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1645
1646 update_exception_bitmap(vcpu);
1647
1648 if (emulate_invalid_guest_state)
1649 return;
1650
1651 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1652 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1653 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1654 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1655
1656 vmcs_write16(GUEST_SS_SELECTOR, 0);
1657 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1658
1659 vmcs_write16(GUEST_CS_SELECTOR,
1660 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1661 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1662 }
1663
1664 static gva_t rmode_tss_base(struct kvm *kvm)
1665 {
1666 if (!kvm->arch.tss_addr) {
1667 struct kvm_memslots *slots;
1668 gfn_t base_gfn;
1669
1670 slots = kvm_memslots(kvm);
1671 base_gfn = slots->memslots[0].base_gfn +
1672 kvm->memslots->memslots[0].npages - 3;
1673 return base_gfn << PAGE_SHIFT;
1674 }
1675 return kvm->arch.tss_addr;
1676 }
1677
1678 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1679 {
1680 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1681
1682 save->selector = vmcs_read16(sf->selector);
1683 save->base = vmcs_readl(sf->base);
1684 save->limit = vmcs_read32(sf->limit);
1685 save->ar = vmcs_read32(sf->ar_bytes);
1686 vmcs_write16(sf->selector, save->base >> 4);
1687 vmcs_write32(sf->base, save->base & 0xfffff);
1688 vmcs_write32(sf->limit, 0xffff);
1689 vmcs_write32(sf->ar_bytes, 0xf3);
1690 }
1691
1692 static void enter_rmode(struct kvm_vcpu *vcpu)
1693 {
1694 unsigned long flags;
1695 struct vcpu_vmx *vmx = to_vmx(vcpu);
1696
1697 if (enable_unrestricted_guest)
1698 return;
1699
1700 vmx->emulation_required = 1;
1701 vmx->rmode.vm86_active = 1;
1702
1703 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1704 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1705
1706 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1707 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1708
1709 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1710 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1711
1712 flags = vmcs_readl(GUEST_RFLAGS);
1713 vmx->rmode.save_rflags = flags;
1714
1715 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1716
1717 vmcs_writel(GUEST_RFLAGS, flags);
1718 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1719 update_exception_bitmap(vcpu);
1720
1721 if (emulate_invalid_guest_state)
1722 goto continue_rmode;
1723
1724 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1725 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1726 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1727
1728 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1729 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1730 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1731 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1732 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1733
1734 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1735 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1736 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1737 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1738
1739 continue_rmode:
1740 kvm_mmu_reset_context(vcpu);
1741 init_rmode(vcpu->kvm);
1742 }
1743
1744 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1745 {
1746 struct vcpu_vmx *vmx = to_vmx(vcpu);
1747 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1748
1749 if (!msr)
1750 return;
1751
1752 /*
1753 * Force kernel_gs_base reloading before EFER changes, as control
1754 * of this msr depends on is_long_mode().
1755 */
1756 vmx_load_host_state(to_vmx(vcpu));
1757 vcpu->arch.efer = efer;
1758 if (efer & EFER_LMA) {
1759 vmcs_write32(VM_ENTRY_CONTROLS,
1760 vmcs_read32(VM_ENTRY_CONTROLS) |
1761 VM_ENTRY_IA32E_MODE);
1762 msr->data = efer;
1763 } else {
1764 vmcs_write32(VM_ENTRY_CONTROLS,
1765 vmcs_read32(VM_ENTRY_CONTROLS) &
1766 ~VM_ENTRY_IA32E_MODE);
1767
1768 msr->data = efer & ~EFER_LME;
1769 }
1770 setup_msrs(vmx);
1771 }
1772
1773 #ifdef CONFIG_X86_64
1774
1775 static void enter_lmode(struct kvm_vcpu *vcpu)
1776 {
1777 u32 guest_tr_ar;
1778
1779 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1780 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1781 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1782 __func__);
1783 vmcs_write32(GUEST_TR_AR_BYTES,
1784 (guest_tr_ar & ~AR_TYPE_MASK)
1785 | AR_TYPE_BUSY_64_TSS);
1786 }
1787 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1788 }
1789
1790 static void exit_lmode(struct kvm_vcpu *vcpu)
1791 {
1792 vmcs_write32(VM_ENTRY_CONTROLS,
1793 vmcs_read32(VM_ENTRY_CONTROLS)
1794 & ~VM_ENTRY_IA32E_MODE);
1795 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1796 }
1797
1798 #endif
1799
1800 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1801 {
1802 vpid_sync_context(to_vmx(vcpu));
1803 if (enable_ept) {
1804 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1805 return;
1806 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1807 }
1808 }
1809
1810 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1811 {
1812 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1813
1814 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1815 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1816 }
1817
1818 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1819 {
1820 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1821
1822 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1823 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1824 }
1825
1826 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1827 {
1828 if (!test_bit(VCPU_EXREG_PDPTR,
1829 (unsigned long *)&vcpu->arch.regs_dirty))
1830 return;
1831
1832 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1833 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1834 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1835 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1836 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1837 }
1838 }
1839
1840 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1841 {
1842 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1843 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1844 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1845 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1846 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1847 }
1848
1849 __set_bit(VCPU_EXREG_PDPTR,
1850 (unsigned long *)&vcpu->arch.regs_avail);
1851 __set_bit(VCPU_EXREG_PDPTR,
1852 (unsigned long *)&vcpu->arch.regs_dirty);
1853 }
1854
1855 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1856
1857 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1858 unsigned long cr0,
1859 struct kvm_vcpu *vcpu)
1860 {
1861 if (!(cr0 & X86_CR0_PG)) {
1862 /* From paging/starting to nonpaging */
1863 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1864 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1865 (CPU_BASED_CR3_LOAD_EXITING |
1866 CPU_BASED_CR3_STORE_EXITING));
1867 vcpu->arch.cr0 = cr0;
1868 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1869 } else if (!is_paging(vcpu)) {
1870 /* From nonpaging to paging */
1871 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1872 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1873 ~(CPU_BASED_CR3_LOAD_EXITING |
1874 CPU_BASED_CR3_STORE_EXITING));
1875 vcpu->arch.cr0 = cr0;
1876 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1877 }
1878
1879 if (!(cr0 & X86_CR0_WP))
1880 *hw_cr0 &= ~X86_CR0_WP;
1881 }
1882
1883 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1884 {
1885 struct vcpu_vmx *vmx = to_vmx(vcpu);
1886 unsigned long hw_cr0;
1887
1888 if (enable_unrestricted_guest)
1889 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1890 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1891 else
1892 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1893
1894 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1895 enter_pmode(vcpu);
1896
1897 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1898 enter_rmode(vcpu);
1899
1900 #ifdef CONFIG_X86_64
1901 if (vcpu->arch.efer & EFER_LME) {
1902 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1903 enter_lmode(vcpu);
1904 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1905 exit_lmode(vcpu);
1906 }
1907 #endif
1908
1909 if (enable_ept)
1910 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1911
1912 if (!vcpu->fpu_active)
1913 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1914
1915 vmcs_writel(CR0_READ_SHADOW, cr0);
1916 vmcs_writel(GUEST_CR0, hw_cr0);
1917 vcpu->arch.cr0 = cr0;
1918 }
1919
1920 static u64 construct_eptp(unsigned long root_hpa)
1921 {
1922 u64 eptp;
1923
1924 /* TODO write the value reading from MSR */
1925 eptp = VMX_EPT_DEFAULT_MT |
1926 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1927 eptp |= (root_hpa & PAGE_MASK);
1928
1929 return eptp;
1930 }
1931
1932 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1933 {
1934 unsigned long guest_cr3;
1935 u64 eptp;
1936
1937 guest_cr3 = cr3;
1938 if (enable_ept) {
1939 eptp = construct_eptp(cr3);
1940 vmcs_write64(EPT_POINTER, eptp);
1941 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1942 vcpu->kvm->arch.ept_identity_map_addr;
1943 ept_load_pdptrs(vcpu);
1944 }
1945
1946 vmx_flush_tlb(vcpu);
1947 vmcs_writel(GUEST_CR3, guest_cr3);
1948 }
1949
1950 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1951 {
1952 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1953 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1954
1955 vcpu->arch.cr4 = cr4;
1956 if (enable_ept) {
1957 if (!is_paging(vcpu)) {
1958 hw_cr4 &= ~X86_CR4_PAE;
1959 hw_cr4 |= X86_CR4_PSE;
1960 } else if (!(cr4 & X86_CR4_PAE)) {
1961 hw_cr4 &= ~X86_CR4_PAE;
1962 }
1963 }
1964
1965 vmcs_writel(CR4_READ_SHADOW, cr4);
1966 vmcs_writel(GUEST_CR4, hw_cr4);
1967 }
1968
1969 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1970 {
1971 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1972
1973 return vmcs_readl(sf->base);
1974 }
1975
1976 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1977 struct kvm_segment *var, int seg)
1978 {
1979 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1980 u32 ar;
1981
1982 var->base = vmcs_readl(sf->base);
1983 var->limit = vmcs_read32(sf->limit);
1984 var->selector = vmcs_read16(sf->selector);
1985 ar = vmcs_read32(sf->ar_bytes);
1986 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1987 ar = 0;
1988 var->type = ar & 15;
1989 var->s = (ar >> 4) & 1;
1990 var->dpl = (ar >> 5) & 3;
1991 var->present = (ar >> 7) & 1;
1992 var->avl = (ar >> 12) & 1;
1993 var->l = (ar >> 13) & 1;
1994 var->db = (ar >> 14) & 1;
1995 var->g = (ar >> 15) & 1;
1996 var->unusable = (ar >> 16) & 1;
1997 }
1998
1999 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2000 {
2001 if (!is_protmode(vcpu))
2002 return 0;
2003
2004 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2005 return 3;
2006
2007 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2008 }
2009
2010 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2011 {
2012 u32 ar;
2013
2014 if (var->unusable)
2015 ar = 1 << 16;
2016 else {
2017 ar = var->type & 15;
2018 ar |= (var->s & 1) << 4;
2019 ar |= (var->dpl & 3) << 5;
2020 ar |= (var->present & 1) << 7;
2021 ar |= (var->avl & 1) << 12;
2022 ar |= (var->l & 1) << 13;
2023 ar |= (var->db & 1) << 14;
2024 ar |= (var->g & 1) << 15;
2025 }
2026 if (ar == 0) /* a 0 value means unusable */
2027 ar = AR_UNUSABLE_MASK;
2028
2029 return ar;
2030 }
2031
2032 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2033 struct kvm_segment *var, int seg)
2034 {
2035 struct vcpu_vmx *vmx = to_vmx(vcpu);
2036 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2037 u32 ar;
2038
2039 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2040 vmx->rmode.tr.selector = var->selector;
2041 vmx->rmode.tr.base = var->base;
2042 vmx->rmode.tr.limit = var->limit;
2043 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2044 return;
2045 }
2046 vmcs_writel(sf->base, var->base);
2047 vmcs_write32(sf->limit, var->limit);
2048 vmcs_write16(sf->selector, var->selector);
2049 if (vmx->rmode.vm86_active && var->s) {
2050 /*
2051 * Hack real-mode segments into vm86 compatibility.
2052 */
2053 if (var->base == 0xffff0000 && var->selector == 0xf000)
2054 vmcs_writel(sf->base, 0xf0000);
2055 ar = 0xf3;
2056 } else
2057 ar = vmx_segment_access_rights(var);
2058
2059 /*
2060 * Fix the "Accessed" bit in AR field of segment registers for older
2061 * qemu binaries.
2062 * IA32 arch specifies that at the time of processor reset the
2063 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2064 * is setting it to 0 in the usedland code. This causes invalid guest
2065 * state vmexit when "unrestricted guest" mode is turned on.
2066 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2067 * tree. Newer qemu binaries with that qemu fix would not need this
2068 * kvm hack.
2069 */
2070 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2071 ar |= 0x1; /* Accessed */
2072
2073 vmcs_write32(sf->ar_bytes, ar);
2074 }
2075
2076 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2077 {
2078 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2079
2080 *db = (ar >> 14) & 1;
2081 *l = (ar >> 13) & 1;
2082 }
2083
2084 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2085 {
2086 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2087 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2088 }
2089
2090 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2091 {
2092 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2093 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2094 }
2095
2096 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2097 {
2098 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2099 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2100 }
2101
2102 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2103 {
2104 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2105 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2106 }
2107
2108 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2109 {
2110 struct kvm_segment var;
2111 u32 ar;
2112
2113 vmx_get_segment(vcpu, &var, seg);
2114 ar = vmx_segment_access_rights(&var);
2115
2116 if (var.base != (var.selector << 4))
2117 return false;
2118 if (var.limit != 0xffff)
2119 return false;
2120 if (ar != 0xf3)
2121 return false;
2122
2123 return true;
2124 }
2125
2126 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2127 {
2128 struct kvm_segment cs;
2129 unsigned int cs_rpl;
2130
2131 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2132 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2133
2134 if (cs.unusable)
2135 return false;
2136 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2137 return false;
2138 if (!cs.s)
2139 return false;
2140 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2141 if (cs.dpl > cs_rpl)
2142 return false;
2143 } else {
2144 if (cs.dpl != cs_rpl)
2145 return false;
2146 }
2147 if (!cs.present)
2148 return false;
2149
2150 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2151 return true;
2152 }
2153
2154 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2155 {
2156 struct kvm_segment ss;
2157 unsigned int ss_rpl;
2158
2159 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2160 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2161
2162 if (ss.unusable)
2163 return true;
2164 if (ss.type != 3 && ss.type != 7)
2165 return false;
2166 if (!ss.s)
2167 return false;
2168 if (ss.dpl != ss_rpl) /* DPL != RPL */
2169 return false;
2170 if (!ss.present)
2171 return false;
2172
2173 return true;
2174 }
2175
2176 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2177 {
2178 struct kvm_segment var;
2179 unsigned int rpl;
2180
2181 vmx_get_segment(vcpu, &var, seg);
2182 rpl = var.selector & SELECTOR_RPL_MASK;
2183
2184 if (var.unusable)
2185 return true;
2186 if (!var.s)
2187 return false;
2188 if (!var.present)
2189 return false;
2190 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2191 if (var.dpl < rpl) /* DPL < RPL */
2192 return false;
2193 }
2194
2195 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2196 * rights flags
2197 */
2198 return true;
2199 }
2200
2201 static bool tr_valid(struct kvm_vcpu *vcpu)
2202 {
2203 struct kvm_segment tr;
2204
2205 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2206
2207 if (tr.unusable)
2208 return false;
2209 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2210 return false;
2211 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2212 return false;
2213 if (!tr.present)
2214 return false;
2215
2216 return true;
2217 }
2218
2219 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2220 {
2221 struct kvm_segment ldtr;
2222
2223 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2224
2225 if (ldtr.unusable)
2226 return true;
2227 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2228 return false;
2229 if (ldtr.type != 2)
2230 return false;
2231 if (!ldtr.present)
2232 return false;
2233
2234 return true;
2235 }
2236
2237 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2238 {
2239 struct kvm_segment cs, ss;
2240
2241 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2242 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2243
2244 return ((cs.selector & SELECTOR_RPL_MASK) ==
2245 (ss.selector & SELECTOR_RPL_MASK));
2246 }
2247
2248 /*
2249 * Check if guest state is valid. Returns true if valid, false if
2250 * not.
2251 * We assume that registers are always usable
2252 */
2253 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2254 {
2255 /* real mode guest state checks */
2256 if (!is_protmode(vcpu)) {
2257 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2258 return false;
2259 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2260 return false;
2261 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2262 return false;
2263 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2264 return false;
2265 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2266 return false;
2267 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2268 return false;
2269 } else {
2270 /* protected mode guest state checks */
2271 if (!cs_ss_rpl_check(vcpu))
2272 return false;
2273 if (!code_segment_valid(vcpu))
2274 return false;
2275 if (!stack_segment_valid(vcpu))
2276 return false;
2277 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2278 return false;
2279 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2280 return false;
2281 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2282 return false;
2283 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2284 return false;
2285 if (!tr_valid(vcpu))
2286 return false;
2287 if (!ldtr_valid(vcpu))
2288 return false;
2289 }
2290 /* TODO:
2291 * - Add checks on RIP
2292 * - Add checks on RFLAGS
2293 */
2294
2295 return true;
2296 }
2297
2298 static int init_rmode_tss(struct kvm *kvm)
2299 {
2300 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2301 u16 data = 0;
2302 int ret = 0;
2303 int r;
2304
2305 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2306 if (r < 0)
2307 goto out;
2308 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2309 r = kvm_write_guest_page(kvm, fn++, &data,
2310 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2311 if (r < 0)
2312 goto out;
2313 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2314 if (r < 0)
2315 goto out;
2316 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2317 if (r < 0)
2318 goto out;
2319 data = ~0;
2320 r = kvm_write_guest_page(kvm, fn, &data,
2321 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2322 sizeof(u8));
2323 if (r < 0)
2324 goto out;
2325
2326 ret = 1;
2327 out:
2328 return ret;
2329 }
2330
2331 static int init_rmode_identity_map(struct kvm *kvm)
2332 {
2333 int i, r, ret;
2334 pfn_t identity_map_pfn;
2335 u32 tmp;
2336
2337 if (!enable_ept)
2338 return 1;
2339 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2340 printk(KERN_ERR "EPT: identity-mapping pagetable "
2341 "haven't been allocated!\n");
2342 return 0;
2343 }
2344 if (likely(kvm->arch.ept_identity_pagetable_done))
2345 return 1;
2346 ret = 0;
2347 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2348 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2349 if (r < 0)
2350 goto out;
2351 /* Set up identity-mapping pagetable for EPT in real mode */
2352 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2353 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2354 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2355 r = kvm_write_guest_page(kvm, identity_map_pfn,
2356 &tmp, i * sizeof(tmp), sizeof(tmp));
2357 if (r < 0)
2358 goto out;
2359 }
2360 kvm->arch.ept_identity_pagetable_done = true;
2361 ret = 1;
2362 out:
2363 return ret;
2364 }
2365
2366 static void seg_setup(int seg)
2367 {
2368 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2369 unsigned int ar;
2370
2371 vmcs_write16(sf->selector, 0);
2372 vmcs_writel(sf->base, 0);
2373 vmcs_write32(sf->limit, 0xffff);
2374 if (enable_unrestricted_guest) {
2375 ar = 0x93;
2376 if (seg == VCPU_SREG_CS)
2377 ar |= 0x08; /* code segment */
2378 } else
2379 ar = 0xf3;
2380
2381 vmcs_write32(sf->ar_bytes, ar);
2382 }
2383
2384 static int alloc_apic_access_page(struct kvm *kvm)
2385 {
2386 struct kvm_userspace_memory_region kvm_userspace_mem;
2387 int r = 0;
2388
2389 mutex_lock(&kvm->slots_lock);
2390 if (kvm->arch.apic_access_page)
2391 goto out;
2392 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2393 kvm_userspace_mem.flags = 0;
2394 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2395 kvm_userspace_mem.memory_size = PAGE_SIZE;
2396 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2397 if (r)
2398 goto out;
2399
2400 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2401 out:
2402 mutex_unlock(&kvm->slots_lock);
2403 return r;
2404 }
2405
2406 static int alloc_identity_pagetable(struct kvm *kvm)
2407 {
2408 struct kvm_userspace_memory_region kvm_userspace_mem;
2409 int r = 0;
2410
2411 mutex_lock(&kvm->slots_lock);
2412 if (kvm->arch.ept_identity_pagetable)
2413 goto out;
2414 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2415 kvm_userspace_mem.flags = 0;
2416 kvm_userspace_mem.guest_phys_addr =
2417 kvm->arch.ept_identity_map_addr;
2418 kvm_userspace_mem.memory_size = PAGE_SIZE;
2419 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2420 if (r)
2421 goto out;
2422
2423 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2424 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2425 out:
2426 mutex_unlock(&kvm->slots_lock);
2427 return r;
2428 }
2429
2430 static void allocate_vpid(struct vcpu_vmx *vmx)
2431 {
2432 int vpid;
2433
2434 vmx->vpid = 0;
2435 if (!enable_vpid)
2436 return;
2437 spin_lock(&vmx_vpid_lock);
2438 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2439 if (vpid < VMX_NR_VPIDS) {
2440 vmx->vpid = vpid;
2441 __set_bit(vpid, vmx_vpid_bitmap);
2442 }
2443 spin_unlock(&vmx_vpid_lock);
2444 }
2445
2446 static void free_vpid(struct vcpu_vmx *vmx)
2447 {
2448 if (!enable_vpid)
2449 return;
2450 spin_lock(&vmx_vpid_lock);
2451 if (vmx->vpid != 0)
2452 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2453 spin_unlock(&vmx_vpid_lock);
2454 }
2455
2456 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2457 {
2458 int f = sizeof(unsigned long);
2459
2460 if (!cpu_has_vmx_msr_bitmap())
2461 return;
2462
2463 /*
2464 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2465 * have the write-low and read-high bitmap offsets the wrong way round.
2466 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2467 */
2468 if (msr <= 0x1fff) {
2469 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2470 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2471 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2472 msr &= 0x1fff;
2473 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2474 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2475 }
2476 }
2477
2478 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2479 {
2480 if (!longmode_only)
2481 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2482 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2483 }
2484
2485 /*
2486 * Sets up the vmcs for emulated real mode.
2487 */
2488 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2489 {
2490 u32 host_sysenter_cs, msr_low, msr_high;
2491 u32 junk;
2492 u64 host_pat;
2493 unsigned long a;
2494 struct desc_ptr dt;
2495 int i;
2496 unsigned long kvm_vmx_return;
2497 u32 exec_control;
2498
2499 /* I/O */
2500 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2501 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2502
2503 if (cpu_has_vmx_msr_bitmap())
2504 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2505
2506 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2507
2508 /* Control */
2509 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2510 vmcs_config.pin_based_exec_ctrl);
2511
2512 exec_control = vmcs_config.cpu_based_exec_ctrl;
2513 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2514 exec_control &= ~CPU_BASED_TPR_SHADOW;
2515 #ifdef CONFIG_X86_64
2516 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2517 CPU_BASED_CR8_LOAD_EXITING;
2518 #endif
2519 }
2520 if (!enable_ept)
2521 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2522 CPU_BASED_CR3_LOAD_EXITING |
2523 CPU_BASED_INVLPG_EXITING;
2524 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2525
2526 if (cpu_has_secondary_exec_ctrls()) {
2527 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2528 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2529 exec_control &=
2530 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2531 if (vmx->vpid == 0)
2532 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2533 if (!enable_ept) {
2534 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2535 enable_unrestricted_guest = 0;
2536 }
2537 if (!enable_unrestricted_guest)
2538 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2539 if (!ple_gap)
2540 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2541 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2542 }
2543
2544 if (ple_gap) {
2545 vmcs_write32(PLE_GAP, ple_gap);
2546 vmcs_write32(PLE_WINDOW, ple_window);
2547 }
2548
2549 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2550 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2551 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2552
2553 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2554 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2555 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2556
2557 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2558 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2559 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2560 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2561 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2562 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2563 #ifdef CONFIG_X86_64
2564 rdmsrl(MSR_FS_BASE, a);
2565 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2566 rdmsrl(MSR_GS_BASE, a);
2567 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2568 #else
2569 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2570 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2571 #endif
2572
2573 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2574
2575 native_store_idt(&dt);
2576 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2577
2578 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2579 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2580 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2581 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2582 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2583 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2584 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2585
2586 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2587 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2588 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2589 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2590 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2591 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2592
2593 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2594 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2595 host_pat = msr_low | ((u64) msr_high << 32);
2596 vmcs_write64(HOST_IA32_PAT, host_pat);
2597 }
2598 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2599 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2600 host_pat = msr_low | ((u64) msr_high << 32);
2601 /* Write the default value follow host pat */
2602 vmcs_write64(GUEST_IA32_PAT, host_pat);
2603 /* Keep arch.pat sync with GUEST_IA32_PAT */
2604 vmx->vcpu.arch.pat = host_pat;
2605 }
2606
2607 for (i = 0; i < NR_VMX_MSR; ++i) {
2608 u32 index = vmx_msr_index[i];
2609 u32 data_low, data_high;
2610 int j = vmx->nmsrs;
2611
2612 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2613 continue;
2614 if (wrmsr_safe(index, data_low, data_high) < 0)
2615 continue;
2616 vmx->guest_msrs[j].index = i;
2617 vmx->guest_msrs[j].data = 0;
2618 vmx->guest_msrs[j].mask = -1ull;
2619 ++vmx->nmsrs;
2620 }
2621
2622 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2623
2624 /* 22.2.1, 20.8.1 */
2625 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2626
2627 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2628 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2629 if (enable_ept)
2630 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2631 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2632
2633 kvm_write_tsc(&vmx->vcpu, 0);
2634
2635 return 0;
2636 }
2637
2638 static int init_rmode(struct kvm *kvm)
2639 {
2640 int idx, ret = 0;
2641
2642 idx = srcu_read_lock(&kvm->srcu);
2643 if (!init_rmode_tss(kvm))
2644 goto exit;
2645 if (!init_rmode_identity_map(kvm))
2646 goto exit;
2647
2648 ret = 1;
2649 exit:
2650 srcu_read_unlock(&kvm->srcu, idx);
2651 return ret;
2652 }
2653
2654 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2655 {
2656 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657 u64 msr;
2658 int ret;
2659
2660 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2661 if (!init_rmode(vmx->vcpu.kvm)) {
2662 ret = -ENOMEM;
2663 goto out;
2664 }
2665
2666 vmx->rmode.vm86_active = 0;
2667
2668 vmx->soft_vnmi_blocked = 0;
2669
2670 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2671 kvm_set_cr8(&vmx->vcpu, 0);
2672 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2673 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2674 msr |= MSR_IA32_APICBASE_BSP;
2675 kvm_set_apic_base(&vmx->vcpu, msr);
2676
2677 ret = fx_init(&vmx->vcpu);
2678 if (ret != 0)
2679 goto out;
2680
2681 seg_setup(VCPU_SREG_CS);
2682 /*
2683 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2684 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2685 */
2686 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2687 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2688 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2689 } else {
2690 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2691 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2692 }
2693
2694 seg_setup(VCPU_SREG_DS);
2695 seg_setup(VCPU_SREG_ES);
2696 seg_setup(VCPU_SREG_FS);
2697 seg_setup(VCPU_SREG_GS);
2698 seg_setup(VCPU_SREG_SS);
2699
2700 vmcs_write16(GUEST_TR_SELECTOR, 0);
2701 vmcs_writel(GUEST_TR_BASE, 0);
2702 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2703 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2704
2705 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2706 vmcs_writel(GUEST_LDTR_BASE, 0);
2707 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2708 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2709
2710 vmcs_write32(GUEST_SYSENTER_CS, 0);
2711 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2712 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2713
2714 vmcs_writel(GUEST_RFLAGS, 0x02);
2715 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2716 kvm_rip_write(vcpu, 0xfff0);
2717 else
2718 kvm_rip_write(vcpu, 0);
2719 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2720
2721 vmcs_writel(GUEST_DR7, 0x400);
2722
2723 vmcs_writel(GUEST_GDTR_BASE, 0);
2724 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2725
2726 vmcs_writel(GUEST_IDTR_BASE, 0);
2727 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2728
2729 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2730 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2731 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2732
2733 /* Special registers */
2734 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2735
2736 setup_msrs(vmx);
2737
2738 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2739
2740 if (cpu_has_vmx_tpr_shadow()) {
2741 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2742 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2743 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2744 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2745 vmcs_write32(TPR_THRESHOLD, 0);
2746 }
2747
2748 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2749 vmcs_write64(APIC_ACCESS_ADDR,
2750 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2751
2752 if (vmx->vpid != 0)
2753 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2754
2755 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2756 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2757 vmx_set_cr4(&vmx->vcpu, 0);
2758 vmx_set_efer(&vmx->vcpu, 0);
2759 vmx_fpu_activate(&vmx->vcpu);
2760 update_exception_bitmap(&vmx->vcpu);
2761
2762 vpid_sync_context(vmx);
2763
2764 ret = 0;
2765
2766 /* HACK: Don't enable emulation on guest boot/reset */
2767 vmx->emulation_required = 0;
2768
2769 out:
2770 return ret;
2771 }
2772
2773 static void enable_irq_window(struct kvm_vcpu *vcpu)
2774 {
2775 u32 cpu_based_vm_exec_control;
2776
2777 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2778 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2780 }
2781
2782 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2783 {
2784 u32 cpu_based_vm_exec_control;
2785
2786 if (!cpu_has_virtual_nmis()) {
2787 enable_irq_window(vcpu);
2788 return;
2789 }
2790
2791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2792 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2794 }
2795
2796 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2797 {
2798 struct vcpu_vmx *vmx = to_vmx(vcpu);
2799 uint32_t intr;
2800 int irq = vcpu->arch.interrupt.nr;
2801
2802 trace_kvm_inj_virq(irq);
2803
2804 ++vcpu->stat.irq_injections;
2805 if (vmx->rmode.vm86_active) {
2806 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2807 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2808 return;
2809 }
2810 intr = irq | INTR_INFO_VALID_MASK;
2811 if (vcpu->arch.interrupt.soft) {
2812 intr |= INTR_TYPE_SOFT_INTR;
2813 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2814 vmx->vcpu.arch.event_exit_inst_len);
2815 } else
2816 intr |= INTR_TYPE_EXT_INTR;
2817 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2818 }
2819
2820 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2821 {
2822 struct vcpu_vmx *vmx = to_vmx(vcpu);
2823
2824 if (!cpu_has_virtual_nmis()) {
2825 /*
2826 * Tracking the NMI-blocked state in software is built upon
2827 * finding the next open IRQ window. This, in turn, depends on
2828 * well-behaving guests: They have to keep IRQs disabled at
2829 * least as long as the NMI handler runs. Otherwise we may
2830 * cause NMI nesting, maybe breaking the guest. But as this is
2831 * highly unlikely, we can live with the residual risk.
2832 */
2833 vmx->soft_vnmi_blocked = 1;
2834 vmx->vnmi_blocked_time = 0;
2835 }
2836
2837 ++vcpu->stat.nmi_injections;
2838 if (vmx->rmode.vm86_active) {
2839 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2840 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2841 return;
2842 }
2843 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2844 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2845 }
2846
2847 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2848 {
2849 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2850 return 0;
2851
2852 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2853 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2854 }
2855
2856 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2857 {
2858 if (!cpu_has_virtual_nmis())
2859 return to_vmx(vcpu)->soft_vnmi_blocked;
2860 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2861 }
2862
2863 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2864 {
2865 struct vcpu_vmx *vmx = to_vmx(vcpu);
2866
2867 if (!cpu_has_virtual_nmis()) {
2868 if (vmx->soft_vnmi_blocked != masked) {
2869 vmx->soft_vnmi_blocked = masked;
2870 vmx->vnmi_blocked_time = 0;
2871 }
2872 } else {
2873 if (masked)
2874 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2875 GUEST_INTR_STATE_NMI);
2876 else
2877 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2878 GUEST_INTR_STATE_NMI);
2879 }
2880 }
2881
2882 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2883 {
2884 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2885 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2886 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2887 }
2888
2889 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2890 {
2891 int ret;
2892 struct kvm_userspace_memory_region tss_mem = {
2893 .slot = TSS_PRIVATE_MEMSLOT,
2894 .guest_phys_addr = addr,
2895 .memory_size = PAGE_SIZE * 3,
2896 .flags = 0,
2897 };
2898
2899 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2900 if (ret)
2901 return ret;
2902 kvm->arch.tss_addr = addr;
2903 return 0;
2904 }
2905
2906 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2907 int vec, u32 err_code)
2908 {
2909 /*
2910 * Instruction with address size override prefix opcode 0x67
2911 * Cause the #SS fault with 0 error code in VM86 mode.
2912 */
2913 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2914 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2915 return 1;
2916 /*
2917 * Forward all other exceptions that are valid in real mode.
2918 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2919 * the required debugging infrastructure rework.
2920 */
2921 switch (vec) {
2922 case DB_VECTOR:
2923 if (vcpu->guest_debug &
2924 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2925 return 0;
2926 kvm_queue_exception(vcpu, vec);
2927 return 1;
2928 case BP_VECTOR:
2929 /*
2930 * Update instruction length as we may reinject the exception
2931 * from user space while in guest debugging mode.
2932 */
2933 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2934 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2935 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2936 return 0;
2937 /* fall through */
2938 case DE_VECTOR:
2939 case OF_VECTOR:
2940 case BR_VECTOR:
2941 case UD_VECTOR:
2942 case DF_VECTOR:
2943 case SS_VECTOR:
2944 case GP_VECTOR:
2945 case MF_VECTOR:
2946 kvm_queue_exception(vcpu, vec);
2947 return 1;
2948 }
2949 return 0;
2950 }
2951
2952 /*
2953 * Trigger machine check on the host. We assume all the MSRs are already set up
2954 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2955 * We pass a fake environment to the machine check handler because we want
2956 * the guest to be always treated like user space, no matter what context
2957 * it used internally.
2958 */
2959 static void kvm_machine_check(void)
2960 {
2961 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2962 struct pt_regs regs = {
2963 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2964 .flags = X86_EFLAGS_IF,
2965 };
2966
2967 do_machine_check(&regs, 0);
2968 #endif
2969 }
2970
2971 static int handle_machine_check(struct kvm_vcpu *vcpu)
2972 {
2973 /* already handled by vcpu_run */
2974 return 1;
2975 }
2976
2977 static int handle_exception(struct kvm_vcpu *vcpu)
2978 {
2979 struct vcpu_vmx *vmx = to_vmx(vcpu);
2980 struct kvm_run *kvm_run = vcpu->run;
2981 u32 intr_info, ex_no, error_code;
2982 unsigned long cr2, rip, dr6;
2983 u32 vect_info;
2984 enum emulation_result er;
2985
2986 vect_info = vmx->idt_vectoring_info;
2987 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2988
2989 if (is_machine_check(intr_info))
2990 return handle_machine_check(vcpu);
2991
2992 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2993 !is_page_fault(intr_info)) {
2994 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2995 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2996 vcpu->run->internal.ndata = 2;
2997 vcpu->run->internal.data[0] = vect_info;
2998 vcpu->run->internal.data[1] = intr_info;
2999 return 0;
3000 }
3001
3002 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3003 return 1; /* already handled by vmx_vcpu_run() */
3004
3005 if (is_no_device(intr_info)) {
3006 vmx_fpu_activate(vcpu);
3007 return 1;
3008 }
3009
3010 if (is_invalid_opcode(intr_info)) {
3011 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3012 if (er != EMULATE_DONE)
3013 kvm_queue_exception(vcpu, UD_VECTOR);
3014 return 1;
3015 }
3016
3017 error_code = 0;
3018 rip = kvm_rip_read(vcpu);
3019 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3020 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3021 if (is_page_fault(intr_info)) {
3022 /* EPT won't cause page fault directly */
3023 if (enable_ept)
3024 BUG();
3025 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3026 trace_kvm_page_fault(cr2, error_code);
3027
3028 if (kvm_event_needs_reinjection(vcpu))
3029 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3030 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3031 }
3032
3033 if (vmx->rmode.vm86_active &&
3034 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3035 error_code)) {
3036 if (vcpu->arch.halt_request) {
3037 vcpu->arch.halt_request = 0;
3038 return kvm_emulate_halt(vcpu);
3039 }
3040 return 1;
3041 }
3042
3043 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3044 switch (ex_no) {
3045 case DB_VECTOR:
3046 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3047 if (!(vcpu->guest_debug &
3048 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3049 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3050 kvm_queue_exception(vcpu, DB_VECTOR);
3051 return 1;
3052 }
3053 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3054 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3055 /* fall through */
3056 case BP_VECTOR:
3057 /*
3058 * Update instruction length as we may reinject #BP from
3059 * user space while in guest debugging mode. Reading it for
3060 * #DB as well causes no harm, it is not used in that case.
3061 */
3062 vmx->vcpu.arch.event_exit_inst_len =
3063 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3064 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3065 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3066 kvm_run->debug.arch.exception = ex_no;
3067 break;
3068 default:
3069 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3070 kvm_run->ex.exception = ex_no;
3071 kvm_run->ex.error_code = error_code;
3072 break;
3073 }
3074 return 0;
3075 }
3076
3077 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3078 {
3079 ++vcpu->stat.irq_exits;
3080 return 1;
3081 }
3082
3083 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3084 {
3085 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3086 return 0;
3087 }
3088
3089 static int handle_io(struct kvm_vcpu *vcpu)
3090 {
3091 unsigned long exit_qualification;
3092 int size, in, string;
3093 unsigned port;
3094
3095 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3096 string = (exit_qualification & 16) != 0;
3097 in = (exit_qualification & 8) != 0;
3098
3099 ++vcpu->stat.io_exits;
3100
3101 if (string || in)
3102 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3103
3104 port = exit_qualification >> 16;
3105 size = (exit_qualification & 7) + 1;
3106 skip_emulated_instruction(vcpu);
3107
3108 return kvm_fast_pio_out(vcpu, size, port);
3109 }
3110
3111 static void
3112 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3113 {
3114 /*
3115 * Patch in the VMCALL instruction:
3116 */
3117 hypercall[0] = 0x0f;
3118 hypercall[1] = 0x01;
3119 hypercall[2] = 0xc1;
3120 }
3121
3122 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3123 {
3124 if (err)
3125 kvm_inject_gp(vcpu, 0);
3126 else
3127 skip_emulated_instruction(vcpu);
3128 }
3129
3130 static int handle_cr(struct kvm_vcpu *vcpu)
3131 {
3132 unsigned long exit_qualification, val;
3133 int cr;
3134 int reg;
3135 int err;
3136
3137 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3138 cr = exit_qualification & 15;
3139 reg = (exit_qualification >> 8) & 15;
3140 switch ((exit_qualification >> 4) & 3) {
3141 case 0: /* mov to cr */
3142 val = kvm_register_read(vcpu, reg);
3143 trace_kvm_cr_write(cr, val);
3144 switch (cr) {
3145 case 0:
3146 err = kvm_set_cr0(vcpu, val);
3147 complete_insn_gp(vcpu, err);
3148 return 1;
3149 case 3:
3150 err = kvm_set_cr3(vcpu, val);
3151 complete_insn_gp(vcpu, err);
3152 return 1;
3153 case 4:
3154 err = kvm_set_cr4(vcpu, val);
3155 complete_insn_gp(vcpu, err);
3156 return 1;
3157 case 8: {
3158 u8 cr8_prev = kvm_get_cr8(vcpu);
3159 u8 cr8 = kvm_register_read(vcpu, reg);
3160 kvm_set_cr8(vcpu, cr8);
3161 skip_emulated_instruction(vcpu);
3162 if (irqchip_in_kernel(vcpu->kvm))
3163 return 1;
3164 if (cr8_prev <= cr8)
3165 return 1;
3166 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3167 return 0;
3168 }
3169 };
3170 break;
3171 case 2: /* clts */
3172 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3173 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3174 skip_emulated_instruction(vcpu);
3175 vmx_fpu_activate(vcpu);
3176 return 1;
3177 case 1: /*mov from cr*/
3178 switch (cr) {
3179 case 3:
3180 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3181 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3182 skip_emulated_instruction(vcpu);
3183 return 1;
3184 case 8:
3185 val = kvm_get_cr8(vcpu);
3186 kvm_register_write(vcpu, reg, val);
3187 trace_kvm_cr_read(cr, val);
3188 skip_emulated_instruction(vcpu);
3189 return 1;
3190 }
3191 break;
3192 case 3: /* lmsw */
3193 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3194 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3195 kvm_lmsw(vcpu, val);
3196
3197 skip_emulated_instruction(vcpu);
3198 return 1;
3199 default:
3200 break;
3201 }
3202 vcpu->run->exit_reason = 0;
3203 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3204 (int)(exit_qualification >> 4) & 3, cr);
3205 return 0;
3206 }
3207
3208 static int handle_dr(struct kvm_vcpu *vcpu)
3209 {
3210 unsigned long exit_qualification;
3211 int dr, reg;
3212
3213 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3214 if (!kvm_require_cpl(vcpu, 0))
3215 return 1;
3216 dr = vmcs_readl(GUEST_DR7);
3217 if (dr & DR7_GD) {
3218 /*
3219 * As the vm-exit takes precedence over the debug trap, we
3220 * need to emulate the latter, either for the host or the
3221 * guest debugging itself.
3222 */
3223 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3224 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3225 vcpu->run->debug.arch.dr7 = dr;
3226 vcpu->run->debug.arch.pc =
3227 vmcs_readl(GUEST_CS_BASE) +
3228 vmcs_readl(GUEST_RIP);
3229 vcpu->run->debug.arch.exception = DB_VECTOR;
3230 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3231 return 0;
3232 } else {
3233 vcpu->arch.dr7 &= ~DR7_GD;
3234 vcpu->arch.dr6 |= DR6_BD;
3235 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3236 kvm_queue_exception(vcpu, DB_VECTOR);
3237 return 1;
3238 }
3239 }
3240
3241 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3242 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3243 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3244 if (exit_qualification & TYPE_MOV_FROM_DR) {
3245 unsigned long val;
3246 if (!kvm_get_dr(vcpu, dr, &val))
3247 kvm_register_write(vcpu, reg, val);
3248 } else
3249 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3250 skip_emulated_instruction(vcpu);
3251 return 1;
3252 }
3253
3254 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3255 {
3256 vmcs_writel(GUEST_DR7, val);
3257 }
3258
3259 static int handle_cpuid(struct kvm_vcpu *vcpu)
3260 {
3261 kvm_emulate_cpuid(vcpu);
3262 return 1;
3263 }
3264
3265 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3266 {
3267 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3268 u64 data;
3269
3270 if (vmx_get_msr(vcpu, ecx, &data)) {
3271 trace_kvm_msr_read_ex(ecx);
3272 kvm_inject_gp(vcpu, 0);
3273 return 1;
3274 }
3275
3276 trace_kvm_msr_read(ecx, data);
3277
3278 /* FIXME: handling of bits 32:63 of rax, rdx */
3279 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3280 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3281 skip_emulated_instruction(vcpu);
3282 return 1;
3283 }
3284
3285 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3286 {
3287 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3288 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3289 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3290
3291 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3292 trace_kvm_msr_write_ex(ecx, data);
3293 kvm_inject_gp(vcpu, 0);
3294 return 1;
3295 }
3296
3297 trace_kvm_msr_write(ecx, data);
3298 skip_emulated_instruction(vcpu);
3299 return 1;
3300 }
3301
3302 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3303 {
3304 kvm_make_request(KVM_REQ_EVENT, vcpu);
3305 return 1;
3306 }
3307
3308 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3309 {
3310 u32 cpu_based_vm_exec_control;
3311
3312 /* clear pending irq */
3313 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3314 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3315 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3316
3317 kvm_make_request(KVM_REQ_EVENT, vcpu);
3318
3319 ++vcpu->stat.irq_window_exits;
3320
3321 /*
3322 * If the user space waits to inject interrupts, exit as soon as
3323 * possible
3324 */
3325 if (!irqchip_in_kernel(vcpu->kvm) &&
3326 vcpu->run->request_interrupt_window &&
3327 !kvm_cpu_has_interrupt(vcpu)) {
3328 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3329 return 0;
3330 }
3331 return 1;
3332 }
3333
3334 static int handle_halt(struct kvm_vcpu *vcpu)
3335 {
3336 skip_emulated_instruction(vcpu);
3337 return kvm_emulate_halt(vcpu);
3338 }
3339
3340 static int handle_vmcall(struct kvm_vcpu *vcpu)
3341 {
3342 skip_emulated_instruction(vcpu);
3343 kvm_emulate_hypercall(vcpu);
3344 return 1;
3345 }
3346
3347 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3348 {
3349 kvm_queue_exception(vcpu, UD_VECTOR);
3350 return 1;
3351 }
3352
3353 static int handle_invlpg(struct kvm_vcpu *vcpu)
3354 {
3355 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3356
3357 kvm_mmu_invlpg(vcpu, exit_qualification);
3358 skip_emulated_instruction(vcpu);
3359 return 1;
3360 }
3361
3362 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3363 {
3364 skip_emulated_instruction(vcpu);
3365 kvm_emulate_wbinvd(vcpu);
3366 return 1;
3367 }
3368
3369 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3370 {
3371 u64 new_bv = kvm_read_edx_eax(vcpu);
3372 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3373
3374 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3375 skip_emulated_instruction(vcpu);
3376 return 1;
3377 }
3378
3379 static int handle_apic_access(struct kvm_vcpu *vcpu)
3380 {
3381 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3382 }
3383
3384 static int handle_task_switch(struct kvm_vcpu *vcpu)
3385 {
3386 struct vcpu_vmx *vmx = to_vmx(vcpu);
3387 unsigned long exit_qualification;
3388 bool has_error_code = false;
3389 u32 error_code = 0;
3390 u16 tss_selector;
3391 int reason, type, idt_v;
3392
3393 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3394 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3395
3396 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3397
3398 reason = (u32)exit_qualification >> 30;
3399 if (reason == TASK_SWITCH_GATE && idt_v) {
3400 switch (type) {
3401 case INTR_TYPE_NMI_INTR:
3402 vcpu->arch.nmi_injected = false;
3403 if (cpu_has_virtual_nmis())
3404 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3405 GUEST_INTR_STATE_NMI);
3406 break;
3407 case INTR_TYPE_EXT_INTR:
3408 case INTR_TYPE_SOFT_INTR:
3409 kvm_clear_interrupt_queue(vcpu);
3410 break;
3411 case INTR_TYPE_HARD_EXCEPTION:
3412 if (vmx->idt_vectoring_info &
3413 VECTORING_INFO_DELIVER_CODE_MASK) {
3414 has_error_code = true;
3415 error_code =
3416 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3417 }
3418 /* fall through */
3419 case INTR_TYPE_SOFT_EXCEPTION:
3420 kvm_clear_exception_queue(vcpu);
3421 break;
3422 default:
3423 break;
3424 }
3425 }
3426 tss_selector = exit_qualification;
3427
3428 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3429 type != INTR_TYPE_EXT_INTR &&
3430 type != INTR_TYPE_NMI_INTR))
3431 skip_emulated_instruction(vcpu);
3432
3433 if (kvm_task_switch(vcpu, tss_selector, reason,
3434 has_error_code, error_code) == EMULATE_FAIL) {
3435 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3436 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3437 vcpu->run->internal.ndata = 0;
3438 return 0;
3439 }
3440
3441 /* clear all local breakpoint enable flags */
3442 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3443
3444 /*
3445 * TODO: What about debug traps on tss switch?
3446 * Are we supposed to inject them and update dr6?
3447 */
3448
3449 return 1;
3450 }
3451
3452 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3453 {
3454 unsigned long exit_qualification;
3455 gpa_t gpa;
3456 int gla_validity;
3457
3458 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3459
3460 if (exit_qualification & (1 << 6)) {
3461 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3462 return -EINVAL;
3463 }
3464
3465 gla_validity = (exit_qualification >> 7) & 0x3;
3466 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3467 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3468 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3469 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3470 vmcs_readl(GUEST_LINEAR_ADDRESS));
3471 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3472 (long unsigned int)exit_qualification);
3473 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3474 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3475 return 0;
3476 }
3477
3478 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3479 trace_kvm_page_fault(gpa, exit_qualification);
3480 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3481 }
3482
3483 static u64 ept_rsvd_mask(u64 spte, int level)
3484 {
3485 int i;
3486 u64 mask = 0;
3487
3488 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3489 mask |= (1ULL << i);
3490
3491 if (level > 2)
3492 /* bits 7:3 reserved */
3493 mask |= 0xf8;
3494 else if (level == 2) {
3495 if (spte & (1ULL << 7))
3496 /* 2MB ref, bits 20:12 reserved */
3497 mask |= 0x1ff000;
3498 else
3499 /* bits 6:3 reserved */
3500 mask |= 0x78;
3501 }
3502
3503 return mask;
3504 }
3505
3506 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3507 int level)
3508 {
3509 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3510
3511 /* 010b (write-only) */
3512 WARN_ON((spte & 0x7) == 0x2);
3513
3514 /* 110b (write/execute) */
3515 WARN_ON((spte & 0x7) == 0x6);
3516
3517 /* 100b (execute-only) and value not supported by logical processor */
3518 if (!cpu_has_vmx_ept_execute_only())
3519 WARN_ON((spte & 0x7) == 0x4);
3520
3521 /* not 000b */
3522 if ((spte & 0x7)) {
3523 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3524
3525 if (rsvd_bits != 0) {
3526 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3527 __func__, rsvd_bits);
3528 WARN_ON(1);
3529 }
3530
3531 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3532 u64 ept_mem_type = (spte & 0x38) >> 3;
3533
3534 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3535 ept_mem_type == 7) {
3536 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3537 __func__, ept_mem_type);
3538 WARN_ON(1);
3539 }
3540 }
3541 }
3542 }
3543
3544 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3545 {
3546 u64 sptes[4];
3547 int nr_sptes, i;
3548 gpa_t gpa;
3549
3550 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3551
3552 printk(KERN_ERR "EPT: Misconfiguration.\n");
3553 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3554
3555 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3556
3557 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3558 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3559
3560 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3561 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3562
3563 return 0;
3564 }
3565
3566 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3567 {
3568 u32 cpu_based_vm_exec_control;
3569
3570 /* clear pending NMI */
3571 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3572 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3574 ++vcpu->stat.nmi_window_exits;
3575 kvm_make_request(KVM_REQ_EVENT, vcpu);
3576
3577 return 1;
3578 }
3579
3580 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3581 {
3582 struct vcpu_vmx *vmx = to_vmx(vcpu);
3583 enum emulation_result err = EMULATE_DONE;
3584 int ret = 1;
3585 u32 cpu_exec_ctrl;
3586 bool intr_window_requested;
3587
3588 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3589 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3590
3591 while (!guest_state_valid(vcpu)) {
3592 if (intr_window_requested
3593 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3594 return handle_interrupt_window(&vmx->vcpu);
3595
3596 err = emulate_instruction(vcpu, 0, 0, 0);
3597
3598 if (err == EMULATE_DO_MMIO) {
3599 ret = 0;
3600 goto out;
3601 }
3602
3603 if (err != EMULATE_DONE)
3604 return 0;
3605
3606 if (signal_pending(current))
3607 goto out;
3608 if (need_resched())
3609 schedule();
3610 }
3611
3612 vmx->emulation_required = 0;
3613 out:
3614 return ret;
3615 }
3616
3617 /*
3618 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3619 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3620 */
3621 static int handle_pause(struct kvm_vcpu *vcpu)
3622 {
3623 skip_emulated_instruction(vcpu);
3624 kvm_vcpu_on_spin(vcpu);
3625
3626 return 1;
3627 }
3628
3629 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3630 {
3631 kvm_queue_exception(vcpu, UD_VECTOR);
3632 return 1;
3633 }
3634
3635 /*
3636 * The exit handlers return 1 if the exit was handled fully and guest execution
3637 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3638 * to be done to userspace and return 0.
3639 */
3640 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3641 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3642 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3643 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3644 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3645 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3646 [EXIT_REASON_CR_ACCESS] = handle_cr,
3647 [EXIT_REASON_DR_ACCESS] = handle_dr,
3648 [EXIT_REASON_CPUID] = handle_cpuid,
3649 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3650 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3651 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3652 [EXIT_REASON_HLT] = handle_halt,
3653 [EXIT_REASON_INVLPG] = handle_invlpg,
3654 [EXIT_REASON_VMCALL] = handle_vmcall,
3655 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3656 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3657 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3658 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3659 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3660 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3661 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3662 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3663 [EXIT_REASON_VMON] = handle_vmx_insn,
3664 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3665 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3666 [EXIT_REASON_WBINVD] = handle_wbinvd,
3667 [EXIT_REASON_XSETBV] = handle_xsetbv,
3668 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3669 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3670 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3671 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3672 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3673 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3674 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3675 };
3676
3677 static const int kvm_vmx_max_exit_handlers =
3678 ARRAY_SIZE(kvm_vmx_exit_handlers);
3679
3680 /*
3681 * The guest has exited. See if we can fix it or if we need userspace
3682 * assistance.
3683 */
3684 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3685 {
3686 struct vcpu_vmx *vmx = to_vmx(vcpu);
3687 u32 exit_reason = vmx->exit_reason;
3688 u32 vectoring_info = vmx->idt_vectoring_info;
3689
3690 trace_kvm_exit(exit_reason, vcpu);
3691
3692 /* If guest state is invalid, start emulating */
3693 if (vmx->emulation_required && emulate_invalid_guest_state)
3694 return handle_invalid_guest_state(vcpu);
3695
3696 /* Access CR3 don't cause VMExit in paging mode, so we need
3697 * to sync with guest real CR3. */
3698 if (enable_ept && is_paging(vcpu))
3699 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3700
3701 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3702 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3703 vcpu->run->fail_entry.hardware_entry_failure_reason
3704 = exit_reason;
3705 return 0;
3706 }
3707
3708 if (unlikely(vmx->fail)) {
3709 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3710 vcpu->run->fail_entry.hardware_entry_failure_reason
3711 = vmcs_read32(VM_INSTRUCTION_ERROR);
3712 return 0;
3713 }
3714
3715 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3716 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3717 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3718 exit_reason != EXIT_REASON_TASK_SWITCH))
3719 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3720 "(0x%x) and exit reason is 0x%x\n",
3721 __func__, vectoring_info, exit_reason);
3722
3723 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3724 if (vmx_interrupt_allowed(vcpu)) {
3725 vmx->soft_vnmi_blocked = 0;
3726 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3727 vcpu->arch.nmi_pending) {
3728 /*
3729 * This CPU don't support us in finding the end of an
3730 * NMI-blocked window if the guest runs with IRQs
3731 * disabled. So we pull the trigger after 1 s of
3732 * futile waiting, but inform the user about this.
3733 */
3734 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3735 "state on VCPU %d after 1 s timeout\n",
3736 __func__, vcpu->vcpu_id);
3737 vmx->soft_vnmi_blocked = 0;
3738 }
3739 }
3740
3741 if (exit_reason < kvm_vmx_max_exit_handlers
3742 && kvm_vmx_exit_handlers[exit_reason])
3743 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3744 else {
3745 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3746 vcpu->run->hw.hardware_exit_reason = exit_reason;
3747 }
3748 return 0;
3749 }
3750
3751 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3752 {
3753 if (irr == -1 || tpr < irr) {
3754 vmcs_write32(TPR_THRESHOLD, 0);
3755 return;
3756 }
3757
3758 vmcs_write32(TPR_THRESHOLD, irr);
3759 }
3760
3761 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3762 {
3763 u32 exit_intr_info = vmx->exit_intr_info;
3764
3765 /* Handle machine checks before interrupts are enabled */
3766 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3767 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3768 && is_machine_check(exit_intr_info)))
3769 kvm_machine_check();
3770
3771 /* We need to handle NMIs before interrupts are enabled */
3772 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3773 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3774 kvm_before_handle_nmi(&vmx->vcpu);
3775 asm("int $2");
3776 kvm_after_handle_nmi(&vmx->vcpu);
3777 }
3778 }
3779
3780 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3781 {
3782 u32 exit_intr_info = vmx->exit_intr_info;
3783 bool unblock_nmi;
3784 u8 vector;
3785 bool idtv_info_valid;
3786
3787 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3788
3789 if (cpu_has_virtual_nmis()) {
3790 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3791 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3792 /*
3793 * SDM 3: 27.7.1.2 (September 2008)
3794 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3795 * a guest IRET fault.
3796 * SDM 3: 23.2.2 (September 2008)
3797 * Bit 12 is undefined in any of the following cases:
3798 * If the VM exit sets the valid bit in the IDT-vectoring
3799 * information field.
3800 * If the VM exit is due to a double fault.
3801 */
3802 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3803 vector != DF_VECTOR && !idtv_info_valid)
3804 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3805 GUEST_INTR_STATE_NMI);
3806 } else if (unlikely(vmx->soft_vnmi_blocked))
3807 vmx->vnmi_blocked_time +=
3808 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3809 }
3810
3811 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3812 u32 idt_vectoring_info,
3813 int instr_len_field,
3814 int error_code_field)
3815 {
3816 u8 vector;
3817 int type;
3818 bool idtv_info_valid;
3819
3820 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3821
3822 vmx->vcpu.arch.nmi_injected = false;
3823 kvm_clear_exception_queue(&vmx->vcpu);
3824 kvm_clear_interrupt_queue(&vmx->vcpu);
3825
3826 if (!idtv_info_valid)
3827 return;
3828
3829 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3830
3831 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3832 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3833
3834 switch (type) {
3835 case INTR_TYPE_NMI_INTR:
3836 vmx->vcpu.arch.nmi_injected = true;
3837 /*
3838 * SDM 3: 27.7.1.2 (September 2008)
3839 * Clear bit "block by NMI" before VM entry if a NMI
3840 * delivery faulted.
3841 */
3842 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3843 GUEST_INTR_STATE_NMI);
3844 break;
3845 case INTR_TYPE_SOFT_EXCEPTION:
3846 vmx->vcpu.arch.event_exit_inst_len =
3847 vmcs_read32(instr_len_field);
3848 /* fall through */
3849 case INTR_TYPE_HARD_EXCEPTION:
3850 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3851 u32 err = vmcs_read32(error_code_field);
3852 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3853 } else
3854 kvm_queue_exception(&vmx->vcpu, vector);
3855 break;
3856 case INTR_TYPE_SOFT_INTR:
3857 vmx->vcpu.arch.event_exit_inst_len =
3858 vmcs_read32(instr_len_field);
3859 /* fall through */
3860 case INTR_TYPE_EXT_INTR:
3861 kvm_queue_interrupt(&vmx->vcpu, vector,
3862 type == INTR_TYPE_SOFT_INTR);
3863 break;
3864 default:
3865 break;
3866 }
3867 }
3868
3869 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3870 {
3871 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3872 VM_EXIT_INSTRUCTION_LEN,
3873 IDT_VECTORING_ERROR_CODE);
3874 }
3875
3876 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3877 {
3878 __vmx_complete_interrupts(to_vmx(vcpu),
3879 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3880 VM_ENTRY_INSTRUCTION_LEN,
3881 VM_ENTRY_EXCEPTION_ERROR_CODE);
3882
3883 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3884 }
3885
3886 #ifdef CONFIG_X86_64
3887 #define R "r"
3888 #define Q "q"
3889 #else
3890 #define R "e"
3891 #define Q "l"
3892 #endif
3893
3894 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3895 {
3896 struct vcpu_vmx *vmx = to_vmx(vcpu);
3897
3898 /* Record the guest's net vcpu time for enforced NMI injections. */
3899 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3900 vmx->entry_time = ktime_get();
3901
3902 /* Don't enter VMX if guest state is invalid, let the exit handler
3903 start emulation until we arrive back to a valid state */
3904 if (vmx->emulation_required && emulate_invalid_guest_state)
3905 return;
3906
3907 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3908 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3909 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3910 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3911
3912 /* When single-stepping over STI and MOV SS, we must clear the
3913 * corresponding interruptibility bits in the guest state. Otherwise
3914 * vmentry fails as it then expects bit 14 (BS) in pending debug
3915 * exceptions being set, but that's not correct for the guest debugging
3916 * case. */
3917 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3918 vmx_set_interrupt_shadow(vcpu, 0);
3919
3920 asm(
3921 /* Store host registers */
3922 "push %%"R"dx; push %%"R"bp;"
3923 "push %%"R"cx \n\t"
3924 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3925 "je 1f \n\t"
3926 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3927 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3928 "1: \n\t"
3929 /* Reload cr2 if changed */
3930 "mov %c[cr2](%0), %%"R"ax \n\t"
3931 "mov %%cr2, %%"R"dx \n\t"
3932 "cmp %%"R"ax, %%"R"dx \n\t"
3933 "je 2f \n\t"
3934 "mov %%"R"ax, %%cr2 \n\t"
3935 "2: \n\t"
3936 /* Check if vmlaunch of vmresume is needed */
3937 "cmpl $0, %c[launched](%0) \n\t"
3938 /* Load guest registers. Don't clobber flags. */
3939 "mov %c[rax](%0), %%"R"ax \n\t"
3940 "mov %c[rbx](%0), %%"R"bx \n\t"
3941 "mov %c[rdx](%0), %%"R"dx \n\t"
3942 "mov %c[rsi](%0), %%"R"si \n\t"
3943 "mov %c[rdi](%0), %%"R"di \n\t"
3944 "mov %c[rbp](%0), %%"R"bp \n\t"
3945 #ifdef CONFIG_X86_64
3946 "mov %c[r8](%0), %%r8 \n\t"
3947 "mov %c[r9](%0), %%r9 \n\t"
3948 "mov %c[r10](%0), %%r10 \n\t"
3949 "mov %c[r11](%0), %%r11 \n\t"
3950 "mov %c[r12](%0), %%r12 \n\t"
3951 "mov %c[r13](%0), %%r13 \n\t"
3952 "mov %c[r14](%0), %%r14 \n\t"
3953 "mov %c[r15](%0), %%r15 \n\t"
3954 #endif
3955 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3956
3957 /* Enter guest mode */
3958 "jne .Llaunched \n\t"
3959 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3960 "jmp .Lkvm_vmx_return \n\t"
3961 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3962 ".Lkvm_vmx_return: "
3963 /* Save guest registers, load host registers, keep flags */
3964 "xchg %0, (%%"R"sp) \n\t"
3965 "mov %%"R"ax, %c[rax](%0) \n\t"
3966 "mov %%"R"bx, %c[rbx](%0) \n\t"
3967 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3968 "mov %%"R"dx, %c[rdx](%0) \n\t"
3969 "mov %%"R"si, %c[rsi](%0) \n\t"
3970 "mov %%"R"di, %c[rdi](%0) \n\t"
3971 "mov %%"R"bp, %c[rbp](%0) \n\t"
3972 #ifdef CONFIG_X86_64
3973 "mov %%r8, %c[r8](%0) \n\t"
3974 "mov %%r9, %c[r9](%0) \n\t"
3975 "mov %%r10, %c[r10](%0) \n\t"
3976 "mov %%r11, %c[r11](%0) \n\t"
3977 "mov %%r12, %c[r12](%0) \n\t"
3978 "mov %%r13, %c[r13](%0) \n\t"
3979 "mov %%r14, %c[r14](%0) \n\t"
3980 "mov %%r15, %c[r15](%0) \n\t"
3981 #endif
3982 "mov %%cr2, %%"R"ax \n\t"
3983 "mov %%"R"ax, %c[cr2](%0) \n\t"
3984
3985 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3986 "setbe %c[fail](%0) \n\t"
3987 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3988 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3989 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3990 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3991 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3992 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3993 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3994 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3995 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3996 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3997 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3998 #ifdef CONFIG_X86_64
3999 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4000 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4001 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4002 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4003 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4004 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4005 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4006 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4007 #endif
4008 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4009 : "cc", "memory"
4010 , R"ax", R"bx", R"di", R"si"
4011 #ifdef CONFIG_X86_64
4012 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4013 #endif
4014 );
4015
4016 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4017 | (1 << VCPU_EXREG_PDPTR));
4018 vcpu->arch.regs_dirty = 0;
4019
4020 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4021
4022 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4023 vmx->launched = 1;
4024
4025 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4026 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4027
4028 vmx_complete_atomic_exit(vmx);
4029 vmx_recover_nmi_blocking(vmx);
4030 vmx_complete_interrupts(vmx);
4031 }
4032
4033 #undef R
4034 #undef Q
4035
4036 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4037 {
4038 struct vcpu_vmx *vmx = to_vmx(vcpu);
4039
4040 if (vmx->vmcs) {
4041 vcpu_clear(vmx);
4042 free_vmcs(vmx->vmcs);
4043 vmx->vmcs = NULL;
4044 }
4045 }
4046
4047 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4048 {
4049 struct vcpu_vmx *vmx = to_vmx(vcpu);
4050
4051 free_vpid(vmx);
4052 vmx_free_vmcs(vcpu);
4053 kfree(vmx->guest_msrs);
4054 kvm_vcpu_uninit(vcpu);
4055 kmem_cache_free(kvm_vcpu_cache, vmx);
4056 }
4057
4058 static inline void vmcs_init(struct vmcs *vmcs)
4059 {
4060 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4061
4062 if (!vmm_exclusive)
4063 kvm_cpu_vmxon(phys_addr);
4064
4065 vmcs_clear(vmcs);
4066
4067 if (!vmm_exclusive)
4068 kvm_cpu_vmxoff();
4069 }
4070
4071 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4072 {
4073 int err;
4074 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4075 int cpu;
4076
4077 if (!vmx)
4078 return ERR_PTR(-ENOMEM);
4079
4080 allocate_vpid(vmx);
4081
4082 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4083 if (err)
4084 goto free_vcpu;
4085
4086 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4087 if (!vmx->guest_msrs) {
4088 err = -ENOMEM;
4089 goto uninit_vcpu;
4090 }
4091
4092 vmx->vmcs = alloc_vmcs();
4093 if (!vmx->vmcs)
4094 goto free_msrs;
4095
4096 vmcs_init(vmx->vmcs);
4097
4098 cpu = get_cpu();
4099 vmx_vcpu_load(&vmx->vcpu, cpu);
4100 vmx->vcpu.cpu = cpu;
4101 err = vmx_vcpu_setup(vmx);
4102 vmx_vcpu_put(&vmx->vcpu);
4103 put_cpu();
4104 if (err)
4105 goto free_vmcs;
4106 if (vm_need_virtualize_apic_accesses(kvm))
4107 if (alloc_apic_access_page(kvm) != 0)
4108 goto free_vmcs;
4109
4110 if (enable_ept) {
4111 if (!kvm->arch.ept_identity_map_addr)
4112 kvm->arch.ept_identity_map_addr =
4113 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4114 if (alloc_identity_pagetable(kvm) != 0)
4115 goto free_vmcs;
4116 }
4117
4118 return &vmx->vcpu;
4119
4120 free_vmcs:
4121 free_vmcs(vmx->vmcs);
4122 free_msrs:
4123 kfree(vmx->guest_msrs);
4124 uninit_vcpu:
4125 kvm_vcpu_uninit(&vmx->vcpu);
4126 free_vcpu:
4127 free_vpid(vmx);
4128 kmem_cache_free(kvm_vcpu_cache, vmx);
4129 return ERR_PTR(err);
4130 }
4131
4132 static void __init vmx_check_processor_compat(void *rtn)
4133 {
4134 struct vmcs_config vmcs_conf;
4135
4136 *(int *)rtn = 0;
4137 if (setup_vmcs_config(&vmcs_conf) < 0)
4138 *(int *)rtn = -EIO;
4139 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4140 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4141 smp_processor_id());
4142 *(int *)rtn = -EIO;
4143 }
4144 }
4145
4146 static int get_ept_level(void)
4147 {
4148 return VMX_EPT_DEFAULT_GAW + 1;
4149 }
4150
4151 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4152 {
4153 u64 ret;
4154
4155 /* For VT-d and EPT combination
4156 * 1. MMIO: always map as UC
4157 * 2. EPT with VT-d:
4158 * a. VT-d without snooping control feature: can't guarantee the
4159 * result, try to trust guest.
4160 * b. VT-d with snooping control feature: snooping control feature of
4161 * VT-d engine can guarantee the cache correctness. Just set it
4162 * to WB to keep consistent with host. So the same as item 3.
4163 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4164 * consistent with host MTRR
4165 */
4166 if (is_mmio)
4167 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4168 else if (vcpu->kvm->arch.iommu_domain &&
4169 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4170 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4171 VMX_EPT_MT_EPTE_SHIFT;
4172 else
4173 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4174 | VMX_EPT_IPAT_BIT;
4175
4176 return ret;
4177 }
4178
4179 #define _ER(x) { EXIT_REASON_##x, #x }
4180
4181 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4182 _ER(EXCEPTION_NMI),
4183 _ER(EXTERNAL_INTERRUPT),
4184 _ER(TRIPLE_FAULT),
4185 _ER(PENDING_INTERRUPT),
4186 _ER(NMI_WINDOW),
4187 _ER(TASK_SWITCH),
4188 _ER(CPUID),
4189 _ER(HLT),
4190 _ER(INVLPG),
4191 _ER(RDPMC),
4192 _ER(RDTSC),
4193 _ER(VMCALL),
4194 _ER(VMCLEAR),
4195 _ER(VMLAUNCH),
4196 _ER(VMPTRLD),
4197 _ER(VMPTRST),
4198 _ER(VMREAD),
4199 _ER(VMRESUME),
4200 _ER(VMWRITE),
4201 _ER(VMOFF),
4202 _ER(VMON),
4203 _ER(CR_ACCESS),
4204 _ER(DR_ACCESS),
4205 _ER(IO_INSTRUCTION),
4206 _ER(MSR_READ),
4207 _ER(MSR_WRITE),
4208 _ER(MWAIT_INSTRUCTION),
4209 _ER(MONITOR_INSTRUCTION),
4210 _ER(PAUSE_INSTRUCTION),
4211 _ER(MCE_DURING_VMENTRY),
4212 _ER(TPR_BELOW_THRESHOLD),
4213 _ER(APIC_ACCESS),
4214 _ER(EPT_VIOLATION),
4215 _ER(EPT_MISCONFIG),
4216 _ER(WBINVD),
4217 { -1, NULL }
4218 };
4219
4220 #undef _ER
4221
4222 static int vmx_get_lpage_level(void)
4223 {
4224 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4225 return PT_DIRECTORY_LEVEL;
4226 else
4227 /* For shadow and EPT supported 1GB page */
4228 return PT_PDPE_LEVEL;
4229 }
4230
4231 static inline u32 bit(int bitno)
4232 {
4233 return 1 << (bitno & 31);
4234 }
4235
4236 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4237 {
4238 struct kvm_cpuid_entry2 *best;
4239 struct vcpu_vmx *vmx = to_vmx(vcpu);
4240 u32 exec_control;
4241
4242 vmx->rdtscp_enabled = false;
4243 if (vmx_rdtscp_supported()) {
4244 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4245 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4246 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4247 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4248 vmx->rdtscp_enabled = true;
4249 else {
4250 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4251 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4252 exec_control);
4253 }
4254 }
4255 }
4256 }
4257
4258 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4259 {
4260 }
4261
4262 static struct kvm_x86_ops vmx_x86_ops = {
4263 .cpu_has_kvm_support = cpu_has_kvm_support,
4264 .disabled_by_bios = vmx_disabled_by_bios,
4265 .hardware_setup = hardware_setup,
4266 .hardware_unsetup = hardware_unsetup,
4267 .check_processor_compatibility = vmx_check_processor_compat,
4268 .hardware_enable = hardware_enable,
4269 .hardware_disable = hardware_disable,
4270 .cpu_has_accelerated_tpr = report_flexpriority,
4271
4272 .vcpu_create = vmx_create_vcpu,
4273 .vcpu_free = vmx_free_vcpu,
4274 .vcpu_reset = vmx_vcpu_reset,
4275
4276 .prepare_guest_switch = vmx_save_host_state,
4277 .vcpu_load = vmx_vcpu_load,
4278 .vcpu_put = vmx_vcpu_put,
4279
4280 .set_guest_debug = set_guest_debug,
4281 .get_msr = vmx_get_msr,
4282 .set_msr = vmx_set_msr,
4283 .get_segment_base = vmx_get_segment_base,
4284 .get_segment = vmx_get_segment,
4285 .set_segment = vmx_set_segment,
4286 .get_cpl = vmx_get_cpl,
4287 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4288 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4289 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4290 .set_cr0 = vmx_set_cr0,
4291 .set_cr3 = vmx_set_cr3,
4292 .set_cr4 = vmx_set_cr4,
4293 .set_efer = vmx_set_efer,
4294 .get_idt = vmx_get_idt,
4295 .set_idt = vmx_set_idt,
4296 .get_gdt = vmx_get_gdt,
4297 .set_gdt = vmx_set_gdt,
4298 .set_dr7 = vmx_set_dr7,
4299 .cache_reg = vmx_cache_reg,
4300 .get_rflags = vmx_get_rflags,
4301 .set_rflags = vmx_set_rflags,
4302 .fpu_activate = vmx_fpu_activate,
4303 .fpu_deactivate = vmx_fpu_deactivate,
4304
4305 .tlb_flush = vmx_flush_tlb,
4306
4307 .run = vmx_vcpu_run,
4308 .handle_exit = vmx_handle_exit,
4309 .skip_emulated_instruction = skip_emulated_instruction,
4310 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4311 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4312 .patch_hypercall = vmx_patch_hypercall,
4313 .set_irq = vmx_inject_irq,
4314 .set_nmi = vmx_inject_nmi,
4315 .queue_exception = vmx_queue_exception,
4316 .cancel_injection = vmx_cancel_injection,
4317 .interrupt_allowed = vmx_interrupt_allowed,
4318 .nmi_allowed = vmx_nmi_allowed,
4319 .get_nmi_mask = vmx_get_nmi_mask,
4320 .set_nmi_mask = vmx_set_nmi_mask,
4321 .enable_nmi_window = enable_nmi_window,
4322 .enable_irq_window = enable_irq_window,
4323 .update_cr8_intercept = update_cr8_intercept,
4324
4325 .set_tss_addr = vmx_set_tss_addr,
4326 .get_tdp_level = get_ept_level,
4327 .get_mt_mask = vmx_get_mt_mask,
4328
4329 .exit_reasons_str = vmx_exit_reasons_str,
4330 .get_lpage_level = vmx_get_lpage_level,
4331
4332 .cpuid_update = vmx_cpuid_update,
4333
4334 .rdtscp_supported = vmx_rdtscp_supported,
4335
4336 .set_supported_cpuid = vmx_set_supported_cpuid,
4337
4338 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4339
4340 .write_tsc_offset = vmx_write_tsc_offset,
4341 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4342
4343 .set_tdp_cr3 = vmx_set_cr3,
4344 };
4345
4346 static int __init vmx_init(void)
4347 {
4348 int r, i;
4349
4350 rdmsrl_safe(MSR_EFER, &host_efer);
4351
4352 for (i = 0; i < NR_VMX_MSR; ++i)
4353 kvm_define_shared_msr(i, vmx_msr_index[i]);
4354
4355 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4356 if (!vmx_io_bitmap_a)
4357 return -ENOMEM;
4358
4359 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4360 if (!vmx_io_bitmap_b) {
4361 r = -ENOMEM;
4362 goto out;
4363 }
4364
4365 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4366 if (!vmx_msr_bitmap_legacy) {
4367 r = -ENOMEM;
4368 goto out1;
4369 }
4370
4371 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4372 if (!vmx_msr_bitmap_longmode) {
4373 r = -ENOMEM;
4374 goto out2;
4375 }
4376
4377 /*
4378 * Allow direct access to the PC debug port (it is often used for I/O
4379 * delays, but the vmexits simply slow things down).
4380 */
4381 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4382 clear_bit(0x80, vmx_io_bitmap_a);
4383
4384 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4385
4386 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4387 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4388
4389 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4390
4391 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4392 __alignof__(struct vcpu_vmx), THIS_MODULE);
4393 if (r)
4394 goto out3;
4395
4396 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4397 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4398 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4399 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4400 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4401 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4402
4403 if (enable_ept) {
4404 bypass_guest_pf = 0;
4405 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4406 VMX_EPT_WRITABLE_MASK);
4407 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4408 VMX_EPT_EXECUTABLE_MASK);
4409 kvm_enable_tdp();
4410 } else
4411 kvm_disable_tdp();
4412
4413 if (bypass_guest_pf)
4414 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4415
4416 return 0;
4417
4418 out3:
4419 free_page((unsigned long)vmx_msr_bitmap_longmode);
4420 out2:
4421 free_page((unsigned long)vmx_msr_bitmap_legacy);
4422 out1:
4423 free_page((unsigned long)vmx_io_bitmap_b);
4424 out:
4425 free_page((unsigned long)vmx_io_bitmap_a);
4426 return r;
4427 }
4428
4429 static void __exit vmx_exit(void)
4430 {
4431 free_page((unsigned long)vmx_msr_bitmap_legacy);
4432 free_page((unsigned long)vmx_msr_bitmap_longmode);
4433 free_page((unsigned long)vmx_io_bitmap_b);
4434 free_page((unsigned long)vmx_io_bitmap_a);
4435
4436 kvm_exit();
4437 }
4438
4439 module_init(vmx_init)
4440 module_exit(vmx_exit)
Linux kernel - Deliverables
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