2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf
= 1;
51 module_param(bypass_guest_pf
, bool, S_IRUGO
);
53 static int __read_mostly enable_vpid
= 1;
54 module_param_named(vpid
, enable_vpid
, bool, 0444);
56 static int __read_mostly flexpriority_enabled
= 1;
57 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
59 static int __read_mostly enable_ept
= 1;
60 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
62 static int __read_mostly enable_unrestricted_guest
= 1;
63 module_param_named(unrestricted_guest
,
64 enable_unrestricted_guest
, bool, S_IRUGO
);
66 static int __read_mostly emulate_invalid_guest_state
= 0;
67 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
69 static int __read_mostly vmm_exclusive
= 1;
70 module_param(vmm_exclusive
, bool, S_IRUGO
);
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
103 module_param(ple_gap
, int, S_IRUGO
);
105 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
106 module_param(ple_window
, int, S_IRUGO
);
108 #define NR_AUTOLOAD_MSRS 1
116 struct shared_msr_entry
{
123 struct kvm_vcpu vcpu
;
124 struct list_head local_vcpus_link
;
125 unsigned long host_rsp
;
128 u32 idt_vectoring_info
;
129 struct shared_msr_entry
*guest_msrs
;
133 u64 msr_host_kernel_gs_base
;
134 u64 msr_guest_kernel_gs_base
;
137 struct msr_autoload
{
139 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
140 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
144 u16 fs_sel
, gs_sel
, ldt_sel
;
145 int gs_ldt_reload_needed
;
146 int fs_reload_needed
;
151 struct kvm_save_segment
{
156 } tr
, es
, ds
, fs
, gs
;
164 bool emulation_required
;
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked
;
169 s64 vnmi_blocked_time
;
175 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
177 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
180 static int init_rmode(struct kvm
*kvm
);
181 static u64
construct_eptp(unsigned long root_hpa
);
182 static void kvm_cpu_vmxon(u64 addr
);
183 static void kvm_cpu_vmxoff(void);
185 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
186 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
187 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
188 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
190 static unsigned long *vmx_io_bitmap_a
;
191 static unsigned long *vmx_io_bitmap_b
;
192 static unsigned long *vmx_msr_bitmap_legacy
;
193 static unsigned long *vmx_msr_bitmap_longmode
;
195 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
196 static DEFINE_SPINLOCK(vmx_vpid_lock
);
198 static struct vmcs_config
{
202 u32 pin_based_exec_ctrl
;
203 u32 cpu_based_exec_ctrl
;
204 u32 cpu_based_2nd_exec_ctrl
;
209 static struct vmx_capability
{
214 #define VMX_SEGMENT_FIELD(seg) \
215 [VCPU_SREG_##seg] = { \
216 .selector = GUEST_##seg##_SELECTOR, \
217 .base = GUEST_##seg##_BASE, \
218 .limit = GUEST_##seg##_LIMIT, \
219 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 static struct kvm_vmx_segment_field
{
227 } kvm_vmx_segment_fields
[] = {
228 VMX_SEGMENT_FIELD(CS
),
229 VMX_SEGMENT_FIELD(DS
),
230 VMX_SEGMENT_FIELD(ES
),
231 VMX_SEGMENT_FIELD(FS
),
232 VMX_SEGMENT_FIELD(GS
),
233 VMX_SEGMENT_FIELD(SS
),
234 VMX_SEGMENT_FIELD(TR
),
235 VMX_SEGMENT_FIELD(LDTR
),
238 static u64 host_efer
;
240 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
243 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
244 * away by decrementing the array size.
246 static const u32 vmx_msr_index
[] = {
248 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
250 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
254 static inline bool is_page_fault(u32 intr_info
)
256 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
257 INTR_INFO_VALID_MASK
)) ==
258 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
261 static inline bool is_no_device(u32 intr_info
)
263 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
264 INTR_INFO_VALID_MASK
)) ==
265 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
268 static inline bool is_invalid_opcode(u32 intr_info
)
270 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
271 INTR_INFO_VALID_MASK
)) ==
272 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
275 static inline bool is_external_interrupt(u32 intr_info
)
277 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
278 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
281 static inline bool is_machine_check(u32 intr_info
)
283 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
284 INTR_INFO_VALID_MASK
)) ==
285 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
288 static inline bool cpu_has_vmx_msr_bitmap(void)
290 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
293 static inline bool cpu_has_vmx_tpr_shadow(void)
295 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
298 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
300 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
303 static inline bool cpu_has_secondary_exec_ctrls(void)
305 return vmcs_config
.cpu_based_exec_ctrl
&
306 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
311 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
312 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
315 static inline bool cpu_has_vmx_flexpriority(void)
317 return cpu_has_vmx_tpr_shadow() &&
318 cpu_has_vmx_virtualize_apic_accesses();
321 static inline bool cpu_has_vmx_ept_execute_only(void)
323 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
328 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
331 static inline bool cpu_has_vmx_eptp_writeback(void)
333 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
336 static inline bool cpu_has_vmx_ept_2m_page(void)
338 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
341 static inline bool cpu_has_vmx_ept_1g_page(void)
343 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
346 static inline bool cpu_has_vmx_ept_4levels(void)
348 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
351 static inline bool cpu_has_vmx_invept_individual_addr(void)
353 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
356 static inline bool cpu_has_vmx_invept_context(void)
358 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
361 static inline bool cpu_has_vmx_invept_global(void)
363 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
366 static inline bool cpu_has_vmx_invvpid_single(void)
368 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
371 static inline bool cpu_has_vmx_invvpid_global(void)
373 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
376 static inline bool cpu_has_vmx_ept(void)
378 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
379 SECONDARY_EXEC_ENABLE_EPT
;
382 static inline bool cpu_has_vmx_unrestricted_guest(void)
384 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
385 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
388 static inline bool cpu_has_vmx_ple(void)
390 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
391 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
394 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
396 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
399 static inline bool cpu_has_vmx_vpid(void)
401 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
402 SECONDARY_EXEC_ENABLE_VPID
;
405 static inline bool cpu_has_vmx_rdtscp(void)
407 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
408 SECONDARY_EXEC_RDTSCP
;
411 static inline bool cpu_has_virtual_nmis(void)
413 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
416 static inline bool cpu_has_vmx_wbinvd_exit(void)
418 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
419 SECONDARY_EXEC_WBINVD_EXITING
;
422 static inline bool report_flexpriority(void)
424 return flexpriority_enabled
;
427 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
431 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
432 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
437 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
443 } operand
= { vpid
, 0, gva
};
445 asm volatile (__ex(ASM_VMX_INVVPID
)
446 /* CF==1 or ZF==1 --> rc = -1 */
448 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
451 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
455 } operand
= {eptp
, gpa
};
457 asm volatile (__ex(ASM_VMX_INVEPT
)
458 /* CF==1 or ZF==1 --> rc = -1 */
459 "; ja 1f ; ud2 ; 1:\n"
460 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
463 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
467 i
= __find_msr_index(vmx
, msr
);
469 return &vmx
->guest_msrs
[i
];
473 static void vmcs_clear(struct vmcs
*vmcs
)
475 u64 phys_addr
= __pa(vmcs
);
478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
479 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
482 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
486 static void vmcs_load(struct vmcs
*vmcs
)
488 u64 phys_addr
= __pa(vmcs
);
491 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
492 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
495 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
499 static void __vcpu_clear(void *arg
)
501 struct vcpu_vmx
*vmx
= arg
;
502 int cpu
= raw_smp_processor_id();
504 if (vmx
->vcpu
.cpu
== cpu
)
505 vmcs_clear(vmx
->vmcs
);
506 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
507 per_cpu(current_vmcs
, cpu
) = NULL
;
508 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
509 list_del(&vmx
->local_vcpus_link
);
514 static void vcpu_clear(struct vcpu_vmx
*vmx
)
516 if (vmx
->vcpu
.cpu
== -1)
518 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
530 static inline void vpid_sync_vcpu_global(void)
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
536 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx
);
541 vpid_sync_vcpu_global();
544 static inline void ept_sync_global(void)
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
550 static inline void ept_sync_context(u64 eptp
)
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
560 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
567 ept_sync_context(eptp
);
571 static unsigned long vmcs_readl(unsigned long field
)
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
576 : "=a"(value
) : "d"(field
) : "cc");
580 static u16
vmcs_read16(unsigned long field
)
582 return vmcs_readl(field
);
585 static u32
vmcs_read32(unsigned long field
)
587 return vmcs_readl(field
);
590 static u64
vmcs_read64(unsigned long field
)
593 return vmcs_readl(field
);
595 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
599 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
601 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
602 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
606 static void vmcs_writel(unsigned long field
, unsigned long value
)
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
611 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
613 vmwrite_error(field
, value
);
616 static void vmcs_write16(unsigned long field
, u16 value
)
618 vmcs_writel(field
, value
);
621 static void vmcs_write32(unsigned long field
, u32 value
)
623 vmcs_writel(field
, value
);
626 static void vmcs_write64(unsigned long field
, u64 value
)
628 vmcs_writel(field
, value
);
629 #ifndef CONFIG_X86_64
631 vmcs_writel(field
+1, value
>> 32);
635 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
637 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
640 static void vmcs_set_bits(unsigned long field
, u32 mask
)
642 vmcs_writel(field
, vmcs_readl(field
) | mask
);
645 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
649 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
650 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
651 if ((vcpu
->guest_debug
&
652 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
653 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
654 eb
|= 1u << BP_VECTOR
;
655 if (to_vmx(vcpu
)->rmode
.vm86_active
)
658 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
659 if (vcpu
->fpu_active
)
660 eb
&= ~(1u << NM_VECTOR
);
661 vmcs_write32(EXCEPTION_BITMAP
, eb
);
664 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
667 struct msr_autoload
*m
= &vmx
->msr_autoload
;
669 for (i
= 0; i
< m
->nr
; ++i
)
670 if (m
->guest
[i
].index
== msr
)
676 m
->guest
[i
] = m
->guest
[m
->nr
];
677 m
->host
[i
] = m
->host
[m
->nr
];
678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
679 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
682 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
683 u64 guest_val
, u64 host_val
)
686 struct msr_autoload
*m
= &vmx
->msr_autoload
;
688 for (i
= 0; i
< m
->nr
; ++i
)
689 if (m
->guest
[i
].index
== msr
)
694 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
695 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
698 m
->guest
[i
].index
= msr
;
699 m
->guest
[i
].value
= guest_val
;
700 m
->host
[i
].index
= msr
;
701 m
->host
[i
].value
= host_val
;
704 static void reload_tss(void)
707 * VT restores TR but not its size. Useless.
710 struct desc_struct
*descs
;
712 native_store_gdt(&gdt
);
713 descs
= (void *)gdt
.address
;
714 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
718 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
723 guest_efer
= vmx
->vcpu
.arch
.efer
;
726 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
729 ignore_bits
= EFER_NX
| EFER_SCE
;
731 ignore_bits
|= EFER_LMA
| EFER_LME
;
732 /* SCE is meaningful only in long mode on Intel */
733 if (guest_efer
& EFER_LMA
)
734 ignore_bits
&= ~(u64
)EFER_SCE
;
736 guest_efer
&= ~ignore_bits
;
737 guest_efer
|= host_efer
& ignore_bits
;
738 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
739 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
741 clear_atomic_switch_msr(vmx
, MSR_EFER
);
742 /* On ept, can't emulate nx, and must switch nx atomically */
743 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
744 guest_efer
= vmx
->vcpu
.arch
.efer
;
745 if (!(guest_efer
& EFER_LMA
))
746 guest_efer
&= ~EFER_LME
;
747 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
754 static unsigned long segment_base(u16 selector
)
757 struct desc_struct
*d
;
758 unsigned long table_base
;
761 if (!(selector
& ~3))
764 native_store_gdt(&gdt
);
765 table_base
= gdt
.address
;
767 if (selector
& 4) { /* from ldt */
768 u16 ldt_selector
= kvm_read_ldt();
770 if (!(ldt_selector
& ~3))
773 table_base
= segment_base(ldt_selector
);
775 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
776 v
= get_desc_base(d
);
778 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
779 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
784 static inline unsigned long kvm_read_tr_base(void)
787 asm("str %0" : "=g"(tr
));
788 return segment_base(tr
);
791 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
793 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
796 if (vmx
->host_state
.loaded
)
799 vmx
->host_state
.loaded
= 1;
801 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
802 * allow segment selectors with cpl > 0 or ti == 1.
804 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
805 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
806 savesegment(fs
, vmx
->host_state
.fs_sel
);
807 if (!(vmx
->host_state
.fs_sel
& 7)) {
808 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
809 vmx
->host_state
.fs_reload_needed
= 0;
811 vmcs_write16(HOST_FS_SELECTOR
, 0);
812 vmx
->host_state
.fs_reload_needed
= 1;
814 savesegment(gs
, vmx
->host_state
.gs_sel
);
815 if (!(vmx
->host_state
.gs_sel
& 7))
816 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
818 vmcs_write16(HOST_GS_SELECTOR
, 0);
819 vmx
->host_state
.gs_ldt_reload_needed
= 1;
823 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
824 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
826 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
827 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
831 if (is_long_mode(&vmx
->vcpu
)) {
832 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
833 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
836 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
837 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
838 vmx
->guest_msrs
[i
].data
,
839 vmx
->guest_msrs
[i
].mask
);
842 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
844 if (!vmx
->host_state
.loaded
)
847 ++vmx
->vcpu
.stat
.host_state_reload
;
848 vmx
->host_state
.loaded
= 0;
849 if (vmx
->host_state
.fs_reload_needed
)
850 loadsegment(fs
, vmx
->host_state
.fs_sel
);
851 if (vmx
->host_state
.gs_ldt_reload_needed
) {
852 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
854 load_gs_index(vmx
->host_state
.gs_sel
);
855 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
857 loadsegment(gs
, vmx
->host_state
.gs_sel
);
862 if (is_long_mode(&vmx
->vcpu
)) {
863 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
864 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
867 if (current_thread_info()->status
& TS_USEDFPU
)
869 load_gdt(&__get_cpu_var(host_gdt
));
872 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
875 __vmx_load_host_state(vmx
);
880 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
881 * vcpu mutex is already taken.
883 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
886 u64 tsc_this
, delta
, new_offset
;
887 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
890 kvm_cpu_vmxon(phys_addr
);
891 else if (vcpu
->cpu
!= cpu
)
894 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
895 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
896 vmcs_load(vmx
->vmcs
);
899 if (vcpu
->cpu
!= cpu
) {
901 unsigned long sysenter_esp
;
903 kvm_migrate_timers(vcpu
);
904 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
906 list_add(&vmx
->local_vcpus_link
,
907 &per_cpu(vcpus_on_cpu
, cpu
));
912 * Linux uses per-cpu TSS and GDT, so set these when switching
915 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
916 native_store_gdt(&dt
);
917 vmcs_writel(HOST_GDTR_BASE
, dt
.address
); /* 22.2.4 */
919 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
920 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
923 * Make sure the time stamp counter is monotonous.
926 if (tsc_this
< vcpu
->arch
.host_tsc
) {
927 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
928 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
929 vmcs_write64(TSC_OFFSET
, new_offset
);
934 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
936 __vmx_load_host_state(to_vmx(vcpu
));
937 if (!vmm_exclusive
) {
938 __vcpu_clear(to_vmx(vcpu
));
943 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
947 if (vcpu
->fpu_active
)
949 vcpu
->fpu_active
= 1;
950 cr0
= vmcs_readl(GUEST_CR0
);
951 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
952 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
953 vmcs_writel(GUEST_CR0
, cr0
);
954 update_exception_bitmap(vcpu
);
955 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
956 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
959 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
961 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
963 vmx_decache_cr0_guest_bits(vcpu
);
964 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
965 update_exception_bitmap(vcpu
);
966 vcpu
->arch
.cr0_guest_owned_bits
= 0;
967 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
968 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
971 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
973 unsigned long rflags
, save_rflags
;
975 rflags
= vmcs_readl(GUEST_RFLAGS
);
976 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
977 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
978 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
979 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
984 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
986 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
987 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
988 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
990 vmcs_writel(GUEST_RFLAGS
, rflags
);
993 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
995 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
998 if (interruptibility
& GUEST_INTR_STATE_STI
)
999 ret
|= KVM_X86_SHADOW_INT_STI
;
1000 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1001 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1006 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1008 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1009 u32 interruptibility
= interruptibility_old
;
1011 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1013 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1014 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1015 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1016 interruptibility
|= GUEST_INTR_STATE_STI
;
1018 if ((interruptibility
!= interruptibility_old
))
1019 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1022 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1026 rip
= kvm_rip_read(vcpu
);
1027 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1028 kvm_rip_write(vcpu
, rip
);
1030 /* skipping an emulated instruction also counts */
1031 vmx_set_interrupt_shadow(vcpu
, 0);
1034 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1035 bool has_error_code
, u32 error_code
,
1038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1039 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1041 if (has_error_code
) {
1042 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1043 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1046 if (vmx
->rmode
.vm86_active
) {
1047 vmx
->rmode
.irq
.pending
= true;
1048 vmx
->rmode
.irq
.vector
= nr
;
1049 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
1050 if (kvm_exception_is_soft(nr
))
1051 vmx
->rmode
.irq
.rip
+=
1052 vmx
->vcpu
.arch
.event_exit_inst_len
;
1053 intr_info
|= INTR_TYPE_SOFT_INTR
;
1054 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1055 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
1056 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
1060 if (kvm_exception_is_soft(nr
)) {
1061 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1062 vmx
->vcpu
.arch
.event_exit_inst_len
);
1063 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1065 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1067 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1070 static bool vmx_rdtscp_supported(void)
1072 return cpu_has_vmx_rdtscp();
1076 * Swap MSR entry in host/guest MSR entry array.
1078 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1080 struct shared_msr_entry tmp
;
1082 tmp
= vmx
->guest_msrs
[to
];
1083 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1084 vmx
->guest_msrs
[from
] = tmp
;
1088 * Set up the vmcs to automatically save and restore system
1089 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1090 * mode, as fiddling with msrs is very expensive.
1092 static void setup_msrs(struct vcpu_vmx
*vmx
)
1094 int save_nmsrs
, index
;
1095 unsigned long *msr_bitmap
;
1097 vmx_load_host_state(vmx
);
1099 #ifdef CONFIG_X86_64
1100 if (is_long_mode(&vmx
->vcpu
)) {
1101 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1103 move_msr_up(vmx
, index
, save_nmsrs
++);
1104 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1106 move_msr_up(vmx
, index
, save_nmsrs
++);
1107 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1109 move_msr_up(vmx
, index
, save_nmsrs
++);
1110 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1111 if (index
>= 0 && vmx
->rdtscp_enabled
)
1112 move_msr_up(vmx
, index
, save_nmsrs
++);
1114 * MSR_STAR is only needed on long mode guests, and only
1115 * if efer.sce is enabled.
1117 index
= __find_msr_index(vmx
, MSR_STAR
);
1118 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1119 move_msr_up(vmx
, index
, save_nmsrs
++);
1122 index
= __find_msr_index(vmx
, MSR_EFER
);
1123 if (index
>= 0 && update_transition_efer(vmx
, index
))
1124 move_msr_up(vmx
, index
, save_nmsrs
++);
1126 vmx
->save_nmsrs
= save_nmsrs
;
1128 if (cpu_has_vmx_msr_bitmap()) {
1129 if (is_long_mode(&vmx
->vcpu
))
1130 msr_bitmap
= vmx_msr_bitmap_longmode
;
1132 msr_bitmap
= vmx_msr_bitmap_legacy
;
1134 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1139 * reads and returns guest's timestamp counter "register"
1140 * guest_tsc = host_tsc + tsc_offset -- 21.3
1142 static u64
guest_read_tsc(void)
1144 u64 host_tsc
, tsc_offset
;
1147 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1148 return host_tsc
+ tsc_offset
;
1152 * writes 'guest_tsc' into guest's timestamp counter "register"
1153 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1155 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
1157 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
1161 * Reads an msr value (of 'msr_index') into 'pdata'.
1162 * Returns 0 on success, non-0 otherwise.
1163 * Assumes vcpu_load() was already called.
1165 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1168 struct shared_msr_entry
*msr
;
1171 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1175 switch (msr_index
) {
1176 #ifdef CONFIG_X86_64
1178 data
= vmcs_readl(GUEST_FS_BASE
);
1181 data
= vmcs_readl(GUEST_GS_BASE
);
1183 case MSR_KERNEL_GS_BASE
:
1184 vmx_load_host_state(to_vmx(vcpu
));
1185 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1189 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1191 data
= guest_read_tsc();
1193 case MSR_IA32_SYSENTER_CS
:
1194 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1196 case MSR_IA32_SYSENTER_EIP
:
1197 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1199 case MSR_IA32_SYSENTER_ESP
:
1200 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1203 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1205 /* Otherwise falls through */
1207 vmx_load_host_state(to_vmx(vcpu
));
1208 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1210 vmx_load_host_state(to_vmx(vcpu
));
1214 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1222 * Writes msr value into into the appropriate "register".
1223 * Returns 0 on success, non-0 otherwise.
1224 * Assumes vcpu_load() was already called.
1226 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1228 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1229 struct shared_msr_entry
*msr
;
1233 switch (msr_index
) {
1235 vmx_load_host_state(vmx
);
1236 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1238 #ifdef CONFIG_X86_64
1240 vmcs_writel(GUEST_FS_BASE
, data
);
1243 vmcs_writel(GUEST_GS_BASE
, data
);
1245 case MSR_KERNEL_GS_BASE
:
1246 vmx_load_host_state(vmx
);
1247 vmx
->msr_guest_kernel_gs_base
= data
;
1250 case MSR_IA32_SYSENTER_CS
:
1251 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1253 case MSR_IA32_SYSENTER_EIP
:
1254 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1256 case MSR_IA32_SYSENTER_ESP
:
1257 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1261 guest_write_tsc(data
, host_tsc
);
1263 case MSR_IA32_CR_PAT
:
1264 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1265 vmcs_write64(GUEST_IA32_PAT
, data
);
1266 vcpu
->arch
.pat
= data
;
1269 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1272 if (!vmx
->rdtscp_enabled
)
1274 /* Check reserved bit, higher 32 bits should be zero */
1275 if ((data
>> 32) != 0)
1277 /* Otherwise falls through */
1279 msr
= find_msr_entry(vmx
, msr_index
);
1281 vmx_load_host_state(vmx
);
1285 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1291 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1293 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1296 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1299 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1301 case VCPU_EXREG_PDPTR
:
1303 ept_save_pdptrs(vcpu
);
1310 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1312 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1313 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1315 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1317 update_exception_bitmap(vcpu
);
1320 static __init
int cpu_has_kvm_support(void)
1322 return cpu_has_vmx();
1325 static __init
int vmx_disabled_by_bios(void)
1329 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1330 if (msr
& FEATURE_CONTROL_LOCKED
) {
1331 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1334 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1335 && !tboot_enabled())
1340 /* locked but not enabled */
1343 static void kvm_cpu_vmxon(u64 addr
)
1345 asm volatile (ASM_VMX_VMXON_RAX
1346 : : "a"(&addr
), "m"(addr
)
1350 static int hardware_enable(void *garbage
)
1352 int cpu
= raw_smp_processor_id();
1353 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1356 if (read_cr4() & X86_CR4_VMXE
)
1359 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1360 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1362 test_bits
= FEATURE_CONTROL_LOCKED
;
1363 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1364 if (tboot_enabled())
1365 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
1367 if ((old
& test_bits
) != test_bits
) {
1368 /* enable and lock */
1369 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
1371 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1373 if (vmm_exclusive
) {
1374 kvm_cpu_vmxon(phys_addr
);
1378 store_gdt(&__get_cpu_var(host_gdt
));
1383 static void vmclear_local_vcpus(void)
1385 int cpu
= raw_smp_processor_id();
1386 struct vcpu_vmx
*vmx
, *n
;
1388 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1394 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1397 static void kvm_cpu_vmxoff(void)
1399 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1402 static void hardware_disable(void *garbage
)
1404 if (vmm_exclusive
) {
1405 vmclear_local_vcpus();
1408 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1411 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1412 u32 msr
, u32
*result
)
1414 u32 vmx_msr_low
, vmx_msr_high
;
1415 u32 ctl
= ctl_min
| ctl_opt
;
1417 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1419 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1420 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1422 /* Ensure minimum (required) set of control bits are supported. */
1430 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1432 u32 vmx_msr_low
, vmx_msr_high
;
1433 u32 min
, opt
, min2
, opt2
;
1434 u32 _pin_based_exec_control
= 0;
1435 u32 _cpu_based_exec_control
= 0;
1436 u32 _cpu_based_2nd_exec_control
= 0;
1437 u32 _vmexit_control
= 0;
1438 u32 _vmentry_control
= 0;
1440 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1441 opt
= PIN_BASED_VIRTUAL_NMIS
;
1442 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1443 &_pin_based_exec_control
) < 0)
1446 min
= CPU_BASED_HLT_EXITING
|
1447 #ifdef CONFIG_X86_64
1448 CPU_BASED_CR8_LOAD_EXITING
|
1449 CPU_BASED_CR8_STORE_EXITING
|
1451 CPU_BASED_CR3_LOAD_EXITING
|
1452 CPU_BASED_CR3_STORE_EXITING
|
1453 CPU_BASED_USE_IO_BITMAPS
|
1454 CPU_BASED_MOV_DR_EXITING
|
1455 CPU_BASED_USE_TSC_OFFSETING
|
1456 CPU_BASED_MWAIT_EXITING
|
1457 CPU_BASED_MONITOR_EXITING
|
1458 CPU_BASED_INVLPG_EXITING
;
1459 opt
= CPU_BASED_TPR_SHADOW
|
1460 CPU_BASED_USE_MSR_BITMAPS
|
1461 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1462 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1463 &_cpu_based_exec_control
) < 0)
1465 #ifdef CONFIG_X86_64
1466 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1467 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1468 ~CPU_BASED_CR8_STORE_EXITING
;
1470 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1472 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1473 SECONDARY_EXEC_WBINVD_EXITING
|
1474 SECONDARY_EXEC_ENABLE_VPID
|
1475 SECONDARY_EXEC_ENABLE_EPT
|
1476 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1477 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1478 SECONDARY_EXEC_RDTSCP
;
1479 if (adjust_vmx_controls(min2
, opt2
,
1480 MSR_IA32_VMX_PROCBASED_CTLS2
,
1481 &_cpu_based_2nd_exec_control
) < 0)
1484 #ifndef CONFIG_X86_64
1485 if (!(_cpu_based_2nd_exec_control
&
1486 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1487 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1489 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1490 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1492 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1493 CPU_BASED_CR3_STORE_EXITING
|
1494 CPU_BASED_INVLPG_EXITING
);
1495 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1496 vmx_capability
.ept
, vmx_capability
.vpid
);
1500 #ifdef CONFIG_X86_64
1501 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1503 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1504 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1505 &_vmexit_control
) < 0)
1509 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1510 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1511 &_vmentry_control
) < 0)
1514 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1516 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1517 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1520 #ifdef CONFIG_X86_64
1521 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1522 if (vmx_msr_high
& (1u<<16))
1526 /* Require Write-Back (WB) memory type for VMCS accesses. */
1527 if (((vmx_msr_high
>> 18) & 15) != 6)
1530 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1531 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1532 vmcs_conf
->revision_id
= vmx_msr_low
;
1534 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1535 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1536 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1537 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1538 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1543 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1545 int node
= cpu_to_node(cpu
);
1549 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1552 vmcs
= page_address(pages
);
1553 memset(vmcs
, 0, vmcs_config
.size
);
1554 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1558 static struct vmcs
*alloc_vmcs(void)
1560 return alloc_vmcs_cpu(raw_smp_processor_id());
1563 static void free_vmcs(struct vmcs
*vmcs
)
1565 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1568 static void free_kvm_area(void)
1572 for_each_possible_cpu(cpu
) {
1573 free_vmcs(per_cpu(vmxarea
, cpu
));
1574 per_cpu(vmxarea
, cpu
) = NULL
;
1578 static __init
int alloc_kvm_area(void)
1582 for_each_possible_cpu(cpu
) {
1585 vmcs
= alloc_vmcs_cpu(cpu
);
1591 per_cpu(vmxarea
, cpu
) = vmcs
;
1596 static __init
int hardware_setup(void)
1598 if (setup_vmcs_config(&vmcs_config
) < 0)
1601 if (boot_cpu_has(X86_FEATURE_NX
))
1602 kvm_enable_efer_bits(EFER_NX
);
1604 if (!cpu_has_vmx_vpid())
1607 if (!cpu_has_vmx_ept() ||
1608 !cpu_has_vmx_ept_4levels()) {
1610 enable_unrestricted_guest
= 0;
1613 if (!cpu_has_vmx_unrestricted_guest())
1614 enable_unrestricted_guest
= 0;
1616 if (!cpu_has_vmx_flexpriority())
1617 flexpriority_enabled
= 0;
1619 if (!cpu_has_vmx_tpr_shadow())
1620 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1622 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1623 kvm_disable_largepages();
1625 if (!cpu_has_vmx_ple())
1628 return alloc_kvm_area();
1631 static __exit
void hardware_unsetup(void)
1636 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1638 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1640 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1641 vmcs_write16(sf
->selector
, save
->selector
);
1642 vmcs_writel(sf
->base
, save
->base
);
1643 vmcs_write32(sf
->limit
, save
->limit
);
1644 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1646 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1648 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1652 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1654 unsigned long flags
;
1655 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1657 vmx
->emulation_required
= 1;
1658 vmx
->rmode
.vm86_active
= 0;
1660 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1661 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1662 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1664 flags
= vmcs_readl(GUEST_RFLAGS
);
1665 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1666 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1667 vmcs_writel(GUEST_RFLAGS
, flags
);
1669 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1670 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1672 update_exception_bitmap(vcpu
);
1674 if (emulate_invalid_guest_state
)
1677 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1678 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1679 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1680 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1682 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1683 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1685 vmcs_write16(GUEST_CS_SELECTOR
,
1686 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1687 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1690 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1692 if (!kvm
->arch
.tss_addr
) {
1693 struct kvm_memslots
*slots
;
1696 slots
= kvm_memslots(kvm
);
1697 base_gfn
= slots
->memslots
[0].base_gfn
+
1698 kvm
->memslots
->memslots
[0].npages
- 3;
1699 return base_gfn
<< PAGE_SHIFT
;
1701 return kvm
->arch
.tss_addr
;
1704 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1706 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1708 save
->selector
= vmcs_read16(sf
->selector
);
1709 save
->base
= vmcs_readl(sf
->base
);
1710 save
->limit
= vmcs_read32(sf
->limit
);
1711 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1712 vmcs_write16(sf
->selector
, save
->base
>> 4);
1713 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1714 vmcs_write32(sf
->limit
, 0xffff);
1715 vmcs_write32(sf
->ar_bytes
, 0xf3);
1718 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1720 unsigned long flags
;
1721 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1723 if (enable_unrestricted_guest
)
1726 vmx
->emulation_required
= 1;
1727 vmx
->rmode
.vm86_active
= 1;
1729 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1730 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1732 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1733 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1735 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1736 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1738 flags
= vmcs_readl(GUEST_RFLAGS
);
1739 vmx
->rmode
.save_rflags
= flags
;
1741 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1743 vmcs_writel(GUEST_RFLAGS
, flags
);
1744 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1745 update_exception_bitmap(vcpu
);
1747 if (emulate_invalid_guest_state
)
1748 goto continue_rmode
;
1750 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1751 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1752 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1754 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1755 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1756 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1757 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1758 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1760 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1761 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1762 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1763 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1766 kvm_mmu_reset_context(vcpu
);
1767 init_rmode(vcpu
->kvm
);
1770 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1773 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1779 * Force kernel_gs_base reloading before EFER changes, as control
1780 * of this msr depends on is_long_mode().
1782 vmx_load_host_state(to_vmx(vcpu
));
1783 vcpu
->arch
.efer
= efer
;
1784 if (efer
& EFER_LMA
) {
1785 vmcs_write32(VM_ENTRY_CONTROLS
,
1786 vmcs_read32(VM_ENTRY_CONTROLS
) |
1787 VM_ENTRY_IA32E_MODE
);
1790 vmcs_write32(VM_ENTRY_CONTROLS
,
1791 vmcs_read32(VM_ENTRY_CONTROLS
) &
1792 ~VM_ENTRY_IA32E_MODE
);
1794 msr
->data
= efer
& ~EFER_LME
;
1799 #ifdef CONFIG_X86_64
1801 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1805 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1806 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1807 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1809 vmcs_write32(GUEST_TR_AR_BYTES
,
1810 (guest_tr_ar
& ~AR_TYPE_MASK
)
1811 | AR_TYPE_BUSY_64_TSS
);
1813 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
1816 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1818 vmcs_write32(VM_ENTRY_CONTROLS
,
1819 vmcs_read32(VM_ENTRY_CONTROLS
)
1820 & ~VM_ENTRY_IA32E_MODE
);
1821 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
1826 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1828 vpid_sync_context(to_vmx(vcpu
));
1830 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
1832 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1836 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1838 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
1840 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
1841 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
1844 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1846 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1848 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1849 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1852 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1854 if (!test_bit(VCPU_EXREG_PDPTR
,
1855 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1858 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1859 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1860 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1861 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1862 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1866 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1868 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1869 vcpu
->arch
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1870 vcpu
->arch
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1871 vcpu
->arch
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1872 vcpu
->arch
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1875 __set_bit(VCPU_EXREG_PDPTR
,
1876 (unsigned long *)&vcpu
->arch
.regs_avail
);
1877 __set_bit(VCPU_EXREG_PDPTR
,
1878 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1881 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1883 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1885 struct kvm_vcpu
*vcpu
)
1887 if (!(cr0
& X86_CR0_PG
)) {
1888 /* From paging/starting to nonpaging */
1889 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1890 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1891 (CPU_BASED_CR3_LOAD_EXITING
|
1892 CPU_BASED_CR3_STORE_EXITING
));
1893 vcpu
->arch
.cr0
= cr0
;
1894 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1895 } else if (!is_paging(vcpu
)) {
1896 /* From nonpaging to paging */
1897 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1898 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1899 ~(CPU_BASED_CR3_LOAD_EXITING
|
1900 CPU_BASED_CR3_STORE_EXITING
));
1901 vcpu
->arch
.cr0
= cr0
;
1902 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1905 if (!(cr0
& X86_CR0_WP
))
1906 *hw_cr0
&= ~X86_CR0_WP
;
1909 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1911 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1912 unsigned long hw_cr0
;
1914 if (enable_unrestricted_guest
)
1915 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1916 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1918 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1920 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1923 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1926 #ifdef CONFIG_X86_64
1927 if (vcpu
->arch
.efer
& EFER_LME
) {
1928 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1930 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1936 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1938 if (!vcpu
->fpu_active
)
1939 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
1941 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1942 vmcs_writel(GUEST_CR0
, hw_cr0
);
1943 vcpu
->arch
.cr0
= cr0
;
1946 static u64
construct_eptp(unsigned long root_hpa
)
1950 /* TODO write the value reading from MSR */
1951 eptp
= VMX_EPT_DEFAULT_MT
|
1952 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1953 eptp
|= (root_hpa
& PAGE_MASK
);
1958 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1960 unsigned long guest_cr3
;
1965 eptp
= construct_eptp(cr3
);
1966 vmcs_write64(EPT_POINTER
, eptp
);
1967 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1968 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1969 ept_load_pdptrs(vcpu
);
1972 vmx_flush_tlb(vcpu
);
1973 vmcs_writel(GUEST_CR3
, guest_cr3
);
1976 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1978 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1979 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1981 vcpu
->arch
.cr4
= cr4
;
1983 if (!is_paging(vcpu
)) {
1984 hw_cr4
&= ~X86_CR4_PAE
;
1985 hw_cr4
|= X86_CR4_PSE
;
1986 } else if (!(cr4
& X86_CR4_PAE
)) {
1987 hw_cr4
&= ~X86_CR4_PAE
;
1991 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1992 vmcs_writel(GUEST_CR4
, hw_cr4
);
1995 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1997 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1999 return vmcs_readl(sf
->base
);
2002 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2003 struct kvm_segment
*var
, int seg
)
2005 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2008 var
->base
= vmcs_readl(sf
->base
);
2009 var
->limit
= vmcs_read32(sf
->limit
);
2010 var
->selector
= vmcs_read16(sf
->selector
);
2011 ar
= vmcs_read32(sf
->ar_bytes
);
2012 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2014 var
->type
= ar
& 15;
2015 var
->s
= (ar
>> 4) & 1;
2016 var
->dpl
= (ar
>> 5) & 3;
2017 var
->present
= (ar
>> 7) & 1;
2018 var
->avl
= (ar
>> 12) & 1;
2019 var
->l
= (ar
>> 13) & 1;
2020 var
->db
= (ar
>> 14) & 1;
2021 var
->g
= (ar
>> 15) & 1;
2022 var
->unusable
= (ar
>> 16) & 1;
2025 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2027 if (!is_protmode(vcpu
))
2030 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
2033 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
2036 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
2043 ar
= var
->type
& 15;
2044 ar
|= (var
->s
& 1) << 4;
2045 ar
|= (var
->dpl
& 3) << 5;
2046 ar
|= (var
->present
& 1) << 7;
2047 ar
|= (var
->avl
& 1) << 12;
2048 ar
|= (var
->l
& 1) << 13;
2049 ar
|= (var
->db
& 1) << 14;
2050 ar
|= (var
->g
& 1) << 15;
2052 if (ar
== 0) /* a 0 value means unusable */
2053 ar
= AR_UNUSABLE_MASK
;
2058 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
2059 struct kvm_segment
*var
, int seg
)
2061 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2062 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2065 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2066 vmx
->rmode
.tr
.selector
= var
->selector
;
2067 vmx
->rmode
.tr
.base
= var
->base
;
2068 vmx
->rmode
.tr
.limit
= var
->limit
;
2069 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2072 vmcs_writel(sf
->base
, var
->base
);
2073 vmcs_write32(sf
->limit
, var
->limit
);
2074 vmcs_write16(sf
->selector
, var
->selector
);
2075 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2077 * Hack real-mode segments into vm86 compatibility.
2079 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2080 vmcs_writel(sf
->base
, 0xf0000);
2083 ar
= vmx_segment_access_rights(var
);
2086 * Fix the "Accessed" bit in AR field of segment registers for older
2088 * IA32 arch specifies that at the time of processor reset the
2089 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2090 * is setting it to 0 in the usedland code. This causes invalid guest
2091 * state vmexit when "unrestricted guest" mode is turned on.
2092 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2093 * tree. Newer qemu binaries with that qemu fix would not need this
2096 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2097 ar
|= 0x1; /* Accessed */
2099 vmcs_write32(sf
->ar_bytes
, ar
);
2102 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2104 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
2106 *db
= (ar
>> 14) & 1;
2107 *l
= (ar
>> 13) & 1;
2110 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2112 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2113 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2116 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2118 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
2119 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
2122 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2124 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
2125 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
2128 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2130 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
2131 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
2134 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2136 struct kvm_segment var
;
2139 vmx_get_segment(vcpu
, &var
, seg
);
2140 ar
= vmx_segment_access_rights(&var
);
2142 if (var
.base
!= (var
.selector
<< 4))
2144 if (var
.limit
!= 0xffff)
2152 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
2154 struct kvm_segment cs
;
2155 unsigned int cs_rpl
;
2157 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2158 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
2162 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
2166 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
2167 if (cs
.dpl
> cs_rpl
)
2170 if (cs
.dpl
!= cs_rpl
)
2176 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2180 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2182 struct kvm_segment ss
;
2183 unsigned int ss_rpl
;
2185 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2186 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2190 if (ss
.type
!= 3 && ss
.type
!= 7)
2194 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2202 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2204 struct kvm_segment var
;
2207 vmx_get_segment(vcpu
, &var
, seg
);
2208 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2216 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2217 if (var
.dpl
< rpl
) /* DPL < RPL */
2221 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2227 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2229 struct kvm_segment tr
;
2231 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2235 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2237 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2245 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2247 struct kvm_segment ldtr
;
2249 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2253 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2263 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2265 struct kvm_segment cs
, ss
;
2267 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2268 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2270 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2271 (ss
.selector
& SELECTOR_RPL_MASK
));
2275 * Check if guest state is valid. Returns true if valid, false if
2277 * We assume that registers are always usable
2279 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2281 /* real mode guest state checks */
2282 if (!is_protmode(vcpu
)) {
2283 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2285 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2287 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2289 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2291 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2293 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2296 /* protected mode guest state checks */
2297 if (!cs_ss_rpl_check(vcpu
))
2299 if (!code_segment_valid(vcpu
))
2301 if (!stack_segment_valid(vcpu
))
2303 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2305 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2307 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2309 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2311 if (!tr_valid(vcpu
))
2313 if (!ldtr_valid(vcpu
))
2317 * - Add checks on RIP
2318 * - Add checks on RFLAGS
2324 static int init_rmode_tss(struct kvm
*kvm
)
2326 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2331 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2334 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2335 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2336 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2339 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2342 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2346 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2347 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2357 static int init_rmode_identity_map(struct kvm
*kvm
)
2360 pfn_t identity_map_pfn
;
2365 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2366 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2367 "haven't been allocated!\n");
2370 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2373 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2374 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2377 /* Set up identity-mapping pagetable for EPT in real mode */
2378 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2379 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2380 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2381 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2382 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2386 kvm
->arch
.ept_identity_pagetable_done
= true;
2392 static void seg_setup(int seg
)
2394 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2397 vmcs_write16(sf
->selector
, 0);
2398 vmcs_writel(sf
->base
, 0);
2399 vmcs_write32(sf
->limit
, 0xffff);
2400 if (enable_unrestricted_guest
) {
2402 if (seg
== VCPU_SREG_CS
)
2403 ar
|= 0x08; /* code segment */
2407 vmcs_write32(sf
->ar_bytes
, ar
);
2410 static int alloc_apic_access_page(struct kvm
*kvm
)
2412 struct kvm_userspace_memory_region kvm_userspace_mem
;
2415 mutex_lock(&kvm
->slots_lock
);
2416 if (kvm
->arch
.apic_access_page
)
2418 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2419 kvm_userspace_mem
.flags
= 0;
2420 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2421 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2422 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2426 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2428 mutex_unlock(&kvm
->slots_lock
);
2432 static int alloc_identity_pagetable(struct kvm
*kvm
)
2434 struct kvm_userspace_memory_region kvm_userspace_mem
;
2437 mutex_lock(&kvm
->slots_lock
);
2438 if (kvm
->arch
.ept_identity_pagetable
)
2440 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2441 kvm_userspace_mem
.flags
= 0;
2442 kvm_userspace_mem
.guest_phys_addr
=
2443 kvm
->arch
.ept_identity_map_addr
;
2444 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2445 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2449 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2450 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2452 mutex_unlock(&kvm
->slots_lock
);
2456 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2463 spin_lock(&vmx_vpid_lock
);
2464 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2465 if (vpid
< VMX_NR_VPIDS
) {
2467 __set_bit(vpid
, vmx_vpid_bitmap
);
2469 spin_unlock(&vmx_vpid_lock
);
2472 static void free_vpid(struct vcpu_vmx
*vmx
)
2476 spin_lock(&vmx_vpid_lock
);
2478 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2479 spin_unlock(&vmx_vpid_lock
);
2482 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2484 int f
= sizeof(unsigned long);
2486 if (!cpu_has_vmx_msr_bitmap())
2490 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2491 * have the write-low and read-high bitmap offsets the wrong way round.
2492 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2494 if (msr
<= 0x1fff) {
2495 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2496 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2497 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2499 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2500 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2504 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2507 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2508 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2512 * Sets up the vmcs for emulated real mode.
2514 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2516 u32 host_sysenter_cs
, msr_low
, msr_high
;
2518 u64 host_pat
, tsc_this
, tsc_base
;
2522 unsigned long kvm_vmx_return
;
2526 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2527 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2529 if (cpu_has_vmx_msr_bitmap())
2530 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2532 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2535 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2536 vmcs_config
.pin_based_exec_ctrl
);
2538 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2539 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2540 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2541 #ifdef CONFIG_X86_64
2542 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2543 CPU_BASED_CR8_LOAD_EXITING
;
2547 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2548 CPU_BASED_CR3_LOAD_EXITING
|
2549 CPU_BASED_INVLPG_EXITING
;
2550 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2552 if (cpu_has_secondary_exec_ctrls()) {
2553 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2554 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2556 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2558 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2560 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2561 enable_unrestricted_guest
= 0;
2563 if (!enable_unrestricted_guest
)
2564 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2566 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2571 vmcs_write32(PLE_GAP
, ple_gap
);
2572 vmcs_write32(PLE_WINDOW
, ple_window
);
2575 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2576 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2577 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2579 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
2580 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2581 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2583 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2584 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2585 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2586 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
2587 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
2588 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2589 #ifdef CONFIG_X86_64
2590 rdmsrl(MSR_FS_BASE
, a
);
2591 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2592 rdmsrl(MSR_GS_BASE
, a
);
2593 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2595 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2596 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2599 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2601 native_store_idt(&dt
);
2602 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
2604 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2605 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2606 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2607 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2608 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
2609 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2610 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
2612 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2613 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2614 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2615 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2616 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2617 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2619 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2620 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2621 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2622 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2624 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2625 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2626 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2627 /* Write the default value follow host pat */
2628 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2629 /* Keep arch.pat sync with GUEST_IA32_PAT */
2630 vmx
->vcpu
.arch
.pat
= host_pat
;
2633 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2634 u32 index
= vmx_msr_index
[i
];
2635 u32 data_low
, data_high
;
2638 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2640 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2642 vmx
->guest_msrs
[j
].index
= i
;
2643 vmx
->guest_msrs
[j
].data
= 0;
2644 vmx
->guest_msrs
[j
].mask
= -1ull;
2648 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2650 /* 22.2.1, 20.8.1 */
2651 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2653 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2654 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2656 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2657 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2659 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2661 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2662 tsc_base
= tsc_this
;
2664 guest_write_tsc(0, tsc_base
);
2669 static int init_rmode(struct kvm
*kvm
)
2673 idx
= srcu_read_lock(&kvm
->srcu
);
2674 if (!init_rmode_tss(kvm
))
2676 if (!init_rmode_identity_map(kvm
))
2681 srcu_read_unlock(&kvm
->srcu
, idx
);
2685 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2687 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2691 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2692 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2697 vmx
->rmode
.vm86_active
= 0;
2699 vmx
->soft_vnmi_blocked
= 0;
2701 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2702 kvm_set_cr8(&vmx
->vcpu
, 0);
2703 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2704 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2705 msr
|= MSR_IA32_APICBASE_BSP
;
2706 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2708 ret
= fx_init(&vmx
->vcpu
);
2712 seg_setup(VCPU_SREG_CS
);
2714 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2715 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2717 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2718 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2719 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2721 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2722 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2725 seg_setup(VCPU_SREG_DS
);
2726 seg_setup(VCPU_SREG_ES
);
2727 seg_setup(VCPU_SREG_FS
);
2728 seg_setup(VCPU_SREG_GS
);
2729 seg_setup(VCPU_SREG_SS
);
2731 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2732 vmcs_writel(GUEST_TR_BASE
, 0);
2733 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2734 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2736 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2737 vmcs_writel(GUEST_LDTR_BASE
, 0);
2738 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2739 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2741 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2742 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2743 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2745 vmcs_writel(GUEST_RFLAGS
, 0x02);
2746 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2747 kvm_rip_write(vcpu
, 0xfff0);
2749 kvm_rip_write(vcpu
, 0);
2750 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2752 vmcs_writel(GUEST_DR7
, 0x400);
2754 vmcs_writel(GUEST_GDTR_BASE
, 0);
2755 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2757 vmcs_writel(GUEST_IDTR_BASE
, 0);
2758 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2760 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2761 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2762 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2764 /* Special registers */
2765 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2771 if (cpu_has_vmx_tpr_shadow()) {
2772 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2773 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2774 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2775 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2776 vmcs_write32(TPR_THRESHOLD
, 0);
2779 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2780 vmcs_write64(APIC_ACCESS_ADDR
,
2781 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2784 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2786 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2787 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
2788 vmx_set_cr4(&vmx
->vcpu
, 0);
2789 vmx_set_efer(&vmx
->vcpu
, 0);
2790 vmx_fpu_activate(&vmx
->vcpu
);
2791 update_exception_bitmap(&vmx
->vcpu
);
2793 vpid_sync_context(vmx
);
2797 /* HACK: Don't enable emulation on guest boot/reset */
2798 vmx
->emulation_required
= 0;
2804 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2806 u32 cpu_based_vm_exec_control
;
2808 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2809 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2810 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2813 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2815 u32 cpu_based_vm_exec_control
;
2817 if (!cpu_has_virtual_nmis()) {
2818 enable_irq_window(vcpu
);
2822 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2823 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2824 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2827 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2829 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2831 int irq
= vcpu
->arch
.interrupt
.nr
;
2833 trace_kvm_inj_virq(irq
);
2835 ++vcpu
->stat
.irq_injections
;
2836 if (vmx
->rmode
.vm86_active
) {
2837 vmx
->rmode
.irq
.pending
= true;
2838 vmx
->rmode
.irq
.vector
= irq
;
2839 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2840 if (vcpu
->arch
.interrupt
.soft
)
2841 vmx
->rmode
.irq
.rip
+=
2842 vmx
->vcpu
.arch
.event_exit_inst_len
;
2843 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2844 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2845 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2846 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2849 intr
= irq
| INTR_INFO_VALID_MASK
;
2850 if (vcpu
->arch
.interrupt
.soft
) {
2851 intr
|= INTR_TYPE_SOFT_INTR
;
2852 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2853 vmx
->vcpu
.arch
.event_exit_inst_len
);
2855 intr
|= INTR_TYPE_EXT_INTR
;
2856 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2859 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2863 if (!cpu_has_virtual_nmis()) {
2865 * Tracking the NMI-blocked state in software is built upon
2866 * finding the next open IRQ window. This, in turn, depends on
2867 * well-behaving guests: They have to keep IRQs disabled at
2868 * least as long as the NMI handler runs. Otherwise we may
2869 * cause NMI nesting, maybe breaking the guest. But as this is
2870 * highly unlikely, we can live with the residual risk.
2872 vmx
->soft_vnmi_blocked
= 1;
2873 vmx
->vnmi_blocked_time
= 0;
2876 ++vcpu
->stat
.nmi_injections
;
2877 if (vmx
->rmode
.vm86_active
) {
2878 vmx
->rmode
.irq
.pending
= true;
2879 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2880 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2881 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2882 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2883 INTR_INFO_VALID_MASK
);
2884 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2885 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2888 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2889 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2892 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2894 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2897 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2898 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_NMI
));
2901 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2903 if (!cpu_has_virtual_nmis())
2904 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2905 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
2908 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2910 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2912 if (!cpu_has_virtual_nmis()) {
2913 if (vmx
->soft_vnmi_blocked
!= masked
) {
2914 vmx
->soft_vnmi_blocked
= masked
;
2915 vmx
->vnmi_blocked_time
= 0;
2919 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2920 GUEST_INTR_STATE_NMI
);
2922 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2923 GUEST_INTR_STATE_NMI
);
2927 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2929 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2930 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2931 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2934 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2937 struct kvm_userspace_memory_region tss_mem
= {
2938 .slot
= TSS_PRIVATE_MEMSLOT
,
2939 .guest_phys_addr
= addr
,
2940 .memory_size
= PAGE_SIZE
* 3,
2944 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2947 kvm
->arch
.tss_addr
= addr
;
2951 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2952 int vec
, u32 err_code
)
2955 * Instruction with address size override prefix opcode 0x67
2956 * Cause the #SS fault with 0 error code in VM86 mode.
2958 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2959 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
)
2962 * Forward all other exceptions that are valid in real mode.
2963 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2964 * the required debugging infrastructure rework.
2968 if (vcpu
->guest_debug
&
2969 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2971 kvm_queue_exception(vcpu
, vec
);
2975 * Update instruction length as we may reinject the exception
2976 * from user space while in guest debugging mode.
2978 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
2979 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2980 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2991 kvm_queue_exception(vcpu
, vec
);
2998 * Trigger machine check on the host. We assume all the MSRs are already set up
2999 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3000 * We pass a fake environment to the machine check handler because we want
3001 * the guest to be always treated like user space, no matter what context
3002 * it used internally.
3004 static void kvm_machine_check(void)
3006 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3007 struct pt_regs regs
= {
3008 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
3009 .flags
= X86_EFLAGS_IF
,
3012 do_machine_check(®s
, 0);
3016 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
3018 /* already handled by vcpu_run */
3022 static int handle_exception(struct kvm_vcpu
*vcpu
)
3024 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3025 struct kvm_run
*kvm_run
= vcpu
->run
;
3026 u32 intr_info
, ex_no
, error_code
;
3027 unsigned long cr2
, rip
, dr6
;
3029 enum emulation_result er
;
3031 vect_info
= vmx
->idt_vectoring_info
;
3032 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3034 if (is_machine_check(intr_info
))
3035 return handle_machine_check(vcpu
);
3037 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
3038 !is_page_fault(intr_info
)) {
3039 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3040 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
3041 vcpu
->run
->internal
.ndata
= 2;
3042 vcpu
->run
->internal
.data
[0] = vect_info
;
3043 vcpu
->run
->internal
.data
[1] = intr_info
;
3047 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
3048 return 1; /* already handled by vmx_vcpu_run() */
3050 if (is_no_device(intr_info
)) {
3051 vmx_fpu_activate(vcpu
);
3055 if (is_invalid_opcode(intr_info
)) {
3056 er
= emulate_instruction(vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
3057 if (er
!= EMULATE_DONE
)
3058 kvm_queue_exception(vcpu
, UD_VECTOR
);
3063 rip
= kvm_rip_read(vcpu
);
3064 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
3065 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
3066 if (is_page_fault(intr_info
)) {
3067 /* EPT won't cause page fault directly */
3070 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3071 trace_kvm_page_fault(cr2
, error_code
);
3073 if (kvm_event_needs_reinjection(vcpu
))
3074 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3075 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
3078 if (vmx
->rmode
.vm86_active
&&
3079 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3081 if (vcpu
->arch
.halt_request
) {
3082 vcpu
->arch
.halt_request
= 0;
3083 return kvm_emulate_halt(vcpu
);
3088 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3091 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3092 if (!(vcpu
->guest_debug
&
3093 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3094 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3095 kvm_queue_exception(vcpu
, DB_VECTOR
);
3098 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3099 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3103 * Update instruction length as we may reinject #BP from
3104 * user space while in guest debugging mode. Reading it for
3105 * #DB as well causes no harm, it is not used in that case.
3107 vmx
->vcpu
.arch
.event_exit_inst_len
=
3108 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3109 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3110 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3111 kvm_run
->debug
.arch
.exception
= ex_no
;
3114 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3115 kvm_run
->ex
.exception
= ex_no
;
3116 kvm_run
->ex
.error_code
= error_code
;
3122 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3124 ++vcpu
->stat
.irq_exits
;
3128 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3130 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
3134 static int handle_io(struct kvm_vcpu
*vcpu
)
3136 unsigned long exit_qualification
;
3137 int size
, in
, string
;
3140 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3141 string
= (exit_qualification
& 16) != 0;
3142 in
= (exit_qualification
& 8) != 0;
3144 ++vcpu
->stat
.io_exits
;
3147 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
3149 port
= exit_qualification
>> 16;
3150 size
= (exit_qualification
& 7) + 1;
3151 skip_emulated_instruction(vcpu
);
3153 return kvm_fast_pio_out(vcpu
, size
, port
);
3157 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3160 * Patch in the VMCALL instruction:
3162 hypercall
[0] = 0x0f;
3163 hypercall
[1] = 0x01;
3164 hypercall
[2] = 0xc1;
3167 static void complete_insn_gp(struct kvm_vcpu
*vcpu
, int err
)
3170 kvm_inject_gp(vcpu
, 0);
3172 skip_emulated_instruction(vcpu
);
3175 static int handle_cr(struct kvm_vcpu
*vcpu
)
3177 unsigned long exit_qualification
, val
;
3182 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3183 cr
= exit_qualification
& 15;
3184 reg
= (exit_qualification
>> 8) & 15;
3185 switch ((exit_qualification
>> 4) & 3) {
3186 case 0: /* mov to cr */
3187 val
= kvm_register_read(vcpu
, reg
);
3188 trace_kvm_cr_write(cr
, val
);
3191 err
= kvm_set_cr0(vcpu
, val
);
3192 complete_insn_gp(vcpu
, err
);
3195 err
= kvm_set_cr3(vcpu
, val
);
3196 complete_insn_gp(vcpu
, err
);
3199 err
= kvm_set_cr4(vcpu
, val
);
3200 complete_insn_gp(vcpu
, err
);
3203 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3204 u8 cr8
= kvm_register_read(vcpu
, reg
);
3205 kvm_set_cr8(vcpu
, cr8
);
3206 skip_emulated_instruction(vcpu
);
3207 if (irqchip_in_kernel(vcpu
->kvm
))
3209 if (cr8_prev
<= cr8
)
3211 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3217 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3218 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3219 skip_emulated_instruction(vcpu
);
3220 vmx_fpu_activate(vcpu
);
3222 case 1: /*mov from cr*/
3225 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3226 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3227 skip_emulated_instruction(vcpu
);
3230 val
= kvm_get_cr8(vcpu
);
3231 kvm_register_write(vcpu
, reg
, val
);
3232 trace_kvm_cr_read(cr
, val
);
3233 skip_emulated_instruction(vcpu
);
3238 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3239 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3240 kvm_lmsw(vcpu
, val
);
3242 skip_emulated_instruction(vcpu
);
3247 vcpu
->run
->exit_reason
= 0;
3248 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3249 (int)(exit_qualification
>> 4) & 3, cr
);
3253 static int handle_dr(struct kvm_vcpu
*vcpu
)
3255 unsigned long exit_qualification
;
3258 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3259 if (!kvm_require_cpl(vcpu
, 0))
3261 dr
= vmcs_readl(GUEST_DR7
);
3264 * As the vm-exit takes precedence over the debug trap, we
3265 * need to emulate the latter, either for the host or the
3266 * guest debugging itself.
3268 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3269 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3270 vcpu
->run
->debug
.arch
.dr7
= dr
;
3271 vcpu
->run
->debug
.arch
.pc
=
3272 vmcs_readl(GUEST_CS_BASE
) +
3273 vmcs_readl(GUEST_RIP
);
3274 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3275 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3278 vcpu
->arch
.dr7
&= ~DR7_GD
;
3279 vcpu
->arch
.dr6
|= DR6_BD
;
3280 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3281 kvm_queue_exception(vcpu
, DB_VECTOR
);
3286 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3287 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3288 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3289 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3291 if (!kvm_get_dr(vcpu
, dr
, &val
))
3292 kvm_register_write(vcpu
, reg
, val
);
3294 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
3295 skip_emulated_instruction(vcpu
);
3299 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
3301 vmcs_writel(GUEST_DR7
, val
);
3304 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3306 kvm_emulate_cpuid(vcpu
);
3310 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3312 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3315 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3316 trace_kvm_msr_read_ex(ecx
);
3317 kvm_inject_gp(vcpu
, 0);
3321 trace_kvm_msr_read(ecx
, data
);
3323 /* FIXME: handling of bits 32:63 of rax, rdx */
3324 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3325 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3326 skip_emulated_instruction(vcpu
);
3330 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3332 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3333 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3334 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3336 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3337 trace_kvm_msr_write_ex(ecx
, data
);
3338 kvm_inject_gp(vcpu
, 0);
3342 trace_kvm_msr_write(ecx
, data
);
3343 skip_emulated_instruction(vcpu
);
3347 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3352 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3354 u32 cpu_based_vm_exec_control
;
3356 /* clear pending irq */
3357 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3358 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3359 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3361 ++vcpu
->stat
.irq_window_exits
;
3364 * If the user space waits to inject interrupts, exit as soon as
3367 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3368 vcpu
->run
->request_interrupt_window
&&
3369 !kvm_cpu_has_interrupt(vcpu
)) {
3370 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3376 static int handle_halt(struct kvm_vcpu
*vcpu
)
3378 skip_emulated_instruction(vcpu
);
3379 return kvm_emulate_halt(vcpu
);
3382 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3384 skip_emulated_instruction(vcpu
);
3385 kvm_emulate_hypercall(vcpu
);
3389 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3391 kvm_queue_exception(vcpu
, UD_VECTOR
);
3395 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3397 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3399 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3400 skip_emulated_instruction(vcpu
);
3404 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3406 skip_emulated_instruction(vcpu
);
3407 kvm_emulate_wbinvd(vcpu
);
3411 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
3413 u64 new_bv
= kvm_read_edx_eax(vcpu
);
3414 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
3416 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
3417 skip_emulated_instruction(vcpu
);
3421 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3423 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
3426 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3429 unsigned long exit_qualification
;
3430 bool has_error_code
= false;
3433 int reason
, type
, idt_v
;
3435 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3436 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3438 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3440 reason
= (u32
)exit_qualification
>> 30;
3441 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3443 case INTR_TYPE_NMI_INTR
:
3444 vcpu
->arch
.nmi_injected
= false;
3445 if (cpu_has_virtual_nmis())
3446 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3447 GUEST_INTR_STATE_NMI
);
3449 case INTR_TYPE_EXT_INTR
:
3450 case INTR_TYPE_SOFT_INTR
:
3451 kvm_clear_interrupt_queue(vcpu
);
3453 case INTR_TYPE_HARD_EXCEPTION
:
3454 if (vmx
->idt_vectoring_info
&
3455 VECTORING_INFO_DELIVER_CODE_MASK
) {
3456 has_error_code
= true;
3458 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3461 case INTR_TYPE_SOFT_EXCEPTION
:
3462 kvm_clear_exception_queue(vcpu
);
3468 tss_selector
= exit_qualification
;
3470 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3471 type
!= INTR_TYPE_EXT_INTR
&&
3472 type
!= INTR_TYPE_NMI_INTR
))
3473 skip_emulated_instruction(vcpu
);
3475 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
3476 has_error_code
, error_code
) == EMULATE_FAIL
) {
3477 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3478 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3479 vcpu
->run
->internal
.ndata
= 0;
3483 /* clear all local breakpoint enable flags */
3484 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3487 * TODO: What about debug traps on tss switch?
3488 * Are we supposed to inject them and update dr6?
3494 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3496 unsigned long exit_qualification
;
3500 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3502 if (exit_qualification
& (1 << 6)) {
3503 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3507 gla_validity
= (exit_qualification
>> 7) & 0x3;
3508 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3509 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3510 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3511 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3512 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3513 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3514 (long unsigned int)exit_qualification
);
3515 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3516 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3520 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3521 trace_kvm_page_fault(gpa
, exit_qualification
);
3522 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3525 static u64
ept_rsvd_mask(u64 spte
, int level
)
3530 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3531 mask
|= (1ULL << i
);
3534 /* bits 7:3 reserved */
3536 else if (level
== 2) {
3537 if (spte
& (1ULL << 7))
3538 /* 2MB ref, bits 20:12 reserved */
3541 /* bits 6:3 reserved */
3548 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3551 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3553 /* 010b (write-only) */
3554 WARN_ON((spte
& 0x7) == 0x2);
3556 /* 110b (write/execute) */
3557 WARN_ON((spte
& 0x7) == 0x6);
3559 /* 100b (execute-only) and value not supported by logical processor */
3560 if (!cpu_has_vmx_ept_execute_only())
3561 WARN_ON((spte
& 0x7) == 0x4);
3565 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3567 if (rsvd_bits
!= 0) {
3568 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3569 __func__
, rsvd_bits
);
3573 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3574 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3576 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3577 ept_mem_type
== 7) {
3578 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3579 __func__
, ept_mem_type
);
3586 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3592 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3594 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3595 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3597 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3599 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3600 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3602 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3603 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3608 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3610 u32 cpu_based_vm_exec_control
;
3612 /* clear pending NMI */
3613 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3614 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3616 ++vcpu
->stat
.nmi_window_exits
;
3621 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3623 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3624 enum emulation_result err
= EMULATE_DONE
;
3627 while (!guest_state_valid(vcpu
)) {
3628 err
= emulate_instruction(vcpu
, 0, 0, 0);
3630 if (err
== EMULATE_DO_MMIO
) {
3635 if (err
!= EMULATE_DONE
)
3638 if (signal_pending(current
))
3644 vmx
->emulation_required
= 0;
3650 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3651 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3653 static int handle_pause(struct kvm_vcpu
*vcpu
)
3655 skip_emulated_instruction(vcpu
);
3656 kvm_vcpu_on_spin(vcpu
);
3661 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3663 kvm_queue_exception(vcpu
, UD_VECTOR
);
3668 * The exit handlers return 1 if the exit was handled fully and guest execution
3669 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3670 * to be done to userspace and return 0.
3672 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3673 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3674 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3675 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3676 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3677 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3678 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3679 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3680 [EXIT_REASON_CPUID
] = handle_cpuid
,
3681 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3682 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3683 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3684 [EXIT_REASON_HLT
] = handle_halt
,
3685 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3686 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3687 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3688 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3689 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3690 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3691 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3692 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3693 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3694 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3695 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3696 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3697 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3698 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3699 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
3700 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3701 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3702 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3703 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3704 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3705 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3706 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3709 static const int kvm_vmx_max_exit_handlers
=
3710 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3713 * The guest has exited. See if we can fix it or if we need userspace
3716 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3718 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3719 u32 exit_reason
= vmx
->exit_reason
;
3720 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3722 trace_kvm_exit(exit_reason
, vcpu
);
3724 /* If guest state is invalid, start emulating */
3725 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3726 return handle_invalid_guest_state(vcpu
);
3728 /* Access CR3 don't cause VMExit in paging mode, so we need
3729 * to sync with guest real CR3. */
3730 if (enable_ept
&& is_paging(vcpu
))
3731 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3733 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
3734 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3735 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3740 if (unlikely(vmx
->fail
)) {
3741 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3742 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3743 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3747 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3748 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3749 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3750 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3751 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3752 "(0x%x) and exit reason is 0x%x\n",
3753 __func__
, vectoring_info
, exit_reason
);
3755 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3756 if (vmx_interrupt_allowed(vcpu
)) {
3757 vmx
->soft_vnmi_blocked
= 0;
3758 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3759 vcpu
->arch
.nmi_pending
) {
3761 * This CPU don't support us in finding the end of an
3762 * NMI-blocked window if the guest runs with IRQs
3763 * disabled. So we pull the trigger after 1 s of
3764 * futile waiting, but inform the user about this.
3766 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3767 "state on VCPU %d after 1 s timeout\n",
3768 __func__
, vcpu
->vcpu_id
);
3769 vmx
->soft_vnmi_blocked
= 0;
3773 if (exit_reason
< kvm_vmx_max_exit_handlers
3774 && kvm_vmx_exit_handlers
[exit_reason
])
3775 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3777 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3778 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3783 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3785 if (irr
== -1 || tpr
< irr
) {
3786 vmcs_write32(TPR_THRESHOLD
, 0);
3790 vmcs_write32(TPR_THRESHOLD
, irr
);
3793 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3796 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3800 bool idtv_info_valid
;
3802 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3804 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3806 /* Handle machine checks before interrupts are enabled */
3807 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3808 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3809 && is_machine_check(exit_intr_info
)))
3810 kvm_machine_check();
3812 /* We need to handle NMIs before interrupts are enabled */
3813 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3814 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
3815 kvm_before_handle_nmi(&vmx
->vcpu
);
3817 kvm_after_handle_nmi(&vmx
->vcpu
);
3820 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3822 if (cpu_has_virtual_nmis()) {
3823 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3824 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3826 * SDM 3: 27.7.1.2 (September 2008)
3827 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3828 * a guest IRET fault.
3829 * SDM 3: 23.2.2 (September 2008)
3830 * Bit 12 is undefined in any of the following cases:
3831 * If the VM exit sets the valid bit in the IDT-vectoring
3832 * information field.
3833 * If the VM exit is due to a double fault.
3835 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3836 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3837 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3838 GUEST_INTR_STATE_NMI
);
3839 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3840 vmx
->vnmi_blocked_time
+=
3841 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3843 vmx
->vcpu
.arch
.nmi_injected
= false;
3844 kvm_clear_exception_queue(&vmx
->vcpu
);
3845 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3847 if (!idtv_info_valid
)
3850 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3851 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3854 case INTR_TYPE_NMI_INTR
:
3855 vmx
->vcpu
.arch
.nmi_injected
= true;
3857 * SDM 3: 27.7.1.2 (September 2008)
3858 * Clear bit "block by NMI" before VM entry if a NMI
3861 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3862 GUEST_INTR_STATE_NMI
);
3864 case INTR_TYPE_SOFT_EXCEPTION
:
3865 vmx
->vcpu
.arch
.event_exit_inst_len
=
3866 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3868 case INTR_TYPE_HARD_EXCEPTION
:
3869 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3870 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3871 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3873 kvm_queue_exception(&vmx
->vcpu
, vector
);
3875 case INTR_TYPE_SOFT_INTR
:
3876 vmx
->vcpu
.arch
.event_exit_inst_len
=
3877 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3879 case INTR_TYPE_EXT_INTR
:
3880 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3881 type
== INTR_TYPE_SOFT_INTR
);
3889 * Failure to inject an interrupt should give us the information
3890 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3891 * when fetching the interrupt redirection bitmap in the real-mode
3892 * tss, this doesn't happen. So we do it ourselves.
3894 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3896 vmx
->rmode
.irq
.pending
= 0;
3897 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3899 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3900 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3901 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3902 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3905 vmx
->idt_vectoring_info
=
3906 VECTORING_INFO_VALID_MASK
3907 | INTR_TYPE_EXT_INTR
3908 | vmx
->rmode
.irq
.vector
;
3911 #ifdef CONFIG_X86_64
3919 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3923 /* Record the guest's net vcpu time for enforced NMI injections. */
3924 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3925 vmx
->entry_time
= ktime_get();
3927 /* Don't enter VMX if guest state is invalid, let the exit handler
3928 start emulation until we arrive back to a valid state */
3929 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3932 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3933 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3934 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3935 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3937 /* When single-stepping over STI and MOV SS, we must clear the
3938 * corresponding interruptibility bits in the guest state. Otherwise
3939 * vmentry fails as it then expects bit 14 (BS) in pending debug
3940 * exceptions being set, but that's not correct for the guest debugging
3942 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3943 vmx_set_interrupt_shadow(vcpu
, 0);
3946 /* Store host registers */
3947 "push %%"R
"dx; push %%"R
"bp;"
3949 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3951 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3952 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3954 /* Reload cr2 if changed */
3955 "mov %c[cr2](%0), %%"R
"ax \n\t"
3956 "mov %%cr2, %%"R
"dx \n\t"
3957 "cmp %%"R
"ax, %%"R
"dx \n\t"
3959 "mov %%"R
"ax, %%cr2 \n\t"
3961 /* Check if vmlaunch of vmresume is needed */
3962 "cmpl $0, %c[launched](%0) \n\t"
3963 /* Load guest registers. Don't clobber flags. */
3964 "mov %c[rax](%0), %%"R
"ax \n\t"
3965 "mov %c[rbx](%0), %%"R
"bx \n\t"
3966 "mov %c[rdx](%0), %%"R
"dx \n\t"
3967 "mov %c[rsi](%0), %%"R
"si \n\t"
3968 "mov %c[rdi](%0), %%"R
"di \n\t"
3969 "mov %c[rbp](%0), %%"R
"bp \n\t"
3970 #ifdef CONFIG_X86_64
3971 "mov %c[r8](%0), %%r8 \n\t"
3972 "mov %c[r9](%0), %%r9 \n\t"
3973 "mov %c[r10](%0), %%r10 \n\t"
3974 "mov %c[r11](%0), %%r11 \n\t"
3975 "mov %c[r12](%0), %%r12 \n\t"
3976 "mov %c[r13](%0), %%r13 \n\t"
3977 "mov %c[r14](%0), %%r14 \n\t"
3978 "mov %c[r15](%0), %%r15 \n\t"
3980 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3982 /* Enter guest mode */
3983 "jne .Llaunched \n\t"
3984 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3985 "jmp .Lkvm_vmx_return \n\t"
3986 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3987 ".Lkvm_vmx_return: "
3988 /* Save guest registers, load host registers, keep flags */
3989 "xchg %0, (%%"R
"sp) \n\t"
3990 "mov %%"R
"ax, %c[rax](%0) \n\t"
3991 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3992 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3993 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3994 "mov %%"R
"si, %c[rsi](%0) \n\t"
3995 "mov %%"R
"di, %c[rdi](%0) \n\t"
3996 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3997 #ifdef CONFIG_X86_64
3998 "mov %%r8, %c[r8](%0) \n\t"
3999 "mov %%r9, %c[r9](%0) \n\t"
4000 "mov %%r10, %c[r10](%0) \n\t"
4001 "mov %%r11, %c[r11](%0) \n\t"
4002 "mov %%r12, %c[r12](%0) \n\t"
4003 "mov %%r13, %c[r13](%0) \n\t"
4004 "mov %%r14, %c[r14](%0) \n\t"
4005 "mov %%r15, %c[r15](%0) \n\t"
4007 "mov %%cr2, %%"R
"ax \n\t"
4008 "mov %%"R
"ax, %c[cr2](%0) \n\t"
4010 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
4011 "setbe %c[fail](%0) \n\t"
4012 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
4013 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
4014 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
4015 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
4016 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
4017 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4018 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4019 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4020 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4021 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4022 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
4023 #ifdef CONFIG_X86_64
4024 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4025 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4026 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4027 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4028 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4029 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4030 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4031 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
4033 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
4035 , R
"bx", R
"di", R
"si"
4036 #ifdef CONFIG_X86_64
4037 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4041 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
4042 | (1 << VCPU_EXREG_PDPTR
));
4043 vcpu
->arch
.regs_dirty
= 0;
4045 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
4046 if (vmx
->rmode
.irq
.pending
)
4047 fixup_rmode_irq(vmx
);
4049 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
4052 vmx_complete_interrupts(vmx
);
4058 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
4060 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4064 free_vmcs(vmx
->vmcs
);
4069 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
4071 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4074 vmx_free_vmcs(vcpu
);
4075 kfree(vmx
->guest_msrs
);
4076 kvm_vcpu_uninit(vcpu
);
4077 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4080 static inline void vmcs_init(struct vmcs
*vmcs
)
4082 u64 phys_addr
= __pa(per_cpu(vmxarea
, raw_smp_processor_id()));
4085 kvm_cpu_vmxon(phys_addr
);
4093 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
4096 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
4100 return ERR_PTR(-ENOMEM
);
4104 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
4108 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
4109 if (!vmx
->guest_msrs
) {
4114 vmx
->vmcs
= alloc_vmcs();
4118 vmcs_init(vmx
->vmcs
);
4121 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
4122 err
= vmx_vcpu_setup(vmx
);
4123 vmx_vcpu_put(&vmx
->vcpu
);
4127 if (vm_need_virtualize_apic_accesses(kvm
))
4128 if (alloc_apic_access_page(kvm
) != 0)
4132 if (!kvm
->arch
.ept_identity_map_addr
)
4133 kvm
->arch
.ept_identity_map_addr
=
4134 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4135 if (alloc_identity_pagetable(kvm
) != 0)
4142 free_vmcs(vmx
->vmcs
);
4144 kfree(vmx
->guest_msrs
);
4146 kvm_vcpu_uninit(&vmx
->vcpu
);
4149 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4150 return ERR_PTR(err
);
4153 static void __init
vmx_check_processor_compat(void *rtn
)
4155 struct vmcs_config vmcs_conf
;
4158 if (setup_vmcs_config(&vmcs_conf
) < 0)
4160 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
4161 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
4162 smp_processor_id());
4167 static int get_ept_level(void)
4169 return VMX_EPT_DEFAULT_GAW
+ 1;
4172 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4176 /* For VT-d and EPT combination
4177 * 1. MMIO: always map as UC
4179 * a. VT-d without snooping control feature: can't guarantee the
4180 * result, try to trust guest.
4181 * b. VT-d with snooping control feature: snooping control feature of
4182 * VT-d engine can guarantee the cache correctness. Just set it
4183 * to WB to keep consistent with host. So the same as item 3.
4184 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4185 * consistent with host MTRR
4188 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4189 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4190 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4191 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4192 VMX_EPT_MT_EPTE_SHIFT
;
4194 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4200 #define _ER(x) { EXIT_REASON_##x, #x }
4202 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4204 _ER(EXTERNAL_INTERRUPT
),
4206 _ER(PENDING_INTERRUPT
),
4226 _ER(IO_INSTRUCTION
),
4229 _ER(MWAIT_INSTRUCTION
),
4230 _ER(MONITOR_INSTRUCTION
),
4231 _ER(PAUSE_INSTRUCTION
),
4232 _ER(MCE_DURING_VMENTRY
),
4233 _ER(TPR_BELOW_THRESHOLD
),
4243 static int vmx_get_lpage_level(void)
4245 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
4246 return PT_DIRECTORY_LEVEL
;
4248 /* For shadow and EPT supported 1GB page */
4249 return PT_PDPE_LEVEL
;
4252 static inline u32
bit(int bitno
)
4254 return 1 << (bitno
& 31);
4257 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4259 struct kvm_cpuid_entry2
*best
;
4260 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4263 vmx
->rdtscp_enabled
= false;
4264 if (vmx_rdtscp_supported()) {
4265 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4266 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4267 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4268 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4269 vmx
->rdtscp_enabled
= true;
4271 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4272 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4279 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4283 static struct kvm_x86_ops vmx_x86_ops
= {
4284 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4285 .disabled_by_bios
= vmx_disabled_by_bios
,
4286 .hardware_setup
= hardware_setup
,
4287 .hardware_unsetup
= hardware_unsetup
,
4288 .check_processor_compatibility
= vmx_check_processor_compat
,
4289 .hardware_enable
= hardware_enable
,
4290 .hardware_disable
= hardware_disable
,
4291 .cpu_has_accelerated_tpr
= report_flexpriority
,
4293 .vcpu_create
= vmx_create_vcpu
,
4294 .vcpu_free
= vmx_free_vcpu
,
4295 .vcpu_reset
= vmx_vcpu_reset
,
4297 .prepare_guest_switch
= vmx_save_host_state
,
4298 .vcpu_load
= vmx_vcpu_load
,
4299 .vcpu_put
= vmx_vcpu_put
,
4301 .set_guest_debug
= set_guest_debug
,
4302 .get_msr
= vmx_get_msr
,
4303 .set_msr
= vmx_set_msr
,
4304 .get_segment_base
= vmx_get_segment_base
,
4305 .get_segment
= vmx_get_segment
,
4306 .set_segment
= vmx_set_segment
,
4307 .get_cpl
= vmx_get_cpl
,
4308 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4309 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
4310 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4311 .set_cr0
= vmx_set_cr0
,
4312 .set_cr3
= vmx_set_cr3
,
4313 .set_cr4
= vmx_set_cr4
,
4314 .set_efer
= vmx_set_efer
,
4315 .get_idt
= vmx_get_idt
,
4316 .set_idt
= vmx_set_idt
,
4317 .get_gdt
= vmx_get_gdt
,
4318 .set_gdt
= vmx_set_gdt
,
4319 .set_dr7
= vmx_set_dr7
,
4320 .cache_reg
= vmx_cache_reg
,
4321 .get_rflags
= vmx_get_rflags
,
4322 .set_rflags
= vmx_set_rflags
,
4323 .fpu_activate
= vmx_fpu_activate
,
4324 .fpu_deactivate
= vmx_fpu_deactivate
,
4326 .tlb_flush
= vmx_flush_tlb
,
4328 .run
= vmx_vcpu_run
,
4329 .handle_exit
= vmx_handle_exit
,
4330 .skip_emulated_instruction
= skip_emulated_instruction
,
4331 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4332 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4333 .patch_hypercall
= vmx_patch_hypercall
,
4334 .set_irq
= vmx_inject_irq
,
4335 .set_nmi
= vmx_inject_nmi
,
4336 .queue_exception
= vmx_queue_exception
,
4337 .interrupt_allowed
= vmx_interrupt_allowed
,
4338 .nmi_allowed
= vmx_nmi_allowed
,
4339 .get_nmi_mask
= vmx_get_nmi_mask
,
4340 .set_nmi_mask
= vmx_set_nmi_mask
,
4341 .enable_nmi_window
= enable_nmi_window
,
4342 .enable_irq_window
= enable_irq_window
,
4343 .update_cr8_intercept
= update_cr8_intercept
,
4345 .set_tss_addr
= vmx_set_tss_addr
,
4346 .get_tdp_level
= get_ept_level
,
4347 .get_mt_mask
= vmx_get_mt_mask
,
4349 .exit_reasons_str
= vmx_exit_reasons_str
,
4350 .get_lpage_level
= vmx_get_lpage_level
,
4352 .cpuid_update
= vmx_cpuid_update
,
4354 .rdtscp_supported
= vmx_rdtscp_supported
,
4356 .set_supported_cpuid
= vmx_set_supported_cpuid
,
4358 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
4361 static int __init
vmx_init(void)
4365 rdmsrl_safe(MSR_EFER
, &host_efer
);
4367 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4368 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4370 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4371 if (!vmx_io_bitmap_a
)
4374 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4375 if (!vmx_io_bitmap_b
) {
4380 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4381 if (!vmx_msr_bitmap_legacy
) {
4386 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4387 if (!vmx_msr_bitmap_longmode
) {
4393 * Allow direct access to the PC debug port (it is often used for I/O
4394 * delays, but the vmexits simply slow things down).
4396 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4397 clear_bit(0x80, vmx_io_bitmap_a
);
4399 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4401 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4402 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4404 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4406 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
4407 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
4411 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4412 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4413 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4414 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4415 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4416 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4419 bypass_guest_pf
= 0;
4420 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
4421 VMX_EPT_WRITABLE_MASK
);
4422 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4423 VMX_EPT_EXECUTABLE_MASK
);
4428 if (bypass_guest_pf
)
4429 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4434 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4436 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4438 free_page((unsigned long)vmx_io_bitmap_b
);
4440 free_page((unsigned long)vmx_io_bitmap_a
);
4444 static void __exit
vmx_exit(void)
4446 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4447 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4448 free_page((unsigned long)vmx_io_bitmap_b
);
4449 free_page((unsigned long)vmx_io_bitmap_a
);
4454 module_init(vmx_init
)
4455 module_exit(vmx_exit
)