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KVM: x2apic interface to lapic
[deliverable/linux.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include <linux/kvm_host.h>
22 #include "irq.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "x86.h"
28
29 #include <linux/clocksource.h>
30 #include <linux/interrupt.h>
31 #include <linux/kvm.h>
32 #include <linux/fs.h>
33 #include <linux/vmalloc.h>
34 #include <linux/module.h>
35 #include <linux/mman.h>
36 #include <linux/highmem.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/cpufreq.h>
40 #include <trace/events/kvm.h>
41 #undef TRACE_INCLUDE_FILE
42 #define CREATE_TRACE_POINTS
43 #include "trace.h"
44
45 #include <asm/uaccess.h>
46 #include <asm/msr.h>
47 #include <asm/desc.h>
48 #include <asm/mtrr.h>
49 #include <asm/mce.h>
50
51 #define MAX_IO_MSRS 256
52 #define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56 #define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
63
64 #define KVM_MAX_MCE_BANKS 32
65 #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
67 /* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71 #ifdef CONFIG_X86_64
72 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73 #else
74 static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75 #endif
76
77 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
79
80 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
82
83 struct kvm_x86_ops *kvm_x86_ops;
84 EXPORT_SYMBOL_GPL(kvm_x86_ops);
85
86 int ignore_msrs = 0;
87 module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
88
89 struct kvm_stats_debugfs_item debugfs_entries[] = {
90 { "pf_fixed", VCPU_STAT(pf_fixed) },
91 { "pf_guest", VCPU_STAT(pf_guest) },
92 { "tlb_flush", VCPU_STAT(tlb_flush) },
93 { "invlpg", VCPU_STAT(invlpg) },
94 { "exits", VCPU_STAT(exits) },
95 { "io_exits", VCPU_STAT(io_exits) },
96 { "mmio_exits", VCPU_STAT(mmio_exits) },
97 { "signal_exits", VCPU_STAT(signal_exits) },
98 { "irq_window", VCPU_STAT(irq_window_exits) },
99 { "nmi_window", VCPU_STAT(nmi_window_exits) },
100 { "halt_exits", VCPU_STAT(halt_exits) },
101 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
102 { "hypercalls", VCPU_STAT(hypercalls) },
103 { "request_irq", VCPU_STAT(request_irq_exits) },
104 { "irq_exits", VCPU_STAT(irq_exits) },
105 { "host_state_reload", VCPU_STAT(host_state_reload) },
106 { "efer_reload", VCPU_STAT(efer_reload) },
107 { "fpu_reload", VCPU_STAT(fpu_reload) },
108 { "insn_emulation", VCPU_STAT(insn_emulation) },
109 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
110 { "irq_injections", VCPU_STAT(irq_injections) },
111 { "nmi_injections", VCPU_STAT(nmi_injections) },
112 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
113 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
114 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
115 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
116 { "mmu_flooded", VM_STAT(mmu_flooded) },
117 { "mmu_recycled", VM_STAT(mmu_recycled) },
118 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
119 { "mmu_unsync", VM_STAT(mmu_unsync) },
120 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
121 { "largepages", VM_STAT(lpages) },
122 { NULL }
123 };
124
125 unsigned long segment_base(u16 selector)
126 {
127 struct descriptor_table gdt;
128 struct desc_struct *d;
129 unsigned long table_base;
130 unsigned long v;
131
132 if (selector == 0)
133 return 0;
134
135 asm("sgdt %0" : "=m"(gdt));
136 table_base = gdt.base;
137
138 if (selector & 4) { /* from ldt */
139 u16 ldt_selector;
140
141 asm("sldt %0" : "=g"(ldt_selector));
142 table_base = segment_base(ldt_selector);
143 }
144 d = (struct desc_struct *)(table_base + (selector & ~7));
145 v = d->base0 | ((unsigned long)d->base1 << 16) |
146 ((unsigned long)d->base2 << 24);
147 #ifdef CONFIG_X86_64
148 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
149 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
150 #endif
151 return v;
152 }
153 EXPORT_SYMBOL_GPL(segment_base);
154
155 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
156 {
157 if (irqchip_in_kernel(vcpu->kvm))
158 return vcpu->arch.apic_base;
159 else
160 return vcpu->arch.apic_base;
161 }
162 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
163
164 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
165 {
166 /* TODO: reserve bits check */
167 if (irqchip_in_kernel(vcpu->kvm))
168 kvm_lapic_set_base(vcpu, data);
169 else
170 vcpu->arch.apic_base = data;
171 }
172 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
173
174 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
175 {
176 WARN_ON(vcpu->arch.exception.pending);
177 vcpu->arch.exception.pending = true;
178 vcpu->arch.exception.has_error_code = false;
179 vcpu->arch.exception.nr = nr;
180 }
181 EXPORT_SYMBOL_GPL(kvm_queue_exception);
182
183 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
184 u32 error_code)
185 {
186 ++vcpu->stat.pf_guest;
187
188 if (vcpu->arch.exception.pending) {
189 switch(vcpu->arch.exception.nr) {
190 case DF_VECTOR:
191 /* triple fault -> shutdown */
192 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
193 return;
194 case PF_VECTOR:
195 vcpu->arch.exception.nr = DF_VECTOR;
196 vcpu->arch.exception.error_code = 0;
197 return;
198 default:
199 /* replace previous exception with a new one in a hope
200 that instruction re-execution will regenerate lost
201 exception */
202 vcpu->arch.exception.pending = false;
203 break;
204 }
205 }
206 vcpu->arch.cr2 = addr;
207 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
208 }
209
210 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
211 {
212 vcpu->arch.nmi_pending = 1;
213 }
214 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
215
216 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
217 {
218 WARN_ON(vcpu->arch.exception.pending);
219 vcpu->arch.exception.pending = true;
220 vcpu->arch.exception.has_error_code = true;
221 vcpu->arch.exception.nr = nr;
222 vcpu->arch.exception.error_code = error_code;
223 }
224 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
225
226 static void __queue_exception(struct kvm_vcpu *vcpu)
227 {
228 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
229 vcpu->arch.exception.has_error_code,
230 vcpu->arch.exception.error_code);
231 }
232
233 /*
234 * Load the pae pdptrs. Return true is they are all valid.
235 */
236 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
237 {
238 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
239 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
240 int i;
241 int ret;
242 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
243
244 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
245 offset * sizeof(u64), sizeof(pdpte));
246 if (ret < 0) {
247 ret = 0;
248 goto out;
249 }
250 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
251 if (is_present_gpte(pdpte[i]) &&
252 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
253 ret = 0;
254 goto out;
255 }
256 }
257 ret = 1;
258
259 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
260 __set_bit(VCPU_EXREG_PDPTR,
261 (unsigned long *)&vcpu->arch.regs_avail);
262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_dirty);
264 out:
265
266 return ret;
267 }
268 EXPORT_SYMBOL_GPL(load_pdptrs);
269
270 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
271 {
272 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
273 bool changed = true;
274 int r;
275
276 if (is_long_mode(vcpu) || !is_pae(vcpu))
277 return false;
278
279 if (!test_bit(VCPU_EXREG_PDPTR,
280 (unsigned long *)&vcpu->arch.regs_avail))
281 return true;
282
283 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
284 if (r < 0)
285 goto out;
286 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
287 out:
288
289 return changed;
290 }
291
292 void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
293 {
294 if (cr0 & CR0_RESERVED_BITS) {
295 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
296 cr0, vcpu->arch.cr0);
297 kvm_inject_gp(vcpu, 0);
298 return;
299 }
300
301 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
302 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
303 kvm_inject_gp(vcpu, 0);
304 return;
305 }
306
307 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
308 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
309 "and a clear PE flag\n");
310 kvm_inject_gp(vcpu, 0);
311 return;
312 }
313
314 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
315 #ifdef CONFIG_X86_64
316 if ((vcpu->arch.shadow_efer & EFER_LME)) {
317 int cs_db, cs_l;
318
319 if (!is_pae(vcpu)) {
320 printk(KERN_DEBUG "set_cr0: #GP, start paging "
321 "in long mode while PAE is disabled\n");
322 kvm_inject_gp(vcpu, 0);
323 return;
324 }
325 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
326 if (cs_l) {
327 printk(KERN_DEBUG "set_cr0: #GP, start paging "
328 "in long mode while CS.L == 1\n");
329 kvm_inject_gp(vcpu, 0);
330 return;
331
332 }
333 } else
334 #endif
335 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
336 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
337 "reserved bits\n");
338 kvm_inject_gp(vcpu, 0);
339 return;
340 }
341
342 }
343
344 kvm_x86_ops->set_cr0(vcpu, cr0);
345 vcpu->arch.cr0 = cr0;
346
347 kvm_mmu_reset_context(vcpu);
348 return;
349 }
350 EXPORT_SYMBOL_GPL(kvm_set_cr0);
351
352 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
353 {
354 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
355 }
356 EXPORT_SYMBOL_GPL(kvm_lmsw);
357
358 void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
359 {
360 unsigned long old_cr4 = vcpu->arch.cr4;
361 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
362
363 if (cr4 & CR4_RESERVED_BITS) {
364 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
365 kvm_inject_gp(vcpu, 0);
366 return;
367 }
368
369 if (is_long_mode(vcpu)) {
370 if (!(cr4 & X86_CR4_PAE)) {
371 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
372 "in long mode\n");
373 kvm_inject_gp(vcpu, 0);
374 return;
375 }
376 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
377 && ((cr4 ^ old_cr4) & pdptr_bits)
378 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
379 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
380 kvm_inject_gp(vcpu, 0);
381 return;
382 }
383
384 if (cr4 & X86_CR4_VMXE) {
385 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
386 kvm_inject_gp(vcpu, 0);
387 return;
388 }
389 kvm_x86_ops->set_cr4(vcpu, cr4);
390 vcpu->arch.cr4 = cr4;
391 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
392 kvm_mmu_reset_context(vcpu);
393 }
394 EXPORT_SYMBOL_GPL(kvm_set_cr4);
395
396 void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
397 {
398 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
399 kvm_mmu_sync_roots(vcpu);
400 kvm_mmu_flush_tlb(vcpu);
401 return;
402 }
403
404 if (is_long_mode(vcpu)) {
405 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
406 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
407 kvm_inject_gp(vcpu, 0);
408 return;
409 }
410 } else {
411 if (is_pae(vcpu)) {
412 if (cr3 & CR3_PAE_RESERVED_BITS) {
413 printk(KERN_DEBUG
414 "set_cr3: #GP, reserved bits\n");
415 kvm_inject_gp(vcpu, 0);
416 return;
417 }
418 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
419 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
420 "reserved bits\n");
421 kvm_inject_gp(vcpu, 0);
422 return;
423 }
424 }
425 /*
426 * We don't check reserved bits in nonpae mode, because
427 * this isn't enforced, and VMware depends on this.
428 */
429 }
430
431 /*
432 * Does the new cr3 value map to physical memory? (Note, we
433 * catch an invalid cr3 even in real-mode, because it would
434 * cause trouble later on when we turn on paging anyway.)
435 *
436 * A real CPU would silently accept an invalid cr3 and would
437 * attempt to use it - with largely undefined (and often hard
438 * to debug) behavior on the guest side.
439 */
440 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
441 kvm_inject_gp(vcpu, 0);
442 else {
443 vcpu->arch.cr3 = cr3;
444 vcpu->arch.mmu.new_cr3(vcpu);
445 }
446 }
447 EXPORT_SYMBOL_GPL(kvm_set_cr3);
448
449 void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
450 {
451 if (cr8 & CR8_RESERVED_BITS) {
452 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
453 kvm_inject_gp(vcpu, 0);
454 return;
455 }
456 if (irqchip_in_kernel(vcpu->kvm))
457 kvm_lapic_set_tpr(vcpu, cr8);
458 else
459 vcpu->arch.cr8 = cr8;
460 }
461 EXPORT_SYMBOL_GPL(kvm_set_cr8);
462
463 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
464 {
465 if (irqchip_in_kernel(vcpu->kvm))
466 return kvm_lapic_get_cr8(vcpu);
467 else
468 return vcpu->arch.cr8;
469 }
470 EXPORT_SYMBOL_GPL(kvm_get_cr8);
471
472 static inline u32 bit(int bitno)
473 {
474 return 1 << (bitno & 31);
475 }
476
477 /*
478 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
479 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
480 *
481 * This list is modified at module load time to reflect the
482 * capabilities of the host cpu.
483 */
484 static u32 msrs_to_save[] = {
485 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
486 MSR_K6_STAR,
487 #ifdef CONFIG_X86_64
488 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
489 #endif
490 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
491 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
492 };
493
494 static unsigned num_msrs_to_save;
495
496 static u32 emulated_msrs[] = {
497 MSR_IA32_MISC_ENABLE,
498 };
499
500 static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
501 {
502 if (efer & efer_reserved_bits) {
503 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
504 efer);
505 kvm_inject_gp(vcpu, 0);
506 return;
507 }
508
509 if (is_paging(vcpu)
510 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
511 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
512 kvm_inject_gp(vcpu, 0);
513 return;
514 }
515
516 if (efer & EFER_FFXSR) {
517 struct kvm_cpuid_entry2 *feat;
518
519 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
520 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
521 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
522 kvm_inject_gp(vcpu, 0);
523 return;
524 }
525 }
526
527 if (efer & EFER_SVME) {
528 struct kvm_cpuid_entry2 *feat;
529
530 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
531 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
532 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
533 kvm_inject_gp(vcpu, 0);
534 return;
535 }
536 }
537
538 kvm_x86_ops->set_efer(vcpu, efer);
539
540 efer &= ~EFER_LMA;
541 efer |= vcpu->arch.shadow_efer & EFER_LMA;
542
543 vcpu->arch.shadow_efer = efer;
544
545 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
546 kvm_mmu_reset_context(vcpu);
547 }
548
549 void kvm_enable_efer_bits(u64 mask)
550 {
551 efer_reserved_bits &= ~mask;
552 }
553 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
554
555
556 /*
557 * Writes msr value into into the appropriate "register".
558 * Returns 0 on success, non-0 otherwise.
559 * Assumes vcpu_load() was already called.
560 */
561 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
562 {
563 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
564 }
565
566 /*
567 * Adapt set_msr() to msr_io()'s calling convention
568 */
569 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
570 {
571 return kvm_set_msr(vcpu, index, *data);
572 }
573
574 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
575 {
576 static int version;
577 struct pvclock_wall_clock wc;
578 struct timespec now, sys, boot;
579
580 if (!wall_clock)
581 return;
582
583 version++;
584
585 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
586
587 /*
588 * The guest calculates current wall clock time by adding
589 * system time (updated by kvm_write_guest_time below) to the
590 * wall clock specified here. guest system time equals host
591 * system time for us, thus we must fill in host boot time here.
592 */
593 now = current_kernel_time();
594 ktime_get_ts(&sys);
595 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
596
597 wc.sec = boot.tv_sec;
598 wc.nsec = boot.tv_nsec;
599 wc.version = version;
600
601 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
602
603 version++;
604 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
605 }
606
607 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
608 {
609 uint32_t quotient, remainder;
610
611 /* Don't try to replace with do_div(), this one calculates
612 * "(dividend << 32) / divisor" */
613 __asm__ ( "divl %4"
614 : "=a" (quotient), "=d" (remainder)
615 : "0" (0), "1" (dividend), "r" (divisor) );
616 return quotient;
617 }
618
619 static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
620 {
621 uint64_t nsecs = 1000000000LL;
622 int32_t shift = 0;
623 uint64_t tps64;
624 uint32_t tps32;
625
626 tps64 = tsc_khz * 1000LL;
627 while (tps64 > nsecs*2) {
628 tps64 >>= 1;
629 shift--;
630 }
631
632 tps32 = (uint32_t)tps64;
633 while (tps32 <= (uint32_t)nsecs) {
634 tps32 <<= 1;
635 shift++;
636 }
637
638 hv_clock->tsc_shift = shift;
639 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
640
641 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
642 __func__, tsc_khz, hv_clock->tsc_shift,
643 hv_clock->tsc_to_system_mul);
644 }
645
646 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
647
648 static void kvm_write_guest_time(struct kvm_vcpu *v)
649 {
650 struct timespec ts;
651 unsigned long flags;
652 struct kvm_vcpu_arch *vcpu = &v->arch;
653 void *shared_kaddr;
654 unsigned long this_tsc_khz;
655
656 if ((!vcpu->time_page))
657 return;
658
659 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
660 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
661 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
662 vcpu->hv_clock_tsc_khz = this_tsc_khz;
663 }
664 put_cpu_var(cpu_tsc_khz);
665
666 /* Keep irq disabled to prevent changes to the clock */
667 local_irq_save(flags);
668 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
669 ktime_get_ts(&ts);
670 local_irq_restore(flags);
671
672 /* With all the info we got, fill in the values */
673
674 vcpu->hv_clock.system_time = ts.tv_nsec +
675 (NSEC_PER_SEC * (u64)ts.tv_sec);
676 /*
677 * The interface expects us to write an even number signaling that the
678 * update is finished. Since the guest won't see the intermediate
679 * state, we just increase by 2 at the end.
680 */
681 vcpu->hv_clock.version += 2;
682
683 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
684
685 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
686 sizeof(vcpu->hv_clock));
687
688 kunmap_atomic(shared_kaddr, KM_USER0);
689
690 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
691 }
692
693 static int kvm_request_guest_time_update(struct kvm_vcpu *v)
694 {
695 struct kvm_vcpu_arch *vcpu = &v->arch;
696
697 if (!vcpu->time_page)
698 return 0;
699 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
700 return 1;
701 }
702
703 static bool msr_mtrr_valid(unsigned msr)
704 {
705 switch (msr) {
706 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
707 case MSR_MTRRfix64K_00000:
708 case MSR_MTRRfix16K_80000:
709 case MSR_MTRRfix16K_A0000:
710 case MSR_MTRRfix4K_C0000:
711 case MSR_MTRRfix4K_C8000:
712 case MSR_MTRRfix4K_D0000:
713 case MSR_MTRRfix4K_D8000:
714 case MSR_MTRRfix4K_E0000:
715 case MSR_MTRRfix4K_E8000:
716 case MSR_MTRRfix4K_F0000:
717 case MSR_MTRRfix4K_F8000:
718 case MSR_MTRRdefType:
719 case MSR_IA32_CR_PAT:
720 return true;
721 case 0x2f8:
722 return true;
723 }
724 return false;
725 }
726
727 static bool valid_pat_type(unsigned t)
728 {
729 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
730 }
731
732 static bool valid_mtrr_type(unsigned t)
733 {
734 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
735 }
736
737 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
738 {
739 int i;
740
741 if (!msr_mtrr_valid(msr))
742 return false;
743
744 if (msr == MSR_IA32_CR_PAT) {
745 for (i = 0; i < 8; i++)
746 if (!valid_pat_type((data >> (i * 8)) & 0xff))
747 return false;
748 return true;
749 } else if (msr == MSR_MTRRdefType) {
750 if (data & ~0xcff)
751 return false;
752 return valid_mtrr_type(data & 0xff);
753 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
754 for (i = 0; i < 8 ; i++)
755 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
756 return false;
757 return true;
758 }
759
760 /* variable MTRRs */
761 return valid_mtrr_type(data & 0xff);
762 }
763
764 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
765 {
766 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
767
768 if (!mtrr_valid(vcpu, msr, data))
769 return 1;
770
771 if (msr == MSR_MTRRdefType) {
772 vcpu->arch.mtrr_state.def_type = data;
773 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
774 } else if (msr == MSR_MTRRfix64K_00000)
775 p[0] = data;
776 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
777 p[1 + msr - MSR_MTRRfix16K_80000] = data;
778 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
779 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
780 else if (msr == MSR_IA32_CR_PAT)
781 vcpu->arch.pat = data;
782 else { /* Variable MTRRs */
783 int idx, is_mtrr_mask;
784 u64 *pt;
785
786 idx = (msr - 0x200) / 2;
787 is_mtrr_mask = msr - 0x200 - 2 * idx;
788 if (!is_mtrr_mask)
789 pt =
790 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
791 else
792 pt =
793 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
794 *pt = data;
795 }
796
797 kvm_mmu_reset_context(vcpu);
798 return 0;
799 }
800
801 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
802 {
803 u64 mcg_cap = vcpu->arch.mcg_cap;
804 unsigned bank_num = mcg_cap & 0xff;
805
806 switch (msr) {
807 case MSR_IA32_MCG_STATUS:
808 vcpu->arch.mcg_status = data;
809 break;
810 case MSR_IA32_MCG_CTL:
811 if (!(mcg_cap & MCG_CTL_P))
812 return 1;
813 if (data != 0 && data != ~(u64)0)
814 return -1;
815 vcpu->arch.mcg_ctl = data;
816 break;
817 default:
818 if (msr >= MSR_IA32_MC0_CTL &&
819 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
820 u32 offset = msr - MSR_IA32_MC0_CTL;
821 /* only 0 or all 1s can be written to IA32_MCi_CTL */
822 if ((offset & 0x3) == 0 &&
823 data != 0 && data != ~(u64)0)
824 return -1;
825 vcpu->arch.mce_banks[offset] = data;
826 break;
827 }
828 return 1;
829 }
830 return 0;
831 }
832
833 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
834 {
835 switch (msr) {
836 case MSR_EFER:
837 set_efer(vcpu, data);
838 break;
839 case MSR_K7_HWCR:
840 data &= ~(u64)0x40; /* ignore flush filter disable */
841 if (data != 0) {
842 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
843 data);
844 return 1;
845 }
846 break;
847 case MSR_AMD64_NB_CFG:
848 break;
849 case MSR_IA32_DEBUGCTLMSR:
850 if (!data) {
851 /* We support the non-activated case already */
852 break;
853 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
854 /* Values other than LBR and BTF are vendor-specific,
855 thus reserved and should throw a #GP */
856 return 1;
857 }
858 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
859 __func__, data);
860 break;
861 case MSR_IA32_UCODE_REV:
862 case MSR_IA32_UCODE_WRITE:
863 case MSR_VM_HSAVE_PA:
864 break;
865 case 0x200 ... 0x2ff:
866 return set_msr_mtrr(vcpu, msr, data);
867 case MSR_IA32_APICBASE:
868 kvm_set_apic_base(vcpu, data);
869 break;
870 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
871 return kvm_x2apic_msr_write(vcpu, msr, data);
872 case MSR_IA32_MISC_ENABLE:
873 vcpu->arch.ia32_misc_enable_msr = data;
874 break;
875 case MSR_KVM_WALL_CLOCK:
876 vcpu->kvm->arch.wall_clock = data;
877 kvm_write_wall_clock(vcpu->kvm, data);
878 break;
879 case MSR_KVM_SYSTEM_TIME: {
880 if (vcpu->arch.time_page) {
881 kvm_release_page_dirty(vcpu->arch.time_page);
882 vcpu->arch.time_page = NULL;
883 }
884
885 vcpu->arch.time = data;
886
887 /* we verify if the enable bit is set... */
888 if (!(data & 1))
889 break;
890
891 /* ...but clean it before doing the actual write */
892 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
893
894 vcpu->arch.time_page =
895 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
896
897 if (is_error_page(vcpu->arch.time_page)) {
898 kvm_release_page_clean(vcpu->arch.time_page);
899 vcpu->arch.time_page = NULL;
900 }
901
902 kvm_request_guest_time_update(vcpu);
903 break;
904 }
905 case MSR_IA32_MCG_CTL:
906 case MSR_IA32_MCG_STATUS:
907 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
908 return set_msr_mce(vcpu, msr, data);
909
910 /* Performance counters are not protected by a CPUID bit,
911 * so we should check all of them in the generic path for the sake of
912 * cross vendor migration.
913 * Writing a zero into the event select MSRs disables them,
914 * which we perfectly emulate ;-). Any other value should be at least
915 * reported, some guests depend on them.
916 */
917 case MSR_P6_EVNTSEL0:
918 case MSR_P6_EVNTSEL1:
919 case MSR_K7_EVNTSEL0:
920 case MSR_K7_EVNTSEL1:
921 case MSR_K7_EVNTSEL2:
922 case MSR_K7_EVNTSEL3:
923 if (data != 0)
924 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
925 "0x%x data 0x%llx\n", msr, data);
926 break;
927 /* at least RHEL 4 unconditionally writes to the perfctr registers,
928 * so we ignore writes to make it happy.
929 */
930 case MSR_P6_PERFCTR0:
931 case MSR_P6_PERFCTR1:
932 case MSR_K7_PERFCTR0:
933 case MSR_K7_PERFCTR1:
934 case MSR_K7_PERFCTR2:
935 case MSR_K7_PERFCTR3:
936 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
937 "0x%x data 0x%llx\n", msr, data);
938 break;
939 default:
940 if (!ignore_msrs) {
941 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
942 msr, data);
943 return 1;
944 } else {
945 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
946 msr, data);
947 break;
948 }
949 }
950 return 0;
951 }
952 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
953
954
955 /*
956 * Reads an msr value (of 'msr_index') into 'pdata'.
957 * Returns 0 on success, non-0 otherwise.
958 * Assumes vcpu_load() was already called.
959 */
960 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
961 {
962 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
963 }
964
965 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
966 {
967 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
968
969 if (!msr_mtrr_valid(msr))
970 return 1;
971
972 if (msr == MSR_MTRRdefType)
973 *pdata = vcpu->arch.mtrr_state.def_type +
974 (vcpu->arch.mtrr_state.enabled << 10);
975 else if (msr == MSR_MTRRfix64K_00000)
976 *pdata = p[0];
977 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
978 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
979 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
980 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
981 else if (msr == MSR_IA32_CR_PAT)
982 *pdata = vcpu->arch.pat;
983 else { /* Variable MTRRs */
984 int idx, is_mtrr_mask;
985 u64 *pt;
986
987 idx = (msr - 0x200) / 2;
988 is_mtrr_mask = msr - 0x200 - 2 * idx;
989 if (!is_mtrr_mask)
990 pt =
991 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
992 else
993 pt =
994 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
995 *pdata = *pt;
996 }
997
998 return 0;
999 }
1000
1001 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1002 {
1003 u64 data;
1004 u64 mcg_cap = vcpu->arch.mcg_cap;
1005 unsigned bank_num = mcg_cap & 0xff;
1006
1007 switch (msr) {
1008 case MSR_IA32_P5_MC_ADDR:
1009 case MSR_IA32_P5_MC_TYPE:
1010 data = 0;
1011 break;
1012 case MSR_IA32_MCG_CAP:
1013 data = vcpu->arch.mcg_cap;
1014 break;
1015 case MSR_IA32_MCG_CTL:
1016 if (!(mcg_cap & MCG_CTL_P))
1017 return 1;
1018 data = vcpu->arch.mcg_ctl;
1019 break;
1020 case MSR_IA32_MCG_STATUS:
1021 data = vcpu->arch.mcg_status;
1022 break;
1023 default:
1024 if (msr >= MSR_IA32_MC0_CTL &&
1025 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1026 u32 offset = msr - MSR_IA32_MC0_CTL;
1027 data = vcpu->arch.mce_banks[offset];
1028 break;
1029 }
1030 return 1;
1031 }
1032 *pdata = data;
1033 return 0;
1034 }
1035
1036 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1037 {
1038 u64 data;
1039
1040 switch (msr) {
1041 case MSR_IA32_PLATFORM_ID:
1042 case MSR_IA32_UCODE_REV:
1043 case MSR_IA32_EBL_CR_POWERON:
1044 case MSR_IA32_DEBUGCTLMSR:
1045 case MSR_IA32_LASTBRANCHFROMIP:
1046 case MSR_IA32_LASTBRANCHTOIP:
1047 case MSR_IA32_LASTINTFROMIP:
1048 case MSR_IA32_LASTINTTOIP:
1049 case MSR_K8_SYSCFG:
1050 case MSR_K7_HWCR:
1051 case MSR_VM_HSAVE_PA:
1052 case MSR_P6_EVNTSEL0:
1053 case MSR_P6_EVNTSEL1:
1054 case MSR_K7_EVNTSEL0:
1055 case MSR_K8_INT_PENDING_MSG:
1056 case MSR_AMD64_NB_CFG:
1057 data = 0;
1058 break;
1059 case MSR_MTRRcap:
1060 data = 0x500 | KVM_NR_VAR_MTRR;
1061 break;
1062 case 0x200 ... 0x2ff:
1063 return get_msr_mtrr(vcpu, msr, pdata);
1064 case 0xcd: /* fsb frequency */
1065 data = 3;
1066 break;
1067 case MSR_IA32_APICBASE:
1068 data = kvm_get_apic_base(vcpu);
1069 break;
1070 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1071 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1072 break;
1073 case MSR_IA32_MISC_ENABLE:
1074 data = vcpu->arch.ia32_misc_enable_msr;
1075 break;
1076 case MSR_IA32_PERF_STATUS:
1077 /* TSC increment by tick */
1078 data = 1000ULL;
1079 /* CPU multiplier */
1080 data |= (((uint64_t)4ULL) << 40);
1081 break;
1082 case MSR_EFER:
1083 data = vcpu->arch.shadow_efer;
1084 break;
1085 case MSR_KVM_WALL_CLOCK:
1086 data = vcpu->kvm->arch.wall_clock;
1087 break;
1088 case MSR_KVM_SYSTEM_TIME:
1089 data = vcpu->arch.time;
1090 break;
1091 case MSR_IA32_P5_MC_ADDR:
1092 case MSR_IA32_P5_MC_TYPE:
1093 case MSR_IA32_MCG_CAP:
1094 case MSR_IA32_MCG_CTL:
1095 case MSR_IA32_MCG_STATUS:
1096 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1097 return get_msr_mce(vcpu, msr, pdata);
1098 default:
1099 if (!ignore_msrs) {
1100 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1101 return 1;
1102 } else {
1103 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1104 data = 0;
1105 }
1106 break;
1107 }
1108 *pdata = data;
1109 return 0;
1110 }
1111 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1112
1113 /*
1114 * Read or write a bunch of msrs. All parameters are kernel addresses.
1115 *
1116 * @return number of msrs set successfully.
1117 */
1118 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1119 struct kvm_msr_entry *entries,
1120 int (*do_msr)(struct kvm_vcpu *vcpu,
1121 unsigned index, u64 *data))
1122 {
1123 int i;
1124
1125 vcpu_load(vcpu);
1126
1127 down_read(&vcpu->kvm->slots_lock);
1128 for (i = 0; i < msrs->nmsrs; ++i)
1129 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1130 break;
1131 up_read(&vcpu->kvm->slots_lock);
1132
1133 vcpu_put(vcpu);
1134
1135 return i;
1136 }
1137
1138 /*
1139 * Read or write a bunch of msrs. Parameters are user addresses.
1140 *
1141 * @return number of msrs set successfully.
1142 */
1143 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1144 int (*do_msr)(struct kvm_vcpu *vcpu,
1145 unsigned index, u64 *data),
1146 int writeback)
1147 {
1148 struct kvm_msrs msrs;
1149 struct kvm_msr_entry *entries;
1150 int r, n;
1151 unsigned size;
1152
1153 r = -EFAULT;
1154 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1155 goto out;
1156
1157 r = -E2BIG;
1158 if (msrs.nmsrs >= MAX_IO_MSRS)
1159 goto out;
1160
1161 r = -ENOMEM;
1162 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1163 entries = vmalloc(size);
1164 if (!entries)
1165 goto out;
1166
1167 r = -EFAULT;
1168 if (copy_from_user(entries, user_msrs->entries, size))
1169 goto out_free;
1170
1171 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1172 if (r < 0)
1173 goto out_free;
1174
1175 r = -EFAULT;
1176 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1177 goto out_free;
1178
1179 r = n;
1180
1181 out_free:
1182 vfree(entries);
1183 out:
1184 return r;
1185 }
1186
1187 int kvm_dev_ioctl_check_extension(long ext)
1188 {
1189 int r;
1190
1191 switch (ext) {
1192 case KVM_CAP_IRQCHIP:
1193 case KVM_CAP_HLT:
1194 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
1195 case KVM_CAP_SET_TSS_ADDR:
1196 case KVM_CAP_EXT_CPUID:
1197 case KVM_CAP_CLOCKSOURCE:
1198 case KVM_CAP_PIT:
1199 case KVM_CAP_NOP_IO_DELAY:
1200 case KVM_CAP_MP_STATE:
1201 case KVM_CAP_SYNC_MMU:
1202 case KVM_CAP_REINJECT_CONTROL:
1203 case KVM_CAP_IRQ_INJECT_STATUS:
1204 case KVM_CAP_ASSIGN_DEV_IRQ:
1205 case KVM_CAP_IRQFD:
1206 case KVM_CAP_PIT2:
1207 r = 1;
1208 break;
1209 case KVM_CAP_COALESCED_MMIO:
1210 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1211 break;
1212 case KVM_CAP_VAPIC:
1213 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1214 break;
1215 case KVM_CAP_NR_VCPUS:
1216 r = KVM_MAX_VCPUS;
1217 break;
1218 case KVM_CAP_NR_MEMSLOTS:
1219 r = KVM_MEMORY_SLOTS;
1220 break;
1221 case KVM_CAP_PV_MMU:
1222 r = !tdp_enabled;
1223 break;
1224 case KVM_CAP_IOMMU:
1225 r = iommu_found();
1226 break;
1227 case KVM_CAP_MCE:
1228 r = KVM_MAX_MCE_BANKS;
1229 break;
1230 default:
1231 r = 0;
1232 break;
1233 }
1234 return r;
1235
1236 }
1237
1238 long kvm_arch_dev_ioctl(struct file *filp,
1239 unsigned int ioctl, unsigned long arg)
1240 {
1241 void __user *argp = (void __user *)arg;
1242 long r;
1243
1244 switch (ioctl) {
1245 case KVM_GET_MSR_INDEX_LIST: {
1246 struct kvm_msr_list __user *user_msr_list = argp;
1247 struct kvm_msr_list msr_list;
1248 unsigned n;
1249
1250 r = -EFAULT;
1251 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1252 goto out;
1253 n = msr_list.nmsrs;
1254 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1255 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1256 goto out;
1257 r = -E2BIG;
1258 if (n < msr_list.nmsrs)
1259 goto out;
1260 r = -EFAULT;
1261 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1262 num_msrs_to_save * sizeof(u32)))
1263 goto out;
1264 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
1265 &emulated_msrs,
1266 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1267 goto out;
1268 r = 0;
1269 break;
1270 }
1271 case KVM_GET_SUPPORTED_CPUID: {
1272 struct kvm_cpuid2 __user *cpuid_arg = argp;
1273 struct kvm_cpuid2 cpuid;
1274
1275 r = -EFAULT;
1276 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1277 goto out;
1278 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1279 cpuid_arg->entries);
1280 if (r)
1281 goto out;
1282
1283 r = -EFAULT;
1284 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1285 goto out;
1286 r = 0;
1287 break;
1288 }
1289 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1290 u64 mce_cap;
1291
1292 mce_cap = KVM_MCE_CAP_SUPPORTED;
1293 r = -EFAULT;
1294 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1295 goto out;
1296 r = 0;
1297 break;
1298 }
1299 default:
1300 r = -EINVAL;
1301 }
1302 out:
1303 return r;
1304 }
1305
1306 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1307 {
1308 kvm_x86_ops->vcpu_load(vcpu, cpu);
1309 kvm_request_guest_time_update(vcpu);
1310 }
1311
1312 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1313 {
1314 kvm_x86_ops->vcpu_put(vcpu);
1315 kvm_put_guest_fpu(vcpu);
1316 }
1317
1318 static int is_efer_nx(void)
1319 {
1320 unsigned long long efer = 0;
1321
1322 rdmsrl_safe(MSR_EFER, &efer);
1323 return efer & EFER_NX;
1324 }
1325
1326 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1327 {
1328 int i;
1329 struct kvm_cpuid_entry2 *e, *entry;
1330
1331 entry = NULL;
1332 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1333 e = &vcpu->arch.cpuid_entries[i];
1334 if (e->function == 0x80000001) {
1335 entry = e;
1336 break;
1337 }
1338 }
1339 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
1340 entry->edx &= ~(1 << 20);
1341 printk(KERN_INFO "kvm: guest NX capability removed\n");
1342 }
1343 }
1344
1345 /* when an old userspace process fills a new kernel module */
1346 static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1347 struct kvm_cpuid *cpuid,
1348 struct kvm_cpuid_entry __user *entries)
1349 {
1350 int r, i;
1351 struct kvm_cpuid_entry *cpuid_entries;
1352
1353 r = -E2BIG;
1354 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1355 goto out;
1356 r = -ENOMEM;
1357 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1358 if (!cpuid_entries)
1359 goto out;
1360 r = -EFAULT;
1361 if (copy_from_user(cpuid_entries, entries,
1362 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1363 goto out_free;
1364 for (i = 0; i < cpuid->nent; i++) {
1365 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1366 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1367 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1368 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1369 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1370 vcpu->arch.cpuid_entries[i].index = 0;
1371 vcpu->arch.cpuid_entries[i].flags = 0;
1372 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1373 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1374 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1375 }
1376 vcpu->arch.cpuid_nent = cpuid->nent;
1377 cpuid_fix_nx_cap(vcpu);
1378 r = 0;
1379 kvm_apic_set_version(vcpu);
1380
1381 out_free:
1382 vfree(cpuid_entries);
1383 out:
1384 return r;
1385 }
1386
1387 static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1388 struct kvm_cpuid2 *cpuid,
1389 struct kvm_cpuid_entry2 __user *entries)
1390 {
1391 int r;
1392
1393 r = -E2BIG;
1394 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1395 goto out;
1396 r = -EFAULT;
1397 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
1398 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
1399 goto out;
1400 vcpu->arch.cpuid_nent = cpuid->nent;
1401 kvm_apic_set_version(vcpu);
1402 return 0;
1403
1404 out:
1405 return r;
1406 }
1407
1408 static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1409 struct kvm_cpuid2 *cpuid,
1410 struct kvm_cpuid_entry2 __user *entries)
1411 {
1412 int r;
1413
1414 r = -E2BIG;
1415 if (cpuid->nent < vcpu->arch.cpuid_nent)
1416 goto out;
1417 r = -EFAULT;
1418 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1419 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
1420 goto out;
1421 return 0;
1422
1423 out:
1424 cpuid->nent = vcpu->arch.cpuid_nent;
1425 return r;
1426 }
1427
1428 static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1429 u32 index)
1430 {
1431 entry->function = function;
1432 entry->index = index;
1433 cpuid_count(entry->function, entry->index,
1434 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1435 entry->flags = 0;
1436 }
1437
1438 #define F(x) bit(X86_FEATURE_##x)
1439
1440 static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1441 u32 index, int *nent, int maxnent)
1442 {
1443 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
1444 #ifdef CONFIG_X86_64
1445 unsigned f_lm = F(LM);
1446 #else
1447 unsigned f_lm = 0;
1448 #endif
1449
1450 /* cpuid 1.edx */
1451 const u32 kvm_supported_word0_x86_features =
1452 F(FPU) | F(VME) | F(DE) | F(PSE) |
1453 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1454 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1455 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1456 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1457 0 /* Reserved, DS, ACPI */ | F(MMX) |
1458 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1459 0 /* HTT, TM, Reserved, PBE */;
1460 /* cpuid 0x80000001.edx */
1461 const u32 kvm_supported_word1_x86_features =
1462 F(FPU) | F(VME) | F(DE) | F(PSE) |
1463 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1464 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1465 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1466 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1467 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1468 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1469 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1470 /* cpuid 1.ecx */
1471 const u32 kvm_supported_word4_x86_features =
1472 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1473 0 /* DS-CPL, VMX, SMX, EST */ |
1474 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1475 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1476 0 /* Reserved, DCA */ | F(XMM4_1) |
1477 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
1478 0 /* Reserved, XSAVE, OSXSAVE */;
1479 /* cpuid 0x80000001.ecx */
1480 const u32 kvm_supported_word6_x86_features =
1481 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1482 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1483 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1484 0 /* SKINIT */ | 0 /* WDT */;
1485
1486 /* all calls to cpuid_count() should be made on the same cpu */
1487 get_cpu();
1488 do_cpuid_1_ent(entry, function, index);
1489 ++*nent;
1490
1491 switch (function) {
1492 case 0:
1493 entry->eax = min(entry->eax, (u32)0xb);
1494 break;
1495 case 1:
1496 entry->edx &= kvm_supported_word0_x86_features;
1497 entry->ecx &= kvm_supported_word4_x86_features;
1498 break;
1499 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1500 * may return different values. This forces us to get_cpu() before
1501 * issuing the first command, and also to emulate this annoying behavior
1502 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1503 case 2: {
1504 int t, times = entry->eax & 0xff;
1505
1506 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1507 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
1508 for (t = 1; t < times && *nent < maxnent; ++t) {
1509 do_cpuid_1_ent(&entry[t], function, 0);
1510 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1511 ++*nent;
1512 }
1513 break;
1514 }
1515 /* function 4 and 0xb have additional index. */
1516 case 4: {
1517 int i, cache_type;
1518
1519 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1520 /* read more entries until cache_type is zero */
1521 for (i = 1; *nent < maxnent; ++i) {
1522 cache_type = entry[i - 1].eax & 0x1f;
1523 if (!cache_type)
1524 break;
1525 do_cpuid_1_ent(&entry[i], function, i);
1526 entry[i].flags |=
1527 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1528 ++*nent;
1529 }
1530 break;
1531 }
1532 case 0xb: {
1533 int i, level_type;
1534
1535 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1536 /* read more entries until level_type is zero */
1537 for (i = 1; *nent < maxnent; ++i) {
1538 level_type = entry[i - 1].ecx & 0xff00;
1539 if (!level_type)
1540 break;
1541 do_cpuid_1_ent(&entry[i], function, i);
1542 entry[i].flags |=
1543 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1544 ++*nent;
1545 }
1546 break;
1547 }
1548 case 0x80000000:
1549 entry->eax = min(entry->eax, 0x8000001a);
1550 break;
1551 case 0x80000001:
1552 entry->edx &= kvm_supported_word1_x86_features;
1553 entry->ecx &= kvm_supported_word6_x86_features;
1554 break;
1555 }
1556 put_cpu();
1557 }
1558
1559 #undef F
1560
1561 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
1562 struct kvm_cpuid_entry2 __user *entries)
1563 {
1564 struct kvm_cpuid_entry2 *cpuid_entries;
1565 int limit, nent = 0, r = -E2BIG;
1566 u32 func;
1567
1568 if (cpuid->nent < 1)
1569 goto out;
1570 r = -ENOMEM;
1571 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1572 if (!cpuid_entries)
1573 goto out;
1574
1575 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1576 limit = cpuid_entries[0].eax;
1577 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1578 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1579 &nent, cpuid->nent);
1580 r = -E2BIG;
1581 if (nent >= cpuid->nent)
1582 goto out_free;
1583
1584 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1585 limit = cpuid_entries[nent - 1].eax;
1586 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1587 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1588 &nent, cpuid->nent);
1589 r = -E2BIG;
1590 if (nent >= cpuid->nent)
1591 goto out_free;
1592
1593 r = -EFAULT;
1594 if (copy_to_user(entries, cpuid_entries,
1595 nent * sizeof(struct kvm_cpuid_entry2)))
1596 goto out_free;
1597 cpuid->nent = nent;
1598 r = 0;
1599
1600 out_free:
1601 vfree(cpuid_entries);
1602 out:
1603 return r;
1604 }
1605
1606 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1607 struct kvm_lapic_state *s)
1608 {
1609 vcpu_load(vcpu);
1610 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
1611 vcpu_put(vcpu);
1612
1613 return 0;
1614 }
1615
1616 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1617 struct kvm_lapic_state *s)
1618 {
1619 vcpu_load(vcpu);
1620 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
1621 kvm_apic_post_state_restore(vcpu);
1622 vcpu_put(vcpu);
1623
1624 return 0;
1625 }
1626
1627 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1628 struct kvm_interrupt *irq)
1629 {
1630 if (irq->irq < 0 || irq->irq >= 256)
1631 return -EINVAL;
1632 if (irqchip_in_kernel(vcpu->kvm))
1633 return -ENXIO;
1634 vcpu_load(vcpu);
1635
1636 kvm_queue_interrupt(vcpu, irq->irq, false);
1637
1638 vcpu_put(vcpu);
1639
1640 return 0;
1641 }
1642
1643 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1644 {
1645 vcpu_load(vcpu);
1646 kvm_inject_nmi(vcpu);
1647 vcpu_put(vcpu);
1648
1649 return 0;
1650 }
1651
1652 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1653 struct kvm_tpr_access_ctl *tac)
1654 {
1655 if (tac->flags)
1656 return -EINVAL;
1657 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1658 return 0;
1659 }
1660
1661 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1662 u64 mcg_cap)
1663 {
1664 int r;
1665 unsigned bank_num = mcg_cap & 0xff, bank;
1666
1667 r = -EINVAL;
1668 if (!bank_num)
1669 goto out;
1670 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1671 goto out;
1672 r = 0;
1673 vcpu->arch.mcg_cap = mcg_cap;
1674 /* Init IA32_MCG_CTL to all 1s */
1675 if (mcg_cap & MCG_CTL_P)
1676 vcpu->arch.mcg_ctl = ~(u64)0;
1677 /* Init IA32_MCi_CTL to all 1s */
1678 for (bank = 0; bank < bank_num; bank++)
1679 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1680 out:
1681 return r;
1682 }
1683
1684 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1685 struct kvm_x86_mce *mce)
1686 {
1687 u64 mcg_cap = vcpu->arch.mcg_cap;
1688 unsigned bank_num = mcg_cap & 0xff;
1689 u64 *banks = vcpu->arch.mce_banks;
1690
1691 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1692 return -EINVAL;
1693 /*
1694 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1695 * reporting is disabled
1696 */
1697 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1698 vcpu->arch.mcg_ctl != ~(u64)0)
1699 return 0;
1700 banks += 4 * mce->bank;
1701 /*
1702 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1703 * reporting is disabled for the bank
1704 */
1705 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1706 return 0;
1707 if (mce->status & MCI_STATUS_UC) {
1708 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1709 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1710 printk(KERN_DEBUG "kvm: set_mce: "
1711 "injects mce exception while "
1712 "previous one is in progress!\n");
1713 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1714 return 0;
1715 }
1716 if (banks[1] & MCI_STATUS_VAL)
1717 mce->status |= MCI_STATUS_OVER;
1718 banks[2] = mce->addr;
1719 banks[3] = mce->misc;
1720 vcpu->arch.mcg_status = mce->mcg_status;
1721 banks[1] = mce->status;
1722 kvm_queue_exception(vcpu, MC_VECTOR);
1723 } else if (!(banks[1] & MCI_STATUS_VAL)
1724 || !(banks[1] & MCI_STATUS_UC)) {
1725 if (banks[1] & MCI_STATUS_VAL)
1726 mce->status |= MCI_STATUS_OVER;
1727 banks[2] = mce->addr;
1728 banks[3] = mce->misc;
1729 banks[1] = mce->status;
1730 } else
1731 banks[1] |= MCI_STATUS_OVER;
1732 return 0;
1733 }
1734
1735 long kvm_arch_vcpu_ioctl(struct file *filp,
1736 unsigned int ioctl, unsigned long arg)
1737 {
1738 struct kvm_vcpu *vcpu = filp->private_data;
1739 void __user *argp = (void __user *)arg;
1740 int r;
1741 struct kvm_lapic_state *lapic = NULL;
1742
1743 switch (ioctl) {
1744 case KVM_GET_LAPIC: {
1745 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1746
1747 r = -ENOMEM;
1748 if (!lapic)
1749 goto out;
1750 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
1751 if (r)
1752 goto out;
1753 r = -EFAULT;
1754 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
1755 goto out;
1756 r = 0;
1757 break;
1758 }
1759 case KVM_SET_LAPIC: {
1760 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1761 r = -ENOMEM;
1762 if (!lapic)
1763 goto out;
1764 r = -EFAULT;
1765 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
1766 goto out;
1767 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
1768 if (r)
1769 goto out;
1770 r = 0;
1771 break;
1772 }
1773 case KVM_INTERRUPT: {
1774 struct kvm_interrupt irq;
1775
1776 r = -EFAULT;
1777 if (copy_from_user(&irq, argp, sizeof irq))
1778 goto out;
1779 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1780 if (r)
1781 goto out;
1782 r = 0;
1783 break;
1784 }
1785 case KVM_NMI: {
1786 r = kvm_vcpu_ioctl_nmi(vcpu);
1787 if (r)
1788 goto out;
1789 r = 0;
1790 break;
1791 }
1792 case KVM_SET_CPUID: {
1793 struct kvm_cpuid __user *cpuid_arg = argp;
1794 struct kvm_cpuid cpuid;
1795
1796 r = -EFAULT;
1797 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1798 goto out;
1799 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1800 if (r)
1801 goto out;
1802 break;
1803 }
1804 case KVM_SET_CPUID2: {
1805 struct kvm_cpuid2 __user *cpuid_arg = argp;
1806 struct kvm_cpuid2 cpuid;
1807
1808 r = -EFAULT;
1809 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1810 goto out;
1811 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1812 cpuid_arg->entries);
1813 if (r)
1814 goto out;
1815 break;
1816 }
1817 case KVM_GET_CPUID2: {
1818 struct kvm_cpuid2 __user *cpuid_arg = argp;
1819 struct kvm_cpuid2 cpuid;
1820
1821 r = -EFAULT;
1822 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1823 goto out;
1824 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1825 cpuid_arg->entries);
1826 if (r)
1827 goto out;
1828 r = -EFAULT;
1829 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1830 goto out;
1831 r = 0;
1832 break;
1833 }
1834 case KVM_GET_MSRS:
1835 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1836 break;
1837 case KVM_SET_MSRS:
1838 r = msr_io(vcpu, argp, do_set_msr, 0);
1839 break;
1840 case KVM_TPR_ACCESS_REPORTING: {
1841 struct kvm_tpr_access_ctl tac;
1842
1843 r = -EFAULT;
1844 if (copy_from_user(&tac, argp, sizeof tac))
1845 goto out;
1846 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1847 if (r)
1848 goto out;
1849 r = -EFAULT;
1850 if (copy_to_user(argp, &tac, sizeof tac))
1851 goto out;
1852 r = 0;
1853 break;
1854 };
1855 case KVM_SET_VAPIC_ADDR: {
1856 struct kvm_vapic_addr va;
1857
1858 r = -EINVAL;
1859 if (!irqchip_in_kernel(vcpu->kvm))
1860 goto out;
1861 r = -EFAULT;
1862 if (copy_from_user(&va, argp, sizeof va))
1863 goto out;
1864 r = 0;
1865 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1866 break;
1867 }
1868 case KVM_X86_SETUP_MCE: {
1869 u64 mcg_cap;
1870
1871 r = -EFAULT;
1872 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1873 goto out;
1874 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1875 break;
1876 }
1877 case KVM_X86_SET_MCE: {
1878 struct kvm_x86_mce mce;
1879
1880 r = -EFAULT;
1881 if (copy_from_user(&mce, argp, sizeof mce))
1882 goto out;
1883 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1884 break;
1885 }
1886 default:
1887 r = -EINVAL;
1888 }
1889 out:
1890 kfree(lapic);
1891 return r;
1892 }
1893
1894 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1895 {
1896 int ret;
1897
1898 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1899 return -1;
1900 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1901 return ret;
1902 }
1903
1904 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1905 u32 kvm_nr_mmu_pages)
1906 {
1907 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1908 return -EINVAL;
1909
1910 down_write(&kvm->slots_lock);
1911 spin_lock(&kvm->mmu_lock);
1912
1913 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
1914 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1915
1916 spin_unlock(&kvm->mmu_lock);
1917 up_write(&kvm->slots_lock);
1918 return 0;
1919 }
1920
1921 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1922 {
1923 return kvm->arch.n_alloc_mmu_pages;
1924 }
1925
1926 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1927 {
1928 int i;
1929 struct kvm_mem_alias *alias;
1930
1931 for (i = 0; i < kvm->arch.naliases; ++i) {
1932 alias = &kvm->arch.aliases[i];
1933 if (gfn >= alias->base_gfn
1934 && gfn < alias->base_gfn + alias->npages)
1935 return alias->target_gfn + gfn - alias->base_gfn;
1936 }
1937 return gfn;
1938 }
1939
1940 /*
1941 * Set a new alias region. Aliases map a portion of physical memory into
1942 * another portion. This is useful for memory windows, for example the PC
1943 * VGA region.
1944 */
1945 static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1946 struct kvm_memory_alias *alias)
1947 {
1948 int r, n;
1949 struct kvm_mem_alias *p;
1950
1951 r = -EINVAL;
1952 /* General sanity checks */
1953 if (alias->memory_size & (PAGE_SIZE - 1))
1954 goto out;
1955 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1956 goto out;
1957 if (alias->slot >= KVM_ALIAS_SLOTS)
1958 goto out;
1959 if (alias->guest_phys_addr + alias->memory_size
1960 < alias->guest_phys_addr)
1961 goto out;
1962 if (alias->target_phys_addr + alias->memory_size
1963 < alias->target_phys_addr)
1964 goto out;
1965
1966 down_write(&kvm->slots_lock);
1967 spin_lock(&kvm->mmu_lock);
1968
1969 p = &kvm->arch.aliases[alias->slot];
1970 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1971 p->npages = alias->memory_size >> PAGE_SHIFT;
1972 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1973
1974 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
1975 if (kvm->arch.aliases[n - 1].npages)
1976 break;
1977 kvm->arch.naliases = n;
1978
1979 spin_unlock(&kvm->mmu_lock);
1980 kvm_mmu_zap_all(kvm);
1981
1982 up_write(&kvm->slots_lock);
1983
1984 return 0;
1985
1986 out:
1987 return r;
1988 }
1989
1990 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1991 {
1992 int r;
1993
1994 r = 0;
1995 switch (chip->chip_id) {
1996 case KVM_IRQCHIP_PIC_MASTER:
1997 memcpy(&chip->chip.pic,
1998 &pic_irqchip(kvm)->pics[0],
1999 sizeof(struct kvm_pic_state));
2000 break;
2001 case KVM_IRQCHIP_PIC_SLAVE:
2002 memcpy(&chip->chip.pic,
2003 &pic_irqchip(kvm)->pics[1],
2004 sizeof(struct kvm_pic_state));
2005 break;
2006 case KVM_IRQCHIP_IOAPIC:
2007 memcpy(&chip->chip.ioapic,
2008 ioapic_irqchip(kvm),
2009 sizeof(struct kvm_ioapic_state));
2010 break;
2011 default:
2012 r = -EINVAL;
2013 break;
2014 }
2015 return r;
2016 }
2017
2018 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2019 {
2020 int r;
2021
2022 r = 0;
2023 switch (chip->chip_id) {
2024 case KVM_IRQCHIP_PIC_MASTER:
2025 spin_lock(&pic_irqchip(kvm)->lock);
2026 memcpy(&pic_irqchip(kvm)->pics[0],
2027 &chip->chip.pic,
2028 sizeof(struct kvm_pic_state));
2029 spin_unlock(&pic_irqchip(kvm)->lock);
2030 break;
2031 case KVM_IRQCHIP_PIC_SLAVE:
2032 spin_lock(&pic_irqchip(kvm)->lock);
2033 memcpy(&pic_irqchip(kvm)->pics[1],
2034 &chip->chip.pic,
2035 sizeof(struct kvm_pic_state));
2036 spin_unlock(&pic_irqchip(kvm)->lock);
2037 break;
2038 case KVM_IRQCHIP_IOAPIC:
2039 mutex_lock(&kvm->irq_lock);
2040 memcpy(ioapic_irqchip(kvm),
2041 &chip->chip.ioapic,
2042 sizeof(struct kvm_ioapic_state));
2043 mutex_unlock(&kvm->irq_lock);
2044 break;
2045 default:
2046 r = -EINVAL;
2047 break;
2048 }
2049 kvm_pic_update_irq(pic_irqchip(kvm));
2050 return r;
2051 }
2052
2053 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2054 {
2055 int r = 0;
2056
2057 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2058 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2059 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2060 return r;
2061 }
2062
2063 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2064 {
2065 int r = 0;
2066
2067 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2068 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2069 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
2070 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2071 return r;
2072 }
2073
2074 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2075 struct kvm_reinject_control *control)
2076 {
2077 if (!kvm->arch.vpit)
2078 return -ENXIO;
2079 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2080 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2081 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2082 return 0;
2083 }
2084
2085 /*
2086 * Get (and clear) the dirty memory log for a memory slot.
2087 */
2088 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2089 struct kvm_dirty_log *log)
2090 {
2091 int r;
2092 int n;
2093 struct kvm_memory_slot *memslot;
2094 int is_dirty = 0;
2095
2096 down_write(&kvm->slots_lock);
2097
2098 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2099 if (r)
2100 goto out;
2101
2102 /* If nothing is dirty, don't bother messing with page tables. */
2103 if (is_dirty) {
2104 spin_lock(&kvm->mmu_lock);
2105 kvm_mmu_slot_remove_write_access(kvm, log->slot);
2106 spin_unlock(&kvm->mmu_lock);
2107 kvm_flush_remote_tlbs(kvm);
2108 memslot = &kvm->memslots[log->slot];
2109 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2110 memset(memslot->dirty_bitmap, 0, n);
2111 }
2112 r = 0;
2113 out:
2114 up_write(&kvm->slots_lock);
2115 return r;
2116 }
2117
2118 long kvm_arch_vm_ioctl(struct file *filp,
2119 unsigned int ioctl, unsigned long arg)
2120 {
2121 struct kvm *kvm = filp->private_data;
2122 void __user *argp = (void __user *)arg;
2123 int r = -EINVAL;
2124 /*
2125 * This union makes it completely explicit to gcc-3.x
2126 * that these two variables' stack usage should be
2127 * combined, not added together.
2128 */
2129 union {
2130 struct kvm_pit_state ps;
2131 struct kvm_memory_alias alias;
2132 struct kvm_pit_config pit_config;
2133 } u;
2134
2135 switch (ioctl) {
2136 case KVM_SET_TSS_ADDR:
2137 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2138 if (r < 0)
2139 goto out;
2140 break;
2141 case KVM_SET_MEMORY_REGION: {
2142 struct kvm_memory_region kvm_mem;
2143 struct kvm_userspace_memory_region kvm_userspace_mem;
2144
2145 r = -EFAULT;
2146 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2147 goto out;
2148 kvm_userspace_mem.slot = kvm_mem.slot;
2149 kvm_userspace_mem.flags = kvm_mem.flags;
2150 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2151 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2152 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2153 if (r)
2154 goto out;
2155 break;
2156 }
2157 case KVM_SET_NR_MMU_PAGES:
2158 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2159 if (r)
2160 goto out;
2161 break;
2162 case KVM_GET_NR_MMU_PAGES:
2163 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2164 break;
2165 case KVM_SET_MEMORY_ALIAS:
2166 r = -EFAULT;
2167 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
2168 goto out;
2169 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
2170 if (r)
2171 goto out;
2172 break;
2173 case KVM_CREATE_IRQCHIP:
2174 r = -ENOMEM;
2175 kvm->arch.vpic = kvm_create_pic(kvm);
2176 if (kvm->arch.vpic) {
2177 r = kvm_ioapic_init(kvm);
2178 if (r) {
2179 kfree(kvm->arch.vpic);
2180 kvm->arch.vpic = NULL;
2181 goto out;
2182 }
2183 } else
2184 goto out;
2185 r = kvm_setup_default_irq_routing(kvm);
2186 if (r) {
2187 kfree(kvm->arch.vpic);
2188 kfree(kvm->arch.vioapic);
2189 goto out;
2190 }
2191 break;
2192 case KVM_CREATE_PIT:
2193 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2194 goto create_pit;
2195 case KVM_CREATE_PIT2:
2196 r = -EFAULT;
2197 if (copy_from_user(&u.pit_config, argp,
2198 sizeof(struct kvm_pit_config)))
2199 goto out;
2200 create_pit:
2201 down_write(&kvm->slots_lock);
2202 r = -EEXIST;
2203 if (kvm->arch.vpit)
2204 goto create_pit_unlock;
2205 r = -ENOMEM;
2206 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
2207 if (kvm->arch.vpit)
2208 r = 0;
2209 create_pit_unlock:
2210 up_write(&kvm->slots_lock);
2211 break;
2212 case KVM_IRQ_LINE_STATUS:
2213 case KVM_IRQ_LINE: {
2214 struct kvm_irq_level irq_event;
2215
2216 r = -EFAULT;
2217 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2218 goto out;
2219 if (irqchip_in_kernel(kvm)) {
2220 __s32 status;
2221 mutex_lock(&kvm->irq_lock);
2222 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2223 irq_event.irq, irq_event.level);
2224 mutex_unlock(&kvm->irq_lock);
2225 if (ioctl == KVM_IRQ_LINE_STATUS) {
2226 irq_event.status = status;
2227 if (copy_to_user(argp, &irq_event,
2228 sizeof irq_event))
2229 goto out;
2230 }
2231 r = 0;
2232 }
2233 break;
2234 }
2235 case KVM_GET_IRQCHIP: {
2236 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2237 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2238
2239 r = -ENOMEM;
2240 if (!chip)
2241 goto out;
2242 r = -EFAULT;
2243 if (copy_from_user(chip, argp, sizeof *chip))
2244 goto get_irqchip_out;
2245 r = -ENXIO;
2246 if (!irqchip_in_kernel(kvm))
2247 goto get_irqchip_out;
2248 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
2249 if (r)
2250 goto get_irqchip_out;
2251 r = -EFAULT;
2252 if (copy_to_user(argp, chip, sizeof *chip))
2253 goto get_irqchip_out;
2254 r = 0;
2255 get_irqchip_out:
2256 kfree(chip);
2257 if (r)
2258 goto out;
2259 break;
2260 }
2261 case KVM_SET_IRQCHIP: {
2262 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
2263 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
2264
2265 r = -ENOMEM;
2266 if (!chip)
2267 goto out;
2268 r = -EFAULT;
2269 if (copy_from_user(chip, argp, sizeof *chip))
2270 goto set_irqchip_out;
2271 r = -ENXIO;
2272 if (!irqchip_in_kernel(kvm))
2273 goto set_irqchip_out;
2274 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
2275 if (r)
2276 goto set_irqchip_out;
2277 r = 0;
2278 set_irqchip_out:
2279 kfree(chip);
2280 if (r)
2281 goto out;
2282 break;
2283 }
2284 case KVM_GET_PIT: {
2285 r = -EFAULT;
2286 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
2287 goto out;
2288 r = -ENXIO;
2289 if (!kvm->arch.vpit)
2290 goto out;
2291 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
2292 if (r)
2293 goto out;
2294 r = -EFAULT;
2295 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
2296 goto out;
2297 r = 0;
2298 break;
2299 }
2300 case KVM_SET_PIT: {
2301 r = -EFAULT;
2302 if (copy_from_user(&u.ps, argp, sizeof u.ps))
2303 goto out;
2304 r = -ENXIO;
2305 if (!kvm->arch.vpit)
2306 goto out;
2307 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
2308 if (r)
2309 goto out;
2310 r = 0;
2311 break;
2312 }
2313 case KVM_REINJECT_CONTROL: {
2314 struct kvm_reinject_control control;
2315 r = -EFAULT;
2316 if (copy_from_user(&control, argp, sizeof(control)))
2317 goto out;
2318 r = kvm_vm_ioctl_reinject(kvm, &control);
2319 if (r)
2320 goto out;
2321 r = 0;
2322 break;
2323 }
2324 default:
2325 ;
2326 }
2327 out:
2328 return r;
2329 }
2330
2331 static void kvm_init_msr_list(void)
2332 {
2333 u32 dummy[2];
2334 unsigned i, j;
2335
2336 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2337 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2338 continue;
2339 if (j < i)
2340 msrs_to_save[j] = msrs_to_save[i];
2341 j++;
2342 }
2343 num_msrs_to_save = j;
2344 }
2345
2346 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2347 const void *v)
2348 {
2349 if (vcpu->arch.apic &&
2350 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2351 return 0;
2352
2353 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
2354 }
2355
2356 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
2357 {
2358 if (vcpu->arch.apic &&
2359 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2360 return 0;
2361
2362 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
2363 }
2364
2365 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2366 struct kvm_vcpu *vcpu)
2367 {
2368 void *data = val;
2369 int r = X86EMUL_CONTINUE;
2370
2371 while (bytes) {
2372 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2373 unsigned offset = addr & (PAGE_SIZE-1);
2374 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
2375 int ret;
2376
2377 if (gpa == UNMAPPED_GVA) {
2378 r = X86EMUL_PROPAGATE_FAULT;
2379 goto out;
2380 }
2381 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
2382 if (ret < 0) {
2383 r = X86EMUL_UNHANDLEABLE;
2384 goto out;
2385 }
2386
2387 bytes -= toread;
2388 data += toread;
2389 addr += toread;
2390 }
2391 out:
2392 return r;
2393 }
2394
2395 static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2396 struct kvm_vcpu *vcpu)
2397 {
2398 void *data = val;
2399 int r = X86EMUL_CONTINUE;
2400
2401 while (bytes) {
2402 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2403 unsigned offset = addr & (PAGE_SIZE-1);
2404 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2405 int ret;
2406
2407 if (gpa == UNMAPPED_GVA) {
2408 r = X86EMUL_PROPAGATE_FAULT;
2409 goto out;
2410 }
2411 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2412 if (ret < 0) {
2413 r = X86EMUL_UNHANDLEABLE;
2414 goto out;
2415 }
2416
2417 bytes -= towrite;
2418 data += towrite;
2419 addr += towrite;
2420 }
2421 out:
2422 return r;
2423 }
2424
2425
2426 static int emulator_read_emulated(unsigned long addr,
2427 void *val,
2428 unsigned int bytes,
2429 struct kvm_vcpu *vcpu)
2430 {
2431 gpa_t gpa;
2432
2433 if (vcpu->mmio_read_completed) {
2434 memcpy(val, vcpu->mmio_data, bytes);
2435 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2436 vcpu->mmio_phys_addr, *(u64 *)val);
2437 vcpu->mmio_read_completed = 0;
2438 return X86EMUL_CONTINUE;
2439 }
2440
2441 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2442
2443 /* For APIC access vmexit */
2444 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2445 goto mmio;
2446
2447 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2448 == X86EMUL_CONTINUE)
2449 return X86EMUL_CONTINUE;
2450 if (gpa == UNMAPPED_GVA)
2451 return X86EMUL_PROPAGATE_FAULT;
2452
2453 mmio:
2454 /*
2455 * Is this MMIO handled locally?
2456 */
2457 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2458 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
2459 return X86EMUL_CONTINUE;
2460 }
2461
2462 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
2463
2464 vcpu->mmio_needed = 1;
2465 vcpu->mmio_phys_addr = gpa;
2466 vcpu->mmio_size = bytes;
2467 vcpu->mmio_is_write = 0;
2468
2469 return X86EMUL_UNHANDLEABLE;
2470 }
2471
2472 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
2473 const void *val, int bytes)
2474 {
2475 int ret;
2476
2477 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
2478 if (ret < 0)
2479 return 0;
2480 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
2481 return 1;
2482 }
2483
2484 static int emulator_write_emulated_onepage(unsigned long addr,
2485 const void *val,
2486 unsigned int bytes,
2487 struct kvm_vcpu *vcpu)
2488 {
2489 gpa_t gpa;
2490
2491 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2492
2493 if (gpa == UNMAPPED_GVA) {
2494 kvm_inject_page_fault(vcpu, addr, 2);
2495 return X86EMUL_PROPAGATE_FAULT;
2496 }
2497
2498 /* For APIC access vmexit */
2499 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2500 goto mmio;
2501
2502 if (emulator_write_phys(vcpu, gpa, val, bytes))
2503 return X86EMUL_CONTINUE;
2504
2505 mmio:
2506 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
2507 /*
2508 * Is this MMIO handled locally?
2509 */
2510 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
2511 return X86EMUL_CONTINUE;
2512
2513 vcpu->mmio_needed = 1;
2514 vcpu->mmio_phys_addr = gpa;
2515 vcpu->mmio_size = bytes;
2516 vcpu->mmio_is_write = 1;
2517 memcpy(vcpu->mmio_data, val, bytes);
2518
2519 return X86EMUL_CONTINUE;
2520 }
2521
2522 int emulator_write_emulated(unsigned long addr,
2523 const void *val,
2524 unsigned int bytes,
2525 struct kvm_vcpu *vcpu)
2526 {
2527 /* Crossing a page boundary? */
2528 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2529 int rc, now;
2530
2531 now = -addr & ~PAGE_MASK;
2532 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2533 if (rc != X86EMUL_CONTINUE)
2534 return rc;
2535 addr += now;
2536 val += now;
2537 bytes -= now;
2538 }
2539 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2540 }
2541 EXPORT_SYMBOL_GPL(emulator_write_emulated);
2542
2543 static int emulator_cmpxchg_emulated(unsigned long addr,
2544 const void *old,
2545 const void *new,
2546 unsigned int bytes,
2547 struct kvm_vcpu *vcpu)
2548 {
2549 static int reported;
2550
2551 if (!reported) {
2552 reported = 1;
2553 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2554 }
2555 #ifndef CONFIG_X86_64
2556 /* guests cmpxchg8b have to be emulated atomically */
2557 if (bytes == 8) {
2558 gpa_t gpa;
2559 struct page *page;
2560 char *kaddr;
2561 u64 val;
2562
2563 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2564
2565 if (gpa == UNMAPPED_GVA ||
2566 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2567 goto emul_write;
2568
2569 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2570 goto emul_write;
2571
2572 val = *(u64 *)new;
2573
2574 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2575
2576 kaddr = kmap_atomic(page, KM_USER0);
2577 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2578 kunmap_atomic(kaddr, KM_USER0);
2579 kvm_release_page_dirty(page);
2580 }
2581 emul_write:
2582 #endif
2583
2584 return emulator_write_emulated(addr, new, bytes, vcpu);
2585 }
2586
2587 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2588 {
2589 return kvm_x86_ops->get_segment_base(vcpu, seg);
2590 }
2591
2592 int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2593 {
2594 kvm_mmu_invlpg(vcpu, address);
2595 return X86EMUL_CONTINUE;
2596 }
2597
2598 int emulate_clts(struct kvm_vcpu *vcpu)
2599 {
2600 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
2601 return X86EMUL_CONTINUE;
2602 }
2603
2604 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2605 {
2606 struct kvm_vcpu *vcpu = ctxt->vcpu;
2607
2608 switch (dr) {
2609 case 0 ... 3:
2610 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2611 return X86EMUL_CONTINUE;
2612 default:
2613 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
2614 return X86EMUL_UNHANDLEABLE;
2615 }
2616 }
2617
2618 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2619 {
2620 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2621 int exception;
2622
2623 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2624 if (exception) {
2625 /* FIXME: better handling */
2626 return X86EMUL_UNHANDLEABLE;
2627 }
2628 return X86EMUL_CONTINUE;
2629 }
2630
2631 void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2632 {
2633 u8 opcodes[4];
2634 unsigned long rip = kvm_rip_read(vcpu);
2635 unsigned long rip_linear;
2636
2637 if (!printk_ratelimit())
2638 return;
2639
2640 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2641
2642 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
2643
2644 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2645 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
2646 }
2647 EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2648
2649 static struct x86_emulate_ops emulate_ops = {
2650 .read_std = kvm_read_guest_virt,
2651 .read_emulated = emulator_read_emulated,
2652 .write_emulated = emulator_write_emulated,
2653 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2654 };
2655
2656 static void cache_all_regs(struct kvm_vcpu *vcpu)
2657 {
2658 kvm_register_read(vcpu, VCPU_REGS_RAX);
2659 kvm_register_read(vcpu, VCPU_REGS_RSP);
2660 kvm_register_read(vcpu, VCPU_REGS_RIP);
2661 vcpu->arch.regs_dirty = ~0;
2662 }
2663
2664 int emulate_instruction(struct kvm_vcpu *vcpu,
2665 struct kvm_run *run,
2666 unsigned long cr2,
2667 u16 error_code,
2668 int emulation_type)
2669 {
2670 int r, shadow_mask;
2671 struct decode_cache *c;
2672
2673 kvm_clear_exception_queue(vcpu);
2674 vcpu->arch.mmio_fault_cr2 = cr2;
2675 /*
2676 * TODO: fix x86_emulate.c to use guest_read/write_register
2677 * instead of direct ->regs accesses, can save hundred cycles
2678 * on Intel for instructions that don't read/change RSP, for
2679 * for example.
2680 */
2681 cache_all_regs(vcpu);
2682
2683 vcpu->mmio_is_write = 0;
2684 vcpu->arch.pio.string = 0;
2685
2686 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
2687 int cs_db, cs_l;
2688 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2689
2690 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2691 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2692 vcpu->arch.emulate_ctxt.mode =
2693 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
2694 ? X86EMUL_MODE_REAL : cs_l
2695 ? X86EMUL_MODE_PROT64 : cs_db
2696 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2697
2698 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2699
2700 /* Only allow emulation of specific instructions on #UD
2701 * (namely VMMCALL, sysenter, sysexit, syscall)*/
2702 c = &vcpu->arch.emulate_ctxt.decode;
2703 if (emulation_type & EMULTYPE_TRAP_UD) {
2704 if (!c->twobyte)
2705 return EMULATE_FAIL;
2706 switch (c->b) {
2707 case 0x01: /* VMMCALL */
2708 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2709 return EMULATE_FAIL;
2710 break;
2711 case 0x34: /* sysenter */
2712 case 0x35: /* sysexit */
2713 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2714 return EMULATE_FAIL;
2715 break;
2716 case 0x05: /* syscall */
2717 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2718 return EMULATE_FAIL;
2719 break;
2720 default:
2721 return EMULATE_FAIL;
2722 }
2723
2724 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2725 return EMULATE_FAIL;
2726 }
2727
2728 ++vcpu->stat.insn_emulation;
2729 if (r) {
2730 ++vcpu->stat.insn_emulation_fail;
2731 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2732 return EMULATE_DONE;
2733 return EMULATE_FAIL;
2734 }
2735 }
2736
2737 if (emulation_type & EMULTYPE_SKIP) {
2738 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2739 return EMULATE_DONE;
2740 }
2741
2742 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
2743 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2744
2745 if (r == 0)
2746 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
2747
2748 if (vcpu->arch.pio.string)
2749 return EMULATE_DO_MMIO;
2750
2751 if ((r || vcpu->mmio_is_write) && run) {
2752 run->exit_reason = KVM_EXIT_MMIO;
2753 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2754 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2755 run->mmio.len = vcpu->mmio_size;
2756 run->mmio.is_write = vcpu->mmio_is_write;
2757 }
2758
2759 if (r) {
2760 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2761 return EMULATE_DONE;
2762 if (!vcpu->mmio_needed) {
2763 kvm_report_emulation_failure(vcpu, "mmio");
2764 return EMULATE_FAIL;
2765 }
2766 return EMULATE_DO_MMIO;
2767 }
2768
2769 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
2770
2771 if (vcpu->mmio_is_write) {
2772 vcpu->mmio_needed = 0;
2773 return EMULATE_DO_MMIO;
2774 }
2775
2776 return EMULATE_DONE;
2777 }
2778 EXPORT_SYMBOL_GPL(emulate_instruction);
2779
2780 static int pio_copy_data(struct kvm_vcpu *vcpu)
2781 {
2782 void *p = vcpu->arch.pio_data;
2783 gva_t q = vcpu->arch.pio.guest_gva;
2784 unsigned bytes;
2785 int ret;
2786
2787 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2788 if (vcpu->arch.pio.in)
2789 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
2790 else
2791 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2792 return ret;
2793 }
2794
2795 int complete_pio(struct kvm_vcpu *vcpu)
2796 {
2797 struct kvm_pio_request *io = &vcpu->arch.pio;
2798 long delta;
2799 int r;
2800 unsigned long val;
2801
2802 if (!io->string) {
2803 if (io->in) {
2804 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2805 memcpy(&val, vcpu->arch.pio_data, io->size);
2806 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2807 }
2808 } else {
2809 if (io->in) {
2810 r = pio_copy_data(vcpu);
2811 if (r)
2812 return r;
2813 }
2814
2815 delta = 1;
2816 if (io->rep) {
2817 delta *= io->cur_count;
2818 /*
2819 * The size of the register should really depend on
2820 * current address size.
2821 */
2822 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2823 val -= delta;
2824 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
2825 }
2826 if (io->down)
2827 delta = -delta;
2828 delta *= io->size;
2829 if (io->in) {
2830 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2831 val += delta;
2832 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2833 } else {
2834 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2835 val += delta;
2836 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2837 }
2838 }
2839
2840 io->count -= io->cur_count;
2841 io->cur_count = 0;
2842
2843 return 0;
2844 }
2845
2846 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
2847 {
2848 /* TODO: String I/O for in kernel device */
2849 int r;
2850
2851 if (vcpu->arch.pio.in)
2852 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2853 vcpu->arch.pio.size, pd);
2854 else
2855 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2856 vcpu->arch.pio.size, pd);
2857 return r;
2858 }
2859
2860 static int pio_string_write(struct kvm_vcpu *vcpu)
2861 {
2862 struct kvm_pio_request *io = &vcpu->arch.pio;
2863 void *pd = vcpu->arch.pio_data;
2864 int i, r = 0;
2865
2866 for (i = 0; i < io->cur_count; i++) {
2867 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2868 io->port, io->size, pd)) {
2869 r = -EOPNOTSUPP;
2870 break;
2871 }
2872 pd += io->size;
2873 }
2874 return r;
2875 }
2876
2877 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2878 int size, unsigned port)
2879 {
2880 unsigned long val;
2881
2882 vcpu->run->exit_reason = KVM_EXIT_IO;
2883 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2884 vcpu->run->io.size = vcpu->arch.pio.size = size;
2885 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2886 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2887 vcpu->run->io.port = vcpu->arch.pio.port = port;
2888 vcpu->arch.pio.in = in;
2889 vcpu->arch.pio.string = 0;
2890 vcpu->arch.pio.down = 0;
2891 vcpu->arch.pio.rep = 0;
2892
2893 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2894 size, 1);
2895
2896 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2897 memcpy(vcpu->arch.pio_data, &val, 4);
2898
2899 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
2900 complete_pio(vcpu);
2901 return 1;
2902 }
2903 return 0;
2904 }
2905 EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2906
2907 int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2908 int size, unsigned long count, int down,
2909 gva_t address, int rep, unsigned port)
2910 {
2911 unsigned now, in_page;
2912 int ret = 0;
2913
2914 vcpu->run->exit_reason = KVM_EXIT_IO;
2915 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
2916 vcpu->run->io.size = vcpu->arch.pio.size = size;
2917 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
2918 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2919 vcpu->run->io.port = vcpu->arch.pio.port = port;
2920 vcpu->arch.pio.in = in;
2921 vcpu->arch.pio.string = 1;
2922 vcpu->arch.pio.down = down;
2923 vcpu->arch.pio.rep = rep;
2924
2925 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2926 size, count);
2927
2928 if (!count) {
2929 kvm_x86_ops->skip_emulated_instruction(vcpu);
2930 return 1;
2931 }
2932
2933 if (!down)
2934 in_page = PAGE_SIZE - offset_in_page(address);
2935 else
2936 in_page = offset_in_page(address) + size;
2937 now = min(count, (unsigned long)in_page / size);
2938 if (!now)
2939 now = 1;
2940 if (down) {
2941 /*
2942 * String I/O in reverse. Yuck. Kill the guest, fix later.
2943 */
2944 pr_unimpl(vcpu, "guest string pio down\n");
2945 kvm_inject_gp(vcpu, 0);
2946 return 1;
2947 }
2948 vcpu->run->io.count = now;
2949 vcpu->arch.pio.cur_count = now;
2950
2951 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
2952 kvm_x86_ops->skip_emulated_instruction(vcpu);
2953
2954 vcpu->arch.pio.guest_gva = address;
2955
2956 if (!vcpu->arch.pio.in) {
2957 /* string PIO write */
2958 ret = pio_copy_data(vcpu);
2959 if (ret == X86EMUL_PROPAGATE_FAULT) {
2960 kvm_inject_gp(vcpu, 0);
2961 return 1;
2962 }
2963 if (ret == 0 && !pio_string_write(vcpu)) {
2964 complete_pio(vcpu);
2965 if (vcpu->arch.pio.count == 0)
2966 ret = 1;
2967 }
2968 }
2969 /* no string PIO read support yet */
2970
2971 return ret;
2972 }
2973 EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2974
2975 static void bounce_off(void *info)
2976 {
2977 /* nothing */
2978 }
2979
2980 static unsigned int ref_freq;
2981 static unsigned long tsc_khz_ref;
2982
2983 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2984 void *data)
2985 {
2986 struct cpufreq_freqs *freq = data;
2987 struct kvm *kvm;
2988 struct kvm_vcpu *vcpu;
2989 int i, send_ipi = 0;
2990
2991 if (!ref_freq)
2992 ref_freq = freq->old;
2993
2994 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2995 return 0;
2996 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2997 return 0;
2998 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2999
3000 spin_lock(&kvm_lock);
3001 list_for_each_entry(kvm, &vm_list, vm_list) {
3002 kvm_for_each_vcpu(i, vcpu, kvm) {
3003 if (vcpu->cpu != freq->cpu)
3004 continue;
3005 if (!kvm_request_guest_time_update(vcpu))
3006 continue;
3007 if (vcpu->cpu != smp_processor_id())
3008 send_ipi++;
3009 }
3010 }
3011 spin_unlock(&kvm_lock);
3012
3013 if (freq->old < freq->new && send_ipi) {
3014 /*
3015 * We upscale the frequency. Must make the guest
3016 * doesn't see old kvmclock values while running with
3017 * the new frequency, otherwise we risk the guest sees
3018 * time go backwards.
3019 *
3020 * In case we update the frequency for another cpu
3021 * (which might be in guest context) send an interrupt
3022 * to kick the cpu out of guest context. Next time
3023 * guest context is entered kvmclock will be updated,
3024 * so the guest will not see stale values.
3025 */
3026 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3027 }
3028 return 0;
3029 }
3030
3031 static struct notifier_block kvmclock_cpufreq_notifier_block = {
3032 .notifier_call = kvmclock_cpufreq_notifier
3033 };
3034
3035 int kvm_arch_init(void *opaque)
3036 {
3037 int r, cpu;
3038 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3039
3040 if (kvm_x86_ops) {
3041 printk(KERN_ERR "kvm: already loaded the other module\n");
3042 r = -EEXIST;
3043 goto out;
3044 }
3045
3046 if (!ops->cpu_has_kvm_support()) {
3047 printk(KERN_ERR "kvm: no hardware support\n");
3048 r = -EOPNOTSUPP;
3049 goto out;
3050 }
3051 if (ops->disabled_by_bios()) {
3052 printk(KERN_ERR "kvm: disabled by bios\n");
3053 r = -EOPNOTSUPP;
3054 goto out;
3055 }
3056
3057 r = kvm_mmu_module_init();
3058 if (r)
3059 goto out;
3060
3061 kvm_init_msr_list();
3062
3063 kvm_x86_ops = ops;
3064 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
3065 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3066 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
3067 PT_DIRTY_MASK, PT64_NX_MASK, 0);
3068
3069 for_each_possible_cpu(cpu)
3070 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3071 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3072 tsc_khz_ref = tsc_khz;
3073 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3074 CPUFREQ_TRANSITION_NOTIFIER);
3075 }
3076
3077 return 0;
3078
3079 out:
3080 return r;
3081 }
3082
3083 void kvm_arch_exit(void)
3084 {
3085 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3086 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3087 CPUFREQ_TRANSITION_NOTIFIER);
3088 kvm_x86_ops = NULL;
3089 kvm_mmu_module_exit();
3090 }
3091
3092 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3093 {
3094 ++vcpu->stat.halt_exits;
3095 if (irqchip_in_kernel(vcpu->kvm)) {
3096 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
3097 return 1;
3098 } else {
3099 vcpu->run->exit_reason = KVM_EXIT_HLT;
3100 return 0;
3101 }
3102 }
3103 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3104
3105 static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3106 unsigned long a1)
3107 {
3108 if (is_long_mode(vcpu))
3109 return a0;
3110 else
3111 return a0 | ((gpa_t)a1 << 32);
3112 }
3113
3114 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3115 {
3116 unsigned long nr, a0, a1, a2, a3, ret;
3117 int r = 1;
3118
3119 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3120 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3121 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3122 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3123 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
3124
3125 trace_kvm_hypercall(nr, a0, a1, a2, a3);
3126
3127 if (!is_long_mode(vcpu)) {
3128 nr &= 0xFFFFFFFF;
3129 a0 &= 0xFFFFFFFF;
3130 a1 &= 0xFFFFFFFF;
3131 a2 &= 0xFFFFFFFF;
3132 a3 &= 0xFFFFFFFF;
3133 }
3134
3135 switch (nr) {
3136 case KVM_HC_VAPIC_POLL_IRQ:
3137 ret = 0;
3138 break;
3139 case KVM_HC_MMU_OP:
3140 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3141 break;
3142 default:
3143 ret = -KVM_ENOSYS;
3144 break;
3145 }
3146 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3147 ++vcpu->stat.hypercalls;
3148 return r;
3149 }
3150 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3151
3152 int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3153 {
3154 char instruction[3];
3155 int ret = 0;
3156 unsigned long rip = kvm_rip_read(vcpu);
3157
3158
3159 /*
3160 * Blow out the MMU to ensure that no other VCPU has an active mapping
3161 * to ensure that the updated hypercall appears atomically across all
3162 * VCPUs.
3163 */
3164 kvm_mmu_zap_all(vcpu->kvm);
3165
3166 kvm_x86_ops->patch_hypercall(vcpu, instruction);
3167 if (emulator_write_emulated(rip, instruction, 3, vcpu)
3168 != X86EMUL_CONTINUE)
3169 ret = -EFAULT;
3170
3171 return ret;
3172 }
3173
3174 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3175 {
3176 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3177 }
3178
3179 void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3180 {
3181 struct descriptor_table dt = { limit, base };
3182
3183 kvm_x86_ops->set_gdt(vcpu, &dt);
3184 }
3185
3186 void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3187 {
3188 struct descriptor_table dt = { limit, base };
3189
3190 kvm_x86_ops->set_idt(vcpu, &dt);
3191 }
3192
3193 void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3194 unsigned long *rflags)
3195 {
3196 kvm_lmsw(vcpu, msw);
3197 *rflags = kvm_x86_ops->get_rflags(vcpu);
3198 }
3199
3200 unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3201 {
3202 unsigned long value;
3203
3204 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3205 switch (cr) {
3206 case 0:
3207 value = vcpu->arch.cr0;
3208 break;
3209 case 2:
3210 value = vcpu->arch.cr2;
3211 break;
3212 case 3:
3213 value = vcpu->arch.cr3;
3214 break;
3215 case 4:
3216 value = vcpu->arch.cr4;
3217 break;
3218 case 8:
3219 value = kvm_get_cr8(vcpu);
3220 break;
3221 default:
3222 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3223 return 0;
3224 }
3225
3226 return value;
3227 }
3228
3229 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3230 unsigned long *rflags)
3231 {
3232 switch (cr) {
3233 case 0:
3234 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
3235 *rflags = kvm_x86_ops->get_rflags(vcpu);
3236 break;
3237 case 2:
3238 vcpu->arch.cr2 = val;
3239 break;
3240 case 3:
3241 kvm_set_cr3(vcpu, val);
3242 break;
3243 case 4:
3244 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3245 break;
3246 case 8:
3247 kvm_set_cr8(vcpu, val & 0xfUL);
3248 break;
3249 default:
3250 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3251 }
3252 }
3253
3254 static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3255 {
3256 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3257 int j, nent = vcpu->arch.cpuid_nent;
3258
3259 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3260 /* when no next entry is found, the current entry[i] is reselected */
3261 for (j = i + 1; ; j = (j + 1) % nent) {
3262 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
3263 if (ej->function == e->function) {
3264 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3265 return j;
3266 }
3267 }
3268 return 0; /* silence gcc, even though control never reaches here */
3269 }
3270
3271 /* find an entry with matching function, matching index (if needed), and that
3272 * should be read next (if it's stateful) */
3273 static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3274 u32 function, u32 index)
3275 {
3276 if (e->function != function)
3277 return 0;
3278 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3279 return 0;
3280 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
3281 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
3282 return 0;
3283 return 1;
3284 }
3285
3286 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3287 u32 function, u32 index)
3288 {
3289 int i;
3290 struct kvm_cpuid_entry2 *best = NULL;
3291
3292 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
3293 struct kvm_cpuid_entry2 *e;
3294
3295 e = &vcpu->arch.cpuid_entries[i];
3296 if (is_matching_cpuid_entry(e, function, index)) {
3297 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3298 move_to_next_stateful_cpuid_entry(vcpu, i);
3299 best = e;
3300 break;
3301 }
3302 /*
3303 * Both basic or both extended?
3304 */
3305 if (((e->function ^ function) & 0x80000000) == 0)
3306 if (!best || e->function > best->function)
3307 best = e;
3308 }
3309 return best;
3310 }
3311
3312 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3313 {
3314 struct kvm_cpuid_entry2 *best;
3315
3316 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3317 if (best)
3318 return best->eax & 0xff;
3319 return 36;
3320 }
3321
3322 void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3323 {
3324 u32 function, index;
3325 struct kvm_cpuid_entry2 *best;
3326
3327 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3328 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3329 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3330 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3331 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3332 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3333 best = kvm_find_cpuid_entry(vcpu, function, index);
3334 if (best) {
3335 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3336 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3337 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3338 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
3339 }
3340 kvm_x86_ops->skip_emulated_instruction(vcpu);
3341 trace_kvm_cpuid(function,
3342 kvm_register_read(vcpu, VCPU_REGS_RAX),
3343 kvm_register_read(vcpu, VCPU_REGS_RBX),
3344 kvm_register_read(vcpu, VCPU_REGS_RCX),
3345 kvm_register_read(vcpu, VCPU_REGS_RDX));
3346 }
3347 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
3348
3349 /*
3350 * Check if userspace requested an interrupt window, and that the
3351 * interrupt window is open.
3352 *
3353 * No need to exit to userspace if we already have an interrupt queued.
3354 */
3355 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3356 struct kvm_run *kvm_run)
3357 {
3358 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
3359 kvm_run->request_interrupt_window &&
3360 kvm_arch_interrupt_allowed(vcpu));
3361 }
3362
3363 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3364 struct kvm_run *kvm_run)
3365 {
3366 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
3367 kvm_run->cr8 = kvm_get_cr8(vcpu);
3368 kvm_run->apic_base = kvm_get_apic_base(vcpu);
3369 if (irqchip_in_kernel(vcpu->kvm))
3370 kvm_run->ready_for_interrupt_injection = 1;
3371 else
3372 kvm_run->ready_for_interrupt_injection =
3373 kvm_arch_interrupt_allowed(vcpu) &&
3374 !kvm_cpu_has_interrupt(vcpu) &&
3375 !kvm_event_needs_reinjection(vcpu);
3376 }
3377
3378 static void vapic_enter(struct kvm_vcpu *vcpu)
3379 {
3380 struct kvm_lapic *apic = vcpu->arch.apic;
3381 struct page *page;
3382
3383 if (!apic || !apic->vapic_addr)
3384 return;
3385
3386 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3387
3388 vcpu->arch.apic->vapic_page = page;
3389 }
3390
3391 static void vapic_exit(struct kvm_vcpu *vcpu)
3392 {
3393 struct kvm_lapic *apic = vcpu->arch.apic;
3394
3395 if (!apic || !apic->vapic_addr)
3396 return;
3397
3398 down_read(&vcpu->kvm->slots_lock);
3399 kvm_release_page_dirty(apic->vapic_page);
3400 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
3401 up_read(&vcpu->kvm->slots_lock);
3402 }
3403
3404 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3405 {
3406 int max_irr, tpr;
3407
3408 if (!kvm_x86_ops->update_cr8_intercept)
3409 return;
3410
3411 if (!vcpu->arch.apic->vapic_addr)
3412 max_irr = kvm_lapic_find_highest_irr(vcpu);
3413 else
3414 max_irr = -1;
3415
3416 if (max_irr != -1)
3417 max_irr >>= 4;
3418
3419 tpr = kvm_lapic_get_cr8(vcpu);
3420
3421 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3422 }
3423
3424 static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3425 {
3426 /* try to reinject previous events if any */
3427 if (vcpu->arch.nmi_injected) {
3428 kvm_x86_ops->set_nmi(vcpu);
3429 return;
3430 }
3431
3432 if (vcpu->arch.interrupt.pending) {
3433 kvm_x86_ops->set_irq(vcpu);
3434 return;
3435 }
3436
3437 /* try to inject new event if pending */
3438 if (vcpu->arch.nmi_pending) {
3439 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3440 vcpu->arch.nmi_pending = false;
3441 vcpu->arch.nmi_injected = true;
3442 kvm_x86_ops->set_nmi(vcpu);
3443 }
3444 } else if (kvm_cpu_has_interrupt(vcpu)) {
3445 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
3446 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3447 false);
3448 kvm_x86_ops->set_irq(vcpu);
3449 }
3450 }
3451 }
3452
3453 static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3454 {
3455 int r;
3456 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3457 kvm_run->request_interrupt_window;
3458
3459 if (vcpu->requests)
3460 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3461 kvm_mmu_unload(vcpu);
3462
3463 r = kvm_mmu_reload(vcpu);
3464 if (unlikely(r))
3465 goto out;
3466
3467 if (vcpu->requests) {
3468 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
3469 __kvm_migrate_timers(vcpu);
3470 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3471 kvm_write_guest_time(vcpu);
3472 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3473 kvm_mmu_sync_roots(vcpu);
3474 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3475 kvm_x86_ops->tlb_flush(vcpu);
3476 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3477 &vcpu->requests)) {
3478 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3479 r = 0;
3480 goto out;
3481 }
3482 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3483 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3484 r = 0;
3485 goto out;
3486 }
3487 }
3488
3489 preempt_disable();
3490
3491 kvm_x86_ops->prepare_guest_switch(vcpu);
3492 kvm_load_guest_fpu(vcpu);
3493
3494 local_irq_disable();
3495
3496 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3497 smp_mb__after_clear_bit();
3498
3499 if (vcpu->requests || need_resched() || signal_pending(current)) {
3500 local_irq_enable();
3501 preempt_enable();
3502 r = 1;
3503 goto out;
3504 }
3505
3506 if (vcpu->arch.exception.pending)
3507 __queue_exception(vcpu);
3508 else
3509 inject_pending_irq(vcpu, kvm_run);
3510
3511 /* enable NMI/IRQ window open exits if needed */
3512 if (vcpu->arch.nmi_pending)
3513 kvm_x86_ops->enable_nmi_window(vcpu);
3514 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3515 kvm_x86_ops->enable_irq_window(vcpu);
3516
3517 if (kvm_lapic_enabled(vcpu)) {
3518 update_cr8_intercept(vcpu);
3519 kvm_lapic_sync_to_vapic(vcpu);
3520 }
3521
3522 up_read(&vcpu->kvm->slots_lock);
3523
3524 kvm_guest_enter();
3525
3526 get_debugreg(vcpu->arch.host_dr6, 6);
3527 get_debugreg(vcpu->arch.host_dr7, 7);
3528 if (unlikely(vcpu->arch.switch_db_regs)) {
3529 get_debugreg(vcpu->arch.host_db[0], 0);
3530 get_debugreg(vcpu->arch.host_db[1], 1);
3531 get_debugreg(vcpu->arch.host_db[2], 2);
3532 get_debugreg(vcpu->arch.host_db[3], 3);
3533
3534 set_debugreg(0, 7);
3535 set_debugreg(vcpu->arch.eff_db[0], 0);
3536 set_debugreg(vcpu->arch.eff_db[1], 1);
3537 set_debugreg(vcpu->arch.eff_db[2], 2);
3538 set_debugreg(vcpu->arch.eff_db[3], 3);
3539 }
3540
3541 trace_kvm_entry(vcpu->vcpu_id);
3542 kvm_x86_ops->run(vcpu, kvm_run);
3543
3544 if (unlikely(vcpu->arch.switch_db_regs)) {
3545 set_debugreg(0, 7);
3546 set_debugreg(vcpu->arch.host_db[0], 0);
3547 set_debugreg(vcpu->arch.host_db[1], 1);
3548 set_debugreg(vcpu->arch.host_db[2], 2);
3549 set_debugreg(vcpu->arch.host_db[3], 3);
3550 }
3551 set_debugreg(vcpu->arch.host_dr6, 6);
3552 set_debugreg(vcpu->arch.host_dr7, 7);
3553
3554 set_bit(KVM_REQ_KICK, &vcpu->requests);
3555 local_irq_enable();
3556
3557 ++vcpu->stat.exits;
3558
3559 /*
3560 * We must have an instruction between local_irq_enable() and
3561 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3562 * the interrupt shadow. The stat.exits increment will do nicely.
3563 * But we need to prevent reordering, hence this barrier():
3564 */
3565 barrier();
3566
3567 kvm_guest_exit();
3568
3569 preempt_enable();
3570
3571 down_read(&vcpu->kvm->slots_lock);
3572
3573 /*
3574 * Profile KVM exit RIPs:
3575 */
3576 if (unlikely(prof_on == KVM_PROFILING)) {
3577 unsigned long rip = kvm_rip_read(vcpu);
3578 profile_hit(KVM_PROFILING, (void *)rip);
3579 }
3580
3581
3582 kvm_lapic_sync_from_vapic(vcpu);
3583
3584 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
3585 out:
3586 return r;
3587 }
3588
3589
3590 static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3591 {
3592 int r;
3593
3594 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
3595 pr_debug("vcpu %d received sipi with vector # %x\n",
3596 vcpu->vcpu_id, vcpu->arch.sipi_vector);
3597 kvm_lapic_reset(vcpu);
3598 r = kvm_arch_vcpu_reset(vcpu);
3599 if (r)
3600 return r;
3601 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3602 }
3603
3604 down_read(&vcpu->kvm->slots_lock);
3605 vapic_enter(vcpu);
3606
3607 r = 1;
3608 while (r > 0) {
3609 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
3610 r = vcpu_enter_guest(vcpu, kvm_run);
3611 else {
3612 up_read(&vcpu->kvm->slots_lock);
3613 kvm_vcpu_block(vcpu);
3614 down_read(&vcpu->kvm->slots_lock);
3615 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3616 {
3617 switch(vcpu->arch.mp_state) {
3618 case KVM_MP_STATE_HALTED:
3619 vcpu->arch.mp_state =
3620 KVM_MP_STATE_RUNNABLE;
3621 case KVM_MP_STATE_RUNNABLE:
3622 break;
3623 case KVM_MP_STATE_SIPI_RECEIVED:
3624 default:
3625 r = -EINTR;
3626 break;
3627 }
3628 }
3629 }
3630
3631 if (r <= 0)
3632 break;
3633
3634 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3635 if (kvm_cpu_has_pending_timer(vcpu))
3636 kvm_inject_pending_timer_irqs(vcpu);
3637
3638 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3639 r = -EINTR;
3640 kvm_run->exit_reason = KVM_EXIT_INTR;
3641 ++vcpu->stat.request_irq_exits;
3642 }
3643 if (signal_pending(current)) {
3644 r = -EINTR;
3645 kvm_run->exit_reason = KVM_EXIT_INTR;
3646 ++vcpu->stat.signal_exits;
3647 }
3648 if (need_resched()) {
3649 up_read(&vcpu->kvm->slots_lock);
3650 kvm_resched(vcpu);
3651 down_read(&vcpu->kvm->slots_lock);
3652 }
3653 }
3654
3655 up_read(&vcpu->kvm->slots_lock);
3656 post_kvm_run_save(vcpu, kvm_run);
3657
3658 vapic_exit(vcpu);
3659
3660 return r;
3661 }
3662
3663 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3664 {
3665 int r;
3666 sigset_t sigsaved;
3667
3668 vcpu_load(vcpu);
3669
3670 if (vcpu->sigset_active)
3671 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3672
3673 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
3674 kvm_vcpu_block(vcpu);
3675 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
3676 r = -EAGAIN;
3677 goto out;
3678 }
3679
3680 /* re-sync apic's tpr */
3681 if (!irqchip_in_kernel(vcpu->kvm))
3682 kvm_set_cr8(vcpu, kvm_run->cr8);
3683
3684 if (vcpu->arch.pio.cur_count) {
3685 r = complete_pio(vcpu);
3686 if (r)
3687 goto out;
3688 }
3689 #if CONFIG_HAS_IOMEM
3690 if (vcpu->mmio_needed) {
3691 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3692 vcpu->mmio_read_completed = 1;
3693 vcpu->mmio_needed = 0;
3694
3695 down_read(&vcpu->kvm->slots_lock);
3696 r = emulate_instruction(vcpu, kvm_run,
3697 vcpu->arch.mmio_fault_cr2, 0,
3698 EMULTYPE_NO_DECODE);
3699 up_read(&vcpu->kvm->slots_lock);
3700 if (r == EMULATE_DO_MMIO) {
3701 /*
3702 * Read-modify-write. Back to userspace.
3703 */
3704 r = 0;
3705 goto out;
3706 }
3707 }
3708 #endif
3709 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3710 kvm_register_write(vcpu, VCPU_REGS_RAX,
3711 kvm_run->hypercall.ret);
3712
3713 r = __vcpu_run(vcpu, kvm_run);
3714
3715 out:
3716 if (vcpu->sigset_active)
3717 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3718
3719 vcpu_put(vcpu);
3720 return r;
3721 }
3722
3723 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3724 {
3725 vcpu_load(vcpu);
3726
3727 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3728 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3729 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3730 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3731 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3732 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3733 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3734 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3735 #ifdef CONFIG_X86_64
3736 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3737 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3738 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3739 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3740 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3741 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3742 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3743 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
3744 #endif
3745
3746 regs->rip = kvm_rip_read(vcpu);
3747 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3748
3749 /*
3750 * Don't leak debug flags in case they were set for guest debugging
3751 */
3752 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3753 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3754
3755 vcpu_put(vcpu);
3756
3757 return 0;
3758 }
3759
3760 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3761 {
3762 vcpu_load(vcpu);
3763
3764 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3765 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3766 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3767 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3768 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3769 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3770 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3771 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
3772 #ifdef CONFIG_X86_64
3773 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3774 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3775 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3776 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3777 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3778 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3779 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3780 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3781
3782 #endif
3783
3784 kvm_rip_write(vcpu, regs->rip);
3785 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3786
3787
3788 vcpu->arch.exception.pending = false;
3789
3790 vcpu_put(vcpu);
3791
3792 return 0;
3793 }
3794
3795 void kvm_get_segment(struct kvm_vcpu *vcpu,
3796 struct kvm_segment *var, int seg)
3797 {
3798 kvm_x86_ops->get_segment(vcpu, var, seg);
3799 }
3800
3801 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3802 {
3803 struct kvm_segment cs;
3804
3805 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
3806 *db = cs.db;
3807 *l = cs.l;
3808 }
3809 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3810
3811 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3812 struct kvm_sregs *sregs)
3813 {
3814 struct descriptor_table dt;
3815
3816 vcpu_load(vcpu);
3817
3818 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3819 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3820 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3821 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3822 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3823 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
3824
3825 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3826 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
3827
3828 kvm_x86_ops->get_idt(vcpu, &dt);
3829 sregs->idt.limit = dt.limit;
3830 sregs->idt.base = dt.base;
3831 kvm_x86_ops->get_gdt(vcpu, &dt);
3832 sregs->gdt.limit = dt.limit;
3833 sregs->gdt.base = dt.base;
3834
3835 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3836 sregs->cr0 = vcpu->arch.cr0;
3837 sregs->cr2 = vcpu->arch.cr2;
3838 sregs->cr3 = vcpu->arch.cr3;
3839 sregs->cr4 = vcpu->arch.cr4;
3840 sregs->cr8 = kvm_get_cr8(vcpu);
3841 sregs->efer = vcpu->arch.shadow_efer;
3842 sregs->apic_base = kvm_get_apic_base(vcpu);
3843
3844 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
3845
3846 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
3847 set_bit(vcpu->arch.interrupt.nr,
3848 (unsigned long *)sregs->interrupt_bitmap);
3849
3850 vcpu_put(vcpu);
3851
3852 return 0;
3853 }
3854
3855 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3856 struct kvm_mp_state *mp_state)
3857 {
3858 vcpu_load(vcpu);
3859 mp_state->mp_state = vcpu->arch.mp_state;
3860 vcpu_put(vcpu);
3861 return 0;
3862 }
3863
3864 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3865 struct kvm_mp_state *mp_state)
3866 {
3867 vcpu_load(vcpu);
3868 vcpu->arch.mp_state = mp_state->mp_state;
3869 vcpu_put(vcpu);
3870 return 0;
3871 }
3872
3873 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3874 struct kvm_segment *var, int seg)
3875 {
3876 kvm_x86_ops->set_segment(vcpu, var, seg);
3877 }
3878
3879 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3880 struct kvm_segment *kvm_desct)
3881 {
3882 kvm_desct->base = seg_desc->base0;
3883 kvm_desct->base |= seg_desc->base1 << 16;
3884 kvm_desct->base |= seg_desc->base2 << 24;
3885 kvm_desct->limit = seg_desc->limit0;
3886 kvm_desct->limit |= seg_desc->limit << 16;
3887 if (seg_desc->g) {
3888 kvm_desct->limit <<= 12;
3889 kvm_desct->limit |= 0xfff;
3890 }
3891 kvm_desct->selector = selector;
3892 kvm_desct->type = seg_desc->type;
3893 kvm_desct->present = seg_desc->p;
3894 kvm_desct->dpl = seg_desc->dpl;
3895 kvm_desct->db = seg_desc->d;
3896 kvm_desct->s = seg_desc->s;
3897 kvm_desct->l = seg_desc->l;
3898 kvm_desct->g = seg_desc->g;
3899 kvm_desct->avl = seg_desc->avl;
3900 if (!selector)
3901 kvm_desct->unusable = 1;
3902 else
3903 kvm_desct->unusable = 0;
3904 kvm_desct->padding = 0;
3905 }
3906
3907 static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3908 u16 selector,
3909 struct descriptor_table *dtable)
3910 {
3911 if (selector & 1 << 2) {
3912 struct kvm_segment kvm_seg;
3913
3914 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
3915
3916 if (kvm_seg.unusable)
3917 dtable->limit = 0;
3918 else
3919 dtable->limit = kvm_seg.limit;
3920 dtable->base = kvm_seg.base;
3921 }
3922 else
3923 kvm_x86_ops->get_gdt(vcpu, dtable);
3924 }
3925
3926 /* allowed just for 8 bytes segments */
3927 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3928 struct desc_struct *seg_desc)
3929 {
3930 gpa_t gpa;
3931 struct descriptor_table dtable;
3932 u16 index = selector >> 3;
3933
3934 get_segment_descriptor_dtable(vcpu, selector, &dtable);
3935
3936 if (dtable.limit < index * 8 + 7) {
3937 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3938 return 1;
3939 }
3940 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3941 gpa += index * 8;
3942 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
3943 }
3944
3945 /* allowed just for 8 bytes segments */
3946 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3947 struct desc_struct *seg_desc)
3948 {
3949 gpa_t gpa;
3950 struct descriptor_table dtable;
3951 u16 index = selector >> 3;
3952
3953 get_segment_descriptor_dtable(vcpu, selector, &dtable);
3954
3955 if (dtable.limit < index * 8 + 7)
3956 return 1;
3957 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3958 gpa += index * 8;
3959 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
3960 }
3961
3962 static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3963 struct desc_struct *seg_desc)
3964 {
3965 u32 base_addr;
3966
3967 base_addr = seg_desc->base0;
3968 base_addr |= (seg_desc->base1 << 16);
3969 base_addr |= (seg_desc->base2 << 24);
3970
3971 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
3972 }
3973
3974 static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3975 {
3976 struct kvm_segment kvm_seg;
3977
3978 kvm_get_segment(vcpu, &kvm_seg, seg);
3979 return kvm_seg.selector;
3980 }
3981
3982 static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3983 u16 selector,
3984 struct kvm_segment *kvm_seg)
3985 {
3986 struct desc_struct seg_desc;
3987
3988 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3989 return 1;
3990 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3991 return 0;
3992 }
3993
3994 static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
3995 {
3996 struct kvm_segment segvar = {
3997 .base = selector << 4,
3998 .limit = 0xffff,
3999 .selector = selector,
4000 .type = 3,
4001 .present = 1,
4002 .dpl = 3,
4003 .db = 0,
4004 .s = 1,
4005 .l = 0,
4006 .g = 0,
4007 .avl = 0,
4008 .unusable = 0,
4009 };
4010 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4011 return 0;
4012 }
4013
4014 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4015 int type_bits, int seg)
4016 {
4017 struct kvm_segment kvm_seg;
4018
4019 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4020 return kvm_load_realmode_segment(vcpu, selector, seg);
4021 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4022 return 1;
4023 kvm_seg.type |= type_bits;
4024
4025 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4026 seg != VCPU_SREG_LDTR)
4027 if (!kvm_seg.s)
4028 kvm_seg.unusable = 1;
4029
4030 kvm_set_segment(vcpu, &kvm_seg, seg);
4031 return 0;
4032 }
4033
4034 static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4035 struct tss_segment_32 *tss)
4036 {
4037 tss->cr3 = vcpu->arch.cr3;
4038 tss->eip = kvm_rip_read(vcpu);
4039 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
4040 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4041 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4042 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4043 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4044 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4045 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4046 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4047 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4048 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4049 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4050 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4051 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4052 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4053 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4054 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4055 }
4056
4057 static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4058 struct tss_segment_32 *tss)
4059 {
4060 kvm_set_cr3(vcpu, tss->cr3);
4061
4062 kvm_rip_write(vcpu, tss->eip);
4063 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4064
4065 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4066 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4067 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4068 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4069 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4070 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4071 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4072 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
4073
4074 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
4075 return 1;
4076
4077 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4078 return 1;
4079
4080 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4081 return 1;
4082
4083 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4084 return 1;
4085
4086 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4087 return 1;
4088
4089 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
4090 return 1;
4091
4092 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
4093 return 1;
4094 return 0;
4095 }
4096
4097 static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4098 struct tss_segment_16 *tss)
4099 {
4100 tss->ip = kvm_rip_read(vcpu);
4101 tss->flag = kvm_x86_ops->get_rflags(vcpu);
4102 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4103 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4104 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4105 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4106 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4107 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4108 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4109 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
4110
4111 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4112 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4113 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4114 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4115 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4116 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4117 }
4118
4119 static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4120 struct tss_segment_16 *tss)
4121 {
4122 kvm_rip_write(vcpu, tss->ip);
4123 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
4124 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4125 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4126 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4127 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4128 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4129 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4130 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4131 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
4132
4133 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
4134 return 1;
4135
4136 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
4137 return 1;
4138
4139 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
4140 return 1;
4141
4142 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
4143 return 1;
4144
4145 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
4146 return 1;
4147 return 0;
4148 }
4149
4150 static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
4151 u16 old_tss_sel, u32 old_tss_base,
4152 struct desc_struct *nseg_desc)
4153 {
4154 struct tss_segment_16 tss_segment_16;
4155 int ret = 0;
4156
4157 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4158 sizeof tss_segment_16))
4159 goto out;
4160
4161 save_state_to_tss16(vcpu, &tss_segment_16);
4162
4163 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4164 sizeof tss_segment_16))
4165 goto out;
4166
4167 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4168 &tss_segment_16, sizeof tss_segment_16))
4169 goto out;
4170
4171 if (old_tss_sel != 0xffff) {
4172 tss_segment_16.prev_task_link = old_tss_sel;
4173
4174 if (kvm_write_guest(vcpu->kvm,
4175 get_tss_base_addr(vcpu, nseg_desc),
4176 &tss_segment_16.prev_task_link,
4177 sizeof tss_segment_16.prev_task_link))
4178 goto out;
4179 }
4180
4181 if (load_state_from_tss16(vcpu, &tss_segment_16))
4182 goto out;
4183
4184 ret = 1;
4185 out:
4186 return ret;
4187 }
4188
4189 static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
4190 u16 old_tss_sel, u32 old_tss_base,
4191 struct desc_struct *nseg_desc)
4192 {
4193 struct tss_segment_32 tss_segment_32;
4194 int ret = 0;
4195
4196 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4197 sizeof tss_segment_32))
4198 goto out;
4199
4200 save_state_to_tss32(vcpu, &tss_segment_32);
4201
4202 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4203 sizeof tss_segment_32))
4204 goto out;
4205
4206 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4207 &tss_segment_32, sizeof tss_segment_32))
4208 goto out;
4209
4210 if (old_tss_sel != 0xffff) {
4211 tss_segment_32.prev_task_link = old_tss_sel;
4212
4213 if (kvm_write_guest(vcpu->kvm,
4214 get_tss_base_addr(vcpu, nseg_desc),
4215 &tss_segment_32.prev_task_link,
4216 sizeof tss_segment_32.prev_task_link))
4217 goto out;
4218 }
4219
4220 if (load_state_from_tss32(vcpu, &tss_segment_32))
4221 goto out;
4222
4223 ret = 1;
4224 out:
4225 return ret;
4226 }
4227
4228 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4229 {
4230 struct kvm_segment tr_seg;
4231 struct desc_struct cseg_desc;
4232 struct desc_struct nseg_desc;
4233 int ret = 0;
4234 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4235 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
4236
4237 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
4238
4239 /* FIXME: Handle errors. Failure to read either TSS or their
4240 * descriptors should generate a pagefault.
4241 */
4242 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4243 goto out;
4244
4245 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
4246 goto out;
4247
4248 if (reason != TASK_SWITCH_IRET) {
4249 int cpl;
4250
4251 cpl = kvm_x86_ops->get_cpl(vcpu);
4252 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4253 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4254 return 1;
4255 }
4256 }
4257
4258 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4259 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4260 return 1;
4261 }
4262
4263 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
4264 cseg_desc.type &= ~(1 << 1); //clear the B flag
4265 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
4266 }
4267
4268 if (reason == TASK_SWITCH_IRET) {
4269 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4270 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4271 }
4272
4273 /* set back link to prev task only if NT bit is set in eflags
4274 note that old_tss_sel is not used afetr this point */
4275 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4276 old_tss_sel = 0xffff;
4277
4278 /* set back link to prev task only if NT bit is set in eflags
4279 note that old_tss_sel is not used afetr this point */
4280 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4281 old_tss_sel = 0xffff;
4282
4283 if (nseg_desc.type & 8)
4284 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4285 old_tss_base, &nseg_desc);
4286 else
4287 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4288 old_tss_base, &nseg_desc);
4289
4290 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4291 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4292 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4293 }
4294
4295 if (reason != TASK_SWITCH_IRET) {
4296 nseg_desc.type |= (1 << 1);
4297 save_guest_segment_descriptor(vcpu, tss_selector,
4298 &nseg_desc);
4299 }
4300
4301 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4302 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4303 tr_seg.type = 11;
4304 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
4305 out:
4306 return ret;
4307 }
4308 EXPORT_SYMBOL_GPL(kvm_task_switch);
4309
4310 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4311 struct kvm_sregs *sregs)
4312 {
4313 int mmu_reset_needed = 0;
4314 int pending_vec, max_bits;
4315 struct descriptor_table dt;
4316
4317 vcpu_load(vcpu);
4318
4319 dt.limit = sregs->idt.limit;
4320 dt.base = sregs->idt.base;
4321 kvm_x86_ops->set_idt(vcpu, &dt);
4322 dt.limit = sregs->gdt.limit;
4323 dt.base = sregs->gdt.base;
4324 kvm_x86_ops->set_gdt(vcpu, &dt);
4325
4326 vcpu->arch.cr2 = sregs->cr2;
4327 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
4328
4329 down_read(&vcpu->kvm->slots_lock);
4330 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4331 vcpu->arch.cr3 = sregs->cr3;
4332 else
4333 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4334 up_read(&vcpu->kvm->slots_lock);
4335
4336 kvm_set_cr8(vcpu, sregs->cr8);
4337
4338 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4339 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4340 kvm_set_apic_base(vcpu, sregs->apic_base);
4341
4342 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4343
4344 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4345 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4346 vcpu->arch.cr0 = sregs->cr0;
4347
4348 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4349 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4350 if (!is_long_mode(vcpu) && is_pae(vcpu))
4351 load_pdptrs(vcpu, vcpu->arch.cr3);
4352
4353 if (mmu_reset_needed)
4354 kvm_mmu_reset_context(vcpu);
4355
4356 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4357 pending_vec = find_first_bit(
4358 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4359 if (pending_vec < max_bits) {
4360 kvm_queue_interrupt(vcpu, pending_vec, false);
4361 pr_debug("Set back pending irq %d\n", pending_vec);
4362 if (irqchip_in_kernel(vcpu->kvm))
4363 kvm_pic_clear_isr_ack(vcpu->kvm);
4364 }
4365
4366 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4367 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4368 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4369 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4370 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4371 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
4372
4373 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4374 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
4375
4376 /* Older userspace won't unhalt the vcpu on reset. */
4377 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
4378 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4379 !(vcpu->arch.cr0 & X86_CR0_PE))
4380 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4381
4382 vcpu_put(vcpu);
4383
4384 return 0;
4385 }
4386
4387 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4388 struct kvm_guest_debug *dbg)
4389 {
4390 int i, r;
4391
4392 vcpu_load(vcpu);
4393
4394 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4395 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4396 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4397 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4398 vcpu->arch.switch_db_regs =
4399 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4400 } else {
4401 for (i = 0; i < KVM_NR_DB_REGS; i++)
4402 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4403 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4404 }
4405
4406 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4407
4408 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4409 kvm_queue_exception(vcpu, DB_VECTOR);
4410 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4411 kvm_queue_exception(vcpu, BP_VECTOR);
4412
4413 vcpu_put(vcpu);
4414
4415 return r;
4416 }
4417
4418 /*
4419 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4420 * we have asm/x86/processor.h
4421 */
4422 struct fxsave {
4423 u16 cwd;
4424 u16 swd;
4425 u16 twd;
4426 u16 fop;
4427 u64 rip;
4428 u64 rdp;
4429 u32 mxcsr;
4430 u32 mxcsr_mask;
4431 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4432 #ifdef CONFIG_X86_64
4433 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4434 #else
4435 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4436 #endif
4437 };
4438
4439 /*
4440 * Translate a guest virtual address to a guest physical address.
4441 */
4442 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4443 struct kvm_translation *tr)
4444 {
4445 unsigned long vaddr = tr->linear_address;
4446 gpa_t gpa;
4447
4448 vcpu_load(vcpu);
4449 down_read(&vcpu->kvm->slots_lock);
4450 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
4451 up_read(&vcpu->kvm->slots_lock);
4452 tr->physical_address = gpa;
4453 tr->valid = gpa != UNMAPPED_GVA;
4454 tr->writeable = 1;
4455 tr->usermode = 0;
4456 vcpu_put(vcpu);
4457
4458 return 0;
4459 }
4460
4461 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4462 {
4463 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4464
4465 vcpu_load(vcpu);
4466
4467 memcpy(fpu->fpr, fxsave->st_space, 128);
4468 fpu->fcw = fxsave->cwd;
4469 fpu->fsw = fxsave->swd;
4470 fpu->ftwx = fxsave->twd;
4471 fpu->last_opcode = fxsave->fop;
4472 fpu->last_ip = fxsave->rip;
4473 fpu->last_dp = fxsave->rdp;
4474 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4475
4476 vcpu_put(vcpu);
4477
4478 return 0;
4479 }
4480
4481 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4482 {
4483 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
4484
4485 vcpu_load(vcpu);
4486
4487 memcpy(fxsave->st_space, fpu->fpr, 128);
4488 fxsave->cwd = fpu->fcw;
4489 fxsave->swd = fpu->fsw;
4490 fxsave->twd = fpu->ftwx;
4491 fxsave->fop = fpu->last_opcode;
4492 fxsave->rip = fpu->last_ip;
4493 fxsave->rdp = fpu->last_dp;
4494 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4495
4496 vcpu_put(vcpu);
4497
4498 return 0;
4499 }
4500
4501 void fx_init(struct kvm_vcpu *vcpu)
4502 {
4503 unsigned after_mxcsr_mask;
4504
4505 /*
4506 * Touch the fpu the first time in non atomic context as if
4507 * this is the first fpu instruction the exception handler
4508 * will fire before the instruction returns and it'll have to
4509 * allocate ram with GFP_KERNEL.
4510 */
4511 if (!used_math())
4512 kvm_fx_save(&vcpu->arch.host_fx_image);
4513
4514 /* Initialize guest FPU by resetting ours and saving into guest's */
4515 preempt_disable();
4516 kvm_fx_save(&vcpu->arch.host_fx_image);
4517 kvm_fx_finit();
4518 kvm_fx_save(&vcpu->arch.guest_fx_image);
4519 kvm_fx_restore(&vcpu->arch.host_fx_image);
4520 preempt_enable();
4521
4522 vcpu->arch.cr0 |= X86_CR0_ET;
4523 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
4524 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4525 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
4526 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4527 }
4528 EXPORT_SYMBOL_GPL(fx_init);
4529
4530 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4531 {
4532 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4533 return;
4534
4535 vcpu->guest_fpu_loaded = 1;
4536 kvm_fx_save(&vcpu->arch.host_fx_image);
4537 kvm_fx_restore(&vcpu->arch.guest_fx_image);
4538 }
4539 EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4540
4541 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4542 {
4543 if (!vcpu->guest_fpu_loaded)
4544 return;
4545
4546 vcpu->guest_fpu_loaded = 0;
4547 kvm_fx_save(&vcpu->arch.guest_fx_image);
4548 kvm_fx_restore(&vcpu->arch.host_fx_image);
4549 ++vcpu->stat.fpu_reload;
4550 }
4551 EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
4552
4553 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4554 {
4555 if (vcpu->arch.time_page) {
4556 kvm_release_page_dirty(vcpu->arch.time_page);
4557 vcpu->arch.time_page = NULL;
4558 }
4559
4560 kvm_x86_ops->vcpu_free(vcpu);
4561 }
4562
4563 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4564 unsigned int id)
4565 {
4566 return kvm_x86_ops->vcpu_create(kvm, id);
4567 }
4568
4569 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4570 {
4571 int r;
4572
4573 /* We do fxsave: this must be aligned. */
4574 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
4575
4576 vcpu->arch.mtrr_state.have_fixed = 1;
4577 vcpu_load(vcpu);
4578 r = kvm_arch_vcpu_reset(vcpu);
4579 if (r == 0)
4580 r = kvm_mmu_setup(vcpu);
4581 vcpu_put(vcpu);
4582 if (r < 0)
4583 goto free_vcpu;
4584
4585 return 0;
4586 free_vcpu:
4587 kvm_x86_ops->vcpu_free(vcpu);
4588 return r;
4589 }
4590
4591 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
4592 {
4593 vcpu_load(vcpu);
4594 kvm_mmu_unload(vcpu);
4595 vcpu_put(vcpu);
4596
4597 kvm_x86_ops->vcpu_free(vcpu);
4598 }
4599
4600 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4601 {
4602 vcpu->arch.nmi_pending = false;
4603 vcpu->arch.nmi_injected = false;
4604
4605 vcpu->arch.switch_db_regs = 0;
4606 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4607 vcpu->arch.dr6 = DR6_FIXED_1;
4608 vcpu->arch.dr7 = DR7_FIXED_1;
4609
4610 return kvm_x86_ops->vcpu_reset(vcpu);
4611 }
4612
4613 void kvm_arch_hardware_enable(void *garbage)
4614 {
4615 kvm_x86_ops->hardware_enable(garbage);
4616 }
4617
4618 void kvm_arch_hardware_disable(void *garbage)
4619 {
4620 kvm_x86_ops->hardware_disable(garbage);
4621 }
4622
4623 int kvm_arch_hardware_setup(void)
4624 {
4625 return kvm_x86_ops->hardware_setup();
4626 }
4627
4628 void kvm_arch_hardware_unsetup(void)
4629 {
4630 kvm_x86_ops->hardware_unsetup();
4631 }
4632
4633 void kvm_arch_check_processor_compat(void *rtn)
4634 {
4635 kvm_x86_ops->check_processor_compatibility(rtn);
4636 }
4637
4638 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4639 {
4640 struct page *page;
4641 struct kvm *kvm;
4642 int r;
4643
4644 BUG_ON(vcpu->kvm == NULL);
4645 kvm = vcpu->kvm;
4646
4647 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4648 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
4649 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4650 else
4651 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
4652
4653 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4654 if (!page) {
4655 r = -ENOMEM;
4656 goto fail;
4657 }
4658 vcpu->arch.pio_data = page_address(page);
4659
4660 r = kvm_mmu_create(vcpu);
4661 if (r < 0)
4662 goto fail_free_pio_data;
4663
4664 if (irqchip_in_kernel(kvm)) {
4665 r = kvm_create_lapic(vcpu);
4666 if (r < 0)
4667 goto fail_mmu_destroy;
4668 }
4669
4670 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4671 GFP_KERNEL);
4672 if (!vcpu->arch.mce_banks) {
4673 r = -ENOMEM;
4674 goto fail_mmu_destroy;
4675 }
4676 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4677
4678 return 0;
4679
4680 fail_mmu_destroy:
4681 kvm_mmu_destroy(vcpu);
4682 fail_free_pio_data:
4683 free_page((unsigned long)vcpu->arch.pio_data);
4684 fail:
4685 return r;
4686 }
4687
4688 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4689 {
4690 kvm_free_lapic(vcpu);
4691 down_read(&vcpu->kvm->slots_lock);
4692 kvm_mmu_destroy(vcpu);
4693 up_read(&vcpu->kvm->slots_lock);
4694 free_page((unsigned long)vcpu->arch.pio_data);
4695 }
4696
4697 struct kvm *kvm_arch_create_vm(void)
4698 {
4699 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4700
4701 if (!kvm)
4702 return ERR_PTR(-ENOMEM);
4703
4704 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4705 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
4706
4707 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4708 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4709
4710 rdtscll(kvm->arch.vm_init_tsc);
4711
4712 return kvm;
4713 }
4714
4715 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4716 {
4717 vcpu_load(vcpu);
4718 kvm_mmu_unload(vcpu);
4719 vcpu_put(vcpu);
4720 }
4721
4722 static void kvm_free_vcpus(struct kvm *kvm)
4723 {
4724 unsigned int i;
4725 struct kvm_vcpu *vcpu;
4726
4727 /*
4728 * Unpin any mmu pages first.
4729 */
4730 kvm_for_each_vcpu(i, vcpu, kvm)
4731 kvm_unload_vcpu_mmu(vcpu);
4732 kvm_for_each_vcpu(i, vcpu, kvm)
4733 kvm_arch_vcpu_free(vcpu);
4734
4735 mutex_lock(&kvm->lock);
4736 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4737 kvm->vcpus[i] = NULL;
4738
4739 atomic_set(&kvm->online_vcpus, 0);
4740 mutex_unlock(&kvm->lock);
4741 }
4742
4743 void kvm_arch_sync_events(struct kvm *kvm)
4744 {
4745 kvm_free_all_assigned_devices(kvm);
4746 }
4747
4748 void kvm_arch_destroy_vm(struct kvm *kvm)
4749 {
4750 kvm_iommu_unmap_guest(kvm);
4751 kvm_free_pit(kvm);
4752 kfree(kvm->arch.vpic);
4753 kfree(kvm->arch.vioapic);
4754 kvm_free_vcpus(kvm);
4755 kvm_free_physmem(kvm);
4756 if (kvm->arch.apic_access_page)
4757 put_page(kvm->arch.apic_access_page);
4758 if (kvm->arch.ept_identity_pagetable)
4759 put_page(kvm->arch.ept_identity_pagetable);
4760 kfree(kvm);
4761 }
4762
4763 int kvm_arch_set_memory_region(struct kvm *kvm,
4764 struct kvm_userspace_memory_region *mem,
4765 struct kvm_memory_slot old,
4766 int user_alloc)
4767 {
4768 int npages = mem->memory_size >> PAGE_SHIFT;
4769 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4770
4771 /*To keep backward compatibility with older userspace,
4772 *x86 needs to hanlde !user_alloc case.
4773 */
4774 if (!user_alloc) {
4775 if (npages && !old.rmap) {
4776 unsigned long userspace_addr;
4777
4778 down_write(&current->mm->mmap_sem);
4779 userspace_addr = do_mmap(NULL, 0,
4780 npages * PAGE_SIZE,
4781 PROT_READ | PROT_WRITE,
4782 MAP_PRIVATE | MAP_ANONYMOUS,
4783 0);
4784 up_write(&current->mm->mmap_sem);
4785
4786 if (IS_ERR((void *)userspace_addr))
4787 return PTR_ERR((void *)userspace_addr);
4788
4789 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4790 spin_lock(&kvm->mmu_lock);
4791 memslot->userspace_addr = userspace_addr;
4792 spin_unlock(&kvm->mmu_lock);
4793 } else {
4794 if (!old.user_alloc && old.rmap) {
4795 int ret;
4796
4797 down_write(&current->mm->mmap_sem);
4798 ret = do_munmap(current->mm, old.userspace_addr,
4799 old.npages * PAGE_SIZE);
4800 up_write(&current->mm->mmap_sem);
4801 if (ret < 0)
4802 printk(KERN_WARNING
4803 "kvm_vm_ioctl_set_memory_region: "
4804 "failed to munmap memory\n");
4805 }
4806 }
4807 }
4808
4809 spin_lock(&kvm->mmu_lock);
4810 if (!kvm->arch.n_requested_mmu_pages) {
4811 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4812 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4813 }
4814
4815 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4816 spin_unlock(&kvm->mmu_lock);
4817 kvm_flush_remote_tlbs(kvm);
4818
4819 return 0;
4820 }
4821
4822 void kvm_arch_flush_shadow(struct kvm *kvm)
4823 {
4824 kvm_mmu_zap_all(kvm);
4825 kvm_reload_remote_mmus(kvm);
4826 }
4827
4828 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4829 {
4830 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
4831 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4832 || vcpu->arch.nmi_pending;
4833 }
4834
4835 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4836 {
4837 int me;
4838 int cpu = vcpu->cpu;
4839
4840 if (waitqueue_active(&vcpu->wq)) {
4841 wake_up_interruptible(&vcpu->wq);
4842 ++vcpu->stat.halt_wakeup;
4843 }
4844
4845 me = get_cpu();
4846 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4847 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4848 smp_send_reschedule(cpu);
4849 put_cpu();
4850 }
4851
4852 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4853 {
4854 return kvm_x86_ops->interrupt_allowed(vcpu);
4855 }
4856
4857 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4858 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4859 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4860 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4861 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Linux kernel - Deliverables
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