arch/x86/pci/amd_bus.c

   1 #include <linux/init.h>
   2 #include <linux/pci.h>
   3 #include <linux/topology.h>
   4 #include <linux/cpu.h>
   5 #include <asm/pci_x86.h>
   6
   7 #ifdef CONFIG_X86_64
   8 #include <asm/pci-direct.h>
   9 #include <asm/mpspec.h>
  10 #include <linux/cpumask.h>
  11 #endif
  12
  13 #include "bus_numa.h"
  14
  15 /*
  16  * This discovers the pcibus <-> node mapping on AMD K8.
  17  * also get peer root bus resource for io,mmio
  18  */
  19
  20 #ifdef CONFIG_X86_64
  21
  22 int pci_root_num;
  23 struct pci_root_info pci_root_info[PCI_ROOT_NR];
  24 static int found_all_numa_early;
  25
  26 void x86_pci_root_bus_res_quirks(struct pci_bus *b)
  27 {
  28         int i;
  29         int j;
  30         struct pci_root_info *info;
  31
  32         /* don't go for it if _CRS is used already */
  33         if (b->resource[0] != &ioport_resource ||
  34             b->resource[1] != &iomem_resource)
  35                 return;
  36
  37         if (!pci_root_num)
  38                 return;
  39
  40         /* for amd, if only one root bus, don't need to do anything */
  41         if (pci_root_num < 2 && found_all_numa_early)
  42                 return;
  43
  44         for (i = 0; i < pci_root_num; i++) {
  45                 if (pci_root_info[i].bus_min == b->number)
  46                         break;
  47         }
  48
  49         if (i == pci_root_num)
  50                 return;
  51
  52         printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n",
  53                         b->number);
  54
  55         info = &pci_root_info[i];
  56         for (j = 0; j < info->res_num; j++) {
  57                 struct resource *res;
  58                 struct resource *root;
  59
  60                 res = &info->res[j];
  61                 b->resource[j] = res;
  62                 if (res->flags & IORESOURCE_IO)
  63                         root = &ioport_resource;
  64                 else
  65                         root = &iomem_resource;
  66                 insert_resource(root, res);
  67         }
  68 }
  69
  70 #define RANGE_NUM 16
  71
  72 struct res_range {
  73         size_t start;
  74         size_t end;
  75 };
  76
  77 static void __init update_range(struct res_range *range, size_t start,
  78                                 size_t end)
  79 {
  80         int i;
  81         int j;
  82
  83         for (j = 0; j < RANGE_NUM; j++) {
  84                 if (!range[j].end)
  85                         continue;
  86
  87                 if (start <= range[j].start && end >= range[j].end) {
  88                         range[j].start = 0;
  89                         range[j].end = 0;
  90                         continue;
  91                 }
  92
  93                 if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
  94                         range[j].start = end + 1;
  95                         continue;
  96                 }
  97
  98
  99                 if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
 100                         range[j].end = start - 1;
 101                         continue;
 102                 }
 103
 104                 if (start > range[j].start && end < range[j].end) {
 105                         /* find the new spare */
 106                         for (i = 0; i < RANGE_NUM; i++) {
 107                                 if (range[i].end == 0)
 108                                         break;
 109                         }
 110                         if (i < RANGE_NUM) {
 111                                 range[i].end = range[j].end;
 112                                 range[i].start = end + 1;
 113                         } else {
 114                                 printk(KERN_ERR "run of slot in ranges\n");
 115                         }
 116                         range[j].end = start - 1;
 117                         continue;
 118                 }
 119         }
 120 }
 121
 122 void __init update_res(struct pci_root_info *info, size_t start,
 123                               size_t end, unsigned long flags, int merge)
 124 {
 125         int i;
 126         struct resource *res;
 127
 128         if (start > end)
 129                 return;
 130
 131         if (!merge)
 132                 goto addit;
 133
 134         /* try to merge it with old one */
 135         for (i = 0; i < info->res_num; i++) {
 136                 size_t final_start, final_end;
 137                 size_t common_start, common_end;
 138
 139                 res = &info->res[i];
 140                 if (res->flags != flags)
 141                         continue;
 142
 143                 common_start = max((size_t)res->start, start);
 144                 common_end = min((size_t)res->end, end);
 145                 if (common_start > common_end + 1)
 146                         continue;
 147
 148                 final_start = min((size_t)res->start, start);
 149                 final_end = max((size_t)res->end, end);
 150
 151                 res->start = final_start;
 152                 res->end = final_end;
 153                 return;
 154         }
 155
 156 addit:
 157
 158         /* need to add that */
 159         if (info->res_num >= RES_NUM)
 160                 return;
 161
 162         res = &info->res[info->res_num];
 163         res->name = info->name;
 164         res->flags = flags;
 165         res->start = start;
 166         res->end = end;
 167         res->child = NULL;
 168         info->res_num++;
 169 }
 170
 171 struct pci_hostbridge_probe {
 172         u32 bus;
 173         u32 slot;
 174         u32 vendor;
 175         u32 device;
 176 };
 177
 178 static struct pci_hostbridge_probe pci_probes[] __initdata = {
 179         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
 180         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
 181         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
 182         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
 183 };
 184
 185 static u64 __initdata fam10h_mmconf_start;
 186 static u64 __initdata fam10h_mmconf_end;
 187 static void __init get_pci_mmcfg_amd_fam10h_range(void)
 188 {
 189         u32 address;
 190         u64 base, msr;
 191         unsigned segn_busn_bits;
 192
 193         /* assume all cpus from fam10h have mmconf */
 194         if (boot_cpu_data.x86 < 0x10)
 195                 return;
 196
 197         address = MSR_FAM10H_MMIO_CONF_BASE;
 198         rdmsrl(address, msr);
 199
 200         /* mmconfig is not enable */
 201         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 202                 return;
 203
 204         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 205
 206         segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 207                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 208
 209         fam10h_mmconf_start = base;
 210         fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
 211 }
 212
 213 /**
 214  * early_fill_mp_bus_to_node()
 215  * called before pcibios_scan_root and pci_scan_bus
 216  * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 217  * Registers found in the K8 northbridge
 218  */
 219 static int __init early_fill_mp_bus_info(void)
 220 {
 221         int i;
 222         int j;
 223         unsigned bus;
 224         unsigned slot;
 225         int node;
 226         int link;
 227         int def_node;
 228         int def_link;
 229         struct pci_root_info *info;
 230         u32 reg;
 231         struct resource *res;
 232         size_t start;
 233         size_t end;
 234         struct res_range range[RANGE_NUM];
 235         u64 val;
 236         u32 address;
 237
 238         if (!early_pci_allowed())
 239                 return -1;
 240
 241         found_all_numa_early = 0;
 242         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
 243                 u32 id;
 244                 u16 device;
 245                 u16 vendor;
 246
 247                 bus = pci_probes[i].bus;
 248                 slot = pci_probes[i].slot;
 249                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
 250
 251                 vendor = id & 0xffff;
 252                 device = (id>>16) & 0xffff;
 253                 if (pci_probes[i].vendor == vendor &&
 254                     pci_probes[i].device == device) {
 255                         found_all_numa_early = 1;
 256                         break;
 257                 }
 258         }
 259
 260         if (!found_all_numa_early)
 261                 return 0;
 262
 263         pci_root_num = 0;
 264         for (i = 0; i < 4; i++) {
 265                 int min_bus;
 266                 int max_bus;
 267                 reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
 268
 269                 /* Check if that register is enabled for bus range */
 270                 if ((reg & 7) != 3)
 271                         continue;
 272
 273                 min_bus = (reg >> 16) & 0xff;
 274                 max_bus = (reg >> 24) & 0xff;
 275                 node = (reg >> 4) & 0x07;
 276 #ifdef CONFIG_NUMA
 277                 for (j = min_bus; j <= max_bus; j++)
 278                         set_mp_bus_to_node(j, node);
 279 #endif
 280                 link = (reg >> 8) & 0x03;
 281
 282                 info = &pci_root_info[pci_root_num];
 283                 info->bus_min = min_bus;
 284                 info->bus_max = max_bus;
 285                 info->node = node;
 286                 info->link = link;
 287                 sprintf(info->name, "PCI Bus #%02x", min_bus);
 288                 pci_root_num++;
 289         }
 290
 291         /* get the default node and link for left over res */
 292         reg = read_pci_config(bus, slot, 0, 0x60);
 293         def_node = (reg >> 8) & 0x07;
 294         reg = read_pci_config(bus, slot, 0, 0x64);
 295         def_link = (reg >> 8) & 0x03;
 296
 297         memset(range, 0, sizeof(range));
 298         range[0].end = 0xffff;
 299         /* io port resource */
 300         for (i = 0; i < 4; i++) {
 301                 reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
 302                 if (!(reg & 3))
 303                         continue;
 304
 305                 start = reg & 0xfff000;
 306                 reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
 307                 node = reg & 0x07;
 308                 link = (reg >> 4) & 0x03;
 309                 end = (reg & 0xfff000) | 0xfff;
 310
 311                 /* find the position */
 312                 for (j = 0; j < pci_root_num; j++) {
 313                         info = &pci_root_info[j];
 314                         if (info->node == node && info->link == link)
 315                                 break;
 316                 }
 317                 if (j == pci_root_num)
 318                         continue; /* not found */
 319
 320                 info = &pci_root_info[j];
 321                 printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
 322                        node, link, (u64)start, (u64)end);
 323
 324                 /* kernel only handle 16 bit only */
 325                 if (end > 0xffff)
 326                         end = 0xffff;
 327                 update_res(info, start, end, IORESOURCE_IO, 1);
 328                 update_range(range, start, end);
 329         }
 330         /* add left over io port range to def node/link, [0, 0xffff] */
 331         /* find the position */
 332         for (j = 0; j < pci_root_num; j++) {
 333                 info = &pci_root_info[j];
 334                 if (info->node == def_node && info->link == def_link)
 335                         break;
 336         }
 337         if (j < pci_root_num) {
 338                 info = &pci_root_info[j];
 339                 for (i = 0; i < RANGE_NUM; i++) {
 340                         if (!range[i].end)
 341                                 continue;
 342
 343                         update_res(info, range[i].start, range[i].end,
 344                                    IORESOURCE_IO, 1);
 345                 }
 346         }
 347
 348         memset(range, 0, sizeof(range));
 349         /* 0xfd00000000-0xffffffffff for HT */
 350         range[0].end = (0xfdULL<<32) - 1;
 351
 352         /* need to take out [0, TOM) for RAM*/
 353         address = MSR_K8_TOP_MEM1;
 354         rdmsrl(address, val);
 355         end = (val & 0xffffff800000ULL);
 356         printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
 357         if (end < (1ULL<<32))
 358                 update_range(range, 0, end - 1);
 359
 360         /* get mmconfig */
 361         get_pci_mmcfg_amd_fam10h_range();
 362         /* need to take out mmconf range */
 363         if (fam10h_mmconf_end) {
 364                 printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
 365                 update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
 366         }
 367
 368         /* mmio resource */
 369         for (i = 0; i < 8; i++) {
 370                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 371                 if (!(reg & 3))
 372                         continue;
 373
 374                 start = reg & 0xffffff00; /* 39:16 on 31:8*/
 375                 start <<= 8;
 376                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 377                 node = reg & 0x07;
 378                 link = (reg >> 4) & 0x03;
 379                 end = (reg & 0xffffff00);
 380                 end <<= 8;
 381                 end |= 0xffff;
 382
 383                 /* find the position */
 384                 for (j = 0; j < pci_root_num; j++) {
 385                         info = &pci_root_info[j];
 386                         if (info->node == node && info->link == link)
 387                                 break;
 388                 }
 389                 if (j == pci_root_num)
 390                         continue; /* not found */
 391
 392                 info = &pci_root_info[j];
 393
 394                 printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
 395                        node, link, (u64)start, (u64)end);
 396                 /*
 397                  * some sick allocation would have range overlap with fam10h
 398                  * mmconf range, so need to update start and end.
 399                  */
 400                 if (fam10h_mmconf_end) {
 401                         int changed = 0;
 402                         u64 endx = 0;
 403                         if (start >= fam10h_mmconf_start &&
 404                             start <= fam10h_mmconf_end) {
 405                                 start = fam10h_mmconf_end + 1;
 406                                 changed = 1;
 407                         }
 408
 409                         if (end >= fam10h_mmconf_start &&
 410                             end <= fam10h_mmconf_end) {
 411                                 end = fam10h_mmconf_start - 1;
 412                                 changed = 1;
 413                         }
 414
 415                         if (start < fam10h_mmconf_start &&
 416                             end > fam10h_mmconf_end) {
 417                                 /* we got a hole */
 418                                 endx = fam10h_mmconf_start - 1;
 419                                 update_res(info, start, endx, IORESOURCE_MEM, 0);
 420                                 update_range(range, start, endx);
 421                                 printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
 422                                 start = fam10h_mmconf_end + 1;
 423                                 changed = 1;
 424                         }
 425                         if (changed) {
 426                                 if (start <= end) {
 427                                         printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
 428                                 } else {
 429                                         printk(KERN_CONT "%s\n", endx?"":" ==> none");
 430                                         continue;
 431                                 }
 432                         }
 433                 }
 434
 435                 update_res(info, start, end, IORESOURCE_MEM, 1);
 436                 update_range(range, start, end);
 437                 printk(KERN_CONT "\n");
 438         }
 439
 440         /* need to take out [4G, TOM2) for RAM*/
 441         /* SYS_CFG */
 442         address = MSR_K8_SYSCFG;
 443         rdmsrl(address, val);
 444         /* TOP_MEM2 is enabled? */
 445         if (val & (1<<21)) {
 446                 /* TOP_MEM2 */
 447                 address = MSR_K8_TOP_MEM2;
 448                 rdmsrl(address, val);
 449                 end = (val & 0xffffff800000ULL);
 450                 printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
 451                 update_range(range, 1ULL<<32, end - 1);
 452         }
 453
 454         /*
 455          * add left over mmio range to def node/link ?
 456          * that is tricky, just record range in from start_min to 4G
 457          */
 458         for (j = 0; j < pci_root_num; j++) {
 459                 info = &pci_root_info[j];
 460                 if (info->node == def_node && info->link == def_link)
 461                         break;
 462         }
 463         if (j < pci_root_num) {
 464                 info = &pci_root_info[j];
 465
 466                 for (i = 0; i < RANGE_NUM; i++) {
 467                         if (!range[i].end)
 468                                 continue;
 469
 470                         update_res(info, range[i].start, range[i].end,
 471                                    IORESOURCE_MEM, 1);
 472                 }
 473         }
 474
 475         for (i = 0; i < pci_root_num; i++) {
 476                 int res_num;
 477                 int busnum;
 478
 479                 info = &pci_root_info[i];
 480                 res_num = info->res_num;
 481                 busnum = info->bus_min;
 482                 printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
 483                        info->bus_min, info->bus_max, info->node, info->link);
 484                 for (j = 0; j < res_num; j++) {
 485                         res = &info->res[j];
 486                         printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
 487                                busnum, j,
 488                                (res->flags & IORESOURCE_IO)?"io port":"mmio",
 489                                res->start, res->end);
 490                 }
 491         }
 492
 493         return 0;
 494 }
 495
 496 #else  /* !CONFIG_X86_64 */
 497
 498 static int __init early_fill_mp_bus_info(void) { return 0; }
 499
 500 #endif /* !CONFIG_X86_64 */
 501
 502 /* common 32/64 bit code */
 503
 504 #define ENABLE_CF8_EXT_CFG      (1ULL << 46)
 505
 506 static void enable_pci_io_ecs(void *unused)
 507 {
 508         u64 reg;
 509         rdmsrl(MSR_AMD64_NB_CFG, reg);
 510         if (!(reg & ENABLE_CF8_EXT_CFG)) {
 511                 reg |= ENABLE_CF8_EXT_CFG;
 512                 wrmsrl(MSR_AMD64_NB_CFG, reg);
 513         }
 514 }
 515
 516 static int __cpuinit amd_cpu_notify(struct notifier_block *self,
 517                                     unsigned long action, void *hcpu)
 518 {
 519         int cpu = (long)hcpu;
 520         switch (action) {
 521         case CPU_ONLINE:
 522         case CPU_ONLINE_FROZEN:
 523                 smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
 524                 break;
 525         default:
 526                 break;
 527         }
 528         return NOTIFY_OK;
 529 }
 530
 531 static struct notifier_block __cpuinitdata amd_cpu_notifier = {
 532         .notifier_call  = amd_cpu_notify,
 533 };
 534
 535 static int __init pci_io_ecs_init(void)
 536 {
 537         int cpu;
 538
 539         /* assume all cpus from fam10h have IO ECS */
 540         if (boot_cpu_data.x86 < 0x10)
 541                 return 0;
 542
 543         register_cpu_notifier(&amd_cpu_notifier);
 544         for_each_online_cpu(cpu)
 545                 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
 546                                (void *)(long)cpu);
 547         pci_probe |= PCI_HAS_IO_ECS;
 548
 549         return 0;
 550 }
 551
 552 static int __init amd_postcore_init(void)
 553 {
 554         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
 555                 return 0;
 556
 557         early_fill_mp_bus_info();
 558         pci_io_ecs_init();
 559
 560         return 0;
 561 }
 562
 563 postcore_initcall(amd_postcore_init);