arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/acpi.h>
  16 #include <linux/bitmap.h>
  17 #include <asm/e820.h>
  18 #include <asm/pci_x86.h>
  19
  20 /* aperture is up to 256MB but BIOS may reserve less */
  21 #define MMCONFIG_APER_MIN       (2 * 1024*1024)
  22 #define MMCONFIG_APER_MAX       (256 * 1024*1024)
  23
  24 /* Indicate if the mmcfg resources have been placed into the resource table. */
  25 static int __initdata pci_mmcfg_resources_inserted;
  26
  27 static const char __init *pci_mmcfg_e7520(void)
  28 {
  29         u32 win;
  30         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
  31
  32         win = win & 0xf000;
  33         if(win == 0x0000 || win == 0xf000)
  34                 pci_mmcfg_config_num = 0;
  35         else {
  36                 pci_mmcfg_config_num = 1;
  37                 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
  38                 if (!pci_mmcfg_config)
  39                         return NULL;
  40                 pci_mmcfg_config[0].address = win << 16;
  41                 pci_mmcfg_config[0].pci_segment = 0;
  42                 pci_mmcfg_config[0].start_bus_number = 0;
  43                 pci_mmcfg_config[0].end_bus_number = 255;
  44         }
  45
  46         return "Intel Corporation E7520 Memory Controller Hub";
  47 }
  48
  49 static const char __init *pci_mmcfg_intel_945(void)
  50 {
  51         u32 pciexbar, mask = 0, len = 0;
  52
  53         pci_mmcfg_config_num = 1;
  54
  55         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
  56
  57         /* Enable bit */
  58         if (!(pciexbar & 1))
  59                 pci_mmcfg_config_num = 0;
  60
  61         /* Size bits */
  62         switch ((pciexbar >> 1) & 3) {
  63         case 0:
  64                 mask = 0xf0000000U;
  65                 len  = 0x10000000U;
  66                 break;
  67         case 1:
  68                 mask = 0xf8000000U;
  69                 len  = 0x08000000U;
  70                 break;
  71         case 2:
  72                 mask = 0xfc000000U;
  73                 len  = 0x04000000U;
  74                 break;
  75         default:
  76                 pci_mmcfg_config_num = 0;
  77         }
  78
  79         /* Errata #2, things break when not aligned on a 256Mb boundary */
  80         /* Can only happen in 64M/128M mode */
  81
  82         if ((pciexbar & mask) & 0x0fffffffU)
  83                 pci_mmcfg_config_num = 0;
  84
  85         /* Don't hit the APIC registers and their friends */
  86         if ((pciexbar & mask) >= 0xf0000000U)
  87                 pci_mmcfg_config_num = 0;
  88
  89         if (pci_mmcfg_config_num) {
  90                 pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
  91                 if (!pci_mmcfg_config)
  92                         return NULL;
  93                 pci_mmcfg_config[0].address = pciexbar & mask;
  94                 pci_mmcfg_config[0].pci_segment = 0;
  95                 pci_mmcfg_config[0].start_bus_number = 0;
  96                 pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
  97         }
  98
  99         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 100 }
 101
 102 static const char __init *pci_mmcfg_amd_fam10h(void)
 103 {
 104         u32 low, high, address;
 105         u64 base, msr;
 106         int i;
 107         unsigned segnbits = 0, busnbits;
 108
 109         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 110                 return NULL;
 111
 112         address = MSR_FAM10H_MMIO_CONF_BASE;
 113         if (rdmsr_safe(address, &low, &high))
 114                 return NULL;
 115
 116         msr = high;
 117         msr <<= 32;
 118         msr |= low;
 119
 120         /* mmconfig is not enable */
 121         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 122                 return NULL;
 123
 124         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 125
 126         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 127                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 128
 129         /*
 130          * only handle bus 0 ?
 131          * need to skip it
 132          */
 133         if (!busnbits)
 134                 return NULL;
 135
 136         if (busnbits > 8) {
 137                 segnbits = busnbits - 8;
 138                 busnbits = 8;
 139         }
 140
 141         pci_mmcfg_config_num = (1 << segnbits);
 142         pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]) *
 143                                    pci_mmcfg_config_num, GFP_KERNEL);
 144         if (!pci_mmcfg_config)
 145                 return NULL;
 146
 147         for (i = 0; i < (1 << segnbits); i++) {
 148                 pci_mmcfg_config[i].address = base + (1<<28) * i;
 149                 pci_mmcfg_config[i].pci_segment = i;
 150                 pci_mmcfg_config[i].start_bus_number = 0;
 151                 pci_mmcfg_config[i].end_bus_number = (1 << busnbits) - 1;
 152         }
 153
 154         return "AMD Family 10h NB";
 155 }
 156
 157 struct pci_mmcfg_hostbridge_probe {
 158         u32 bus;
 159         u32 devfn;
 160         u32 vendor;
 161         u32 device;
 162         const char *(*probe)(void);
 163 };
 164
 165 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 166         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 167           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 168         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 169           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 170         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 171           0x1200, pci_mmcfg_amd_fam10h },
 172         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 173           0x1200, pci_mmcfg_amd_fam10h },
 174 };
 175
 176 static int __init pci_mmcfg_check_hostbridge(void)
 177 {
 178         u32 l;
 179         u32 bus, devfn;
 180         u16 vendor, device;
 181         int i;
 182         const char *name;
 183
 184         if (!raw_pci_ops)
 185                 return 0;
 186
 187         pci_mmcfg_config_num = 0;
 188         pci_mmcfg_config = NULL;
 189         name = NULL;
 190
 191         for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 192                 bus =  pci_mmcfg_probes[i].bus;
 193                 devfn = pci_mmcfg_probes[i].devfn;
 194                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 195                 vendor = l & 0xffff;
 196                 device = (l >> 16) & 0xffff;
 197
 198                 if (pci_mmcfg_probes[i].vendor == vendor &&
 199                     pci_mmcfg_probes[i].device == device)
 200                         name = pci_mmcfg_probes[i].probe();
 201         }
 202
 203         if (name) {
 204                 printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
 205                        name, pci_mmcfg_config_num ? "with" : "without");
 206         }
 207
 208         return name != NULL;
 209 }
 210
 211 static void __init pci_mmcfg_insert_resources(void)
 212 {
 213 #define PCI_MMCFG_RESOURCE_NAME_LEN 19
 214         int i;
 215         struct resource *res;
 216         char *names;
 217         unsigned num_buses;
 218
 219         res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
 220                         pci_mmcfg_config_num, GFP_KERNEL);
 221         if (!res) {
 222                 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
 223                 return;
 224         }
 225
 226         names = (void *)&res[pci_mmcfg_config_num];
 227         for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
 228                 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
 229                 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
 230                 res->name = names;
 231                 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
 232                          cfg->pci_segment);
 233                 res->start = cfg->address;
 234                 res->end = res->start + (num_buses << 20) - 1;
 235                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 236                 insert_resource(&iomem_resource, res);
 237                 names += PCI_MMCFG_RESOURCE_NAME_LEN;
 238         }
 239
 240         /* Mark that the resources have been inserted. */
 241         pci_mmcfg_resources_inserted = 1;
 242 }
 243
 244 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
 245                                               void *data)
 246 {
 247         struct resource *mcfg_res = data;
 248         struct acpi_resource_address64 address;
 249         acpi_status status;
 250
 251         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 252                 struct acpi_resource_fixed_memory32 *fixmem32 =
 253                         &res->data.fixed_memory32;
 254                 if (!fixmem32)
 255                         return AE_OK;
 256                 if ((mcfg_res->start >= fixmem32->address) &&
 257                     (mcfg_res->end < (fixmem32->address +
 258                                       fixmem32->address_length))) {
 259                         mcfg_res->flags = 1;
 260                         return AE_CTRL_TERMINATE;
 261                 }
 262         }
 263         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 264             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 265                 return AE_OK;
 266
 267         status = acpi_resource_to_address64(res, &address);
 268         if (ACPI_FAILURE(status) ||
 269            (address.address_length <= 0) ||
 270            (address.resource_type != ACPI_MEMORY_RANGE))
 271                 return AE_OK;
 272
 273         if ((mcfg_res->start >= address.minimum) &&
 274             (mcfg_res->end < (address.minimum + address.address_length))) {
 275                 mcfg_res->flags = 1;
 276                 return AE_CTRL_TERMINATE;
 277         }
 278         return AE_OK;
 279 }
 280
 281 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
 282                 void *context, void **rv)
 283 {
 284         struct resource *mcfg_res = context;
 285
 286         acpi_walk_resources(handle, METHOD_NAME__CRS,
 287                             check_mcfg_resource, context);
 288
 289         if (mcfg_res->flags)
 290                 return AE_CTRL_TERMINATE;
 291
 292         return AE_OK;
 293 }
 294
 295 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 296 {
 297         struct resource mcfg_res;
 298
 299         mcfg_res.start = start;
 300         mcfg_res.end = end;
 301         mcfg_res.flags = 0;
 302
 303         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 304
 305         if (!mcfg_res.flags)
 306                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 307                                  NULL);
 308
 309         return mcfg_res.flags;
 310 }
 311
 312 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 313
 314 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
 315                 u64 addr, u64 size, int i,
 316                 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
 317 {
 318         u64 old_size = size;
 319         int valid = 0;
 320
 321         while (!is_reserved(addr, addr + size - 1, E820_RESERVED)) {
 322                 size >>= 1;
 323                 if (size < (16UL<<20))
 324                         break;
 325         }
 326
 327         if (size >= (16UL<<20) || size == old_size) {
 328                 printk(KERN_NOTICE
 329                        "PCI: MCFG area at %Lx reserved in %s\n",
 330                         addr, with_e820?"E820":"ACPI motherboard resources");
 331                 valid = 1;
 332
 333                 if (old_size != size) {
 334                         /* update end_bus_number */
 335                         cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
 336                         printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
 337                                "segment %hu buses %u - %u\n",
 338                                i, (unsigned long)cfg->address, cfg->pci_segment,
 339                                (unsigned int)cfg->start_bus_number,
 340                                (unsigned int)cfg->end_bus_number);
 341                 }
 342         }
 343
 344         return valid;
 345 }
 346
 347 static void __init pci_mmcfg_reject_broken(int early)
 348 {
 349         typeof(pci_mmcfg_config[0]) *cfg;
 350         int i;
 351
 352         if ((pci_mmcfg_config_num == 0) ||
 353             (pci_mmcfg_config == NULL) ||
 354             (pci_mmcfg_config[0].address == 0))
 355                 return;
 356
 357         cfg = &pci_mmcfg_config[0];
 358
 359         for (i = 0; i < pci_mmcfg_config_num; i++) {
 360                 int valid = 0;
 361                 u64 addr, size;
 362
 363                 cfg = &pci_mmcfg_config[i];
 364                 addr = cfg->start_bus_number;
 365                 addr <<= 20;
 366                 addr += cfg->address;
 367                 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
 368                 size <<= 20;
 369                 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
 370                        "segment %hu buses %u - %u\n",
 371                        i, (unsigned long)cfg->address, cfg->pci_segment,
 372                        (unsigned int)cfg->start_bus_number,
 373                        (unsigned int)cfg->end_bus_number);
 374
 375                 if (!early)
 376                         valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
 377
 378                 if (valid)
 379                         continue;
 380
 381                 if (!early)
 382                         printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
 383                                " reserved in ACPI motherboard resources\n",
 384                                cfg->address);
 385
 386                 /* Don't try to do this check unless configuration
 387                    type 1 is available. how about type 2 ?*/
 388                 if (raw_pci_ops)
 389                         valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
 390
 391                 if (!valid)
 392                         goto reject;
 393         }
 394
 395         return;
 396
 397 reject:
 398         printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
 399         pci_mmcfg_arch_free();
 400         kfree(pci_mmcfg_config);
 401         pci_mmcfg_config = NULL;
 402         pci_mmcfg_config_num = 0;
 403 }
 404
 405 static int __initdata known_bridge;
 406
 407 static void __init __pci_mmcfg_init(int early)
 408 {
 409         /* MMCONFIG disabled */
 410         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 411                 return;
 412
 413         /* MMCONFIG already enabled */
 414         if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
 415                 return;
 416
 417         /* for late to exit */
 418         if (known_bridge)
 419                 return;
 420
 421         if (early) {
 422                 if (pci_mmcfg_check_hostbridge())
 423                         known_bridge = 1;
 424         }
 425
 426         if (!known_bridge) {
 427                 acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
 428                 pci_mmcfg_reject_broken(early);
 429         }
 430
 431         if ((pci_mmcfg_config_num == 0) ||
 432             (pci_mmcfg_config == NULL) ||
 433             (pci_mmcfg_config[0].address == 0))
 434                 return;
 435
 436         if (pci_mmcfg_arch_init())
 437                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 438         else {
 439                 /*
 440                  * Signal not to attempt to insert mmcfg resources because
 441                  * the architecture mmcfg setup could not initialize.
 442                  */
 443                 pci_mmcfg_resources_inserted = 1;
 444         }
 445 }
 446
 447 void __init pci_mmcfg_early_init(void)
 448 {
 449         __pci_mmcfg_init(1);
 450 }
 451
 452 void __init pci_mmcfg_late_init(void)
 453 {
 454         __pci_mmcfg_init(0);
 455 }
 456
 457 static int __init pci_mmcfg_late_insert_resources(void)
 458 {
 459         /*
 460          * If resources are already inserted or we are not using MMCONFIG,
 461          * don't insert the resources.
 462          */
 463         if ((pci_mmcfg_resources_inserted == 1) ||
 464             (pci_probe & PCI_PROBE_MMCONF) == 0 ||
 465             (pci_mmcfg_config_num == 0) ||
 466             (pci_mmcfg_config == NULL) ||
 467             (pci_mmcfg_config[0].address == 0))
 468                 return 1;
 469
 470         /*
 471          * Attempt to insert the mmcfg resources but not with the busy flag
 472          * marked so it won't cause request errors when __request_region is
 473          * called.
 474          */
 475         pci_mmcfg_insert_resources();
 476
 477         return 0;
 478 }
 479
 480 /*
 481  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 482  * misprogrammed MCFG tables that state larger sizes but actually conflict
 483  * with other system resources.
 484  */
 485 late_initcall(pci_mmcfg_late_insert_resources);