2 * Suspend support specific for i386/x86-64.
4 * Distribute under GPLv2
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
11 #include <linux/suspend.h>
12 #include <linux/smp.h>
14 #include <asm/pgtable.h>
15 #include <asm/proto.h>
20 #include <asm/suspend.h>
21 #include <asm/debugreg.h>
24 static struct saved_context saved_context
;
26 unsigned long saved_context_ebx
;
27 unsigned long saved_context_esp
, saved_context_ebp
;
28 unsigned long saved_context_esi
, saved_context_edi
;
29 unsigned long saved_context_eflags
;
32 struct saved_context saved_context
;
36 * __save_processor_state - save CPU registers before creating a
37 * hibernation image and before restoring the memory state from it
38 * @ctxt - structure to store the registers contents in
40 * NOTE: If there is a CPU register the modification of which by the
41 * boot kernel (ie. the kernel used for loading the hibernation image)
42 * might affect the operations of the restored target kernel (ie. the one
43 * saved in the hibernation image), then its contents must be saved by this
44 * function. In other words, if kernel A is hibernated and different
45 * kernel B is used for loading the hibernation image into memory, the
46 * kernel A's __save_processor_state() function must save all registers
47 * needed by kernel A, so that it can operate correctly after the resume
48 * regardless of what kernel B does in the meantime.
50 static void __save_processor_state(struct saved_context
*ctxt
)
53 mtrr_save_fixed_ranges(NULL
);
61 store_gdt(&ctxt
->gdt
);
62 store_idt(&ctxt
->idt
);
65 store_gdt((struct desc_ptr
*)&ctxt
->gdt_limit
);
66 store_idt((struct desc_ptr
*)&ctxt
->idt_limit
);
70 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
75 savesegment(es
, ctxt
->es
);
76 savesegment(fs
, ctxt
->fs
);
77 savesegment(gs
, ctxt
->gs
);
78 savesegment(ss
, ctxt
->ss
);
81 asm volatile ("movw %%ds, %0" : "=m" (ctxt
->ds
));
82 asm volatile ("movw %%es, %0" : "=m" (ctxt
->es
));
83 asm volatile ("movw %%fs, %0" : "=m" (ctxt
->fs
));
84 asm volatile ("movw %%gs, %0" : "=m" (ctxt
->gs
));
85 asm volatile ("movw %%ss, %0" : "=m" (ctxt
->ss
));
87 rdmsrl(MSR_FS_BASE
, ctxt
->fs_base
);
88 rdmsrl(MSR_GS_BASE
, ctxt
->gs_base
);
89 rdmsrl(MSR_KERNEL_GS_BASE
, ctxt
->gs_kernel_base
);
90 mtrr_save_fixed_ranges(NULL
);
92 rdmsrl(MSR_EFER
, ctxt
->efer
);
98 ctxt
->cr0
= read_cr0();
99 ctxt
->cr2
= read_cr2();
100 ctxt
->cr3
= read_cr3();
102 ctxt
->cr4
= read_cr4_safe();
105 ctxt
->cr4
= read_cr4();
106 ctxt
->cr8
= read_cr8();
108 ctxt
->misc_enable_saved
= !rdmsrl_safe(MSR_IA32_MISC_ENABLE
,
112 /* Needed by apm.c */
113 void save_processor_state(void)
115 __save_processor_state(&saved_context
);
118 EXPORT_SYMBOL(save_processor_state
);
121 static void do_fpu_end(void)
124 * Restore FPU regs if necessary.
129 static void fix_processor_context(void)
131 int cpu
= smp_processor_id();
132 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
134 set_tss_desc(cpu
, t
); /*
135 * This just modifies memory; should not be
136 * necessary. But... This is necessary, because
137 * 386 hardware has concept of busy TSS or some
142 get_cpu_gdt_table(cpu
)[GDT_ENTRY_TSS
].type
= 9;
144 syscall_init(); /* This sets MSR_*STAR and related */
146 load_TR_desc(); /* This does ltr */
147 load_LDT(¤t
->active_mm
->context
); /* This does lldt */
151 * __restore_processor_state - restore the contents of CPU registers saved
152 * by __save_processor_state()
153 * @ctxt - structure to load the registers contents from
155 static void __restore_processor_state(struct saved_context
*ctxt
)
157 if (ctxt
->misc_enable_saved
)
158 wrmsrl(MSR_IA32_MISC_ENABLE
, ctxt
->misc_enable
);
162 /* cr4 was introduced in the Pentium CPU */
165 write_cr4(ctxt
->cr4
);
168 wrmsrl(MSR_EFER
, ctxt
->efer
);
169 write_cr8(ctxt
->cr8
);
170 write_cr4(ctxt
->cr4
);
172 write_cr3(ctxt
->cr3
);
173 write_cr2(ctxt
->cr2
);
174 write_cr0(ctxt
->cr0
);
177 * now restore the descriptor tables to their proper values
178 * ltr is done i fix_processor_context().
181 load_gdt(&ctxt
->gdt
);
182 load_idt(&ctxt
->idt
);
185 load_gdt((const struct desc_ptr
*)&ctxt
->gdt_limit
);
186 load_idt((const struct desc_ptr
*)&ctxt
->idt_limit
);
193 loadsegment(es
, ctxt
->es
);
194 loadsegment(fs
, ctxt
->fs
);
195 loadsegment(gs
, ctxt
->gs
);
196 loadsegment(ss
, ctxt
->ss
);
201 if (boot_cpu_has(X86_FEATURE_SEP
))
205 asm volatile ("movw %0, %%ds" :: "r" (ctxt
->ds
));
206 asm volatile ("movw %0, %%es" :: "r" (ctxt
->es
));
207 asm volatile ("movw %0, %%fs" :: "r" (ctxt
->fs
));
208 load_gs_index(ctxt
->gs
);
209 asm volatile ("movw %0, %%ss" :: "r" (ctxt
->ss
));
211 wrmsrl(MSR_FS_BASE
, ctxt
->fs_base
);
212 wrmsrl(MSR_GS_BASE
, ctxt
->gs_base
);
213 wrmsrl(MSR_KERNEL_GS_BASE
, ctxt
->gs_kernel_base
);
217 * restore XCR0 for xsave capable cpu's.
220 xsetbv(XCR_XFEATURE_ENABLED_MASK
, pcntxt_mask
);
222 fix_processor_context();
228 /* Needed by apm.c */
229 void restore_processor_state(void)
231 __restore_processor_state(&saved_context
);
234 EXPORT_SYMBOL(restore_processor_state
);