bfd/cpu-ia64-opc.c

   1 /* Copyright (C) 1998, 1999  Free Software Foundation, Inc.
   2    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   3
   4 This file is part of BFD, the Binary File Descriptor library.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 /* Logically, this code should be part of libopcode but since some of
  21    the operand insertion/extraction functions help bfd to implement
  22    relocations, this code is included as part of elf64-ia64.c.  This
  23    avoids circular dependencies between libopcode and libbfd and also
  24    obviates the need for applications to link in libopcode when all
  25    they really want is libbfd.
  26
  27    --davidm Mon Apr 13 22:14:02 1998 */
  28
  29 #include "../opcodes/ia64-opc.h"
  30
  31 #define NELEMS(a)  ((int) (sizeof (a) / sizeof ((a)[0])))
  32
  33 static const char*
  34 ins_rsvd (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  35 {
  36   return "internal error---this shouldn't happen";
  37 }
  38
  39 static const char*
  40 ext_rsvd (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  41 {
  42   return "internal error---this shouldn't happen";
  43 }
  44
  45 static const char*
  46 ins_const (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  47 {
  48   return 0;
  49 }
  50
  51 static const char*
  52 ext_const (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  53 {
  54   return 0;
  55 }
  56
  57 static const char*
  58 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  59 {
  60   if (value >= 1u << self->field[0].bits)
  61     return "register number out of range";
  62
  63   *code |= value << self->field[0].shift;
  64   return 0;
  65 }
  66
  67 static const char*
  68 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  69 {
  70   *valuep = ((code >> self->field[0].shift)
  71              & ((1u << self->field[0].bits) - 1));
  72   return 0;
  73 }
  74
  75 static const char*
  76 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
  77 {
  78   ia64_insn new = 0;
  79   int i;
  80
  81   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
  82     {
  83       new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
  84               << self->field[i].shift);
  85       value >>= self->field[i].bits;
  86     }
  87   if (value)
  88     return "integer operand out of range";
  89
  90   *code |= new;
  91   return 0;
  92 }
  93
  94 static const char*
  95 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
  96 {
  97   BFD_HOST_U_64_BIT value = 0;
  98   int i, bits = 0, total = 0;
  99
 100   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 101     {
 102       bits = self->field[i].bits;
 103       value |= ((code >> self->field[i].shift)
 104                 & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
 105       total += bits;
 106     }
 107   *valuep = value;
 108   return 0;
 109 }
 110
 111 static const char*
 112 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 113 {
 114   if (value & 0x7)
 115     return "value not an integer multiple of 8";
 116   return ins_immu (self, value >> 3, code);
 117 }
 118
 119 static const char*
 120 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 121 {
 122   const char *result;
 123
 124   result = ext_immu (self, code, valuep);
 125   if (result)
 126     return result;
 127
 128   *valuep = *valuep << 3;
 129   return 0;
 130 }
 131
 132 static const char*
 133 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
 134                  ia64_insn *code, int scale)
 135 {
 136   BFD_HOST_64_BIT svalue = value, sign_bit;
 137   ia64_insn new = 0;
 138   int i;
 139
 140   svalue >>= scale;
 141
 142   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 143     {
 144       new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
 145               << self->field[i].shift);
 146       sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
 147       svalue >>= self->field[i].bits;
 148     }
 149   if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
 150     return "integer operand out of range";
 151
 152   *code |= new;
 153   return 0;
 154 }
 155
 156 static const char*
 157 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
 158                  ia64_insn *valuep, int scale)
 159 {
 160   int i, bits = 0, total = 0, shift;
 161   BFD_HOST_64_BIT val = 0;
 162
 163   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
 164     {
 165       bits = self->field[i].bits;
 166       val |= ((code >> self->field[i].shift)
 167               & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
 168       total += bits;
 169     }
 170   /* sign extend: */
 171   shift = 8*sizeof (val) - total;
 172   val = (val << shift) >> shift;
 173
 174   *valuep = (val << scale);
 175   return 0;
 176 }
 177
 178 static const char*
 179 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 180 {
 181   return ins_imms_scaled (self, value, code, 0);
 182 }
 183
 184 static const char*
 185 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 186 {
 187   if (value == (BFD_HOST_U_64_BIT) 0x100000000)
 188     value = 0;
 189   else
 190     value = (((BFD_HOST_64_BIT)value << 32) >> 32);
 191
 192   return ins_imms_scaled (self, value, code, 0);
 193 }
 194
 195 static const char*
 196 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 197 {
 198   return ext_imms_scaled (self, code, valuep, 0);
 199 }
 200
 201 static const char*
 202 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 203 {
 204   --value;
 205   return ins_imms_scaled (self, value, code, 0);
 206 }
 207
 208 static const char*
 209 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
 210               ia64_insn *code)
 211 {
 212   if (value == (BFD_HOST_U_64_BIT) 0x100000000)
 213     value = 0;
 214   else
 215     value = (((BFD_HOST_64_BIT)value << 32) >> 32);
 216
 217   --value;
 218   return ins_imms_scaled (self, value, code, 0);
 219 }
 220
 221 static const char*
 222 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 223 {
 224   const char *res = ext_imms_scaled (self, code, valuep, 0);
 225
 226   ++*valuep;
 227   return res;
 228 }
 229
 230 static const char*
 231 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 232 {
 233   return ins_imms_scaled (self, value, code, 1);
 234 }
 235
 236 static const char*
 237 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 238 {
 239   return ext_imms_scaled (self, code, valuep, 1);
 240 }
 241
 242 static const char*
 243 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 244 {
 245   return ins_imms_scaled (self, value, code, 4);
 246 }
 247
 248 static const char*
 249 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 250 {
 251   return ext_imms_scaled (self, code, valuep, 4);
 252 }
 253
 254 static const char*
 255 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 256 {
 257   return ins_imms_scaled (self, value, code, 16);
 258 }
 259
 260 static const char*
 261 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 262 {
 263   return ext_imms_scaled (self, code, valuep, 16);
 264 }
 265
 266 static const char*
 267 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 268 {
 269   ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 270   return ins_immu (self, value ^ mask, code);
 271 }
 272
 273 static const char*
 274 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 275 {
 276   const char *result;
 277   ia64_insn mask;
 278
 279   mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 280   result = ext_immu (self, code, valuep);
 281   if (!result)
 282     {
 283       mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
 284       *valuep ^= mask;
 285     }
 286   return result;
 287 }
 288
 289 static const char*
 290 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 291 {
 292   --value;
 293   if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
 294     return "count out of range";
 295
 296   *code |= value << self->field[0].shift;
 297   return 0;
 298 }
 299
 300 static const char*
 301 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 302 {
 303   *valuep = ((code >> self->field[0].shift)
 304              & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
 305   return 0;
 306 }
 307
 308 static const char*
 309 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 310 {
 311   --value;
 312
 313   if (value > 2)
 314     return "count must be in range 1..3";
 315
 316   *code |= value << self->field[0].shift;
 317   return 0;
 318 }
 319
 320 static const char*
 321 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 322 {
 323   *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
 324   return 0;
 325 }
 326
 327 static const char*
 328 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 329 {
 330   switch (value)
 331     {
 332     case 0:     value = 0; break;
 333     case 7:     value = 1; break;
 334     case 15:    value = 2; break;
 335     case 16:    value = 3; break;
 336     default:    return "count must be 0, 7, 15, or 16";
 337     }
 338   *code |= value << self->field[0].shift;
 339   return 0;
 340 }
 341
 342 static const char*
 343 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 344 {
 345   ia64_insn value;
 346
 347   value = (code >> self->field[0].shift) & 0x3;
 348   switch (value)
 349     {
 350     case 0: value =  0; break;
 351     case 1: value =  7; break;
 352     case 2: value = 15; break;
 353     case 3: value = 16; break;
 354     }
 355   *valuep = value;
 356   return 0;
 357 }
 358
 359 static const char*
 360 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 361 {
 362   BFD_HOST_64_BIT val = value;
 363   BFD_HOST_U_64_BIT sign = 0;
 364
 365   if (val < 0)
 366     {
 367       sign = 0x4;
 368       value = -value;
 369     }
 370   switch (value)
 371     {
 372     case  1:    value = 3; break;
 373     case  4:    value = 2; break;
 374     case  8:    value = 1; break;
 375     case 16:    value = 0; break;
 376     default:    return "count must be +/- 1, 4, 8, or 16";
 377     }
 378   *code |= (sign | value) << self->field[0].shift;
 379   return 0;
 380 }
 381
 382 static const char*
 383 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 384 {
 385   BFD_HOST_64_BIT val;
 386   int negate;
 387
 388   val = (code >> self->field[0].shift) & 0x7;
 389   negate = val & 0x4;
 390   switch (val & 0x3)
 391     {
 392     case 0: val = 16; break;
 393     case 1: val =  8; break;
 394     case 2: val =  4; break;
 395     case 3: val =  1; break;
 396     }
 397   if (negate)
 398     val = -val;
 399
 400   *valuep = val;
 401   return 0;
 402 }
 403
 404 #define CST     IA64_OPND_CLASS_CST
 405 #define REG     IA64_OPND_CLASS_REG
 406 #define IND     IA64_OPND_CLASS_IND
 407 #define ABS     IA64_OPND_CLASS_ABS
 408 #define REL     IA64_OPND_CLASS_REL
 409
 410 #define SDEC    IA64_OPND_FLAG_DECIMAL_SIGNED
 411 #define UDEC    IA64_OPND_FLAG_DECIMAL_UNSIGNED
 412
 413 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
 414   {
 415     /* constants: */
 416     { CST, ins_const, ext_const, "NIL",         {{ 0, }}, 0, "<none>" },
 417     { CST, ins_const, ext_const, "ar.ccv",      {{ 0, }}, 0, "ar.ccv" },
 418     { CST, ins_const, ext_const, "ar.pfs",      {{ 0, }}, 0, "ar.pfs" },
 419     { CST, ins_const, ext_const, "1",           {{ 0, }}, 0, "1" },
 420     { CST, ins_const, ext_const, "8",           {{ 0, }}, 0, "1" },
 421     { CST, ins_const, ext_const, "16",          {{ 0, }}, 0, "16" },
 422     { CST, ins_const, ext_const, "r0",          {{ 0, }}, 0, "r0" },
 423     { CST, ins_const, ext_const, "ip",          {{ 0, }}, 0, "ip" },
 424     { CST, ins_const, ext_const, "pr",          {{ 0, }}, 0, "pr" },
 425     { CST, ins_const, ext_const, "pr.rot",      {{ 0, }}, 0, "pr.rot" },
 426     { CST, ins_const, ext_const, "psr",         {{ 0, }}, 0, "psr" },
 427     { CST, ins_const, ext_const, "psr.l",       {{ 0, }}, 0, "psr.l" },
 428     { CST, ins_const, ext_const, "psr.um",      {{ 0, }}, 0, "psr.um" },
 429
 430     /* register operands: */
 431     { REG, ins_reg,   ext_reg,  "ar", {{ 7, 20}}, 0,            /* AR3 */
 432       "an application register" },
 433     { REG, ins_reg,   ext_reg,   "b", {{ 3,  6}}, 0,            /* B1 */
 434       "a branch register" },
 435     { REG, ins_reg,   ext_reg,   "b", {{ 3, 13}}, 0,            /* B2 */
 436       "a branch register"},
 437     { REG, ins_reg,   ext_reg,  "cr", {{ 7, 20}}, 0,            /* CR */
 438       "a control register"},
 439     { REG, ins_reg,   ext_reg,   "f", {{ 7,  6}}, 0,            /* F1 */
 440       "a floating-point register" },
 441     { REG, ins_reg,   ext_reg,   "f", {{ 7, 13}}, 0,            /* F2 */
 442       "a floating-point register" },
 443     { REG, ins_reg,   ext_reg,   "f", {{ 7, 20}}, 0,            /* F3 */
 444       "a floating-point register" },
 445     { REG, ins_reg,   ext_reg,   "f", {{ 7, 27}}, 0,            /* F4 */
 446       "a floating-point register" },
 447     { REG, ins_reg,   ext_reg,   "p", {{ 6,  6}}, 0,            /* P1 */
 448       "a predicate register" },
 449     { REG, ins_reg,   ext_reg,   "p", {{ 6, 27}}, 0,            /* P2 */
 450       "a predicate register" },
 451     { REG, ins_reg,   ext_reg,   "r", {{ 7,  6}}, 0,            /* R1 */
 452       "a general register" },
 453     { REG, ins_reg,   ext_reg,   "r", {{ 7, 13}}, 0,            /* R2 */
 454       "a general register" },
 455     { REG, ins_reg,   ext_reg,   "r", {{ 7, 20}}, 0,            /* R3 */
 456       "a general register" },
 457     { REG, ins_reg,   ext_reg,   "r", {{ 2, 20}}, 0,            /* R3_2 */
 458       "a general register r0-r3" },
 459
 460     /* indirect operands: */
 461     { IND, ins_reg,   ext_reg,  "cpuid", {{7, 20}}, 0,          /* CPUID_R3 */
 462       "a cpuid register" },
 463     { IND, ins_reg,   ext_reg,  "dbr",   {{7, 20}}, 0,          /* DBR_R3 */
 464       "a dbr register" },
 465     { IND, ins_reg,   ext_reg,  "dtr",   {{7, 20}}, 0,          /* DTR_R3 */
 466       "a dtr register" },
 467     { IND, ins_reg,   ext_reg,  "itr",   {{7, 20}}, 0,          /* ITR_R3 */
 468       "an itr register" },
 469     { IND, ins_reg,   ext_reg,  "ibr",   {{7, 20}}, 0,          /* IBR_R3 */
 470       "an ibr register" },
 471     { IND, ins_reg,   ext_reg,  "",      {{7, 20}}, 0,          /* MR3 */
 472       "an indirect memory address" },
 473     { IND, ins_reg,   ext_reg,  "msr",   {{7, 20}}, 0,          /* MSR_R3 */
 474       "an msr register" },
 475     { IND, ins_reg,   ext_reg,  "pkr",   {{7, 20}}, 0,          /* PKR_R3 */
 476       "a pkr register" },
 477     { IND, ins_reg,   ext_reg,  "pmc",   {{7, 20}}, 0,          /* PMC_R3 */
 478       "a pmc register" },
 479     { IND, ins_reg,   ext_reg,  "pmd",   {{7, 20}}, 0,          /* PMD_R3 */
 480       "a pmd register" },
 481     { IND, ins_reg,   ext_reg,  "rr",    {{7, 20}}, 0,          /* RR_R3 */
 482       "an rr register" },
 483
 484     /* immediate operands: */
 485     { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,          /* CCNT5 */
 486       "a 5-bit count (0-31)" },
 487     { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,          /* CNT2a */
 488       "a 2-bit count (1-4)" },
 489     { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,          /* CNT2b */
 490       "a 2-bit count (1-3)" },
 491     { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,          /* CNT2c */
 492       "a count (0, 7, 15, or 16)" },
 493     { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,           /* CNT5 */
 494       "a 5-bit count (0-31)" },
 495     { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,           /* CNT6 */
 496       "a 6-bit count (0-63)" },
 497     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,           /* CPOS6a */
 498       "a 6-bit bit pos (0-63)" },
 499     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,           /* CPOS6b */
 500       "a 6-bit bit pos (0-63)" },
 501     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,           /* CPOS6c */
 502       "a 6-bit bit pos (0-63)" },
 503     { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,           /* IMM1 */
 504       "a 1-bit integer (-1, 0)" },
 505     { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,           /* IMMU2 */
 506       "a 2-bit unsigned (0-3)" },
 507     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,              /* IMMU7a */
 508       "a 7-bit unsigned (0-127)" },
 509     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,              /* IMMU7b */
 510       "a 7-bit unsigned (0-127)" },
 511     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,           /* SOF */
 512       "a frame size (register count)" },
 513     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,           /* SOL */
 514       "a local register count" },
 515     { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,           /* SOR */
 516       "a rotating register count (integer multiple of 8)" },
 517     { ABS, ins_imms,  ext_imms,  0,                             /* IMM8 */
 518       {{ 7, 13}, { 1, 36}}, SDEC,
 519       "an 8-bit integer (-128-127)" },
 520     { ABS, ins_immsu4,  ext_imms,  0,                           /* IMM8U4 */
 521       {{ 7, 13}, { 1, 36}}, SDEC,
 522       "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
 523     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1 */
 524       {{ 7, 13}, { 1, 36}}, SDEC,
 525       "an 8-bit integer (-127-128)" },
 526     { ABS, ins_immsm1u4,  ext_immsm1,  0,                       /* IMM8M1U4 */
 527       {{ 7, 13}, { 1, 36}}, SDEC,
 528       "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
 529     { ABS, ins_immsm1,  ext_immsm1,  0,                         /* IMM8M1U8 */
 530       {{ 7, 13}, { 1, 36}}, SDEC,
 531       "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
 532     { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,    /* IMMU9 */
 533       "a 9-bit unsigned (0-511)" },
 534     { ABS, ins_imms,  ext_imms,  0,                             /* IMM9a */
 535       {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
 536       "a 9-bit integer (-256-255)" },
 537     { ABS, ins_imms,  ext_imms, 0,                              /* IMM9b */
 538       {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
 539       "a 9-bit integer (-256-255)" },
 540     { ABS, ins_imms,  ext_imms, 0,                              /* IMM14 */
 541       {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
 542       "a 14-bit integer (-8192-8191)" },
 543     { ABS, ins_imms1, ext_imms1, 0,                             /* IMM17 */
 544       {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
 545       "a 17-bit integer (-65536-65535)" },
 546     { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,    /* IMMU21 */
 547       "a 21-bit unsigned" },
 548     { ABS, ins_imms,  ext_imms,  0,                             /* IMM22 */
 549       {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
 550       "a 22-bit integer" },
 551     { ABS, ins_immu,  ext_immu,  0,                             /* IMMU24 */
 552       {{21,  6}, { 2, 31}, { 1, 36}}, 0,
 553       "a 24-bit unsigned" },
 554     { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,    /* IMM44 */
 555       "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
 556     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU62 */
 557       "a 62-bit unsigned" },
 558     { ABS, ins_rsvd,  ext_rsvd, 0, {{0,  0}}, 0,                /* IMMU64 */
 559       "a 64-bit unsigned" },
 560     { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,           /* INC3 */
 561       "an increment (+/- 1, 4, 8, or 16)" },
 562     { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,           /* LEN4 */
 563       "a 4-bit length (1-16)" },
 564     { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,           /* LEN6 */
 565       "a 6-bit length (1-64)" },
 566     { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}}, 0,              /* MBTYPE4 */
 567       "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
 568     { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}}, 0,              /* MBTYPE8 */
 569       "an 8-bit mix type" },
 570     { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,           /* POS6 */
 571       "a 6-bit bit pos (0-63)" },
 572     { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,    /* TAG13 */
 573       "a branch tag" },
 574     { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,              /* TAG13b */
 575       "a branch tag" },
 576     { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,    /* TGT25 */
 577       "a branch target" },
 578     { REL, ins_imms4, ext_imms4, 0,                             /* TGT25b */
 579       {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
 580       "a branch target" },
 581     { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,    /* TGT25c */
 582       "a branch target" },
 583     { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
 584       "a branch target" },
 585   };