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Fixes the generation of dwarf line debug information for the msp430, even in the...
[deliverable/binutils-gdb.git] / bfd / elf32-msp430.c
1 /* MSP430-specific support for 32-bit ELF
2 Copyright (C) 2002-2015 Free Software Foundation, Inc.
3 Contributed by Dmitry Diky <diwil@mail.ru>
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include "bfd.h"
24 #include "libiberty.h"
25 #include "libbfd.h"
26 #include "elf-bfd.h"
27 #include "elf/msp430.h"
28
29 static reloc_howto_type elf_msp430_howto_table[] =
30 {
31 HOWTO (R_MSP430_NONE, /* type */
32 0, /* rightshift */
33 3, /* size (0 = byte, 1 = short, 2 = long) */
34 0, /* bitsize */
35 FALSE, /* pc_relative */
36 0, /* bitpos */
37 complain_overflow_dont,/* complain_on_overflow */
38 bfd_elf_generic_reloc, /* special_function */
39 "R_MSP430_NONE", /* name */
40 FALSE, /* partial_inplace */
41 0, /* src_mask */
42 0, /* dst_mask */
43 FALSE), /* pcrel_offset */
44
45 HOWTO (R_MSP430_32, /* type */
46 0, /* rightshift */
47 2, /* size (0 = byte, 1 = short, 2 = long) */
48 32, /* bitsize */
49 FALSE, /* pc_relative */
50 0, /* bitpos */
51 complain_overflow_bitfield,/* complain_on_overflow */
52 bfd_elf_generic_reloc, /* special_function */
53 "R_MSP430_32", /* name */
54 FALSE, /* partial_inplace */
55 0xffffffff, /* src_mask */
56 0xffffffff, /* dst_mask */
57 FALSE), /* pcrel_offset */
58
59 /* A 10 bit PC relative relocation. */
60 HOWTO (R_MSP430_10_PCREL, /* type */
61 1, /* rightshift */
62 1, /* size (0 = byte, 1 = short, 2 = long) */
63 10, /* bitsize */
64 TRUE, /* pc_relative */
65 0, /* bitpos */
66 complain_overflow_bitfield,/* complain_on_overflow */
67 bfd_elf_generic_reloc, /* special_function */
68 "R_MSP430_10_PCREL", /* name */
69 FALSE, /* partial_inplace */
70 0x3ff, /* src_mask */
71 0x3ff, /* dst_mask */
72 TRUE), /* pcrel_offset */
73
74 /* A 16 bit absolute relocation. */
75 HOWTO (R_MSP430_16, /* type */
76 0, /* rightshift */
77 1, /* size (0 = byte, 1 = short, 2 = long) */
78 16, /* bitsize */
79 FALSE, /* pc_relative */
80 0, /* bitpos */
81 complain_overflow_dont,/* complain_on_overflow */
82 bfd_elf_generic_reloc, /* special_function */
83 "R_MSP430_16", /* name */
84 FALSE, /* partial_inplace */
85 0, /* src_mask */
86 0xffff, /* dst_mask */
87 FALSE), /* pcrel_offset */
88
89 /* A 16 bit PC relative relocation for command address. */
90 HOWTO (R_MSP430_16_PCREL, /* type */
91 1, /* rightshift */
92 1, /* size (0 = byte, 1 = short, 2 = long) */
93 16, /* bitsize */
94 TRUE, /* pc_relative */
95 0, /* bitpos */
96 complain_overflow_dont,/* complain_on_overflow */
97 bfd_elf_generic_reloc, /* special_function */
98 "R_MSP430_16_PCREL", /* name */
99 FALSE, /* partial_inplace */
100 0, /* src_mask */
101 0xffff, /* dst_mask */
102 TRUE), /* pcrel_offset */
103
104 /* A 16 bit absolute relocation, byte operations. */
105 HOWTO (R_MSP430_16_BYTE, /* type */
106 0, /* rightshift */
107 1, /* size (0 = byte, 1 = short, 2 = long) */
108 16, /* bitsize */
109 FALSE, /* pc_relative */
110 0, /* bitpos */
111 complain_overflow_dont,/* complain_on_overflow */
112 bfd_elf_generic_reloc, /* special_function */
113 "R_MSP430_16_BYTE", /* name */
114 FALSE, /* partial_inplace */
115 0xffff, /* src_mask */
116 0xffff, /* dst_mask */
117 FALSE), /* pcrel_offset */
118
119 /* A 16 bit absolute relocation for command address. */
120 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */
121 1, /* rightshift */
122 1, /* size (0 = byte, 1 = short, 2 = long) */
123 16, /* bitsize */
124 TRUE, /* pc_relative */
125 0, /* bitpos */
126 complain_overflow_dont,/* complain_on_overflow */
127 bfd_elf_generic_reloc, /* special_function */
128 "R_MSP430_16_PCREL_BYTE",/* name */
129 FALSE, /* partial_inplace */
130 0xffff, /* src_mask */
131 0xffff, /* dst_mask */
132 TRUE), /* pcrel_offset */
133
134 /* A 10 bit PC relative relocation for complicated polymorphs. */
135 HOWTO (R_MSP430_2X_PCREL, /* type */
136 1, /* rightshift */
137 2, /* size (0 = byte, 1 = short, 2 = long) */
138 10, /* bitsize */
139 TRUE, /* pc_relative */
140 0, /* bitpos */
141 complain_overflow_bitfield,/* complain_on_overflow */
142 bfd_elf_generic_reloc, /* special_function */
143 "R_MSP430_2X_PCREL", /* name */
144 FALSE, /* partial_inplace */
145 0x3ff, /* src_mask */
146 0x3ff, /* dst_mask */
147 TRUE), /* pcrel_offset */
148
149 /* A 16 bit relaxable relocation for command address. */
150 HOWTO (R_MSP430_RL_PCREL, /* type */
151 1, /* rightshift */
152 1, /* size (0 = byte, 1 = short, 2 = long) */
153 16, /* bitsize */
154 TRUE, /* pc_relative */
155 0, /* bitpos */
156 complain_overflow_dont,/* complain_on_overflow */
157 bfd_elf_generic_reloc, /* special_function */
158 "R_MSP430_RL_PCREL", /* name */
159 FALSE, /* partial_inplace */
160 0, /* src_mask */
161 0xffff, /* dst_mask */
162 TRUE) /* pcrel_offset */
163
164 /* A 8-bit absolute relocation. */
165 , HOWTO (R_MSP430_8, /* type */
166 0, /* rightshift */
167 0, /* size (0 = byte, 1 = short, 2 = long) */
168 8, /* bitsize */
169 FALSE, /* pc_relative */
170 0, /* bitpos */
171 complain_overflow_dont,/* complain_on_overflow */
172 bfd_elf_generic_reloc, /* special_function */
173 "R_MSP430_8", /* name */
174 FALSE, /* partial_inplace */
175 0, /* src_mask */
176 0xffff, /* dst_mask */
177 FALSE), /* pcrel_offset */
178
179 /* Together with a following reloc, allows for the difference
180 between two symbols to be the real addend of the second reloc. */
181 HOWTO (R_MSP430_SYM_DIFF, /* type */
182 0, /* rightshift */
183 2, /* size (0 = byte, 1 = short, 2 = long) */
184 32, /* bitsize */
185 FALSE, /* pc_relative */
186 0, /* bitpos */
187 complain_overflow_dont,/* complain_on_overflow */
188 NULL, /* special handler. */
189 "R_MSP430_SYM_DIFF", /* name */
190 FALSE, /* partial_inplace */
191 0xffffffff, /* src_mask */
192 0xffffffff, /* dst_mask */
193 FALSE) /* pcrel_offset */
194 };
195
196 static reloc_howto_type elf_msp430x_howto_table[] =
197 {
198 HOWTO (R_MSP430_NONE, /* type */
199 0, /* rightshift */
200 3, /* size (0 = byte, 1 = short, 2 = long) */
201 0, /* bitsize */
202 FALSE, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_dont,/* complain_on_overflow */
205 bfd_elf_generic_reloc, /* special_function */
206 "R_MSP430_NONE", /* name */
207 FALSE, /* partial_inplace */
208 0, /* src_mask */
209 0, /* dst_mask */
210 FALSE), /* pcrel_offset */
211
212 HOWTO (R_MSP430_ABS32, /* type */
213 0, /* rightshift */
214 2, /* size (0 = byte, 1 = short, 2 = long) */
215 32, /* bitsize */
216 FALSE, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_bitfield,/* complain_on_overflow */
219 bfd_elf_generic_reloc, /* special_function */
220 "R_MSP430_ABS32", /* name */
221 FALSE, /* partial_inplace */
222 0xffffffff, /* src_mask */
223 0xffffffff, /* dst_mask */
224 FALSE), /* pcrel_offset */
225
226 HOWTO (R_MSP430_ABS16, /* type */
227 0, /* rightshift */
228 1, /* size (0 = byte, 1 = short, 2 = long) */
229 16, /* bitsize */
230 FALSE, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_dont,/* complain_on_overflow */
233 bfd_elf_generic_reloc, /* special_function */
234 "R_MSP430_ABS16", /* name */
235 FALSE, /* partial_inplace */
236 0, /* src_mask */
237 0xffff, /* dst_mask */
238 FALSE), /* pcrel_offset */
239
240 HOWTO (R_MSP430_ABS8, /* type */
241 0, /* rightshift */
242 0, /* size (0 = byte, 1 = short, 2 = long) */
243 8, /* bitsize */
244 FALSE, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_bitfield,/* complain_on_overflow */
247 bfd_elf_generic_reloc, /* special_function */
248 "R_MSP430_ABS8", /* name */
249 FALSE, /* partial_inplace */
250 0xff, /* src_mask */
251 0xff, /* dst_mask */
252 FALSE), /* pcrel_offset */
253
254 HOWTO (R_MSP430_PCR16, /* type */
255 1, /* rightshift */
256 1, /* size (0 = byte, 1 = short, 2 = long) */
257 16, /* bitsize */
258 TRUE, /* pc_relative */
259 0, /* bitpos */
260 complain_overflow_dont,/* complain_on_overflow */
261 bfd_elf_generic_reloc, /* special_function */
262 "R_MSP430_PCR16", /* name */
263 FALSE, /* partial_inplace */
264 0, /* src_mask */
265 0xffff, /* dst_mask */
266 TRUE), /* pcrel_offset */
267
268 HOWTO (R_MSP430X_PCR20_EXT_SRC,/* type */
269 0, /* rightshift */
270 2, /* size (0 = byte, 1 = short, 2 = long) */
271 32, /* bitsize */
272 TRUE, /* pc_relative */
273 0, /* bitpos */
274 complain_overflow_dont,/* complain_on_overflow */
275 bfd_elf_generic_reloc, /* special_function */
276 "R_MSP430X_PCR20_EXT_SRC",/* name */
277 FALSE, /* partial_inplace */
278 0, /* src_mask */
279 0xffff, /* dst_mask */
280 TRUE), /* pcrel_offset */
281
282 HOWTO (R_MSP430X_PCR20_EXT_DST,/* type */
283 0, /* rightshift */
284 2, /* size (0 = byte, 1 = short, 2 = long) */
285 32, /* bitsize */
286 TRUE, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_dont,/* complain_on_overflow */
289 bfd_elf_generic_reloc, /* special_function */
290 "R_MSP430X_PCR20_EXT_DST",/* name */
291 FALSE, /* partial_inplace */
292 0, /* src_mask */
293 0xffff, /* dst_mask */
294 TRUE), /* pcrel_offset */
295
296 HOWTO (R_MSP430X_PCR20_EXT_ODST,/* type */
297 0, /* rightshift */
298 2, /* size (0 = byte, 1 = short, 2 = long) */
299 32, /* bitsize */
300 TRUE, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_dont,/* complain_on_overflow */
303 bfd_elf_generic_reloc, /* special_function */
304 "R_MSP430X_PCR20_EXT_ODST",/* name */
305 FALSE, /* partial_inplace */
306 0, /* src_mask */
307 0xffff, /* dst_mask */
308 TRUE), /* pcrel_offset */
309
310 HOWTO (R_MSP430X_ABS20_EXT_SRC,/* type */
311 0, /* rightshift */
312 2, /* size (0 = byte, 1 = short, 2 = long) */
313 32, /* bitsize */
314 TRUE, /* pc_relative */
315 0, /* bitpos */
316 complain_overflow_dont,/* complain_on_overflow */
317 bfd_elf_generic_reloc, /* special_function */
318 "R_MSP430X_ABS20_EXT_SRC",/* name */
319 FALSE, /* partial_inplace */
320 0, /* src_mask */
321 0xffff, /* dst_mask */
322 TRUE), /* pcrel_offset */
323
324 HOWTO (R_MSP430X_ABS20_EXT_DST,/* type */
325 0, /* rightshift */
326 2, /* size (0 = byte, 1 = short, 2 = long) */
327 32, /* bitsize */
328 TRUE, /* pc_relative */
329 0, /* bitpos */
330 complain_overflow_dont,/* complain_on_overflow */
331 bfd_elf_generic_reloc, /* special_function */
332 "R_MSP430X_ABS20_EXT_DST",/* name */
333 FALSE, /* partial_inplace */
334 0, /* src_mask */
335 0xffff, /* dst_mask */
336 TRUE), /* pcrel_offset */
337
338 HOWTO (R_MSP430X_ABS20_EXT_ODST,/* type */
339 0, /* rightshift */
340 2, /* size (0 = byte, 1 = short, 2 = long) */
341 32, /* bitsize */
342 TRUE, /* pc_relative */
343 0, /* bitpos */
344 complain_overflow_dont,/* complain_on_overflow */
345 bfd_elf_generic_reloc, /* special_function */
346 "R_MSP430X_ABS20_EXT_ODST",/* name */
347 FALSE, /* partial_inplace */
348 0, /* src_mask */
349 0xffff, /* dst_mask */
350 TRUE), /* pcrel_offset */
351
352 HOWTO (R_MSP430X_ABS20_ADR_SRC,/* type */
353 0, /* rightshift */
354 2, /* size (0 = byte, 1 = short, 2 = long) */
355 32, /* bitsize */
356 TRUE, /* pc_relative */
357 0, /* bitpos */
358 complain_overflow_dont,/* complain_on_overflow */
359 bfd_elf_generic_reloc, /* special_function */
360 "R_MSP430X_ABS20_ADR_SRC",/* name */
361 FALSE, /* partial_inplace */
362 0, /* src_mask */
363 0xffff, /* dst_mask */
364 TRUE), /* pcrel_offset */
365
366 HOWTO (R_MSP430X_ABS20_ADR_DST,/* type */
367 0, /* rightshift */
368 2, /* size (0 = byte, 1 = short, 2 = long) */
369 32, /* bitsize */
370 TRUE, /* pc_relative */
371 0, /* bitpos */
372 complain_overflow_dont,/* complain_on_overflow */
373 bfd_elf_generic_reloc, /* special_function */
374 "R_MSP430X_ABS20_ADR_DST",/* name */
375 FALSE, /* partial_inplace */
376 0, /* src_mask */
377 0xffff, /* dst_mask */
378 TRUE), /* pcrel_offset */
379
380 HOWTO (R_MSP430X_PCR16, /* type */
381 0, /* rightshift */
382 2, /* size (0 = byte, 1 = short, 2 = long) */
383 32, /* bitsize */
384 TRUE, /* pc_relative */
385 0, /* bitpos */
386 complain_overflow_dont,/* complain_on_overflow */
387 bfd_elf_generic_reloc, /* special_function */
388 "R_MSP430X_PCR16", /* name */
389 FALSE, /* partial_inplace */
390 0, /* src_mask */
391 0xffff, /* dst_mask */
392 TRUE), /* pcrel_offset */
393
394 HOWTO (R_MSP430X_PCR20_CALL, /* type */
395 0, /* rightshift */
396 2, /* size (0 = byte, 1 = short, 2 = long) */
397 32, /* bitsize */
398 TRUE, /* pc_relative */
399 0, /* bitpos */
400 complain_overflow_dont,/* complain_on_overflow */
401 bfd_elf_generic_reloc, /* special_function */
402 "R_MSP430X_PCR20_CALL",/* name */
403 FALSE, /* partial_inplace */
404 0, /* src_mask */
405 0xffff, /* dst_mask */
406 TRUE), /* pcrel_offset */
407
408 HOWTO (R_MSP430X_ABS16, /* type */
409 0, /* rightshift */
410 2, /* size (0 = byte, 1 = short, 2 = long) */
411 32, /* bitsize */
412 TRUE, /* pc_relative */
413 0, /* bitpos */
414 complain_overflow_dont,/* complain_on_overflow */
415 bfd_elf_generic_reloc, /* special_function */
416 "R_MSP430X_ABS16", /* name */
417 FALSE, /* partial_inplace */
418 0, /* src_mask */
419 0xffff, /* dst_mask */
420 TRUE), /* pcrel_offset */
421
422 HOWTO (R_MSP430_ABS_HI16, /* type */
423 0, /* rightshift */
424 2, /* size (0 = byte, 1 = short, 2 = long) */
425 32, /* bitsize */
426 TRUE, /* pc_relative */
427 0, /* bitpos */
428 complain_overflow_dont,/* complain_on_overflow */
429 bfd_elf_generic_reloc, /* special_function */
430 "R_MSP430_ABS_HI16", /* name */
431 FALSE, /* partial_inplace */
432 0, /* src_mask */
433 0xffff, /* dst_mask */
434 TRUE), /* pcrel_offset */
435
436 HOWTO (R_MSP430_PREL31, /* type */
437 0, /* rightshift */
438 2, /* size (0 = byte, 1 = short, 2 = long) */
439 32, /* bitsize */
440 TRUE, /* pc_relative */
441 0, /* bitpos */
442 complain_overflow_dont,/* complain_on_overflow */
443 bfd_elf_generic_reloc, /* special_function */
444 "R_MSP430_PREL31", /* name */
445 FALSE, /* partial_inplace */
446 0, /* src_mask */
447 0xffff, /* dst_mask */
448 TRUE), /* pcrel_offset */
449
450 EMPTY_HOWTO (R_MSP430_EHTYPE),
451
452 /* A 10 bit PC relative relocation. */
453 HOWTO (R_MSP430X_10_PCREL, /* type */
454 1, /* rightshift */
455 1, /* size (0 = byte, 1 = short, 2 = long) */
456 10, /* bitsize */
457 TRUE, /* pc_relative */
458 0, /* bitpos */
459 complain_overflow_bitfield,/* complain_on_overflow */
460 bfd_elf_generic_reloc, /* special_function */
461 "R_MSP430X_10_PCREL", /* name */
462 FALSE, /* partial_inplace */
463 0x3ff, /* src_mask */
464 0x3ff, /* dst_mask */
465 TRUE), /* pcrel_offset */
466
467 /* A 10 bit PC relative relocation for complicated polymorphs. */
468 HOWTO (R_MSP430X_2X_PCREL, /* type */
469 1, /* rightshift */
470 2, /* size (0 = byte, 1 = short, 2 = long) */
471 10, /* bitsize */
472 TRUE, /* pc_relative */
473 0, /* bitpos */
474 complain_overflow_bitfield,/* complain_on_overflow */
475 bfd_elf_generic_reloc, /* special_function */
476 "R_MSP430X_2X_PCREL", /* name */
477 FALSE, /* partial_inplace */
478 0x3ff, /* src_mask */
479 0x3ff, /* dst_mask */
480 TRUE), /* pcrel_offset */
481
482 /* Together with a following reloc, allows for the difference
483 between two symbols to be the real addend of the second reloc. */
484 HOWTO (R_MSP430X_SYM_DIFF, /* type */
485 0, /* rightshift */
486 2, /* size (0 = byte, 1 = short, 2 = long) */
487 32, /* bitsize */
488 FALSE, /* pc_relative */
489 0, /* bitpos */
490 complain_overflow_dont,/* complain_on_overflow */
491 NULL, /* special handler. */
492 "R_MSP430X_SYM_DIFF", /* name */
493 FALSE, /* partial_inplace */
494 0xffffffff, /* src_mask */
495 0xffffffff, /* dst_mask */
496 FALSE) /* pcrel_offset */
497 };
498
499 /* Map BFD reloc types to MSP430 ELF reloc types. */
500
501 struct msp430_reloc_map
502 {
503 bfd_reloc_code_real_type bfd_reloc_val;
504 unsigned int elf_reloc_val;
505 };
506
507 static const struct msp430_reloc_map msp430_reloc_map[] =
508 {
509 {BFD_RELOC_NONE, R_MSP430_NONE},
510 {BFD_RELOC_32, R_MSP430_32},
511 {BFD_RELOC_MSP430_10_PCREL, R_MSP430_10_PCREL},
512 {BFD_RELOC_16, R_MSP430_16_BYTE},
513 {BFD_RELOC_MSP430_16_PCREL, R_MSP430_16_PCREL},
514 {BFD_RELOC_MSP430_16, R_MSP430_16},
515 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE},
516 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE},
517 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL},
518 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL},
519 {BFD_RELOC_8, R_MSP430_8},
520 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430_SYM_DIFF}
521 };
522
523 static const struct msp430_reloc_map msp430x_reloc_map[] =
524 {
525 {BFD_RELOC_NONE, R_MSP430_NONE},
526 {BFD_RELOC_32, R_MSP430_ABS32},
527 {BFD_RELOC_16, R_MSP430_ABS16},
528 {BFD_RELOC_8, R_MSP430_ABS8},
529 {BFD_RELOC_MSP430_ABS8, R_MSP430_ABS8},
530 {BFD_RELOC_MSP430X_PCR20_EXT_SRC, R_MSP430X_PCR20_EXT_SRC},
531 {BFD_RELOC_MSP430X_PCR20_EXT_DST, R_MSP430X_PCR20_EXT_DST},
532 {BFD_RELOC_MSP430X_PCR20_EXT_ODST, R_MSP430X_PCR20_EXT_ODST},
533 {BFD_RELOC_MSP430X_ABS20_EXT_SRC, R_MSP430X_ABS20_EXT_SRC},
534 {BFD_RELOC_MSP430X_ABS20_EXT_DST, R_MSP430X_ABS20_EXT_DST},
535 {BFD_RELOC_MSP430X_ABS20_EXT_ODST, R_MSP430X_ABS20_EXT_ODST},
536 {BFD_RELOC_MSP430X_ABS20_ADR_SRC, R_MSP430X_ABS20_ADR_SRC},
537 {BFD_RELOC_MSP430X_ABS20_ADR_DST, R_MSP430X_ABS20_ADR_DST},
538 {BFD_RELOC_MSP430X_PCR16, R_MSP430X_PCR16},
539 {BFD_RELOC_MSP430X_PCR20_CALL, R_MSP430X_PCR20_CALL},
540 {BFD_RELOC_MSP430X_ABS16, R_MSP430X_ABS16},
541 {BFD_RELOC_MSP430_ABS_HI16, R_MSP430_ABS_HI16},
542 {BFD_RELOC_MSP430_PREL31, R_MSP430_PREL31},
543 {BFD_RELOC_MSP430_10_PCREL, R_MSP430X_10_PCREL},
544 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430X_2X_PCREL},
545 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430X_PCR16},
546 {BFD_RELOC_MSP430_SYM_DIFF, R_MSP430X_SYM_DIFF}
547 };
548
549 static inline bfd_boolean
550 uses_msp430x_relocs (bfd * abfd)
551 {
552 extern const bfd_target msp430_elf32_ti_vec;
553
554 return bfd_get_mach (abfd) == bfd_mach_msp430x
555 || abfd->xvec == & msp430_elf32_ti_vec;
556 }
557
558 static reloc_howto_type *
559 bfd_elf32_bfd_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
560 bfd_reloc_code_real_type code)
561 {
562 unsigned int i;
563
564 if (uses_msp430x_relocs (abfd))
565 {
566 for (i = ARRAY_SIZE (msp430x_reloc_map); i--;)
567 if (msp430x_reloc_map[i].bfd_reloc_val == code)
568 return elf_msp430x_howto_table + msp430x_reloc_map[i].elf_reloc_val;
569 }
570 else
571 {
572 for (i = 0; i < ARRAY_SIZE (msp430_reloc_map); i++)
573 if (msp430_reloc_map[i].bfd_reloc_val == code)
574 return &elf_msp430_howto_table[msp430_reloc_map[i].elf_reloc_val];
575 }
576
577 return NULL;
578 }
579
580 static reloc_howto_type *
581 bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
582 const char *r_name)
583 {
584 unsigned int i;
585
586 if (uses_msp430x_relocs (abfd))
587 {
588 for (i = ARRAY_SIZE (elf_msp430x_howto_table); i--;)
589 if (elf_msp430x_howto_table[i].name != NULL
590 && strcasecmp (elf_msp430x_howto_table[i].name, r_name) == 0)
591 return elf_msp430x_howto_table + i;
592 }
593 else
594 {
595 for (i = 0;
596 i < (sizeof (elf_msp430_howto_table)
597 / sizeof (elf_msp430_howto_table[0]));
598 i++)
599 if (elf_msp430_howto_table[i].name != NULL
600 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0)
601 return &elf_msp430_howto_table[i];
602 }
603
604 return NULL;
605 }
606
607 /* Set the howto pointer for an MSP430 ELF reloc. */
608
609 static void
610 msp430_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
611 arelent * cache_ptr,
612 Elf_Internal_Rela * dst)
613 {
614 unsigned int r_type;
615
616 r_type = ELF32_R_TYPE (dst->r_info);
617
618 if (uses_msp430x_relocs (abfd))
619 {
620 if (r_type >= (unsigned int) R_MSP430x_max)
621 {
622 _bfd_error_handler (_("%B: invalid MSP430X reloc number: %d"), abfd, r_type);
623 r_type = 0;
624 }
625 cache_ptr->howto = elf_msp430x_howto_table + r_type;
626 return;
627 }
628
629 if (r_type >= (unsigned int) R_MSP430_max)
630 {
631 _bfd_error_handler (_("%B: invalid MSP430 reloc number: %d"), abfd, r_type);
632 r_type = 0;
633 }
634 cache_ptr->howto = &elf_msp430_howto_table[r_type];
635 }
636
637 /* Look through the relocs for a section during the first phase.
638 Since we don't do .gots or .plts, we just need to consider the
639 virtual table relocs for gc. */
640
641 static bfd_boolean
642 elf32_msp430_check_relocs (bfd * abfd, struct bfd_link_info * info,
643 asection * sec, const Elf_Internal_Rela * relocs)
644 {
645 Elf_Internal_Shdr *symtab_hdr;
646 struct elf_link_hash_entry **sym_hashes;
647 const Elf_Internal_Rela *rel;
648 const Elf_Internal_Rela *rel_end;
649
650 if (info->relocatable)
651 return TRUE;
652
653 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
654 sym_hashes = elf_sym_hashes (abfd);
655
656 rel_end = relocs + sec->reloc_count;
657 for (rel = relocs; rel < rel_end; rel++)
658 {
659 struct elf_link_hash_entry *h;
660 unsigned long r_symndx;
661
662 r_symndx = ELF32_R_SYM (rel->r_info);
663 if (r_symndx < symtab_hdr->sh_info)
664 h = NULL;
665 else
666 {
667 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
668 while (h->root.type == bfd_link_hash_indirect
669 || h->root.type == bfd_link_hash_warning)
670 h = (struct elf_link_hash_entry *) h->root.u.i.link;
671
672 /* PR15323, ref flags aren't set for references in the same
673 object. */
674 h->root.non_ir_ref = 1;
675 }
676 }
677
678 return TRUE;
679 }
680
681 /* Perform a single relocation. By default we use the standard BFD
682 routines, but a few relocs, we have to do them ourselves. */
683
684 static bfd_reloc_status_type
685 msp430_final_link_relocate (reloc_howto_type * howto,
686 bfd * input_bfd,
687 asection * input_section,
688 bfd_byte * contents,
689 Elf_Internal_Rela * rel,
690 bfd_vma relocation,
691 struct bfd_link_info * info)
692 {
693 static asection * sym_diff_section;
694 static bfd_vma sym_diff_value;
695
696 struct bfd_elf_section_data * esd = elf_section_data (input_section);
697 bfd_reloc_status_type r = bfd_reloc_ok;
698 bfd_vma x;
699 bfd_signed_vma srel;
700 bfd_boolean is_rel_reloc = FALSE;
701
702 if (uses_msp430x_relocs (input_bfd))
703 {
704 /* See if we have a REL type relocation. */
705 is_rel_reloc = (esd->rel.hdr != NULL);
706 /* Sanity check - only one type of relocation per section.
707 FIXME: Theoretically it is possible to have both types,
708 but if that happens how can we distinguish between the two ? */
709 BFD_ASSERT (! is_rel_reloc || ! esd->rela.hdr);
710 /* If we are using a REL relocation then the addend should be empty. */
711 BFD_ASSERT (! is_rel_reloc || rel->r_addend == 0);
712 }
713
714 if (sym_diff_section != NULL)
715 {
716 BFD_ASSERT (sym_diff_section == input_section);
717
718 if (uses_msp430x_relocs (input_bfd))
719 switch (howto->type)
720 {
721 case R_MSP430_ABS32:
722 /* If we are computing a 32-bit value for the location lists
723 and the result is 0 then we add one to the value. A zero
724 value can result because of linker relaxation deleteing
725 prologue instructions and using a value of 1 (for the begin
726 and end offsets in the location list entry) results in a
727 nul entry which does not prevent the following entries from
728 being parsed. */
729 if (relocation == sym_diff_value
730 && strcmp (input_section->name, ".debug_loc") == 0)
731 ++ relocation;
732 /* Fall through. */
733 case R_MSP430_ABS16:
734 case R_MSP430X_ABS16:
735 case R_MSP430_ABS8:
736 BFD_ASSERT (! is_rel_reloc);
737 relocation -= sym_diff_value;
738 break;
739
740 default:
741 return bfd_reloc_dangerous;
742 }
743 else
744 switch (howto->type)
745 {
746 case R_MSP430_32:
747 case R_MSP430_16:
748 case R_MSP430_16_BYTE:
749 case R_MSP430_8:
750 relocation -= sym_diff_value;
751 break;
752
753 default:
754 return bfd_reloc_dangerous;
755 }
756
757 sym_diff_section = NULL;
758 }
759
760 if (uses_msp430x_relocs (input_bfd))
761 switch (howto->type)
762 {
763 case R_MSP430X_SYM_DIFF:
764 /* Cache the input section and value.
765 The offset is unreliable, since relaxation may
766 have reduced the following reloc's offset. */
767 BFD_ASSERT (! is_rel_reloc);
768 sym_diff_section = input_section;
769 sym_diff_value = relocation;
770 return bfd_reloc_ok;
771
772 case R_MSP430_ABS16:
773 contents += rel->r_offset;
774 srel = (bfd_signed_vma) relocation;
775 if (is_rel_reloc)
776 srel += bfd_get_16 (input_bfd, contents);
777 else
778 srel += rel->r_addend;
779 bfd_put_16 (input_bfd, srel & 0xffff, contents);
780 break;
781
782 case R_MSP430X_10_PCREL:
783 contents += rel->r_offset;
784 srel = (bfd_signed_vma) relocation;
785 if (is_rel_reloc)
786 srel += bfd_get_16 (input_bfd, contents) & 0x3ff;
787 else
788 srel += rel->r_addend;
789 srel -= rel->r_offset;
790 srel -= 2; /* Branch instructions add 2 to the PC... */
791 srel -= (input_section->output_section->vma +
792 input_section->output_offset);
793 if (srel & 1)
794 return bfd_reloc_outofrange;
795
796 /* MSP430 addresses commands as words. */
797 srel >>= 1;
798
799 /* Check for an overflow. */
800 if (srel < -512 || srel > 511)
801 {
802 if (info->disable_target_specific_optimizations < 0)
803 {
804 static bfd_boolean warned = FALSE;
805 if (! warned)
806 {
807 info->callbacks->warning
808 (info,
809 _("Try enabling relaxation to avoid relocation truncations"),
810 NULL, input_bfd, input_section, relocation);
811 warned = TRUE;
812 }
813 }
814 return bfd_reloc_overflow;
815 }
816
817 x = bfd_get_16 (input_bfd, contents);
818 x = (x & 0xfc00) | (srel & 0x3ff);
819 bfd_put_16 (input_bfd, x, contents);
820 break;
821
822 case R_MSP430X_PCR20_EXT_ODST:
823 /* [0,4]+[48,16] = ---F ---- FFFF */
824 contents += rel->r_offset;
825 srel = (bfd_signed_vma) relocation;
826 if (is_rel_reloc)
827 {
828 bfd_vma addend;
829 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
830 addend |= bfd_get_16 (input_bfd, contents+4);
831 srel += addend;
832
833 }
834 else
835 srel += rel->r_addend;
836 srel -= rel->r_offset;
837 srel -= (input_section->output_section->vma +
838 input_section->output_offset);
839 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
840 x = bfd_get_16 (input_bfd, contents);
841 x = (x & 0xfff0) | ((srel >> 16) & 0xf);
842 bfd_put_16 (input_bfd, x, contents);
843 break;
844
845 case R_MSP430X_ABS20_EXT_SRC:
846 /* [7,4]+[32,16] = -78- FFFF */
847 contents += rel->r_offset;
848 srel = (bfd_signed_vma) relocation;
849 if (is_rel_reloc)
850 {
851 bfd_vma addend;
852 addend = (bfd_get_16 (input_bfd, contents) & 0x0780) << 9;
853 addend |= bfd_get_16 (input_bfd, contents+2);
854 srel += addend;
855 }
856 else
857 srel += rel->r_addend;
858 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
859 srel >>= 16;
860 x = bfd_get_16 (input_bfd, contents);
861 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
862 bfd_put_16 (input_bfd, x, contents);
863 break;
864
865 case R_MSP430_16_PCREL:
866 contents += rel->r_offset;
867 srel = (bfd_signed_vma) relocation;
868 if (is_rel_reloc)
869 srel += bfd_get_16 (input_bfd, contents);
870 else
871 srel += rel->r_addend;
872 srel -= rel->r_offset;
873 /* Only branch instructions add 2 to the PC... */
874 srel -= (input_section->output_section->vma +
875 input_section->output_offset);
876 if (srel & 1)
877 return bfd_reloc_outofrange;
878 bfd_put_16 (input_bfd, srel & 0xffff, contents);
879 break;
880
881 case R_MSP430X_PCR20_EXT_DST:
882 /* [0,4]+[32,16] = ---F FFFF */
883 contents += rel->r_offset;
884 srel = (bfd_signed_vma) relocation;
885 if (is_rel_reloc)
886 {
887 bfd_vma addend;
888 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
889 addend |= bfd_get_16 (input_bfd, contents+2);
890 srel += addend;
891 }
892 else
893 srel += rel->r_addend;
894 srel -= rel->r_offset;
895 srel -= (input_section->output_section->vma +
896 input_section->output_offset);
897 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
898 srel >>= 16;
899 x = bfd_get_16 (input_bfd, contents);
900 x = (x & 0xfff0) | (srel & 0xf);
901 bfd_put_16 (input_bfd, x, contents);
902 break;
903
904 case R_MSP430X_PCR20_EXT_SRC:
905 /* [7,4]+32,16] = -78- FFFF */
906 contents += rel->r_offset;
907 srel = (bfd_signed_vma) relocation;
908 if (is_rel_reloc)
909 {
910 bfd_vma addend;
911 addend = ((bfd_get_16 (input_bfd, contents) & 0x0780) << 9);
912 addend |= bfd_get_16 (input_bfd, contents+2);
913 srel += addend;;
914 }
915 else
916 srel += rel->r_addend;
917 srel -= rel->r_offset;
918 /* Only branch instructions add 2 to the PC... */
919 srel -= (input_section->output_section->vma +
920 input_section->output_offset);
921 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
922 srel >>= 16;
923 x = bfd_get_16 (input_bfd, contents);
924 x = (x & 0xf87f) | ((srel << 7) & 0x0780);
925 bfd_put_16 (input_bfd, x, contents);
926 break;
927
928 case R_MSP430_ABS8:
929 contents += rel->r_offset;
930 srel = (bfd_signed_vma) relocation;
931 if (is_rel_reloc)
932 srel += bfd_get_8 (input_bfd, contents);
933 else
934 srel += rel->r_addend;
935 bfd_put_8 (input_bfd, srel & 0xff, contents);
936 break;
937
938 case R_MSP430X_ABS20_EXT_DST:
939 contents += rel->r_offset;
940 srel = (bfd_signed_vma) relocation;
941 if (is_rel_reloc)
942 srel += bfd_get_16 (input_bfd, contents) & 0xf;
943 else
944 srel += rel->r_addend;
945 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 4);
946 srel >>= 16;
947 x = bfd_get_16 (input_bfd, contents);
948 x = (x & 0xfff0) | (srel & 0xf);
949 bfd_put_16 (input_bfd, x, contents);
950 break;
951
952 case R_MSP430X_ABS20_EXT_ODST:
953 /* [0,4]+[48,16] = ---F ---- FFFF */
954 contents += rel->r_offset;
955 srel = (bfd_signed_vma) relocation;
956 if (is_rel_reloc)
957 {
958 bfd_vma addend;
959 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
960 addend |= bfd_get_16 (input_bfd, contents+4);
961 srel += addend;
962 }
963 else
964 srel += rel->r_addend;
965 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 6);
966 srel >>= 16;
967 x = bfd_get_16 (input_bfd, contents);
968 x = (x & 0xfff0) | (srel & 0xf);
969 bfd_put_16 (input_bfd, x, contents);
970 break;
971
972 case R_MSP430X_ABS20_ADR_SRC:
973 /* [8,4]+[32,16] = -F-- FFFF */
974 contents += rel->r_offset;
975 srel = (bfd_signed_vma) relocation;
976 if (is_rel_reloc)
977 {
978 bfd_vma addend;
979
980 addend = ((bfd_get_16 (input_bfd, contents) & 0xf00) << 8);
981 addend |= bfd_get_16 (input_bfd, contents+2);
982 srel += addend;
983 }
984 else
985 srel += rel->r_addend;
986 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
987 srel >>= 16;
988 x = bfd_get_16 (input_bfd, contents);
989 x = (x & 0xf0ff) | ((srel << 8) & 0x0f00);
990 bfd_put_16 (input_bfd, x, contents);
991 break;
992
993 case R_MSP430X_ABS20_ADR_DST:
994 /* [0,4]+[32,16] = ---F FFFF */
995 contents += rel->r_offset;
996 srel = (bfd_signed_vma) relocation;
997 if (is_rel_reloc)
998 {
999 bfd_vma addend;
1000 addend = ((bfd_get_16 (input_bfd, contents) & 0xf) << 16);
1001 addend |= bfd_get_16 (input_bfd, contents+2);
1002 srel += addend;
1003 }
1004 else
1005 srel += rel->r_addend;
1006 bfd_put_16 (input_bfd, (srel & 0xffff), contents + 2);
1007 srel >>= 16;
1008 x = bfd_get_16 (input_bfd, contents);
1009 x = (x & 0xfff0) | (srel & 0xf);
1010 bfd_put_16 (input_bfd, x, contents);
1011 break;
1012
1013 case R_MSP430X_ABS16:
1014 contents += rel->r_offset;
1015 srel = (bfd_signed_vma) relocation;
1016 if (is_rel_reloc)
1017 srel += bfd_get_16 (input_bfd, contents);
1018 else
1019 srel += rel->r_addend;
1020 x = srel;
1021 if (x > 0xffff)
1022 return bfd_reloc_overflow;
1023 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1024 break;
1025
1026 case R_MSP430_ABS_HI16:
1027 /* The EABI specifies that this must be a RELA reloc. */
1028 BFD_ASSERT (! is_rel_reloc);
1029 contents += rel->r_offset;
1030 srel = (bfd_signed_vma) relocation;
1031 srel += rel->r_addend;
1032 bfd_put_16 (input_bfd, (srel >> 16) & 0xffff, contents);
1033 break;
1034
1035 case R_MSP430X_PCR20_CALL:
1036 /* [0,4]+[32,16] = ---F FFFF*/
1037 contents += rel->r_offset;
1038 srel = (bfd_signed_vma) relocation;
1039 if (is_rel_reloc)
1040 {
1041 bfd_vma addend;
1042 addend = (bfd_get_16 (input_bfd, contents) & 0xf) << 16;
1043 addend |= bfd_get_16 (input_bfd, contents+2);
1044 srel += addend;
1045 }
1046 else
1047 srel += rel->r_addend;
1048 srel -= rel->r_offset;
1049 srel -= (input_section->output_section->vma +
1050 input_section->output_offset);
1051 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2);
1052 srel >>= 16;
1053 x = bfd_get_16 (input_bfd, contents);
1054 x = (x & 0xfff0) | (srel & 0xf);
1055 bfd_put_16 (input_bfd, x, contents);
1056 break;
1057
1058 case R_MSP430X_PCR16:
1059 contents += rel->r_offset;
1060 srel = (bfd_signed_vma) relocation;
1061 if (is_rel_reloc)
1062 srel += bfd_get_16 (input_bfd, contents);
1063 else
1064 srel += rel->r_addend;
1065 srel -= rel->r_offset;
1066 srel -= (input_section->output_section->vma +
1067 input_section->output_offset);
1068 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1069 break;
1070
1071 case R_MSP430_PREL31:
1072 contents += rel->r_offset;
1073 srel = (bfd_signed_vma) relocation;
1074 if (is_rel_reloc)
1075 srel += (bfd_get_32 (input_bfd, contents) & 0x7fffffff);
1076 else
1077 srel += rel->r_addend;
1078 srel += rel->r_addend;
1079 x = bfd_get_32 (input_bfd, contents);
1080 x = (x & 0x80000000) | ((srel >> 31) & 0x7fffffff);
1081 bfd_put_32 (input_bfd, x, contents);
1082 break;
1083
1084 default:
1085 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1086 contents, rel->r_offset,
1087 relocation, rel->r_addend);
1088 }
1089 else
1090 switch (howto->type)
1091 {
1092 case R_MSP430_10_PCREL:
1093 contents += rel->r_offset;
1094 srel = (bfd_signed_vma) relocation;
1095 srel += rel->r_addend;
1096 srel -= rel->r_offset;
1097 srel -= 2; /* Branch instructions add 2 to the PC... */
1098 srel -= (input_section->output_section->vma +
1099 input_section->output_offset);
1100
1101 if (srel & 1)
1102 return bfd_reloc_outofrange;
1103
1104 /* MSP430 addresses commands as words. */
1105 srel >>= 1;
1106
1107 /* Check for an overflow. */
1108 if (srel < -512 || srel > 511)
1109 {
1110 if (info->disable_target_specific_optimizations < 0)
1111 {
1112 static bfd_boolean warned = FALSE;
1113 if (! warned)
1114 {
1115 info->callbacks->warning
1116 (info,
1117 _("Try enabling relaxation to avoid relocation truncations"),
1118 NULL, input_bfd, input_section, relocation);
1119 warned = TRUE;
1120 }
1121 }
1122 return bfd_reloc_overflow;
1123 }
1124
1125 x = bfd_get_16 (input_bfd, contents);
1126 x = (x & 0xfc00) | (srel & 0x3ff);
1127 bfd_put_16 (input_bfd, x, contents);
1128 break;
1129
1130 case R_MSP430_2X_PCREL:
1131 contents += rel->r_offset;
1132 srel = (bfd_signed_vma) relocation;
1133 srel += rel->r_addend;
1134 srel -= rel->r_offset;
1135 srel -= 2; /* Branch instructions add 2 to the PC... */
1136 srel -= (input_section->output_section->vma +
1137 input_section->output_offset);
1138
1139 if (srel & 1)
1140 return bfd_reloc_outofrange;
1141
1142 /* MSP430 addresses commands as words. */
1143 srel >>= 1;
1144
1145 /* Check for an overflow. */
1146 if (srel < -512 || srel > 511)
1147 return bfd_reloc_overflow;
1148
1149 x = bfd_get_16 (input_bfd, contents);
1150 x = (x & 0xfc00) | (srel & 0x3ff);
1151 bfd_put_16 (input_bfd, x, contents);
1152 /* Handle second jump instruction. */
1153 x = bfd_get_16 (input_bfd, contents - 2);
1154 srel += 1;
1155 x = (x & 0xfc00) | (srel & 0x3ff);
1156 bfd_put_16 (input_bfd, x, contents - 2);
1157 break;
1158
1159 case R_MSP430_RL_PCREL:
1160 case R_MSP430_16_PCREL:
1161 contents += rel->r_offset;
1162 srel = (bfd_signed_vma) relocation;
1163 srel += rel->r_addend;
1164 srel -= rel->r_offset;
1165 /* Only branch instructions add 2 to the PC... */
1166 srel -= (input_section->output_section->vma +
1167 input_section->output_offset);
1168
1169 if (srel & 1)
1170 return bfd_reloc_outofrange;
1171
1172 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1173 break;
1174
1175 case R_MSP430_16_PCREL_BYTE:
1176 contents += rel->r_offset;
1177 srel = (bfd_signed_vma) relocation;
1178 srel += rel->r_addend;
1179 srel -= rel->r_offset;
1180 /* Only branch instructions add 2 to the PC... */
1181 srel -= (input_section->output_section->vma +
1182 input_section->output_offset);
1183
1184 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1185 break;
1186
1187 case R_MSP430_16_BYTE:
1188 contents += rel->r_offset;
1189 srel = (bfd_signed_vma) relocation;
1190 srel += rel->r_addend;
1191 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1192 break;
1193
1194 case R_MSP430_16:
1195 contents += rel->r_offset;
1196 srel = (bfd_signed_vma) relocation;
1197 srel += rel->r_addend;
1198
1199 if (srel & 1)
1200 return bfd_reloc_notsupported;
1201
1202 bfd_put_16 (input_bfd, srel & 0xffff, contents);
1203 break;
1204
1205 case R_MSP430_8:
1206 contents += rel->r_offset;
1207 srel = (bfd_signed_vma) relocation;
1208 srel += rel->r_addend;
1209
1210 bfd_put_8 (input_bfd, srel & 0xff, contents);
1211 break;
1212
1213 case R_MSP430_SYM_DIFF:
1214 /* Cache the input section and value.
1215 The offset is unreliable, since relaxation may
1216 have reduced the following reloc's offset. */
1217 sym_diff_section = input_section;
1218 sym_diff_value = relocation;
1219 return bfd_reloc_ok;
1220
1221 default:
1222 r = _bfd_final_link_relocate (howto, input_bfd, input_section,
1223 contents, rel->r_offset,
1224 relocation, rel->r_addend);
1225 }
1226
1227 return r;
1228 }
1229
1230 /* Relocate an MSP430 ELF section. */
1231
1232 static bfd_boolean
1233 elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
1234 struct bfd_link_info * info,
1235 bfd * input_bfd,
1236 asection * input_section,
1237 bfd_byte * contents,
1238 Elf_Internal_Rela * relocs,
1239 Elf_Internal_Sym * local_syms,
1240 asection ** local_sections)
1241 {
1242 Elf_Internal_Shdr *symtab_hdr;
1243 struct elf_link_hash_entry **sym_hashes;
1244 Elf_Internal_Rela *rel;
1245 Elf_Internal_Rela *relend;
1246
1247 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
1248 sym_hashes = elf_sym_hashes (input_bfd);
1249 relend = relocs + input_section->reloc_count;
1250
1251 for (rel = relocs; rel < relend; rel++)
1252 {
1253 reloc_howto_type *howto;
1254 unsigned long r_symndx;
1255 Elf_Internal_Sym *sym;
1256 asection *sec;
1257 struct elf_link_hash_entry *h;
1258 bfd_vma relocation;
1259 bfd_reloc_status_type r;
1260 const char *name = NULL;
1261 int r_type;
1262
1263 r_type = ELF32_R_TYPE (rel->r_info);
1264 r_symndx = ELF32_R_SYM (rel->r_info);
1265
1266 if (uses_msp430x_relocs (input_bfd))
1267 howto = elf_msp430x_howto_table + r_type;
1268 else
1269 howto = elf_msp430_howto_table + r_type;
1270
1271 h = NULL;
1272 sym = NULL;
1273 sec = NULL;
1274
1275 if (r_symndx < symtab_hdr->sh_info)
1276 {
1277 sym = local_syms + r_symndx;
1278 sec = local_sections[r_symndx];
1279 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
1280
1281 name = bfd_elf_string_from_elf_section
1282 (input_bfd, symtab_hdr->sh_link, sym->st_name);
1283 name = (name == NULL || * name == 0) ? bfd_section_name (input_bfd, sec) : name;
1284 }
1285 else
1286 {
1287 bfd_boolean unresolved_reloc, warned, ignored;
1288
1289 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
1290 r_symndx, symtab_hdr, sym_hashes,
1291 h, sec, relocation,
1292 unresolved_reloc, warned, ignored);
1293 name = h->root.root.string;
1294 }
1295
1296 if (sec != NULL && discarded_section (sec))
1297 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
1298 rel, 1, relend, howto, 0, contents);
1299
1300 if (info->relocatable)
1301 continue;
1302
1303 r = msp430_final_link_relocate (howto, input_bfd, input_section,
1304 contents, rel, relocation, info);
1305
1306 if (r != bfd_reloc_ok)
1307 {
1308 const char *msg = (const char *) NULL;
1309
1310 switch (r)
1311 {
1312 case bfd_reloc_overflow:
1313 r = info->callbacks->reloc_overflow
1314 (info, (h ? &h->root : NULL), name, howto->name,
1315 (bfd_vma) 0, input_bfd, input_section,
1316 rel->r_offset);
1317 break;
1318
1319 case bfd_reloc_undefined:
1320 r = info->callbacks->undefined_symbol
1321 (info, name, input_bfd, input_section, rel->r_offset, TRUE);
1322 break;
1323
1324 case bfd_reloc_outofrange:
1325 msg = _("internal error: branch/jump to an odd address detected");
1326 break;
1327
1328 case bfd_reloc_notsupported:
1329 msg = _("internal error: unsupported relocation error");
1330 break;
1331
1332 case bfd_reloc_dangerous:
1333 msg = _("internal error: dangerous relocation");
1334 break;
1335
1336 default:
1337 msg = _("internal error: unknown error");
1338 break;
1339 }
1340
1341 if (msg)
1342 r = info->callbacks->warning
1343 (info, msg, name, input_bfd, input_section, rel->r_offset);
1344
1345 if (!r)
1346 return FALSE;
1347 }
1348
1349 }
1350
1351 return TRUE;
1352 }
1353
1354 /* The final processing done just before writing out a MSP430 ELF object
1355 file. This gets the MSP430 architecture right based on the machine
1356 number. */
1357
1358 static void
1359 bfd_elf_msp430_final_write_processing (bfd * abfd,
1360 bfd_boolean linker ATTRIBUTE_UNUSED)
1361 {
1362 unsigned long val;
1363
1364 switch (bfd_get_mach (abfd))
1365 {
1366 default:
1367 case bfd_mach_msp110: val = E_MSP430_MACH_MSP430x11x1; break;
1368 case bfd_mach_msp11: val = E_MSP430_MACH_MSP430x11; break;
1369 case bfd_mach_msp12: val = E_MSP430_MACH_MSP430x12; break;
1370 case bfd_mach_msp13: val = E_MSP430_MACH_MSP430x13; break;
1371 case bfd_mach_msp14: val = E_MSP430_MACH_MSP430x14; break;
1372 case bfd_mach_msp15: val = E_MSP430_MACH_MSP430x15; break;
1373 case bfd_mach_msp16: val = E_MSP430_MACH_MSP430x16; break;
1374 case bfd_mach_msp31: val = E_MSP430_MACH_MSP430x31; break;
1375 case bfd_mach_msp32: val = E_MSP430_MACH_MSP430x32; break;
1376 case bfd_mach_msp33: val = E_MSP430_MACH_MSP430x33; break;
1377 case bfd_mach_msp41: val = E_MSP430_MACH_MSP430x41; break;
1378 case bfd_mach_msp42: val = E_MSP430_MACH_MSP430x42; break;
1379 case bfd_mach_msp43: val = E_MSP430_MACH_MSP430x43; break;
1380 case bfd_mach_msp44: val = E_MSP430_MACH_MSP430x44; break;
1381 case bfd_mach_msp20: val = E_MSP430_MACH_MSP430x20; break;
1382 case bfd_mach_msp22: val = E_MSP430_MACH_MSP430x22; break;
1383 case bfd_mach_msp23: val = E_MSP430_MACH_MSP430x23; break;
1384 case bfd_mach_msp24: val = E_MSP430_MACH_MSP430x24; break;
1385 case bfd_mach_msp26: val = E_MSP430_MACH_MSP430x26; break;
1386 case bfd_mach_msp46: val = E_MSP430_MACH_MSP430x46; break;
1387 case bfd_mach_msp47: val = E_MSP430_MACH_MSP430x47; break;
1388 case bfd_mach_msp54: val = E_MSP430_MACH_MSP430x54; break;
1389 case bfd_mach_msp430x: val = E_MSP430_MACH_MSP430X; break;
1390 }
1391
1392 elf_elfheader (abfd)->e_machine = EM_MSP430;
1393 elf_elfheader (abfd)->e_flags &= ~EF_MSP430_MACH;
1394 elf_elfheader (abfd)->e_flags |= val;
1395 }
1396
1397 /* Set the right machine number. */
1398
1399 static bfd_boolean
1400 elf32_msp430_object_p (bfd * abfd)
1401 {
1402 int e_set = bfd_mach_msp14;
1403
1404 if (elf_elfheader (abfd)->e_machine == EM_MSP430
1405 || elf_elfheader (abfd)->e_machine == EM_MSP430_OLD)
1406 {
1407 int e_mach = elf_elfheader (abfd)->e_flags & EF_MSP430_MACH;
1408
1409 switch (e_mach)
1410 {
1411 default:
1412 case E_MSP430_MACH_MSP430x11: e_set = bfd_mach_msp11; break;
1413 case E_MSP430_MACH_MSP430x11x1: e_set = bfd_mach_msp110; break;
1414 case E_MSP430_MACH_MSP430x12: e_set = bfd_mach_msp12; break;
1415 case E_MSP430_MACH_MSP430x13: e_set = bfd_mach_msp13; break;
1416 case E_MSP430_MACH_MSP430x14: e_set = bfd_mach_msp14; break;
1417 case E_MSP430_MACH_MSP430x15: e_set = bfd_mach_msp15; break;
1418 case E_MSP430_MACH_MSP430x16: e_set = bfd_mach_msp16; break;
1419 case E_MSP430_MACH_MSP430x31: e_set = bfd_mach_msp31; break;
1420 case E_MSP430_MACH_MSP430x32: e_set = bfd_mach_msp32; break;
1421 case E_MSP430_MACH_MSP430x33: e_set = bfd_mach_msp33; break;
1422 case E_MSP430_MACH_MSP430x41: e_set = bfd_mach_msp41; break;
1423 case E_MSP430_MACH_MSP430x42: e_set = bfd_mach_msp42; break;
1424 case E_MSP430_MACH_MSP430x43: e_set = bfd_mach_msp43; break;
1425 case E_MSP430_MACH_MSP430x44: e_set = bfd_mach_msp44; break;
1426 case E_MSP430_MACH_MSP430x20: e_set = bfd_mach_msp20; break;
1427 case E_MSP430_MACH_MSP430x22: e_set = bfd_mach_msp22; break;
1428 case E_MSP430_MACH_MSP430x23: e_set = bfd_mach_msp23; break;
1429 case E_MSP430_MACH_MSP430x24: e_set = bfd_mach_msp24; break;
1430 case E_MSP430_MACH_MSP430x26: e_set = bfd_mach_msp26; break;
1431 case E_MSP430_MACH_MSP430x46: e_set = bfd_mach_msp46; break;
1432 case E_MSP430_MACH_MSP430x47: e_set = bfd_mach_msp47; break;
1433 case E_MSP430_MACH_MSP430x54: e_set = bfd_mach_msp54; break;
1434 case E_MSP430_MACH_MSP430X: e_set = bfd_mach_msp430x; break;
1435 }
1436 }
1437
1438 return bfd_default_set_arch_mach (abfd, bfd_arch_msp430, e_set);
1439 }
1440
1441 /* These functions handle relaxing for the msp430.
1442 Relaxation required only in two cases:
1443 - Bad hand coding like jumps from one section to another or
1444 from file to file.
1445 - Sibling calls. This will affect only 'jump label' polymorph. Without
1446 relaxing this enlarges code by 2 bytes. Sibcalls implemented but
1447 do not work in gcc's port by the reason I do not know.
1448 - To convert out of range conditional jump instructions (found inside
1449 a function) into inverted jumps over an unconditional branch instruction.
1450 Anyway, if a relaxation required, user should pass -relax option to the
1451 linker.
1452
1453 There are quite a few relaxing opportunities available on the msp430:
1454
1455 ================================================================
1456
1457 1. 3 words -> 1 word
1458
1459 eq == jeq label jne +4; br lab
1460 ne != jne label jeq +4; br lab
1461 lt < jl label jge +4; br lab
1462 ltu < jlo label lhs +4; br lab
1463 ge >= jge label jl +4; br lab
1464 geu >= jhs label jlo +4; br lab
1465
1466 2. 4 words -> 1 word
1467
1468 ltn < jn jn +2; jmp +4; br lab
1469
1470 3. 4 words -> 2 words
1471
1472 gt > jeq +2; jge label jeq +6; jl +4; br label
1473 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
1474
1475 4. 4 words -> 2 words and 2 labels
1476
1477 leu <= jeq label; jlo label jeq +2; jhs +4; br label
1478 le <= jeq label; jl label jeq +2; jge +4; br label
1479 =================================================================
1480
1481 codemap for first cases is (labels masked ):
1482 eq: 0x2002,0x4010,0x0000 -> 0x2400
1483 ne: 0x2402,0x4010,0x0000 -> 0x2000
1484 lt: 0x3402,0x4010,0x0000 -> 0x3800
1485 ltu: 0x2c02,0x4010,0x0000 -> 0x2800
1486 ge: 0x3802,0x4010,0x0000 -> 0x3400
1487 geu: 0x2802,0x4010,0x0000 -> 0x2c00
1488
1489 second case:
1490 ltn: 0x3001,0x3c02,0x4010,0x0000 -> 0x3000
1491
1492 third case:
1493 gt: 0x2403,0x3802,0x4010,0x0000 -> 0x2401,0x3400
1494 gtu: 0x2403,0x2802,0x4010,0x0000 -> 0x2401,0x2c00
1495
1496 fourth case:
1497 leu: 0x2401,0x2c02,0x4010,0x0000 -> 0x2400,0x2800
1498 le: 0x2401,0x3402,0x4010,0x0000 -> 0x2400,0x3800
1499
1500 Unspecified case :)
1501 jump: 0x4010,0x0000 -> 0x3c00. */
1502
1503 #define NUMB_RELAX_CODES 12
1504 static struct rcodes_s
1505 {
1506 int f0, f1; /* From code. */
1507 int t0, t1; /* To code. */
1508 int labels; /* Position of labels: 1 - one label at first
1509 word, 2 - one at second word, 3 - two
1510 labels at both. */
1511 int cdx; /* Words to match. */
1512 int bs; /* Shrink bytes. */
1513 int off; /* Offset from old label for new code. */
1514 int ncl; /* New code length. */
1515 } rcode[] =
1516 {/* lab,cdx,bs,off,ncl */
1517 { 0x0000, 0x0000, 0x3c00, 0x0000, 1, 0, 2, 2, 2}, /* jump */
1518 { 0x0000, 0x2002, 0x2400, 0x0000, 1, 1, 4, 4, 2}, /* eq */
1519 { 0x0000, 0x2402, 0x2000, 0x0000, 1, 1, 4, 4, 2}, /* ne */
1520 { 0x0000, 0x3402, 0x3800, 0x0000, 1, 1, 4, 4, 2}, /* lt */
1521 { 0x0000, 0x2c02, 0x2800, 0x0000, 1, 1, 4, 4, 2}, /* ltu */
1522 { 0x0000, 0x3802, 0x3400, 0x0000, 1, 1, 4, 4, 2}, /* ge */
1523 { 0x0000, 0x2802, 0x2c00, 0x0000, 1, 1, 4, 4, 2}, /* geu */
1524 { 0x3001, 0x3c02, 0x3000, 0x0000, 1, 2, 6, 6, 2}, /* ltn */
1525 { 0x2403, 0x3802, 0x2401, 0x3400, 2, 2, 4, 6, 4}, /* gt */
1526 { 0x2403, 0x2802, 0x2401, 0x2c00, 2, 2, 4, 6, 4}, /* gtu */
1527 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* leu , 2 labels */
1528 { 0x2401, 0x2c02, 0x2400, 0x2800, 3, 2, 4, 6, 4}, /* le , 2 labels */
1529 { 0, 0, 0, 0, 0, 0, 0, 0, 0}
1530 };
1531
1532 /* Return TRUE if a symbol exists at the given address. */
1533
1534 static bfd_boolean
1535 msp430_elf_symbol_address_p (bfd * abfd,
1536 asection * sec,
1537 Elf_Internal_Sym * isym,
1538 bfd_vma addr)
1539 {
1540 Elf_Internal_Shdr *symtab_hdr;
1541 unsigned int sec_shndx;
1542 Elf_Internal_Sym *isymend;
1543 struct elf_link_hash_entry **sym_hashes;
1544 struct elf_link_hash_entry **end_hashes;
1545 unsigned int symcount;
1546
1547 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1548
1549 /* Examine all the local symbols. */
1550 symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
1551 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1552 if (isym->st_shndx == sec_shndx && isym->st_value == addr)
1553 return TRUE;
1554
1555 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1556 - symtab_hdr->sh_info);
1557 sym_hashes = elf_sym_hashes (abfd);
1558 end_hashes = sym_hashes + symcount;
1559 for (; sym_hashes < end_hashes; sym_hashes++)
1560 {
1561 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1562
1563 if ((sym_hash->root.type == bfd_link_hash_defined
1564 || sym_hash->root.type == bfd_link_hash_defweak)
1565 && sym_hash->root.u.def.section == sec
1566 && sym_hash->root.u.def.value == addr)
1567 return TRUE;
1568 }
1569
1570 return FALSE;
1571 }
1572
1573 /* Adjust all local symbols defined as '.section + 0xXXXX' (.section has
1574 sec_shndx) referenced from current and other sections. */
1575
1576 static bfd_boolean
1577 msp430_elf_relax_adjust_locals (bfd * abfd, asection * sec, bfd_vma addr,
1578 int count, unsigned int sec_shndx,
1579 bfd_vma toaddr)
1580 {
1581 Elf_Internal_Shdr *symtab_hdr;
1582 Elf_Internal_Rela *irel;
1583 Elf_Internal_Rela *irelend;
1584 Elf_Internal_Sym *isym;
1585
1586 irel = elf_section_data (sec)->relocs;
1587 if (irel == NULL)
1588 return TRUE;
1589
1590 irelend = irel + sec->reloc_count;
1591 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1592 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1593
1594 for (;irel < irelend; irel++)
1595 {
1596 unsigned int sidx = ELF32_R_SYM(irel->r_info);
1597 Elf_Internal_Sym *lsym = isym + sidx;
1598
1599 /* Adjust symbols referenced by .sec+0xXX */
1600 if (irel->r_addend > addr && irel->r_addend < toaddr
1601 && sidx < symtab_hdr->sh_info
1602 && lsym->st_shndx == sec_shndx)
1603 irel->r_addend -= count;
1604 }
1605
1606 return TRUE;
1607 }
1608
1609 /* Delete some bytes from a section while relaxing. */
1610
1611 static bfd_boolean
1612 msp430_elf_relax_delete_bytes (bfd * abfd, asection * sec, bfd_vma addr,
1613 int count)
1614 {
1615 Elf_Internal_Shdr *symtab_hdr;
1616 unsigned int sec_shndx;
1617 bfd_byte *contents;
1618 Elf_Internal_Rela *irel;
1619 Elf_Internal_Rela *irelend;
1620 bfd_vma toaddr;
1621 Elf_Internal_Sym *isym;
1622 Elf_Internal_Sym *isymend;
1623 struct elf_link_hash_entry **sym_hashes;
1624 struct elf_link_hash_entry **end_hashes;
1625 unsigned int symcount;
1626 asection *p;
1627
1628 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1629
1630 contents = elf_section_data (sec)->this_hdr.contents;
1631
1632 toaddr = sec->size;
1633
1634 irel = elf_section_data (sec)->relocs;
1635 irelend = irel + sec->reloc_count;
1636
1637 /* Actually delete the bytes. */
1638 memmove (contents + addr, contents + addr + count,
1639 (size_t) (toaddr - addr - count));
1640 sec->size -= count;
1641
1642 /* Adjust all the relocs. */
1643 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1644 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1645 for (; irel < irelend; irel++)
1646 {
1647 /* Get the new reloc address. */
1648 if ((irel->r_offset > addr && irel->r_offset < toaddr))
1649 irel->r_offset -= count;
1650 }
1651
1652 for (p = abfd->sections; p != NULL; p = p->next)
1653 msp430_elf_relax_adjust_locals (abfd,p,addr,count,sec_shndx,toaddr);
1654
1655 /* Adjust the local symbols defined in this section. */
1656 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1657 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1658 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1659 {
1660 const char * name;
1661
1662 name = bfd_elf_string_from_elf_section
1663 (abfd, symtab_hdr->sh_link, isym->st_name);
1664 name = (name == NULL || * name == 0) ? bfd_section_name (abfd, sec) : name;
1665
1666 if (isym->st_shndx != sec_shndx)
1667 continue;
1668
1669 if (isym->st_value > addr
1670 && (isym->st_value < toaddr
1671 /* We also adjust a symbol at the end of the section if its name is
1672 on the list below. These symbols are used for debug info
1673 generation and they refer to the end of the current section, not
1674 the start of the next section. */
1675 || (isym->st_value == toaddr
1676 && name != NULL
1677 && (CONST_STRNEQ (name, ".Letext")
1678 || CONST_STRNEQ (name, ".LFE")))))
1679 {
1680 if (isym->st_value < addr + count)
1681 isym->st_value = addr;
1682 else
1683 isym->st_value -= count;
1684 }
1685 /* Adjust the function symbol's size as well. */
1686 else if (ELF_ST_TYPE (isym->st_info) == STT_FUNC
1687 && isym->st_value + isym->st_size > addr
1688 && isym->st_value + isym->st_size < toaddr)
1689 isym->st_size -= count;
1690 }
1691
1692 /* Now adjust the global symbols defined in this section. */
1693 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1694 - symtab_hdr->sh_info);
1695 sym_hashes = elf_sym_hashes (abfd);
1696 end_hashes = sym_hashes + symcount;
1697 for (; sym_hashes < end_hashes; sym_hashes++)
1698 {
1699 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1700
1701 if ((sym_hash->root.type == bfd_link_hash_defined
1702 || sym_hash->root.type == bfd_link_hash_defweak)
1703 && sym_hash->root.u.def.section == sec
1704 && sym_hash->root.u.def.value > addr
1705 && sym_hash->root.u.def.value < toaddr)
1706 {
1707 if (sym_hash->root.u.def.value < addr + count)
1708 sym_hash->root.u.def.value = addr;
1709 else
1710 sym_hash->root.u.def.value -= count;
1711 }
1712 /* Adjust the function symbol's size as well. */
1713 else if (sym_hash->root.type == bfd_link_hash_defined
1714 && sym_hash->root.u.def.section == sec
1715 && sym_hash->type == STT_FUNC
1716 && sym_hash->root.u.def.value + sym_hash->size > addr
1717 && sym_hash->root.u.def.value + sym_hash->size < toaddr)
1718 sym_hash->size -= count;
1719 }
1720
1721 return TRUE;
1722 }
1723
1724 /* Insert two words into a section whilst relaxing. */
1725
1726 static bfd_byte *
1727 msp430_elf_relax_add_two_words (bfd * abfd, asection * sec, bfd_vma addr,
1728 int word1, int word2)
1729 {
1730 Elf_Internal_Shdr *symtab_hdr;
1731 unsigned int sec_shndx;
1732 bfd_byte *contents;
1733 Elf_Internal_Rela *irel;
1734 Elf_Internal_Rela *irelend;
1735 Elf_Internal_Sym *isym;
1736 Elf_Internal_Sym *isymend;
1737 struct elf_link_hash_entry **sym_hashes;
1738 struct elf_link_hash_entry **end_hashes;
1739 unsigned int symcount;
1740 bfd_vma sec_end;
1741 asection *p;
1742
1743 contents = elf_section_data (sec)->this_hdr.contents;
1744 sec_end = sec->size;
1745
1746 /* Make space for the new words. */
1747 contents = bfd_realloc (contents, sec_end + 4);
1748 memmove (contents + addr + 4, contents + addr, sec_end - addr);
1749
1750 /* Insert the new words. */
1751 bfd_put_16 (abfd, word1, contents + addr);
1752 bfd_put_16 (abfd, word2, contents + addr + 2);
1753
1754 /* Update the section information. */
1755 sec->size += 4;
1756 elf_section_data (sec)->this_hdr.contents = contents;
1757
1758 /* Adjust all the relocs. */
1759 irel = elf_section_data (sec)->relocs;
1760 irelend = irel + sec->reloc_count;
1761
1762 for (; irel < irelend; irel++)
1763 if ((irel->r_offset >= addr && irel->r_offset < sec_end))
1764 irel->r_offset += 4;
1765
1766 /* Adjust the local symbols defined in this section. */
1767 sec_shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
1768 for (p = abfd->sections; p != NULL; p = p->next)
1769 msp430_elf_relax_adjust_locals (abfd, p, addr, -4,
1770 sec_shndx, sec_end);
1771
1772 /* Adjust the global symbols affected by the move. */
1773 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1774 isym = (Elf_Internal_Sym *) symtab_hdr->contents;
1775 for (isymend = isym + symtab_hdr->sh_info; isym < isymend; isym++)
1776 if (isym->st_shndx == sec_shndx
1777 && isym->st_value >= addr && isym->st_value < sec_end)
1778 isym->st_value += 4;
1779
1780 /* Now adjust the global symbols defined in this section. */
1781 symcount = (symtab_hdr->sh_size / sizeof (Elf32_External_Sym)
1782 - symtab_hdr->sh_info);
1783 sym_hashes = elf_sym_hashes (abfd);
1784 end_hashes = sym_hashes + symcount;
1785 for (; sym_hashes < end_hashes; sym_hashes++)
1786 {
1787 struct elf_link_hash_entry *sym_hash = *sym_hashes;
1788
1789 if ((sym_hash->root.type == bfd_link_hash_defined
1790 || sym_hash->root.type == bfd_link_hash_defweak)
1791 && sym_hash->root.u.def.section == sec
1792 && sym_hash->root.u.def.value >= addr
1793 && sym_hash->root.u.def.value < sec_end)
1794 sym_hash->root.u.def.value += 4;
1795 }
1796
1797 return contents;
1798 }
1799
1800 static bfd_boolean
1801 msp430_elf_relax_section (bfd * abfd, asection * sec,
1802 struct bfd_link_info * link_info,
1803 bfd_boolean * again)
1804 {
1805 Elf_Internal_Shdr * symtab_hdr;
1806 Elf_Internal_Rela * internal_relocs;
1807 Elf_Internal_Rela * irel;
1808 Elf_Internal_Rela * irelend;
1809 bfd_byte * contents = NULL;
1810 Elf_Internal_Sym * isymbuf = NULL;
1811
1812 /* Assume nothing changes. */
1813 *again = FALSE;
1814
1815 /* We don't have to do anything for a relocatable link, if
1816 this section does not have relocs, or if this is not a
1817 code section. */
1818 if (link_info->relocatable
1819 || (sec->flags & SEC_RELOC) == 0
1820 || sec->reloc_count == 0 || (sec->flags & SEC_CODE) == 0)
1821 return TRUE;
1822
1823 symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
1824
1825 /* Get a copy of the native relocations. */
1826 internal_relocs =
1827 _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
1828 if (internal_relocs == NULL)
1829 goto error_return;
1830
1831 /* Walk through them looking for relaxing opportunities. */
1832 irelend = internal_relocs + sec->reloc_count;
1833
1834 /* Do code size growing relocs first. */
1835 for (irel = internal_relocs; irel < irelend; irel++)
1836 {
1837 bfd_vma symval;
1838
1839 /* If this isn't something that can be relaxed, then ignore
1840 this reloc. */
1841 if (uses_msp430x_relocs (abfd)
1842 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430X_10_PCREL)
1843 ;
1844 else if (! uses_msp430x_relocs (abfd)
1845 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_10_PCREL)
1846 ;
1847 else
1848 continue;
1849
1850 /* Get the section contents if we haven't done so already. */
1851 if (contents == NULL)
1852 {
1853 /* Get cached copy if it exists. */
1854 if (elf_section_data (sec)->this_hdr.contents != NULL)
1855 contents = elf_section_data (sec)->this_hdr.contents;
1856 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
1857 goto error_return;
1858 }
1859
1860 /* Read this BFD's local symbols if we haven't done so already. */
1861 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
1862 {
1863 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
1864 if (isymbuf == NULL)
1865 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
1866 symtab_hdr->sh_info, 0,
1867 NULL, NULL, NULL);
1868 if (isymbuf == NULL)
1869 goto error_return;
1870 }
1871
1872 /* Get the value of the symbol referred to by the reloc. */
1873 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
1874 {
1875 /* A local symbol. */
1876 Elf_Internal_Sym *isym;
1877 asection *sym_sec;
1878
1879 isym = isymbuf + ELF32_R_SYM (irel->r_info);
1880 if (isym->st_shndx == SHN_UNDEF)
1881 sym_sec = bfd_und_section_ptr;
1882 else if (isym->st_shndx == SHN_ABS)
1883 sym_sec = bfd_abs_section_ptr;
1884 else if (isym->st_shndx == SHN_COMMON)
1885 sym_sec = bfd_com_section_ptr;
1886 else
1887 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
1888 symval = (isym->st_value
1889 + sym_sec->output_section->vma + sym_sec->output_offset);
1890 }
1891 else
1892 {
1893 unsigned long indx;
1894 struct elf_link_hash_entry *h;
1895
1896 /* An external symbol. */
1897 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
1898 h = elf_sym_hashes (abfd)[indx];
1899 BFD_ASSERT (h != NULL);
1900
1901 if (h->root.type != bfd_link_hash_defined
1902 && h->root.type != bfd_link_hash_defweak)
1903 /* This appears to be a reference to an undefined
1904 symbol. Just ignore it--it will be caught by the
1905 regular reloc processing. */
1906 continue;
1907
1908 symval = (h->root.u.def.value
1909 + h->root.u.def.section->output_section->vma
1910 + h->root.u.def.section->output_offset);
1911 }
1912
1913 /* For simplicity of coding, we are going to modify the section
1914 contents, the section relocs, and the BFD symbol table. We
1915 must tell the rest of the code not to free up this
1916 information. It would be possible to instead create a table
1917 of changes which have to be made, as is done in coff-mips.c;
1918 that would be more work, but would require less memory when
1919 the linker is run. */
1920
1921 bfd_signed_vma value = symval;
1922 int opcode;
1923
1924 /* Compute the value that will be relocated. */
1925 value += irel->r_addend;
1926 /* Convert to PC relative. */
1927 value -= (sec->output_section->vma + sec->output_offset);
1928 value -= irel->r_offset;
1929 value -= 2;
1930 /* Scale. */
1931 value >>= 1;
1932
1933 /* If it is in range then no modifications are needed. */
1934 if (value >= -512 && value <= 511)
1935 continue;
1936
1937 /* Get the opcode. */
1938 opcode = bfd_get_16 (abfd, contents + irel->r_offset);
1939
1940 /* Compute the new opcode. We are going to convert:
1941 J<cond> label
1942 into:
1943 J<inv-cond> 1f
1944 BR[A] #label
1945 1: */
1946 switch (opcode & 0xfc00)
1947 {
1948 case 0x3800: opcode = 0x3402; break; /* Jl -> Jge +2 */
1949 case 0x3400: opcode = 0x3802; break; /* Jge -> Jl +2 */
1950 case 0x2c00: opcode = 0x2802; break; /* Jhs -> Jlo +2 */
1951 case 0x2800: opcode = 0x2c02; break; /* Jlo -> Jhs +2 */
1952 case 0x2400: opcode = 0x2002; break; /* Jeq -> Jne +2 */
1953 case 0x2000: opcode = 0x2402; break; /* jne -> Jeq +2 */
1954 case 0x3000: /* jn */
1955 /* There is no direct inverse of the Jn insn.
1956 FIXME: we could do this as:
1957 Jn 1f
1958 br 2f
1959 1: br label
1960 2: */
1961 continue;
1962 default:
1963 /* Not a conditional branch instruction. */
1964 /* fprintf (stderr, "unrecog: %x\n", opcode); */
1965 continue;
1966 }
1967
1968 /* Note that we've changed the relocs, section contents, etc. */
1969 elf_section_data (sec)->relocs = internal_relocs;
1970 elf_section_data (sec)->this_hdr.contents = contents;
1971 symtab_hdr->contents = (unsigned char *) isymbuf;
1972
1973 /* Install the new opcode. */
1974 bfd_put_16 (abfd, opcode, contents + irel->r_offset);
1975
1976 /* Insert the new branch instruction. */
1977 if (uses_msp430x_relocs (abfd))
1978 {
1979 /* Insert an absolute branch (aka MOVA) instruction. */
1980 contents = msp430_elf_relax_add_two_words
1981 (abfd, sec, irel->r_offset + 2, 0x0080, 0x0000);
1982
1983 /* Update the relocation to point to the inserted branch
1984 instruction. Note - we are changing a PC-relative reloc
1985 into an absolute reloc, but this is OK because we have
1986 arranged with the assembler to have the reloc's value be
1987 a (local) symbol, not a section+offset value. */
1988 irel->r_offset += 2;
1989 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
1990 R_MSP430X_ABS20_ADR_SRC);
1991 }
1992 else
1993 {
1994 contents = msp430_elf_relax_add_two_words
1995 (abfd, sec, irel->r_offset + 2, 0x4030, 0x0000);
1996
1997 /* See comment above about converting a 10-bit PC-rel
1998 relocation into a 16-bit absolute relocation. */
1999 irel->r_offset += 4;
2000 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2001 R_MSP430_16);
2002 }
2003
2004 /* Growing the section may mean that other
2005 conditional branches need to be fixed. */
2006 *again = TRUE;
2007 }
2008
2009 for (irel = internal_relocs; irel < irelend; irel++)
2010 {
2011 bfd_vma symval;
2012
2013 /* Get the section contents if we haven't done so already. */
2014 if (contents == NULL)
2015 {
2016 /* Get cached copy if it exists. */
2017 if (elf_section_data (sec)->this_hdr.contents != NULL)
2018 contents = elf_section_data (sec)->this_hdr.contents;
2019 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
2020 goto error_return;
2021 }
2022
2023 /* Read this BFD's local symbols if we haven't done so already. */
2024 if (isymbuf == NULL && symtab_hdr->sh_info != 0)
2025 {
2026 isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
2027 if (isymbuf == NULL)
2028 isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
2029 symtab_hdr->sh_info, 0,
2030 NULL, NULL, NULL);
2031 if (isymbuf == NULL)
2032 goto error_return;
2033 }
2034
2035 /* Get the value of the symbol referred to by the reloc. */
2036 if (ELF32_R_SYM (irel->r_info) < symtab_hdr->sh_info)
2037 {
2038 /* A local symbol. */
2039 Elf_Internal_Sym *isym;
2040 asection *sym_sec;
2041
2042 isym = isymbuf + ELF32_R_SYM (irel->r_info);
2043 if (isym->st_shndx == SHN_UNDEF)
2044 sym_sec = bfd_und_section_ptr;
2045 else if (isym->st_shndx == SHN_ABS)
2046 sym_sec = bfd_abs_section_ptr;
2047 else if (isym->st_shndx == SHN_COMMON)
2048 sym_sec = bfd_com_section_ptr;
2049 else
2050 sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
2051 symval = (isym->st_value
2052 + sym_sec->output_section->vma + sym_sec->output_offset);
2053 }
2054 else
2055 {
2056 unsigned long indx;
2057 struct elf_link_hash_entry *h;
2058
2059 /* An external symbol. */
2060 indx = ELF32_R_SYM (irel->r_info) - symtab_hdr->sh_info;
2061 h = elf_sym_hashes (abfd)[indx];
2062 BFD_ASSERT (h != NULL);
2063
2064 if (h->root.type != bfd_link_hash_defined
2065 && h->root.type != bfd_link_hash_defweak)
2066 /* This appears to be a reference to an undefined
2067 symbol. Just ignore it--it will be caught by the
2068 regular reloc processing. */
2069 continue;
2070
2071 symval = (h->root.u.def.value
2072 + h->root.u.def.section->output_section->vma
2073 + h->root.u.def.section->output_offset);
2074 }
2075
2076 /* For simplicity of coding, we are going to modify the section
2077 contents, the section relocs, and the BFD symbol table. We
2078 must tell the rest of the code not to free up this
2079 information. It would be possible to instead create a table
2080 of changes which have to be made, as is done in coff-mips.c;
2081 that would be more work, but would require less memory when
2082 the linker is run. */
2083
2084 /* Try to turn a 16bit pc-relative branch into a 10bit pc-relative
2085 branch. */
2086 /* Paranoia? paranoia... */
2087 if (! uses_msp430x_relocs (abfd)
2088 && ELF32_R_TYPE (irel->r_info) == (int) R_MSP430_RL_PCREL)
2089 {
2090 bfd_vma value = symval;
2091
2092 /* Deal with pc-relative gunk. */
2093 value -= (sec->output_section->vma + sec->output_offset);
2094 value -= irel->r_offset;
2095 value += irel->r_addend;
2096
2097 /* See if the value will fit in 10 bits, note the high value is
2098 1016 as the target will be two bytes closer if we are
2099 able to relax. */
2100 if ((long) value < 1016 && (long) value > -1016)
2101 {
2102 int code0 = 0, code1 = 0, code2 = 0;
2103 int i;
2104 struct rcodes_s *rx;
2105
2106 /* Get the opcode. */
2107 if (irel->r_offset >= 6)
2108 code0 = bfd_get_16 (abfd, contents + irel->r_offset - 6);
2109
2110 if (irel->r_offset >= 4)
2111 code1 = bfd_get_16 (abfd, contents + irel->r_offset - 4);
2112
2113 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2114
2115 if (code2 != 0x4010)
2116 continue;
2117
2118 /* Check r4 and r3. */
2119 for (i = NUMB_RELAX_CODES - 1; i >= 0; i--)
2120 {
2121 rx = &rcode[i];
2122 if (rx->cdx == 2 && rx->f0 == code0 && rx->f1 == code1)
2123 break;
2124 else if (rx->cdx == 1 && rx->f1 == code1)
2125 break;
2126 else if (rx->cdx == 0) /* This is an unconditional jump. */
2127 break;
2128 }
2129
2130 /* Check labels:
2131 .Label0: ; we do not care about this label
2132 jeq +6
2133 .Label1: ; make sure there is no label here
2134 jl +4
2135 .Label2: ; make sure there is no label here
2136 br .Label_dst
2137
2138 So, if there is .Label1 or .Label2 we cannot relax this code.
2139 This actually should not happen, cause for relaxable
2140 instructions we use RL_PCREL reloc instead of 16_PCREL.
2141 Will change this in the future. */
2142
2143 if (rx->cdx > 0
2144 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2145 irel->r_offset - 2))
2146 continue;
2147 if (rx->cdx > 1
2148 && msp430_elf_symbol_address_p (abfd, sec, isymbuf,
2149 irel->r_offset - 4))
2150 continue;
2151
2152 /* Note that we've changed the relocs, section contents, etc. */
2153 elf_section_data (sec)->relocs = internal_relocs;
2154 elf_section_data (sec)->this_hdr.contents = contents;
2155 symtab_hdr->contents = (unsigned char *) isymbuf;
2156
2157 /* Fix the relocation's type. */
2158 if (uses_msp430x_relocs (abfd))
2159 {
2160 if (rx->labels == 3) /* Handle special cases. */
2161 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2162 R_MSP430X_2X_PCREL);
2163 else
2164 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2165 R_MSP430X_10_PCREL);
2166 }
2167 else
2168 {
2169 if (rx->labels == 3) /* Handle special cases. */
2170 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2171 R_MSP430_2X_PCREL);
2172 else
2173 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2174 R_MSP430_10_PCREL);
2175 }
2176
2177 /* Fix the opcode right way. */
2178 bfd_put_16 (abfd, rx->t0, contents + irel->r_offset - rx->off);
2179 if (rx->t1)
2180 bfd_put_16 (abfd, rx->t1,
2181 contents + irel->r_offset - rx->off + 2);
2182
2183 /* Delete bytes. */
2184 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2185 irel->r_offset - rx->off +
2186 rx->ncl, rx->bs))
2187 goto error_return;
2188
2189 /* Handle unconditional jumps. */
2190 if (rx->cdx == 0)
2191 irel->r_offset -= 2;
2192
2193 /* That will change things, so, we should relax again.
2194 Note that this is not required, and it may be slow. */
2195 *again = TRUE;
2196 }
2197 }
2198
2199 /* Try to turn a 16-bit absolute branch into a 10-bit pc-relative
2200 branch. */
2201 if (uses_msp430x_relocs (abfd)
2202 && ELF32_R_TYPE (irel->r_info) == R_MSP430X_ABS16)
2203 {
2204 bfd_vma value = symval;
2205
2206 value -= (sec->output_section->vma + sec->output_offset);
2207 value -= irel->r_offset;
2208 value += irel->r_addend;
2209
2210 /* See if the value will fit in 10 bits, note the high value is
2211 1016 as the target will be two bytes closer if we are
2212 able to relax. */
2213 if ((long) value < 1016 && (long) value > -1016)
2214 {
2215 int code2;
2216
2217 /* Get the opcode. */
2218 code2 = bfd_get_16 (abfd, contents + irel->r_offset - 2);
2219 if (code2 != 0x4030)
2220 continue;
2221 /* FIXME: check r4 and r3 ? */
2222 /* FIXME: Handle 0x4010 as well ? */
2223
2224 /* Note that we've changed the relocs, section contents, etc. */
2225 elf_section_data (sec)->relocs = internal_relocs;
2226 elf_section_data (sec)->this_hdr.contents = contents;
2227 symtab_hdr->contents = (unsigned char *) isymbuf;
2228
2229 /* Fix the relocation's type. */
2230 if (uses_msp430x_relocs (abfd))
2231 {
2232 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2233 R_MSP430X_10_PCREL);
2234 }
2235 else
2236 {
2237 irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
2238 R_MSP430_10_PCREL);
2239 }
2240
2241 /* Fix the opcode right way. */
2242 bfd_put_16 (abfd, 0x3c00, contents + irel->r_offset - 2);
2243 irel->r_offset -= 2;
2244
2245 /* Delete bytes. */
2246 if (!msp430_elf_relax_delete_bytes (abfd, sec,
2247 irel->r_offset + 2, 2))
2248 goto error_return;
2249
2250 /* That will change things, so, we should relax again.
2251 Note that this is not required, and it may be slow. */
2252 *again = TRUE;
2253 }
2254 }
2255 }
2256
2257 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2258 {
2259 if (!link_info->keep_memory)
2260 free (isymbuf);
2261 else
2262 {
2263 /* Cache the symbols for elf_link_input_bfd. */
2264 symtab_hdr->contents = (unsigned char *) isymbuf;
2265 }
2266 }
2267
2268 if (contents != NULL
2269 && elf_section_data (sec)->this_hdr.contents != contents)
2270 {
2271 if (!link_info->keep_memory)
2272 free (contents);
2273 else
2274 {
2275 /* Cache the section contents for elf_link_input_bfd. */
2276 elf_section_data (sec)->this_hdr.contents = contents;
2277 }
2278 }
2279
2280 if (internal_relocs != NULL
2281 && elf_section_data (sec)->relocs != internal_relocs)
2282 free (internal_relocs);
2283
2284 return TRUE;
2285
2286 error_return:
2287 if (isymbuf != NULL && symtab_hdr->contents != (unsigned char *) isymbuf)
2288 free (isymbuf);
2289 if (contents != NULL
2290 && elf_section_data (sec)->this_hdr.contents != contents)
2291 free (contents);
2292 if (internal_relocs != NULL
2293 && elf_section_data (sec)->relocs != internal_relocs)
2294 free (internal_relocs);
2295
2296 return FALSE;
2297 }
2298
2299 /* Handle an MSP430 specific section when reading an object file.
2300 This is called when bfd_section_from_shdr finds a section with
2301 an unknown type. */
2302
2303 static bfd_boolean
2304 elf32_msp430_section_from_shdr (bfd *abfd,
2305 Elf_Internal_Shdr * hdr,
2306 const char *name,
2307 int shindex)
2308 {
2309 switch (hdr->sh_type)
2310 {
2311 case SHT_MSP430_SEC_FLAGS:
2312 case SHT_MSP430_SYM_ALIASES:
2313 case SHT_MSP430_ATTRIBUTES:
2314 return _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex);
2315 default:
2316 return FALSE;
2317 }
2318 }
2319
2320 static bfd_boolean
2321 elf32_msp430_obj_attrs_handle_unknown (bfd *abfd, int tag)
2322 {
2323 _bfd_error_handler
2324 (_("Warning: %B: Unknown MSPABI object attribute %d"),
2325 abfd, tag);
2326 return TRUE;
2327 }
2328
2329 /* Determine whether an object attribute tag takes an integer, a
2330 string or both. */
2331
2332 static int
2333 elf32_msp430_obj_attrs_arg_type (int tag)
2334 {
2335 if (tag == Tag_compatibility)
2336 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
2337
2338 if (tag < 32)
2339 return ATTR_TYPE_FLAG_INT_VAL;
2340
2341 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
2342 }
2343
2344 static inline const char *
2345 isa_type (int isa)
2346 {
2347 switch (isa)
2348 {
2349 case 1: return "MSP430";
2350 case 2: return "MSP430X";
2351 default: return "unknown";
2352 }
2353 }
2354
2355 static inline const char *
2356 code_model (int model)
2357 {
2358 switch (model)
2359 {
2360 case 1: return "small";
2361 case 2: return "large";
2362 default: return "unknown";
2363 }
2364 }
2365
2366 static inline const char *
2367 data_model (int model)
2368 {
2369 switch (model)
2370 {
2371 case 1: return "small";
2372 case 2: return "large";
2373 case 3: return "restricted large";
2374 default: return "unknown";
2375 }
2376 }
2377
2378 /* Merge MSPABI object attributes from IBFD into OBFD.
2379 Raise an error if there are conflicting attributes. */
2380
2381 static bfd_boolean
2382 elf32_msp430_merge_mspabi_attributes (bfd *ibfd, bfd *obfd)
2383 {
2384 obj_attribute *in_attr;
2385 obj_attribute *out_attr;
2386 bfd_boolean result = TRUE;
2387 static bfd * first_input_bfd = NULL;
2388
2389 /* Skip linker created files. */
2390 if (ibfd->flags & BFD_LINKER_CREATED)
2391 return TRUE;
2392
2393 /* If this is the first real object just copy the attributes. */
2394 if (!elf_known_obj_attributes_proc (obfd)[0].i)
2395 {
2396 _bfd_elf_copy_obj_attributes (ibfd, obfd);
2397
2398 out_attr = elf_known_obj_attributes_proc (obfd);
2399
2400 /* Use the Tag_null value to indicate that
2401 the attributes have been initialized. */
2402 out_attr[0].i = 1;
2403
2404 first_input_bfd = ibfd;
2405 return TRUE;
2406 }
2407
2408 in_attr = elf_known_obj_attributes_proc (ibfd);
2409 out_attr = elf_known_obj_attributes_proc (obfd);
2410
2411 /* The ISAs must be the same. */
2412 if (in_attr[OFBA_MSPABI_Tag_ISA].i != out_attr[OFBA_MSPABI_Tag_ISA].i)
2413 {
2414 _bfd_error_handler
2415 (_("error: %B uses %s instructions but %B uses %s"),
2416 ibfd, first_input_bfd,
2417 isa_type (in_attr[OFBA_MSPABI_Tag_ISA].i),
2418 isa_type (out_attr[OFBA_MSPABI_Tag_ISA].i));
2419 result = FALSE;
2420 }
2421
2422 /* The code models must be the same. */
2423 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i !=
2424 out_attr[OFBA_MSPABI_Tag_Code_Model].i)
2425 {
2426 _bfd_error_handler
2427 (_("error: %B uses the %s code model whereas %B uses the %s code model"),
2428 ibfd, first_input_bfd,
2429 code_model (in_attr[OFBA_MSPABI_Tag_Code_Model].i),
2430 code_model (out_attr[OFBA_MSPABI_Tag_Code_Model].i));
2431 result = FALSE;
2432 }
2433
2434 /* The large code model is only supported by the MSP430X. */
2435 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 2
2436 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2437 {
2438 _bfd_error_handler
2439 (_("error: %B uses the large code model but %B uses MSP430 instructions"),
2440 ibfd, first_input_bfd);
2441 result = FALSE;
2442 }
2443
2444 /* The data models must be the same. */
2445 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i !=
2446 out_attr[OFBA_MSPABI_Tag_Data_Model].i)
2447 {
2448 _bfd_error_handler
2449 (_("error: %B uses the %s data model whereas %B uses the %s data model"),
2450 ibfd, first_input_bfd,
2451 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i),
2452 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2453 result = FALSE;
2454 }
2455
2456 /* The small code model requires the use of the small data model. */
2457 if (in_attr[OFBA_MSPABI_Tag_Code_Model].i == 1
2458 && out_attr[OFBA_MSPABI_Tag_Data_Model].i != 1)
2459 {
2460 _bfd_error_handler
2461 (_("error: %B uses the small code model but %B uses the %s data model"),
2462 ibfd, first_input_bfd,
2463 data_model (out_attr[OFBA_MSPABI_Tag_Data_Model].i));
2464 result = FALSE;
2465 }
2466
2467 /* The large data models are only supported by the MSP430X. */
2468 if (in_attr[OFBA_MSPABI_Tag_Data_Model].i > 1
2469 && out_attr[OFBA_MSPABI_Tag_ISA].i != 2)
2470 {
2471 _bfd_error_handler
2472 (_("error: %B uses the %s data model but %B only uses MSP430 instructions"),
2473 ibfd, first_input_bfd,
2474 data_model (in_attr[OFBA_MSPABI_Tag_Data_Model].i));
2475 result = FALSE;
2476 }
2477
2478 return result;
2479 }
2480
2481 /* Merge backend specific data from an object file to the output
2482 object file when linking. */
2483
2484 static bfd_boolean
2485 elf32_msp430_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
2486 {
2487 /* Make sure that the machine number reflects the most
2488 advanced version of the MSP architecture required. */
2489 #define max(a,b) ((a) > (b) ? (a) : (b))
2490 if (bfd_get_mach (ibfd) != bfd_get_mach (obfd))
2491 bfd_default_set_arch_mach (obfd, bfd_get_arch (obfd),
2492 max (bfd_get_mach (ibfd), bfd_get_mach (obfd)));
2493 #undef max
2494
2495 return elf32_msp430_merge_mspabi_attributes (ibfd, obfd);
2496 }
2497
2498 static bfd_boolean
2499 msp430_elf_is_target_special_symbol (bfd *abfd, asymbol *sym)
2500 {
2501 return _bfd_elf_is_local_label_name (abfd, sym->name);
2502 }
2503
2504 /* This is gross. The MSP430 EABI says that (sec 11.5):
2505
2506 "An implementation may choose to use Rel or Rela
2507 type relocations for other relocations."
2508
2509 But it also says that:
2510
2511 "Certain relocations are identified as Rela only. [snip]
2512 Where Rela is specified, an implementation must honor
2513 this requirement."
2514
2515 There is one relocation marked as requiring RELA - R_MSP430_ABS_HI16 - but
2516 to keep things simple we choose to use RELA relocations throughout. The
2517 problem is that the TI compiler generates REL relocations, so we have to
2518 be able to accept those as well. */
2519
2520 #define elf_backend_may_use_rel_p 1
2521 #define elf_backend_may_use_rela_p 1
2522 #define elf_backend_default_use_rela_p 1
2523
2524 #undef elf_backend_obj_attrs_vendor
2525 #define elf_backend_obj_attrs_vendor "mspabi"
2526 #undef elf_backend_obj_attrs_section
2527 #define elf_backend_obj_attrs_section ".MSP430.attributes"
2528 #undef elf_backend_obj_attrs_section_type
2529 #define elf_backend_obj_attrs_section_type SHT_MSP430_ATTRIBUTES
2530 #define elf_backend_section_from_shdr elf32_msp430_section_from_shdr
2531 #define elf_backend_obj_attrs_handle_unknown elf32_msp430_obj_attrs_handle_unknown
2532 #undef elf_backend_obj_attrs_arg_type
2533 #define elf_backend_obj_attrs_arg_type elf32_msp430_obj_attrs_arg_type
2534 #define bfd_elf32_bfd_merge_private_bfd_data elf32_msp430_merge_private_bfd_data
2535
2536 #define ELF_ARCH bfd_arch_msp430
2537 #define ELF_MACHINE_CODE EM_MSP430
2538 #define ELF_MACHINE_ALT1 EM_MSP430_OLD
2539 #define ELF_MAXPAGESIZE 4
2540 #define ELF_OSABI ELFOSABI_STANDALONE
2541
2542 #define TARGET_LITTLE_SYM msp430_elf32_vec
2543 #define TARGET_LITTLE_NAME "elf32-msp430"
2544
2545 #define elf_info_to_howto msp430_info_to_howto_rela
2546 #define elf_info_to_howto_rel NULL
2547 #define elf_backend_relocate_section elf32_msp430_relocate_section
2548 #define elf_backend_check_relocs elf32_msp430_check_relocs
2549 #define elf_backend_can_gc_sections 1
2550 #define elf_backend_final_write_processing bfd_elf_msp430_final_write_processing
2551 #define elf_backend_object_p elf32_msp430_object_p
2552 #define bfd_elf32_bfd_relax_section msp430_elf_relax_section
2553 #define bfd_elf32_bfd_is_target_special_symbol msp430_elf_is_target_special_symbol
2554
2555 #undef elf32_bed
2556 #define elf32_bed elf32_msp430_bed
2557
2558 #include "elf32-target.h"
2559
2560 /* The TI compiler sets the OSABI field to ELFOSABI_NONE. */
2561 #undef TARGET_LITTLE_SYM
2562 #define TARGET_LITTLE_SYM msp430_elf32_ti_vec
2563
2564 #undef elf32_bed
2565 #define elf32_bed elf32_msp430_ti_bed
2566
2567 #undef ELF_OSABI
2568 #define ELF_OSABI ELFOSABI_NONE
2569
2570 static const struct bfd_elf_special_section msp430_ti_elf_special_sections[] =
2571 {
2572 /* prefix, prefix_length, suffix_len, type, attributes. */
2573 { STRING_COMMA_LEN (".TI.symbol.alias"), 0, SHT_MSP430_SYM_ALIASES, 0 },
2574 { STRING_COMMA_LEN (".TI.section.flags"), 0, SHT_MSP430_SEC_FLAGS, 0 },
2575 { STRING_COMMA_LEN ("_TI_build_attrib"), 0, SHT_MSP430_ATTRIBUTES, 0 },
2576 { NULL, 0, 0, 0, 0 }
2577 };
2578
2579 #include "elf32-target.h"
GDB Binutils - Deliverables
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