1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2015 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how
,
489 unsigned int bitsize
,
490 unsigned int rightshift
,
491 unsigned int addrsize
,
494 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
495 bfd_reloc_status_type flag
= bfd_reloc_ok
;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask
= N_ONES (bitsize
);
502 signmask
= ~fieldmask
;
503 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
504 a
= (relocation
& addrmask
) >> rightshift
;
508 case complain_overflow_dont
:
511 case complain_overflow_signed
:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask
= ~ (fieldmask
>> 1);
517 case complain_overflow_bitfield
:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
525 flag
= bfd_reloc_overflow
;
528 case complain_overflow_unsigned
:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a
& signmask
) != 0)
531 flag
= bfd_reloc_overflow
;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd
*abfd
,
574 arelent
*reloc_entry
,
576 asection
*input_section
,
578 char **error_message
)
581 bfd_reloc_status_type flag
= bfd_reloc_ok
;
582 bfd_size_type octets
;
583 bfd_vma output_base
= 0;
584 reloc_howto_type
*howto
= reloc_entry
->howto
;
585 asection
*reloc_target_output_section
;
588 symbol
= *(reloc_entry
->sym_ptr_ptr
);
589 if (bfd_is_abs_section (symbol
->section
)
590 && output_bfd
!= NULL
)
592 reloc_entry
->address
+= input_section
->output_offset
;
596 /* PR 17512: file: 0f67f69d. */
598 return bfd_reloc_undefined
;
600 /* If we are not producing relocatable output, return an error if
601 the symbol is not defined. An undefined weak symbol is
602 considered to have a value of zero (SVR4 ABI, p. 4-27). */
603 if (bfd_is_und_section (symbol
->section
)
604 && (symbol
->flags
& BSF_WEAK
) == 0
605 && output_bfd
== NULL
)
606 flag
= bfd_reloc_undefined
;
608 /* If there is a function supplied to handle this relocation type,
609 call it. It'll return `bfd_reloc_continue' if further processing
611 if (howto
->special_function
)
613 bfd_reloc_status_type cont
;
614 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
615 input_section
, output_bfd
,
617 if (cont
!= bfd_reloc_continue
)
621 /* Is the address of the relocation really within the section?
622 Include the size of the reloc in the test for out of range addresses.
623 PR 17512: file: c146ab8b, 46dff27f, 38e53ebf. */
624 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
625 if (octets
+ bfd_get_reloc_size (howto
)
626 > bfd_get_section_limit_octets (abfd
, input_section
))
627 return bfd_reloc_outofrange
;
629 /* Work out which section the relocation is targeted at and the
630 initial relocation command value. */
632 /* Get symbol value. (Common symbols are special.) */
633 if (bfd_is_com_section (symbol
->section
))
636 relocation
= symbol
->value
;
638 reloc_target_output_section
= symbol
->section
->output_section
;
640 /* Convert input-section-relative symbol value to absolute. */
641 if ((output_bfd
&& ! howto
->partial_inplace
)
642 || reloc_target_output_section
== NULL
)
645 output_base
= reloc_target_output_section
->vma
;
647 relocation
+= output_base
+ symbol
->section
->output_offset
;
649 /* Add in supplied addend. */
650 relocation
+= reloc_entry
->addend
;
652 /* Here the variable relocation holds the final address of the
653 symbol we are relocating against, plus any addend. */
655 if (howto
->pc_relative
)
657 /* This is a PC relative relocation. We want to set RELOCATION
658 to the distance between the address of the symbol and the
659 location. RELOCATION is already the address of the symbol.
661 We start by subtracting the address of the section containing
664 If pcrel_offset is set, we must further subtract the position
665 of the location within the section. Some targets arrange for
666 the addend to be the negative of the position of the location
667 within the section; for example, i386-aout does this. For
668 i386-aout, pcrel_offset is FALSE. Some other targets do not
669 include the position of the location; for example, m88kbcs,
670 or ELF. For those targets, pcrel_offset is TRUE.
672 If we are producing relocatable output, then we must ensure
673 that this reloc will be correctly computed when the final
674 relocation is done. If pcrel_offset is FALSE we want to wind
675 up with the negative of the location within the section,
676 which means we must adjust the existing addend by the change
677 in the location within the section. If pcrel_offset is TRUE
678 we do not want to adjust the existing addend at all.
680 FIXME: This seems logical to me, but for the case of
681 producing relocatable output it is not what the code
682 actually does. I don't want to change it, because it seems
683 far too likely that something will break. */
686 input_section
->output_section
->vma
+ input_section
->output_offset
;
688 if (howto
->pcrel_offset
)
689 relocation
-= reloc_entry
->address
;
692 if (output_bfd
!= NULL
)
694 if (! howto
->partial_inplace
)
696 /* This is a partial relocation, and we want to apply the relocation
697 to the reloc entry rather than the raw data. Modify the reloc
698 inplace to reflect what we now know. */
699 reloc_entry
->addend
= relocation
;
700 reloc_entry
->address
+= input_section
->output_offset
;
705 /* This is a partial relocation, but inplace, so modify the
708 If we've relocated with a symbol with a section, change
709 into a ref to the section belonging to the symbol. */
711 reloc_entry
->address
+= input_section
->output_offset
;
714 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
715 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
716 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
718 /* For m68k-coff, the addend was being subtracted twice during
719 relocation with -r. Removing the line below this comment
720 fixes that problem; see PR 2953.
722 However, Ian wrote the following, regarding removing the line below,
723 which explains why it is still enabled: --djm
725 If you put a patch like that into BFD you need to check all the COFF
726 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
727 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
728 problem in a different way. There may very well be a reason that the
729 code works as it does.
731 Hmmm. The first obvious point is that bfd_perform_relocation should
732 not have any tests that depend upon the flavour. It's seem like
733 entirely the wrong place for such a thing. The second obvious point
734 is that the current code ignores the reloc addend when producing
735 relocatable output for COFF. That's peculiar. In fact, I really
736 have no idea what the point of the line you want to remove is.
738 A typical COFF reloc subtracts the old value of the symbol and adds in
739 the new value to the location in the object file (if it's a pc
740 relative reloc it adds the difference between the symbol value and the
741 location). When relocating we need to preserve that property.
743 BFD handles this by setting the addend to the negative of the old
744 value of the symbol. Unfortunately it handles common symbols in a
745 non-standard way (it doesn't subtract the old value) but that's a
746 different story (we can't change it without losing backward
747 compatibility with old object files) (coff-i386 does subtract the old
748 value, to be compatible with existing coff-i386 targets, like SCO).
750 So everything works fine when not producing relocatable output. When
751 we are producing relocatable output, logically we should do exactly
752 what we do when not producing relocatable output. Therefore, your
753 patch is correct. In fact, it should probably always just set
754 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
755 add the value into the object file. This won't hurt the COFF code,
756 which doesn't use the addend; I'm not sure what it will do to other
757 formats (the thing to check for would be whether any formats both use
758 the addend and set partial_inplace).
760 When I wanted to make coff-i386 produce relocatable output, I ran
761 into the problem that you are running into: I wanted to remove that
762 line. Rather than risk it, I made the coff-i386 relocs use a special
763 function; it's coff_i386_reloc in coff-i386.c. The function
764 specifically adds the addend field into the object file, knowing that
765 bfd_perform_relocation is not going to. If you remove that line, then
766 coff-i386.c will wind up adding the addend field in twice. It's
767 trivial to fix; it just needs to be done.
769 The problem with removing the line is just that it may break some
770 working code. With BFD it's hard to be sure of anything. The right
771 way to deal with this is simply to build and test at least all the
772 supported COFF targets. It should be straightforward if time and disk
773 space consuming. For each target:
775 2) generate some executable, and link it using -r (I would
776 probably use paranoia.o and link against newlib/libc.a, which
777 for all the supported targets would be available in
778 /usr/cygnus/progressive/H-host/target/lib/libc.a).
779 3) make the change to reloc.c
780 4) rebuild the linker
782 6) if the resulting object files are the same, you have at least
784 7) if they are different you have to figure out which version is
787 relocation
-= reloc_entry
->addend
;
788 reloc_entry
->addend
= 0;
792 reloc_entry
->addend
= relocation
;
797 /* FIXME: This overflow checking is incomplete, because the value
798 might have overflowed before we get here. For a correct check we
799 need to compute the value in a size larger than bitsize, but we
800 can't reasonably do that for a reloc the same size as a host
802 FIXME: We should also do overflow checking on the result after
803 adding in the value contained in the object file. */
804 if (howto
->complain_on_overflow
!= complain_overflow_dont
805 && flag
== bfd_reloc_ok
)
806 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
809 bfd_arch_bits_per_address (abfd
),
812 /* Either we are relocating all the way, or we don't want to apply
813 the relocation to the reloc entry (probably because there isn't
814 any room in the output format to describe addends to relocs). */
816 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
817 (OSF version 1.3, compiler version 3.11). It miscompiles the
831 x <<= (unsigned long) s.i0;
835 printf ("succeeded (%lx)\n", x);
839 relocation
>>= (bfd_vma
) howto
->rightshift
;
841 /* Shift everything up to where it's going to be used. */
842 relocation
<<= (bfd_vma
) howto
->bitpos
;
844 /* Wait for the day when all have the mask in them. */
847 i instruction to be left alone
848 o offset within instruction
849 r relocation offset to apply
858 (( i i i i i o o o o o from bfd_get<size>
859 and S S S S S) to get the size offset we want
860 + r r r r r r r r r r) to get the final value to place
861 and D D D D D to chop to right size
862 -----------------------
865 ( i i i i i o o o o o from bfd_get<size>
866 and N N N N N ) get instruction
867 -----------------------
873 -----------------------
874 = R R R R R R R R R R put into bfd_put<size>
878 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
884 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
886 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
892 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
894 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
899 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
901 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
906 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
907 relocation
= -relocation
;
909 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
915 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
916 relocation
= -relocation
;
918 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
929 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
931 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
938 return bfd_reloc_other
;
946 bfd_install_relocation
949 bfd_reloc_status_type bfd_install_relocation
951 arelent *reloc_entry,
952 void *data, bfd_vma data_start,
953 asection *input_section,
954 char **error_message);
957 This looks remarkably like <<bfd_perform_relocation>>, except it
958 does not expect that the section contents have been filled in.
959 I.e., it's suitable for use when creating, rather than applying
962 For now, this function should be considered reserved for the
966 bfd_reloc_status_type
967 bfd_install_relocation (bfd
*abfd
,
968 arelent
*reloc_entry
,
970 bfd_vma data_start_offset
,
971 asection
*input_section
,
972 char **error_message
)
975 bfd_reloc_status_type flag
= bfd_reloc_ok
;
976 bfd_size_type octets
;
977 bfd_vma output_base
= 0;
978 reloc_howto_type
*howto
= reloc_entry
->howto
;
979 asection
*reloc_target_output_section
;
983 symbol
= *(reloc_entry
->sym_ptr_ptr
);
984 if (bfd_is_abs_section (symbol
->section
))
986 reloc_entry
->address
+= input_section
->output_offset
;
990 /* If there is a function supplied to handle this relocation type,
991 call it. It'll return `bfd_reloc_continue' if further processing
993 if (howto
->special_function
)
995 bfd_reloc_status_type cont
;
997 /* XXX - The special_function calls haven't been fixed up to deal
998 with creating new relocations and section contents. */
999 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1000 /* XXX - Non-portable! */
1001 ((bfd_byte
*) data_start
1002 - data_start_offset
),
1003 input_section
, abfd
, error_message
);
1004 if (cont
!= bfd_reloc_continue
)
1008 /* Is the address of the relocation really within the section? */
1009 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1010 if (octets
+ bfd_get_reloc_size (howto
)
1011 > bfd_get_section_limit_octets (abfd
, input_section
))
1012 return bfd_reloc_outofrange
;
1014 /* Work out which section the relocation is targeted at and the
1015 initial relocation command value. */
1017 /* Get symbol value. (Common symbols are special.) */
1018 if (bfd_is_com_section (symbol
->section
))
1021 relocation
= symbol
->value
;
1023 reloc_target_output_section
= symbol
->section
->output_section
;
1025 /* Convert input-section-relative symbol value to absolute. */
1026 if (! howto
->partial_inplace
)
1029 output_base
= reloc_target_output_section
->vma
;
1031 relocation
+= output_base
+ symbol
->section
->output_offset
;
1033 /* Add in supplied addend. */
1034 relocation
+= reloc_entry
->addend
;
1036 /* Here the variable relocation holds the final address of the
1037 symbol we are relocating against, plus any addend. */
1039 if (howto
->pc_relative
)
1041 /* This is a PC relative relocation. We want to set RELOCATION
1042 to the distance between the address of the symbol and the
1043 location. RELOCATION is already the address of the symbol.
1045 We start by subtracting the address of the section containing
1048 If pcrel_offset is set, we must further subtract the position
1049 of the location within the section. Some targets arrange for
1050 the addend to be the negative of the position of the location
1051 within the section; for example, i386-aout does this. For
1052 i386-aout, pcrel_offset is FALSE. Some other targets do not
1053 include the position of the location; for example, m88kbcs,
1054 or ELF. For those targets, pcrel_offset is TRUE.
1056 If we are producing relocatable output, then we must ensure
1057 that this reloc will be correctly computed when the final
1058 relocation is done. If pcrel_offset is FALSE we want to wind
1059 up with the negative of the location within the section,
1060 which means we must adjust the existing addend by the change
1061 in the location within the section. If pcrel_offset is TRUE
1062 we do not want to adjust the existing addend at all.
1064 FIXME: This seems logical to me, but for the case of
1065 producing relocatable output it is not what the code
1066 actually does. I don't want to change it, because it seems
1067 far too likely that something will break. */
1070 input_section
->output_section
->vma
+ input_section
->output_offset
;
1072 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1073 relocation
-= reloc_entry
->address
;
1076 if (! howto
->partial_inplace
)
1078 /* This is a partial relocation, and we want to apply the relocation
1079 to the reloc entry rather than the raw data. Modify the reloc
1080 inplace to reflect what we now know. */
1081 reloc_entry
->addend
= relocation
;
1082 reloc_entry
->address
+= input_section
->output_offset
;
1087 /* This is a partial relocation, but inplace, so modify the
1090 If we've relocated with a symbol with a section, change
1091 into a ref to the section belonging to the symbol. */
1092 reloc_entry
->address
+= input_section
->output_offset
;
1095 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1096 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1097 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1100 /* For m68k-coff, the addend was being subtracted twice during
1101 relocation with -r. Removing the line below this comment
1102 fixes that problem; see PR 2953.
1104 However, Ian wrote the following, regarding removing the line below,
1105 which explains why it is still enabled: --djm
1107 If you put a patch like that into BFD you need to check all the COFF
1108 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1109 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1110 problem in a different way. There may very well be a reason that the
1111 code works as it does.
1113 Hmmm. The first obvious point is that bfd_install_relocation should
1114 not have any tests that depend upon the flavour. It's seem like
1115 entirely the wrong place for such a thing. The second obvious point
1116 is that the current code ignores the reloc addend when producing
1117 relocatable output for COFF. That's peculiar. In fact, I really
1118 have no idea what the point of the line you want to remove is.
1120 A typical COFF reloc subtracts the old value of the symbol and adds in
1121 the new value to the location in the object file (if it's a pc
1122 relative reloc it adds the difference between the symbol value and the
1123 location). When relocating we need to preserve that property.
1125 BFD handles this by setting the addend to the negative of the old
1126 value of the symbol. Unfortunately it handles common symbols in a
1127 non-standard way (it doesn't subtract the old value) but that's a
1128 different story (we can't change it without losing backward
1129 compatibility with old object files) (coff-i386 does subtract the old
1130 value, to be compatible with existing coff-i386 targets, like SCO).
1132 So everything works fine when not producing relocatable output. When
1133 we are producing relocatable output, logically we should do exactly
1134 what we do when not producing relocatable output. Therefore, your
1135 patch is correct. In fact, it should probably always just set
1136 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1137 add the value into the object file. This won't hurt the COFF code,
1138 which doesn't use the addend; I'm not sure what it will do to other
1139 formats (the thing to check for would be whether any formats both use
1140 the addend and set partial_inplace).
1142 When I wanted to make coff-i386 produce relocatable output, I ran
1143 into the problem that you are running into: I wanted to remove that
1144 line. Rather than risk it, I made the coff-i386 relocs use a special
1145 function; it's coff_i386_reloc in coff-i386.c. The function
1146 specifically adds the addend field into the object file, knowing that
1147 bfd_install_relocation is not going to. If you remove that line, then
1148 coff-i386.c will wind up adding the addend field in twice. It's
1149 trivial to fix; it just needs to be done.
1151 The problem with removing the line is just that it may break some
1152 working code. With BFD it's hard to be sure of anything. The right
1153 way to deal with this is simply to build and test at least all the
1154 supported COFF targets. It should be straightforward if time and disk
1155 space consuming. For each target:
1157 2) generate some executable, and link it using -r (I would
1158 probably use paranoia.o and link against newlib/libc.a, which
1159 for all the supported targets would be available in
1160 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1161 3) make the change to reloc.c
1162 4) rebuild the linker
1164 6) if the resulting object files are the same, you have at least
1166 7) if they are different you have to figure out which version is
1168 relocation
-= reloc_entry
->addend
;
1169 /* FIXME: There should be no target specific code here... */
1170 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1171 reloc_entry
->addend
= 0;
1175 reloc_entry
->addend
= relocation
;
1179 /* FIXME: This overflow checking is incomplete, because the value
1180 might have overflowed before we get here. For a correct check we
1181 need to compute the value in a size larger than bitsize, but we
1182 can't reasonably do that for a reloc the same size as a host
1184 FIXME: We should also do overflow checking on the result after
1185 adding in the value contained in the object file. */
1186 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1187 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1190 bfd_arch_bits_per_address (abfd
),
1193 /* Either we are relocating all the way, or we don't want to apply
1194 the relocation to the reloc entry (probably because there isn't
1195 any room in the output format to describe addends to relocs). */
1197 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1198 (OSF version 1.3, compiler version 3.11). It miscompiles the
1212 x <<= (unsigned long) s.i0;
1214 printf ("failed\n");
1216 printf ("succeeded (%lx)\n", x);
1220 relocation
>>= (bfd_vma
) howto
->rightshift
;
1222 /* Shift everything up to where it's going to be used. */
1223 relocation
<<= (bfd_vma
) howto
->bitpos
;
1225 /* Wait for the day when all have the mask in them. */
1228 i instruction to be left alone
1229 o offset within instruction
1230 r relocation offset to apply
1239 (( i i i i i o o o o o from bfd_get<size>
1240 and S S S S S) to get the size offset we want
1241 + r r r r r r r r r r) to get the final value to place
1242 and D D D D D to chop to right size
1243 -----------------------
1246 ( i i i i i o o o o o from bfd_get<size>
1247 and N N N N N ) get instruction
1248 -----------------------
1254 -----------------------
1255 = R R R R R R R R R R put into bfd_put<size>
1259 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1261 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1263 switch (howto
->size
)
1267 char x
= bfd_get_8 (abfd
, data
);
1269 bfd_put_8 (abfd
, x
, data
);
1275 short x
= bfd_get_16 (abfd
, data
);
1277 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1282 long x
= bfd_get_32 (abfd
, data
);
1284 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1289 long x
= bfd_get_32 (abfd
, data
);
1290 relocation
= -relocation
;
1292 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1302 bfd_vma x
= bfd_get_64 (abfd
, data
);
1304 bfd_put_64 (abfd
, x
, data
);
1308 return bfd_reloc_other
;
1314 /* This relocation routine is used by some of the backend linkers.
1315 They do not construct asymbol or arelent structures, so there is no
1316 reason for them to use bfd_perform_relocation. Also,
1317 bfd_perform_relocation is so hacked up it is easier to write a new
1318 function than to try to deal with it.
1320 This routine does a final relocation. Whether it is useful for a
1321 relocatable link depends upon how the object format defines
1324 FIXME: This routine ignores any special_function in the HOWTO,
1325 since the existing special_function values have been written for
1326 bfd_perform_relocation.
1328 HOWTO is the reloc howto information.
1329 INPUT_BFD is the BFD which the reloc applies to.
1330 INPUT_SECTION is the section which the reloc applies to.
1331 CONTENTS is the contents of the section.
1332 ADDRESS is the address of the reloc within INPUT_SECTION.
1333 VALUE is the value of the symbol the reloc refers to.
1334 ADDEND is the addend of the reloc. */
1336 bfd_reloc_status_type
1337 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1339 asection
*input_section
,
1346 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1348 /* Sanity check the address. */
1349 if (octets
+ bfd_get_reloc_size (howto
)
1350 > bfd_get_section_limit_octets (input_bfd
, input_section
))
1351 return bfd_reloc_outofrange
;
1353 /* This function assumes that we are dealing with a basic relocation
1354 against a symbol. We want to compute the value of the symbol to
1355 relocate to. This is just VALUE, the value of the symbol, plus
1356 ADDEND, any addend associated with the reloc. */
1357 relocation
= value
+ addend
;
1359 /* If the relocation is PC relative, we want to set RELOCATION to
1360 the distance between the symbol (currently in RELOCATION) and the
1361 location we are relocating. Some targets (e.g., i386-aout)
1362 arrange for the contents of the section to be the negative of the
1363 offset of the location within the section; for such targets
1364 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1365 simply leave the contents of the section as zero; for such
1366 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1367 need to subtract out the offset of the location within the
1368 section (which is just ADDRESS). */
1369 if (howto
->pc_relative
)
1371 relocation
-= (input_section
->output_section
->vma
1372 + input_section
->output_offset
);
1373 if (howto
->pcrel_offset
)
1374 relocation
-= address
;
1377 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1378 contents
+ address
);
1381 /* Relocate a given location using a given value and howto. */
1383 bfd_reloc_status_type
1384 _bfd_relocate_contents (reloc_howto_type
*howto
,
1391 bfd_reloc_status_type flag
;
1392 unsigned int rightshift
= howto
->rightshift
;
1393 unsigned int bitpos
= howto
->bitpos
;
1395 /* If the size is negative, negate RELOCATION. This isn't very
1397 if (howto
->size
< 0)
1398 relocation
= -relocation
;
1400 /* Get the value we are going to relocate. */
1401 size
= bfd_get_reloc_size (howto
);
1407 return bfd_reloc_ok
;
1409 x
= bfd_get_8 (input_bfd
, location
);
1412 x
= bfd_get_16 (input_bfd
, location
);
1415 x
= bfd_get_32 (input_bfd
, location
);
1419 x
= bfd_get_64 (input_bfd
, location
);
1426 /* Check for overflow. FIXME: We may drop bits during the addition
1427 which we don't check for. We must either check at every single
1428 operation, which would be tedious, or we must do the computations
1429 in a type larger than bfd_vma, which would be inefficient. */
1430 flag
= bfd_reloc_ok
;
1431 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1433 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1436 /* Get the values to be added together. For signed and unsigned
1437 relocations, we assume that all values should be truncated to
1438 the size of an address. For bitfields, all the bits matter.
1439 See also bfd_check_overflow. */
1440 fieldmask
= N_ONES (howto
->bitsize
);
1441 signmask
= ~fieldmask
;
1442 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1443 | (fieldmask
<< rightshift
));
1444 a
= (relocation
& addrmask
) >> rightshift
;
1445 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1446 addrmask
>>= rightshift
;
1448 switch (howto
->complain_on_overflow
)
1450 case complain_overflow_signed
:
1451 /* If any sign bits are set, all sign bits must be set.
1452 That is, A must be a valid negative address after
1454 signmask
= ~(fieldmask
>> 1);
1457 case complain_overflow_bitfield
:
1458 /* Much like the signed check, but for a field one bit
1459 wider. We allow a bitfield to represent numbers in the
1460 range -2**n to 2**n-1, where n is the number of bits in the
1461 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1462 can't overflow, which is exactly what we want. */
1464 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1465 flag
= bfd_reloc_overflow
;
1467 /* We only need this next bit of code if the sign bit of B
1468 is below the sign bit of A. This would only happen if
1469 SRC_MASK had fewer bits than BITSIZE. Note that if
1470 SRC_MASK has more bits than BITSIZE, we can get into
1471 trouble; we would need to verify that B is in range, as
1472 we do for A above. */
1473 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1476 /* Set all the bits above the sign bit. */
1479 /* Now we can do the addition. */
1482 /* See if the result has the correct sign. Bits above the
1483 sign bit are junk now; ignore them. If the sum is
1484 positive, make sure we did not have all negative inputs;
1485 if the sum is negative, make sure we did not have all
1486 positive inputs. The test below looks only at the sign
1487 bits, and it really just
1488 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1490 We mask with addrmask here to explicitly allow an address
1491 wrap-around. The Linux kernel relies on it, and it is
1492 the only way to write assembler code which can run when
1493 loaded at a location 0x80000000 away from the location at
1494 which it is linked. */
1495 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1496 flag
= bfd_reloc_overflow
;
1499 case complain_overflow_unsigned
:
1500 /* Checking for an unsigned overflow is relatively easy:
1501 trim the addresses and add, and trim the result as well.
1502 Overflow is normally indicated when the result does not
1503 fit in the field. However, we also need to consider the
1504 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1505 input is 0x80000000, and bfd_vma is only 32 bits; then we
1506 will get sum == 0, but there is an overflow, since the
1507 inputs did not fit in the field. Instead of doing a
1508 separate test, we can check for this by or-ing in the
1509 operands when testing for the sum overflowing its final
1511 sum
= (a
+ b
) & addrmask
;
1512 if ((a
| b
| sum
) & signmask
)
1513 flag
= bfd_reloc_overflow
;
1521 /* Put RELOCATION in the right bits. */
1522 relocation
>>= (bfd_vma
) rightshift
;
1523 relocation
<<= (bfd_vma
) bitpos
;
1525 /* Add RELOCATION to the right bits of X. */
1526 x
= ((x
& ~howto
->dst_mask
)
1527 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1529 /* Put the relocated value back in the object file. */
1535 bfd_put_8 (input_bfd
, x
, location
);
1538 bfd_put_16 (input_bfd
, x
, location
);
1541 bfd_put_32 (input_bfd
, x
, location
);
1545 bfd_put_64 (input_bfd
, x
, location
);
1555 /* Clear a given location using a given howto, by applying a fixed relocation
1556 value and discarding any in-place addend. This is used for fixed-up
1557 relocations against discarded symbols, to make ignorable debug or unwind
1558 information more obvious. */
1561 _bfd_clear_contents (reloc_howto_type
*howto
,
1563 asection
*input_section
,
1569 /* Get the value we are going to relocate. */
1570 size
= bfd_get_reloc_size (howto
);
1578 x
= bfd_get_8 (input_bfd
, location
);
1581 x
= bfd_get_16 (input_bfd
, location
);
1584 x
= bfd_get_32 (input_bfd
, location
);
1588 x
= bfd_get_64 (input_bfd
, location
);
1595 /* Zero out the unwanted bits of X. */
1596 x
&= ~howto
->dst_mask
;
1598 /* For a range list, use 1 instead of 0 as placeholder. 0
1599 would terminate the list, hiding any later entries. */
1600 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1601 ".debug_ranges") == 0
1602 && (howto
->dst_mask
& 1) != 0)
1605 /* Put the relocated value back in the object file. */
1612 bfd_put_8 (input_bfd
, x
, location
);
1615 bfd_put_16 (input_bfd
, x
, location
);
1618 bfd_put_32 (input_bfd
, x
, location
);
1622 bfd_put_64 (input_bfd
, x
, location
);
1633 howto manager, , typedef arelent, Relocations
1638 When an application wants to create a relocation, but doesn't
1639 know what the target machine might call it, it can find out by
1640 using this bit of code.
1649 The insides of a reloc code. The idea is that, eventually, there
1650 will be one enumerator for every type of relocation we ever do.
1651 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1652 return a howto pointer.
1654 This does mean that the application must determine the correct
1655 enumerator value; you can't get a howto pointer from a random set
1676 Basic absolute relocations of N bits.
1691 PC-relative relocations. Sometimes these are relative to the address
1692 of the relocation itself; sometimes they are relative to the start of
1693 the section containing the relocation. It depends on the specific target.
1695 The 24-bit relocation is used in some Intel 960 configurations.
1700 Section relative relocations. Some targets need this for DWARF2.
1703 BFD_RELOC_32_GOT_PCREL
1705 BFD_RELOC_16_GOT_PCREL
1707 BFD_RELOC_8_GOT_PCREL
1713 BFD_RELOC_LO16_GOTOFF
1715 BFD_RELOC_HI16_GOTOFF
1717 BFD_RELOC_HI16_S_GOTOFF
1721 BFD_RELOC_64_PLT_PCREL
1723 BFD_RELOC_32_PLT_PCREL
1725 BFD_RELOC_24_PLT_PCREL
1727 BFD_RELOC_16_PLT_PCREL
1729 BFD_RELOC_8_PLT_PCREL
1737 BFD_RELOC_LO16_PLTOFF
1739 BFD_RELOC_HI16_PLTOFF
1741 BFD_RELOC_HI16_S_PLTOFF
1755 BFD_RELOC_68K_GLOB_DAT
1757 BFD_RELOC_68K_JMP_SLOT
1759 BFD_RELOC_68K_RELATIVE
1761 BFD_RELOC_68K_TLS_GD32
1763 BFD_RELOC_68K_TLS_GD16
1765 BFD_RELOC_68K_TLS_GD8
1767 BFD_RELOC_68K_TLS_LDM32
1769 BFD_RELOC_68K_TLS_LDM16
1771 BFD_RELOC_68K_TLS_LDM8
1773 BFD_RELOC_68K_TLS_LDO32
1775 BFD_RELOC_68K_TLS_LDO16
1777 BFD_RELOC_68K_TLS_LDO8
1779 BFD_RELOC_68K_TLS_IE32
1781 BFD_RELOC_68K_TLS_IE16
1783 BFD_RELOC_68K_TLS_IE8
1785 BFD_RELOC_68K_TLS_LE32
1787 BFD_RELOC_68K_TLS_LE16
1789 BFD_RELOC_68K_TLS_LE8
1791 Relocations used by 68K ELF.
1794 BFD_RELOC_32_BASEREL
1796 BFD_RELOC_16_BASEREL
1798 BFD_RELOC_LO16_BASEREL
1800 BFD_RELOC_HI16_BASEREL
1802 BFD_RELOC_HI16_S_BASEREL
1808 Linkage-table relative.
1813 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1816 BFD_RELOC_32_PCREL_S2
1818 BFD_RELOC_16_PCREL_S2
1820 BFD_RELOC_23_PCREL_S2
1822 These PC-relative relocations are stored as word displacements --
1823 i.e., byte displacements shifted right two bits. The 30-bit word
1824 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1825 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1826 signed 16-bit displacement is used on the MIPS, and the 23-bit
1827 displacement is used on the Alpha.
1834 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1835 the target word. These are used on the SPARC.
1842 For systems that allocate a Global Pointer register, these are
1843 displacements off that register. These relocation types are
1844 handled specially, because the value the register will have is
1845 decided relatively late.
1848 BFD_RELOC_I960_CALLJ
1850 Reloc types used for i960/b.out.
1855 BFD_RELOC_SPARC_WDISP22
1861 BFD_RELOC_SPARC_GOT10
1863 BFD_RELOC_SPARC_GOT13
1865 BFD_RELOC_SPARC_GOT22
1867 BFD_RELOC_SPARC_PC10
1869 BFD_RELOC_SPARC_PC22
1871 BFD_RELOC_SPARC_WPLT30
1873 BFD_RELOC_SPARC_COPY
1875 BFD_RELOC_SPARC_GLOB_DAT
1877 BFD_RELOC_SPARC_JMP_SLOT
1879 BFD_RELOC_SPARC_RELATIVE
1881 BFD_RELOC_SPARC_UA16
1883 BFD_RELOC_SPARC_UA32
1885 BFD_RELOC_SPARC_UA64
1887 BFD_RELOC_SPARC_GOTDATA_HIX22
1889 BFD_RELOC_SPARC_GOTDATA_LOX10
1891 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1893 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1895 BFD_RELOC_SPARC_GOTDATA_OP
1897 BFD_RELOC_SPARC_JMP_IREL
1899 BFD_RELOC_SPARC_IRELATIVE
1901 SPARC ELF relocations. There is probably some overlap with other
1902 relocation types already defined.
1905 BFD_RELOC_SPARC_BASE13
1907 BFD_RELOC_SPARC_BASE22
1909 I think these are specific to SPARC a.out (e.g., Sun 4).
1919 BFD_RELOC_SPARC_OLO10
1921 BFD_RELOC_SPARC_HH22
1923 BFD_RELOC_SPARC_HM10
1925 BFD_RELOC_SPARC_LM22
1927 BFD_RELOC_SPARC_PC_HH22
1929 BFD_RELOC_SPARC_PC_HM10
1931 BFD_RELOC_SPARC_PC_LM22
1933 BFD_RELOC_SPARC_WDISP16
1935 BFD_RELOC_SPARC_WDISP19
1943 BFD_RELOC_SPARC_DISP64
1946 BFD_RELOC_SPARC_PLT32
1948 BFD_RELOC_SPARC_PLT64
1950 BFD_RELOC_SPARC_HIX22
1952 BFD_RELOC_SPARC_LOX10
1960 BFD_RELOC_SPARC_REGISTER
1964 BFD_RELOC_SPARC_SIZE32
1966 BFD_RELOC_SPARC_SIZE64
1968 BFD_RELOC_SPARC_WDISP10
1973 BFD_RELOC_SPARC_REV32
1975 SPARC little endian relocation
1977 BFD_RELOC_SPARC_TLS_GD_HI22
1979 BFD_RELOC_SPARC_TLS_GD_LO10
1981 BFD_RELOC_SPARC_TLS_GD_ADD
1983 BFD_RELOC_SPARC_TLS_GD_CALL
1985 BFD_RELOC_SPARC_TLS_LDM_HI22
1987 BFD_RELOC_SPARC_TLS_LDM_LO10
1989 BFD_RELOC_SPARC_TLS_LDM_ADD
1991 BFD_RELOC_SPARC_TLS_LDM_CALL
1993 BFD_RELOC_SPARC_TLS_LDO_HIX22
1995 BFD_RELOC_SPARC_TLS_LDO_LOX10
1997 BFD_RELOC_SPARC_TLS_LDO_ADD
1999 BFD_RELOC_SPARC_TLS_IE_HI22
2001 BFD_RELOC_SPARC_TLS_IE_LO10
2003 BFD_RELOC_SPARC_TLS_IE_LD
2005 BFD_RELOC_SPARC_TLS_IE_LDX
2007 BFD_RELOC_SPARC_TLS_IE_ADD
2009 BFD_RELOC_SPARC_TLS_LE_HIX22
2011 BFD_RELOC_SPARC_TLS_LE_LOX10
2013 BFD_RELOC_SPARC_TLS_DTPMOD32
2015 BFD_RELOC_SPARC_TLS_DTPMOD64
2017 BFD_RELOC_SPARC_TLS_DTPOFF32
2019 BFD_RELOC_SPARC_TLS_DTPOFF64
2021 BFD_RELOC_SPARC_TLS_TPOFF32
2023 BFD_RELOC_SPARC_TLS_TPOFF64
2025 SPARC TLS relocations
2034 BFD_RELOC_SPU_IMM10W
2038 BFD_RELOC_SPU_IMM16W
2042 BFD_RELOC_SPU_PCREL9a
2044 BFD_RELOC_SPU_PCREL9b
2046 BFD_RELOC_SPU_PCREL16
2056 BFD_RELOC_SPU_ADD_PIC
2061 BFD_RELOC_ALPHA_GPDISP_HI16
2063 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2064 "addend" in some special way.
2065 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2066 writing; when reading, it will be the absolute section symbol. The
2067 addend is the displacement in bytes of the "lda" instruction from
2068 the "ldah" instruction (which is at the address of this reloc).
2070 BFD_RELOC_ALPHA_GPDISP_LO16
2072 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2073 with GPDISP_HI16 relocs. The addend is ignored when writing the
2074 relocations out, and is filled in with the file's GP value on
2075 reading, for convenience.
2078 BFD_RELOC_ALPHA_GPDISP
2080 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2081 relocation except that there is no accompanying GPDISP_LO16
2085 BFD_RELOC_ALPHA_LITERAL
2087 BFD_RELOC_ALPHA_ELF_LITERAL
2089 BFD_RELOC_ALPHA_LITUSE
2091 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2092 the assembler turns it into a LDQ instruction to load the address of
2093 the symbol, and then fills in a register in the real instruction.
2095 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2096 section symbol. The addend is ignored when writing, but is filled
2097 in with the file's GP value on reading, for convenience, as with the
2100 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2101 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2102 but it generates output not based on the position within the .got
2103 section, but relative to the GP value chosen for the file during the
2106 The LITUSE reloc, on the instruction using the loaded address, gives
2107 information to the linker that it might be able to use to optimize
2108 away some literal section references. The symbol is ignored (read
2109 as the absolute section symbol), and the "addend" indicates the type
2110 of instruction using the register:
2111 1 - "memory" fmt insn
2112 2 - byte-manipulation (byte offset reg)
2113 3 - jsr (target of branch)
2116 BFD_RELOC_ALPHA_HINT
2118 The HINT relocation indicates a value that should be filled into the
2119 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2120 prediction logic which may be provided on some processors.
2123 BFD_RELOC_ALPHA_LINKAGE
2125 The LINKAGE relocation outputs a linkage pair in the object file,
2126 which is filled by the linker.
2129 BFD_RELOC_ALPHA_CODEADDR
2131 The CODEADDR relocation outputs a STO_CA in the object file,
2132 which is filled by the linker.
2135 BFD_RELOC_ALPHA_GPREL_HI16
2137 BFD_RELOC_ALPHA_GPREL_LO16
2139 The GPREL_HI/LO relocations together form a 32-bit offset from the
2143 BFD_RELOC_ALPHA_BRSGP
2145 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2146 share a common GP, and the target address is adjusted for
2147 STO_ALPHA_STD_GPLOAD.
2152 The NOP relocation outputs a NOP if the longword displacement
2153 between two procedure entry points is < 2^21.
2158 The BSR relocation outputs a BSR if the longword displacement
2159 between two procedure entry points is < 2^21.
2164 The LDA relocation outputs a LDA if the longword displacement
2165 between two procedure entry points is < 2^16.
2170 The BOH relocation outputs a BSR if the longword displacement
2171 between two procedure entry points is < 2^21, or else a hint.
2174 BFD_RELOC_ALPHA_TLSGD
2176 BFD_RELOC_ALPHA_TLSLDM
2178 BFD_RELOC_ALPHA_DTPMOD64
2180 BFD_RELOC_ALPHA_GOTDTPREL16
2182 BFD_RELOC_ALPHA_DTPREL64
2184 BFD_RELOC_ALPHA_DTPREL_HI16
2186 BFD_RELOC_ALPHA_DTPREL_LO16
2188 BFD_RELOC_ALPHA_DTPREL16
2190 BFD_RELOC_ALPHA_GOTTPREL16
2192 BFD_RELOC_ALPHA_TPREL64
2194 BFD_RELOC_ALPHA_TPREL_HI16
2196 BFD_RELOC_ALPHA_TPREL_LO16
2198 BFD_RELOC_ALPHA_TPREL16
2200 Alpha thread-local storage relocations.
2205 BFD_RELOC_MICROMIPS_JMP
2207 The MIPS jump instruction.
2210 BFD_RELOC_MIPS16_JMP
2212 The MIPS16 jump instruction.
2215 BFD_RELOC_MIPS16_GPREL
2217 MIPS16 GP relative reloc.
2222 High 16 bits of 32-bit value; simple reloc.
2227 High 16 bits of 32-bit value but the low 16 bits will be sign
2228 extended and added to form the final result. If the low 16
2229 bits form a negative number, we need to add one to the high value
2230 to compensate for the borrow when the low bits are added.
2238 BFD_RELOC_HI16_PCREL
2240 High 16 bits of 32-bit pc-relative value
2242 BFD_RELOC_HI16_S_PCREL
2244 High 16 bits of 32-bit pc-relative value, adjusted
2246 BFD_RELOC_LO16_PCREL
2248 Low 16 bits of pc-relative value
2251 BFD_RELOC_MIPS16_GOT16
2253 BFD_RELOC_MIPS16_CALL16
2255 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2256 16-bit immediate fields
2258 BFD_RELOC_MIPS16_HI16
2260 MIPS16 high 16 bits of 32-bit value.
2262 BFD_RELOC_MIPS16_HI16_S
2264 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2265 extended and added to form the final result. If the low 16
2266 bits form a negative number, we need to add one to the high value
2267 to compensate for the borrow when the low bits are added.
2269 BFD_RELOC_MIPS16_LO16
2274 BFD_RELOC_MIPS16_TLS_GD
2276 BFD_RELOC_MIPS16_TLS_LDM
2278 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2280 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2282 BFD_RELOC_MIPS16_TLS_GOTTPREL
2284 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2286 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2288 MIPS16 TLS relocations
2291 BFD_RELOC_MIPS_LITERAL
2293 BFD_RELOC_MICROMIPS_LITERAL
2295 Relocation against a MIPS literal section.
2298 BFD_RELOC_MICROMIPS_7_PCREL_S1
2300 BFD_RELOC_MICROMIPS_10_PCREL_S1
2302 BFD_RELOC_MICROMIPS_16_PCREL_S1
2304 microMIPS PC-relative relocations.
2307 BFD_RELOC_MIPS_21_PCREL_S2
2309 BFD_RELOC_MIPS_26_PCREL_S2
2311 BFD_RELOC_MIPS_18_PCREL_S3
2313 BFD_RELOC_MIPS_19_PCREL_S2
2315 MIPS PC-relative relocations.
2318 BFD_RELOC_MICROMIPS_GPREL16
2320 BFD_RELOC_MICROMIPS_HI16
2322 BFD_RELOC_MICROMIPS_HI16_S
2324 BFD_RELOC_MICROMIPS_LO16
2326 microMIPS versions of generic BFD relocs.
2329 BFD_RELOC_MIPS_GOT16
2331 BFD_RELOC_MICROMIPS_GOT16
2333 BFD_RELOC_MIPS_CALL16
2335 BFD_RELOC_MICROMIPS_CALL16
2337 BFD_RELOC_MIPS_GOT_HI16
2339 BFD_RELOC_MICROMIPS_GOT_HI16
2341 BFD_RELOC_MIPS_GOT_LO16
2343 BFD_RELOC_MICROMIPS_GOT_LO16
2345 BFD_RELOC_MIPS_CALL_HI16
2347 BFD_RELOC_MICROMIPS_CALL_HI16
2349 BFD_RELOC_MIPS_CALL_LO16
2351 BFD_RELOC_MICROMIPS_CALL_LO16
2355 BFD_RELOC_MICROMIPS_SUB
2357 BFD_RELOC_MIPS_GOT_PAGE
2359 BFD_RELOC_MICROMIPS_GOT_PAGE
2361 BFD_RELOC_MIPS_GOT_OFST
2363 BFD_RELOC_MICROMIPS_GOT_OFST
2365 BFD_RELOC_MIPS_GOT_DISP
2367 BFD_RELOC_MICROMIPS_GOT_DISP
2369 BFD_RELOC_MIPS_SHIFT5
2371 BFD_RELOC_MIPS_SHIFT6
2373 BFD_RELOC_MIPS_INSERT_A
2375 BFD_RELOC_MIPS_INSERT_B
2377 BFD_RELOC_MIPS_DELETE
2379 BFD_RELOC_MIPS_HIGHEST
2381 BFD_RELOC_MICROMIPS_HIGHEST
2383 BFD_RELOC_MIPS_HIGHER
2385 BFD_RELOC_MICROMIPS_HIGHER
2387 BFD_RELOC_MIPS_SCN_DISP
2389 BFD_RELOC_MICROMIPS_SCN_DISP
2391 BFD_RELOC_MIPS_REL16
2393 BFD_RELOC_MIPS_RELGOT
2397 BFD_RELOC_MICROMIPS_JALR
2399 BFD_RELOC_MIPS_TLS_DTPMOD32
2401 BFD_RELOC_MIPS_TLS_DTPREL32
2403 BFD_RELOC_MIPS_TLS_DTPMOD64
2405 BFD_RELOC_MIPS_TLS_DTPREL64
2407 BFD_RELOC_MIPS_TLS_GD
2409 BFD_RELOC_MICROMIPS_TLS_GD
2411 BFD_RELOC_MIPS_TLS_LDM
2413 BFD_RELOC_MICROMIPS_TLS_LDM
2415 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2417 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2419 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2421 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2423 BFD_RELOC_MIPS_TLS_GOTTPREL
2425 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2427 BFD_RELOC_MIPS_TLS_TPREL32
2429 BFD_RELOC_MIPS_TLS_TPREL64
2431 BFD_RELOC_MIPS_TLS_TPREL_HI16
2433 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2435 BFD_RELOC_MIPS_TLS_TPREL_LO16
2437 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2441 MIPS ELF relocations.
2447 BFD_RELOC_MIPS_JUMP_SLOT
2449 MIPS ELF relocations (VxWorks and PLT extensions).
2453 BFD_RELOC_MOXIE_10_PCREL
2455 Moxie ELF relocations.
2467 FT32 ELF relocations.
2471 BFD_RELOC_FRV_LABEL16
2473 BFD_RELOC_FRV_LABEL24
2479 BFD_RELOC_FRV_GPREL12
2481 BFD_RELOC_FRV_GPRELU12
2483 BFD_RELOC_FRV_GPREL32
2485 BFD_RELOC_FRV_GPRELHI
2487 BFD_RELOC_FRV_GPRELLO
2495 BFD_RELOC_FRV_FUNCDESC
2497 BFD_RELOC_FRV_FUNCDESC_GOT12
2499 BFD_RELOC_FRV_FUNCDESC_GOTHI
2501 BFD_RELOC_FRV_FUNCDESC_GOTLO
2503 BFD_RELOC_FRV_FUNCDESC_VALUE
2505 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2507 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2509 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2511 BFD_RELOC_FRV_GOTOFF12
2513 BFD_RELOC_FRV_GOTOFFHI
2515 BFD_RELOC_FRV_GOTOFFLO
2517 BFD_RELOC_FRV_GETTLSOFF
2519 BFD_RELOC_FRV_TLSDESC_VALUE
2521 BFD_RELOC_FRV_GOTTLSDESC12
2523 BFD_RELOC_FRV_GOTTLSDESCHI
2525 BFD_RELOC_FRV_GOTTLSDESCLO
2527 BFD_RELOC_FRV_TLSMOFF12
2529 BFD_RELOC_FRV_TLSMOFFHI
2531 BFD_RELOC_FRV_TLSMOFFLO
2533 BFD_RELOC_FRV_GOTTLSOFF12
2535 BFD_RELOC_FRV_GOTTLSOFFHI
2537 BFD_RELOC_FRV_GOTTLSOFFLO
2539 BFD_RELOC_FRV_TLSOFF
2541 BFD_RELOC_FRV_TLSDESC_RELAX
2543 BFD_RELOC_FRV_GETTLSOFF_RELAX
2545 BFD_RELOC_FRV_TLSOFF_RELAX
2547 BFD_RELOC_FRV_TLSMOFF
2549 Fujitsu Frv Relocations.
2553 BFD_RELOC_MN10300_GOTOFF24
2555 This is a 24bit GOT-relative reloc for the mn10300.
2557 BFD_RELOC_MN10300_GOT32
2559 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2562 BFD_RELOC_MN10300_GOT24
2564 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2567 BFD_RELOC_MN10300_GOT16
2569 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2572 BFD_RELOC_MN10300_COPY
2574 Copy symbol at runtime.
2576 BFD_RELOC_MN10300_GLOB_DAT
2580 BFD_RELOC_MN10300_JMP_SLOT
2584 BFD_RELOC_MN10300_RELATIVE
2586 Adjust by program base.
2588 BFD_RELOC_MN10300_SYM_DIFF
2590 Together with another reloc targeted at the same location,
2591 allows for a value that is the difference of two symbols
2592 in the same section.
2594 BFD_RELOC_MN10300_ALIGN
2596 The addend of this reloc is an alignment power that must
2597 be honoured at the offset's location, regardless of linker
2600 BFD_RELOC_MN10300_TLS_GD
2602 BFD_RELOC_MN10300_TLS_LD
2604 BFD_RELOC_MN10300_TLS_LDO
2606 BFD_RELOC_MN10300_TLS_GOTIE
2608 BFD_RELOC_MN10300_TLS_IE
2610 BFD_RELOC_MN10300_TLS_LE
2612 BFD_RELOC_MN10300_TLS_DTPMOD
2614 BFD_RELOC_MN10300_TLS_DTPOFF
2616 BFD_RELOC_MN10300_TLS_TPOFF
2618 Various TLS-related relocations.
2620 BFD_RELOC_MN10300_32_PCREL
2622 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2625 BFD_RELOC_MN10300_16_PCREL
2627 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2638 BFD_RELOC_386_GLOB_DAT
2640 BFD_RELOC_386_JUMP_SLOT
2642 BFD_RELOC_386_RELATIVE
2644 BFD_RELOC_386_GOTOFF
2648 BFD_RELOC_386_TLS_TPOFF
2650 BFD_RELOC_386_TLS_IE
2652 BFD_RELOC_386_TLS_GOTIE
2654 BFD_RELOC_386_TLS_LE
2656 BFD_RELOC_386_TLS_GD
2658 BFD_RELOC_386_TLS_LDM
2660 BFD_RELOC_386_TLS_LDO_32
2662 BFD_RELOC_386_TLS_IE_32
2664 BFD_RELOC_386_TLS_LE_32
2666 BFD_RELOC_386_TLS_DTPMOD32
2668 BFD_RELOC_386_TLS_DTPOFF32
2670 BFD_RELOC_386_TLS_TPOFF32
2672 BFD_RELOC_386_TLS_GOTDESC
2674 BFD_RELOC_386_TLS_DESC_CALL
2676 BFD_RELOC_386_TLS_DESC
2678 BFD_RELOC_386_IRELATIVE
2680 i386/elf relocations
2683 BFD_RELOC_X86_64_GOT32
2685 BFD_RELOC_X86_64_PLT32
2687 BFD_RELOC_X86_64_COPY
2689 BFD_RELOC_X86_64_GLOB_DAT
2691 BFD_RELOC_X86_64_JUMP_SLOT
2693 BFD_RELOC_X86_64_RELATIVE
2695 BFD_RELOC_X86_64_GOTPCREL
2697 BFD_RELOC_X86_64_32S
2699 BFD_RELOC_X86_64_DTPMOD64
2701 BFD_RELOC_X86_64_DTPOFF64
2703 BFD_RELOC_X86_64_TPOFF64
2705 BFD_RELOC_X86_64_TLSGD
2707 BFD_RELOC_X86_64_TLSLD
2709 BFD_RELOC_X86_64_DTPOFF32
2711 BFD_RELOC_X86_64_GOTTPOFF
2713 BFD_RELOC_X86_64_TPOFF32
2715 BFD_RELOC_X86_64_GOTOFF64
2717 BFD_RELOC_X86_64_GOTPC32
2719 BFD_RELOC_X86_64_GOT64
2721 BFD_RELOC_X86_64_GOTPCREL64
2723 BFD_RELOC_X86_64_GOTPC64
2725 BFD_RELOC_X86_64_GOTPLT64
2727 BFD_RELOC_X86_64_PLTOFF64
2729 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2731 BFD_RELOC_X86_64_TLSDESC_CALL
2733 BFD_RELOC_X86_64_TLSDESC
2735 BFD_RELOC_X86_64_IRELATIVE
2737 BFD_RELOC_X86_64_PC32_BND
2739 BFD_RELOC_X86_64_PLT32_BND
2741 x86-64/elf relocations
2744 BFD_RELOC_NS32K_IMM_8
2746 BFD_RELOC_NS32K_IMM_16
2748 BFD_RELOC_NS32K_IMM_32
2750 BFD_RELOC_NS32K_IMM_8_PCREL
2752 BFD_RELOC_NS32K_IMM_16_PCREL
2754 BFD_RELOC_NS32K_IMM_32_PCREL
2756 BFD_RELOC_NS32K_DISP_8
2758 BFD_RELOC_NS32K_DISP_16
2760 BFD_RELOC_NS32K_DISP_32
2762 BFD_RELOC_NS32K_DISP_8_PCREL
2764 BFD_RELOC_NS32K_DISP_16_PCREL
2766 BFD_RELOC_NS32K_DISP_32_PCREL
2771 BFD_RELOC_PDP11_DISP_8_PCREL
2773 BFD_RELOC_PDP11_DISP_6_PCREL
2778 BFD_RELOC_PJ_CODE_HI16
2780 BFD_RELOC_PJ_CODE_LO16
2782 BFD_RELOC_PJ_CODE_DIR16
2784 BFD_RELOC_PJ_CODE_DIR32
2786 BFD_RELOC_PJ_CODE_REL16
2788 BFD_RELOC_PJ_CODE_REL32
2790 Picojava relocs. Not all of these appear in object files.
2801 BFD_RELOC_PPC_B16_BRTAKEN
2803 BFD_RELOC_PPC_B16_BRNTAKEN
2807 BFD_RELOC_PPC_BA16_BRTAKEN
2809 BFD_RELOC_PPC_BA16_BRNTAKEN
2813 BFD_RELOC_PPC_GLOB_DAT
2815 BFD_RELOC_PPC_JMP_SLOT
2817 BFD_RELOC_PPC_RELATIVE
2819 BFD_RELOC_PPC_LOCAL24PC
2821 BFD_RELOC_PPC_EMB_NADDR32
2823 BFD_RELOC_PPC_EMB_NADDR16
2825 BFD_RELOC_PPC_EMB_NADDR16_LO
2827 BFD_RELOC_PPC_EMB_NADDR16_HI
2829 BFD_RELOC_PPC_EMB_NADDR16_HA
2831 BFD_RELOC_PPC_EMB_SDAI16
2833 BFD_RELOC_PPC_EMB_SDA2I16
2835 BFD_RELOC_PPC_EMB_SDA2REL
2837 BFD_RELOC_PPC_EMB_SDA21
2839 BFD_RELOC_PPC_EMB_MRKREF
2841 BFD_RELOC_PPC_EMB_RELSEC16
2843 BFD_RELOC_PPC_EMB_RELST_LO
2845 BFD_RELOC_PPC_EMB_RELST_HI
2847 BFD_RELOC_PPC_EMB_RELST_HA
2849 BFD_RELOC_PPC_EMB_BIT_FLD
2851 BFD_RELOC_PPC_EMB_RELSDA
2853 BFD_RELOC_PPC_VLE_REL8
2855 BFD_RELOC_PPC_VLE_REL15
2857 BFD_RELOC_PPC_VLE_REL24
2859 BFD_RELOC_PPC_VLE_LO16A
2861 BFD_RELOC_PPC_VLE_LO16D
2863 BFD_RELOC_PPC_VLE_HI16A
2865 BFD_RELOC_PPC_VLE_HI16D
2867 BFD_RELOC_PPC_VLE_HA16A
2869 BFD_RELOC_PPC_VLE_HA16D
2871 BFD_RELOC_PPC_VLE_SDA21
2873 BFD_RELOC_PPC_VLE_SDA21_LO
2875 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2877 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2879 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2881 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2883 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2885 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2887 BFD_RELOC_PPC64_HIGHER
2889 BFD_RELOC_PPC64_HIGHER_S
2891 BFD_RELOC_PPC64_HIGHEST
2893 BFD_RELOC_PPC64_HIGHEST_S
2895 BFD_RELOC_PPC64_TOC16_LO
2897 BFD_RELOC_PPC64_TOC16_HI
2899 BFD_RELOC_PPC64_TOC16_HA
2903 BFD_RELOC_PPC64_PLTGOT16
2905 BFD_RELOC_PPC64_PLTGOT16_LO
2907 BFD_RELOC_PPC64_PLTGOT16_HI
2909 BFD_RELOC_PPC64_PLTGOT16_HA
2911 BFD_RELOC_PPC64_ADDR16_DS
2913 BFD_RELOC_PPC64_ADDR16_LO_DS
2915 BFD_RELOC_PPC64_GOT16_DS
2917 BFD_RELOC_PPC64_GOT16_LO_DS
2919 BFD_RELOC_PPC64_PLT16_LO_DS
2921 BFD_RELOC_PPC64_SECTOFF_DS
2923 BFD_RELOC_PPC64_SECTOFF_LO_DS
2925 BFD_RELOC_PPC64_TOC16_DS
2927 BFD_RELOC_PPC64_TOC16_LO_DS
2929 BFD_RELOC_PPC64_PLTGOT16_DS
2931 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2933 BFD_RELOC_PPC64_ADDR16_HIGH
2935 BFD_RELOC_PPC64_ADDR16_HIGHA
2937 BFD_RELOC_PPC64_ADDR64_LOCAL
2939 Power(rs6000) and PowerPC relocations.
2948 BFD_RELOC_PPC_DTPMOD
2950 BFD_RELOC_PPC_TPREL16
2952 BFD_RELOC_PPC_TPREL16_LO
2954 BFD_RELOC_PPC_TPREL16_HI
2956 BFD_RELOC_PPC_TPREL16_HA
2960 BFD_RELOC_PPC_DTPREL16
2962 BFD_RELOC_PPC_DTPREL16_LO
2964 BFD_RELOC_PPC_DTPREL16_HI
2966 BFD_RELOC_PPC_DTPREL16_HA
2968 BFD_RELOC_PPC_DTPREL
2970 BFD_RELOC_PPC_GOT_TLSGD16
2972 BFD_RELOC_PPC_GOT_TLSGD16_LO
2974 BFD_RELOC_PPC_GOT_TLSGD16_HI
2976 BFD_RELOC_PPC_GOT_TLSGD16_HA
2978 BFD_RELOC_PPC_GOT_TLSLD16
2980 BFD_RELOC_PPC_GOT_TLSLD16_LO
2982 BFD_RELOC_PPC_GOT_TLSLD16_HI
2984 BFD_RELOC_PPC_GOT_TLSLD16_HA
2986 BFD_RELOC_PPC_GOT_TPREL16
2988 BFD_RELOC_PPC_GOT_TPREL16_LO
2990 BFD_RELOC_PPC_GOT_TPREL16_HI
2992 BFD_RELOC_PPC_GOT_TPREL16_HA
2994 BFD_RELOC_PPC_GOT_DTPREL16
2996 BFD_RELOC_PPC_GOT_DTPREL16_LO
2998 BFD_RELOC_PPC_GOT_DTPREL16_HI
3000 BFD_RELOC_PPC_GOT_DTPREL16_HA
3002 BFD_RELOC_PPC64_TPREL16_DS
3004 BFD_RELOC_PPC64_TPREL16_LO_DS
3006 BFD_RELOC_PPC64_TPREL16_HIGHER
3008 BFD_RELOC_PPC64_TPREL16_HIGHERA
3010 BFD_RELOC_PPC64_TPREL16_HIGHEST
3012 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3014 BFD_RELOC_PPC64_DTPREL16_DS
3016 BFD_RELOC_PPC64_DTPREL16_LO_DS
3018 BFD_RELOC_PPC64_DTPREL16_HIGHER
3020 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3022 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3024 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3026 BFD_RELOC_PPC64_TPREL16_HIGH
3028 BFD_RELOC_PPC64_TPREL16_HIGHA
3030 BFD_RELOC_PPC64_DTPREL16_HIGH
3032 BFD_RELOC_PPC64_DTPREL16_HIGHA
3034 PowerPC and PowerPC64 thread-local storage relocations.
3039 IBM 370/390 relocations
3044 The type of reloc used to build a constructor table - at the moment
3045 probably a 32 bit wide absolute relocation, but the target can choose.
3046 It generally does map to one of the other relocation types.
3049 BFD_RELOC_ARM_PCREL_BRANCH
3051 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3052 not stored in the instruction.
3054 BFD_RELOC_ARM_PCREL_BLX
3056 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3057 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3058 field in the instruction.
3060 BFD_RELOC_THUMB_PCREL_BLX
3062 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3063 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3064 field in the instruction.
3066 BFD_RELOC_ARM_PCREL_CALL
3068 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3070 BFD_RELOC_ARM_PCREL_JUMP
3072 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3075 BFD_RELOC_THUMB_PCREL_BRANCH7
3077 BFD_RELOC_THUMB_PCREL_BRANCH9
3079 BFD_RELOC_THUMB_PCREL_BRANCH12
3081 BFD_RELOC_THUMB_PCREL_BRANCH20
3083 BFD_RELOC_THUMB_PCREL_BRANCH23
3085 BFD_RELOC_THUMB_PCREL_BRANCH25
3087 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3088 The lowest bit must be zero and is not stored in the instruction.
3089 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3090 "nn" one smaller in all cases. Note further that BRANCH23
3091 corresponds to R_ARM_THM_CALL.
3094 BFD_RELOC_ARM_OFFSET_IMM
3096 12-bit immediate offset, used in ARM-format ldr and str instructions.
3099 BFD_RELOC_ARM_THUMB_OFFSET
3101 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3104 BFD_RELOC_ARM_TARGET1
3106 Pc-relative or absolute relocation depending on target. Used for
3107 entries in .init_array sections.
3109 BFD_RELOC_ARM_ROSEGREL32
3111 Read-only segment base relative address.
3113 BFD_RELOC_ARM_SBREL32
3115 Data segment base relative address.
3117 BFD_RELOC_ARM_TARGET2
3119 This reloc is used for references to RTTI data from exception handling
3120 tables. The actual definition depends on the target. It may be a
3121 pc-relative or some form of GOT-indirect relocation.
3123 BFD_RELOC_ARM_PREL31
3125 31-bit PC relative address.
3131 BFD_RELOC_ARM_MOVW_PCREL
3133 BFD_RELOC_ARM_MOVT_PCREL
3135 BFD_RELOC_ARM_THUMB_MOVW
3137 BFD_RELOC_ARM_THUMB_MOVT
3139 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3141 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3143 Low and High halfword relocations for MOVW and MOVT instructions.
3146 BFD_RELOC_ARM_JUMP_SLOT
3148 BFD_RELOC_ARM_GLOB_DAT
3154 BFD_RELOC_ARM_RELATIVE
3156 BFD_RELOC_ARM_GOTOFF
3160 BFD_RELOC_ARM_GOT_PREL
3162 Relocations for setting up GOTs and PLTs for shared libraries.
3165 BFD_RELOC_ARM_TLS_GD32
3167 BFD_RELOC_ARM_TLS_LDO32
3169 BFD_RELOC_ARM_TLS_LDM32
3171 BFD_RELOC_ARM_TLS_DTPOFF32
3173 BFD_RELOC_ARM_TLS_DTPMOD32
3175 BFD_RELOC_ARM_TLS_TPOFF32
3177 BFD_RELOC_ARM_TLS_IE32
3179 BFD_RELOC_ARM_TLS_LE32
3181 BFD_RELOC_ARM_TLS_GOTDESC
3183 BFD_RELOC_ARM_TLS_CALL
3185 BFD_RELOC_ARM_THM_TLS_CALL
3187 BFD_RELOC_ARM_TLS_DESCSEQ
3189 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3191 BFD_RELOC_ARM_TLS_DESC
3193 ARM thread-local storage relocations.
3196 BFD_RELOC_ARM_ALU_PC_G0_NC
3198 BFD_RELOC_ARM_ALU_PC_G0
3200 BFD_RELOC_ARM_ALU_PC_G1_NC
3202 BFD_RELOC_ARM_ALU_PC_G1
3204 BFD_RELOC_ARM_ALU_PC_G2
3206 BFD_RELOC_ARM_LDR_PC_G0
3208 BFD_RELOC_ARM_LDR_PC_G1
3210 BFD_RELOC_ARM_LDR_PC_G2
3212 BFD_RELOC_ARM_LDRS_PC_G0
3214 BFD_RELOC_ARM_LDRS_PC_G1
3216 BFD_RELOC_ARM_LDRS_PC_G2
3218 BFD_RELOC_ARM_LDC_PC_G0
3220 BFD_RELOC_ARM_LDC_PC_G1
3222 BFD_RELOC_ARM_LDC_PC_G2
3224 BFD_RELOC_ARM_ALU_SB_G0_NC
3226 BFD_RELOC_ARM_ALU_SB_G0
3228 BFD_RELOC_ARM_ALU_SB_G1_NC
3230 BFD_RELOC_ARM_ALU_SB_G1
3232 BFD_RELOC_ARM_ALU_SB_G2
3234 BFD_RELOC_ARM_LDR_SB_G0
3236 BFD_RELOC_ARM_LDR_SB_G1
3238 BFD_RELOC_ARM_LDR_SB_G2
3240 BFD_RELOC_ARM_LDRS_SB_G0
3242 BFD_RELOC_ARM_LDRS_SB_G1
3244 BFD_RELOC_ARM_LDRS_SB_G2
3246 BFD_RELOC_ARM_LDC_SB_G0
3248 BFD_RELOC_ARM_LDC_SB_G1
3250 BFD_RELOC_ARM_LDC_SB_G2
3252 ARM group relocations.
3257 Annotation of BX instructions.
3260 BFD_RELOC_ARM_IRELATIVE
3262 ARM support for STT_GNU_IFUNC.
3265 BFD_RELOC_ARM_IMMEDIATE
3267 BFD_RELOC_ARM_ADRL_IMMEDIATE
3269 BFD_RELOC_ARM_T32_IMMEDIATE
3271 BFD_RELOC_ARM_T32_ADD_IMM
3273 BFD_RELOC_ARM_T32_IMM12
3275 BFD_RELOC_ARM_T32_ADD_PC12
3277 BFD_RELOC_ARM_SHIFT_IMM
3287 BFD_RELOC_ARM_CP_OFF_IMM
3289 BFD_RELOC_ARM_CP_OFF_IMM_S2
3291 BFD_RELOC_ARM_T32_CP_OFF_IMM
3293 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3295 BFD_RELOC_ARM_ADR_IMM
3297 BFD_RELOC_ARM_LDR_IMM
3299 BFD_RELOC_ARM_LITERAL
3301 BFD_RELOC_ARM_IN_POOL
3303 BFD_RELOC_ARM_OFFSET_IMM8
3305 BFD_RELOC_ARM_T32_OFFSET_U8
3307 BFD_RELOC_ARM_T32_OFFSET_IMM
3309 BFD_RELOC_ARM_HWLITERAL
3311 BFD_RELOC_ARM_THUMB_ADD
3313 BFD_RELOC_ARM_THUMB_IMM
3315 BFD_RELOC_ARM_THUMB_SHIFT
3317 These relocs are only used within the ARM assembler. They are not
3318 (at present) written to any object files.
3321 BFD_RELOC_SH_PCDISP8BY2
3323 BFD_RELOC_SH_PCDISP12BY2
3331 BFD_RELOC_SH_DISP12BY2
3333 BFD_RELOC_SH_DISP12BY4
3335 BFD_RELOC_SH_DISP12BY8
3339 BFD_RELOC_SH_DISP20BY8
3343 BFD_RELOC_SH_IMM4BY2
3345 BFD_RELOC_SH_IMM4BY4
3349 BFD_RELOC_SH_IMM8BY2
3351 BFD_RELOC_SH_IMM8BY4
3353 BFD_RELOC_SH_PCRELIMM8BY2
3355 BFD_RELOC_SH_PCRELIMM8BY4
3357 BFD_RELOC_SH_SWITCH16
3359 BFD_RELOC_SH_SWITCH32
3373 BFD_RELOC_SH_LOOP_START
3375 BFD_RELOC_SH_LOOP_END
3379 BFD_RELOC_SH_GLOB_DAT
3381 BFD_RELOC_SH_JMP_SLOT
3383 BFD_RELOC_SH_RELATIVE
3387 BFD_RELOC_SH_GOT_LOW16
3389 BFD_RELOC_SH_GOT_MEDLOW16
3391 BFD_RELOC_SH_GOT_MEDHI16
3393 BFD_RELOC_SH_GOT_HI16
3395 BFD_RELOC_SH_GOTPLT_LOW16
3397 BFD_RELOC_SH_GOTPLT_MEDLOW16
3399 BFD_RELOC_SH_GOTPLT_MEDHI16
3401 BFD_RELOC_SH_GOTPLT_HI16
3403 BFD_RELOC_SH_PLT_LOW16
3405 BFD_RELOC_SH_PLT_MEDLOW16
3407 BFD_RELOC_SH_PLT_MEDHI16
3409 BFD_RELOC_SH_PLT_HI16
3411 BFD_RELOC_SH_GOTOFF_LOW16
3413 BFD_RELOC_SH_GOTOFF_MEDLOW16
3415 BFD_RELOC_SH_GOTOFF_MEDHI16
3417 BFD_RELOC_SH_GOTOFF_HI16
3419 BFD_RELOC_SH_GOTPC_LOW16
3421 BFD_RELOC_SH_GOTPC_MEDLOW16
3423 BFD_RELOC_SH_GOTPC_MEDHI16
3425 BFD_RELOC_SH_GOTPC_HI16
3429 BFD_RELOC_SH_GLOB_DAT64
3431 BFD_RELOC_SH_JMP_SLOT64
3433 BFD_RELOC_SH_RELATIVE64
3435 BFD_RELOC_SH_GOT10BY4
3437 BFD_RELOC_SH_GOT10BY8
3439 BFD_RELOC_SH_GOTPLT10BY4
3441 BFD_RELOC_SH_GOTPLT10BY8
3443 BFD_RELOC_SH_GOTPLT32
3445 BFD_RELOC_SH_SHMEDIA_CODE
3451 BFD_RELOC_SH_IMMS6BY32
3457 BFD_RELOC_SH_IMMS10BY2
3459 BFD_RELOC_SH_IMMS10BY4
3461 BFD_RELOC_SH_IMMS10BY8
3467 BFD_RELOC_SH_IMM_LOW16
3469 BFD_RELOC_SH_IMM_LOW16_PCREL
3471 BFD_RELOC_SH_IMM_MEDLOW16
3473 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3475 BFD_RELOC_SH_IMM_MEDHI16
3477 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3479 BFD_RELOC_SH_IMM_HI16
3481 BFD_RELOC_SH_IMM_HI16_PCREL
3485 BFD_RELOC_SH_TLS_GD_32
3487 BFD_RELOC_SH_TLS_LD_32
3489 BFD_RELOC_SH_TLS_LDO_32
3491 BFD_RELOC_SH_TLS_IE_32
3493 BFD_RELOC_SH_TLS_LE_32
3495 BFD_RELOC_SH_TLS_DTPMOD32
3497 BFD_RELOC_SH_TLS_DTPOFF32
3499 BFD_RELOC_SH_TLS_TPOFF32
3503 BFD_RELOC_SH_GOTOFF20
3505 BFD_RELOC_SH_GOTFUNCDESC
3507 BFD_RELOC_SH_GOTFUNCDESC20
3509 BFD_RELOC_SH_GOTOFFFUNCDESC
3511 BFD_RELOC_SH_GOTOFFFUNCDESC20
3513 BFD_RELOC_SH_FUNCDESC
3515 Renesas / SuperH SH relocs. Not all of these appear in object files.
3538 BFD_RELOC_ARC_SECTOFF
3540 BFD_RELOC_ARC_S21H_PCREL
3542 BFD_RELOC_ARC_S21W_PCREL
3544 BFD_RELOC_ARC_S25H_PCREL
3546 BFD_RELOC_ARC_S25W_PCREL
3550 BFD_RELOC_ARC_SDA_LDST
3552 BFD_RELOC_ARC_SDA_LDST1
3554 BFD_RELOC_ARC_SDA_LDST2
3556 BFD_RELOC_ARC_SDA16_LD
3558 BFD_RELOC_ARC_SDA16_LD1
3560 BFD_RELOC_ARC_SDA16_LD2
3562 BFD_RELOC_ARC_S13_PCREL
3568 BFD_RELOC_ARC_32_ME_S
3570 BFD_RELOC_ARC_N32_ME
3572 BFD_RELOC_ARC_SECTOFF_ME
3574 BFD_RELOC_ARC_SDA32_ME
3578 BFD_RELOC_AC_SECTOFF_U8
3580 BFD_RELOC_AC_SECTOFF_U8_1
3582 BFD_RELOC_AC_SECTOFF_U8_2
3584 BFD_RELOC_AC_SECTFOFF_S9
3586 BFD_RELOC_AC_SECTFOFF_S9_1
3588 BFD_RELOC_AC_SECTFOFF_S9_2
3590 BFD_RELOC_ARC_SECTOFF_ME_1
3592 BFD_RELOC_ARC_SECTOFF_ME_2
3594 BFD_RELOC_ARC_SECTOFF_1
3596 BFD_RELOC_ARC_SECTOFF_2
3598 BFD_RELOC_ARC_SDA16_ST2
3604 BFD_RELOC_ARC_GOTPC32
3610 BFD_RELOC_ARC_GLOB_DAT
3612 BFD_RELOC_ARC_JMP_SLOT
3614 BFD_RELOC_ARC_RELATIVE
3616 BFD_RELOC_ARC_GOTOFF
3620 BFD_RELOC_ARC_S21W_PCREL_PLT
3622 BFD_RELOC_ARC_S25H_PCREL_PLT
3624 BFD_RELOC_ARC_TLS_DTPMOD
3626 BFD_RELOC_ARC_TLS_TPOFF
3628 BFD_RELOC_ARC_TLS_GD_GOT
3630 BFD_RELOC_ARC_TLS_GD_LD
3632 BFD_RELOC_ARC_TLS_GD_CALL
3634 BFD_RELOC_ARC_TLS_IE_GOT
3636 BFD_RELOC_ARC_TLS_DTPOFF
3638 BFD_RELOC_ARC_TLS_DTPOFF_S9
3640 BFD_RELOC_ARC_TLS_LE_S9
3642 BFD_RELOC_ARC_TLS_LE_32
3644 BFD_RELOC_ARC_S25W_PCREL_PLT
3646 BFD_RELOC_ARC_S21H_PCREL_PLT
3651 BFD_RELOC_BFIN_16_IMM
3653 ADI Blackfin 16 bit immediate absolute reloc.
3655 BFD_RELOC_BFIN_16_HIGH
3657 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3659 BFD_RELOC_BFIN_4_PCREL
3661 ADI Blackfin 'a' part of LSETUP.
3663 BFD_RELOC_BFIN_5_PCREL
3667 BFD_RELOC_BFIN_16_LOW
3669 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3671 BFD_RELOC_BFIN_10_PCREL
3675 BFD_RELOC_BFIN_11_PCREL
3677 ADI Blackfin 'b' part of LSETUP.
3679 BFD_RELOC_BFIN_12_PCREL_JUMP
3683 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3685 ADI Blackfin Short jump, pcrel.
3687 BFD_RELOC_BFIN_24_PCREL_CALL_X
3689 ADI Blackfin Call.x not implemented.
3691 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3693 ADI Blackfin Long Jump pcrel.
3695 BFD_RELOC_BFIN_GOT17M4
3697 BFD_RELOC_BFIN_GOTHI
3699 BFD_RELOC_BFIN_GOTLO
3701 BFD_RELOC_BFIN_FUNCDESC
3703 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3705 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3707 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3709 BFD_RELOC_BFIN_FUNCDESC_VALUE
3711 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3713 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3715 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3717 BFD_RELOC_BFIN_GOTOFF17M4
3719 BFD_RELOC_BFIN_GOTOFFHI
3721 BFD_RELOC_BFIN_GOTOFFLO
3723 ADI Blackfin FD-PIC relocations.
3727 ADI Blackfin GOT relocation.
3729 BFD_RELOC_BFIN_PLTPC
3731 ADI Blackfin PLTPC relocation.
3733 BFD_ARELOC_BFIN_PUSH
3735 ADI Blackfin arithmetic relocation.
3737 BFD_ARELOC_BFIN_CONST
3739 ADI Blackfin arithmetic relocation.
3743 ADI Blackfin arithmetic relocation.
3747 ADI Blackfin arithmetic relocation.
3749 BFD_ARELOC_BFIN_MULT
3751 ADI Blackfin arithmetic relocation.
3755 ADI Blackfin arithmetic relocation.
3759 ADI Blackfin arithmetic relocation.
3761 BFD_ARELOC_BFIN_LSHIFT
3763 ADI Blackfin arithmetic relocation.
3765 BFD_ARELOC_BFIN_RSHIFT
3767 ADI Blackfin arithmetic relocation.
3771 ADI Blackfin arithmetic relocation.
3775 ADI Blackfin arithmetic relocation.
3779 ADI Blackfin arithmetic relocation.
3781 BFD_ARELOC_BFIN_LAND
3783 ADI Blackfin arithmetic relocation.
3787 ADI Blackfin arithmetic relocation.
3791 ADI Blackfin arithmetic relocation.
3795 ADI Blackfin arithmetic relocation.
3797 BFD_ARELOC_BFIN_COMP
3799 ADI Blackfin arithmetic relocation.
3801 BFD_ARELOC_BFIN_PAGE
3803 ADI Blackfin arithmetic relocation.
3805 BFD_ARELOC_BFIN_HWPAGE
3807 ADI Blackfin arithmetic relocation.
3809 BFD_ARELOC_BFIN_ADDR
3811 ADI Blackfin arithmetic relocation.
3814 BFD_RELOC_D10V_10_PCREL_R
3816 Mitsubishi D10V relocs.
3817 This is a 10-bit reloc with the right 2 bits
3820 BFD_RELOC_D10V_10_PCREL_L
3822 Mitsubishi D10V relocs.
3823 This is a 10-bit reloc with the right 2 bits
3824 assumed to be 0. This is the same as the previous reloc
3825 except it is in the left container, i.e.,
3826 shifted left 15 bits.
3830 This is an 18-bit reloc with the right 2 bits
3833 BFD_RELOC_D10V_18_PCREL
3835 This is an 18-bit reloc with the right 2 bits
3841 Mitsubishi D30V relocs.
3842 This is a 6-bit absolute reloc.
3844 BFD_RELOC_D30V_9_PCREL
3846 This is a 6-bit pc-relative reloc with
3847 the right 3 bits assumed to be 0.
3849 BFD_RELOC_D30V_9_PCREL_R
3851 This is a 6-bit pc-relative reloc with
3852 the right 3 bits assumed to be 0. Same
3853 as the previous reloc but on the right side
3858 This is a 12-bit absolute reloc with the
3859 right 3 bitsassumed to be 0.
3861 BFD_RELOC_D30V_15_PCREL
3863 This is a 12-bit pc-relative reloc with
3864 the right 3 bits assumed to be 0.
3866 BFD_RELOC_D30V_15_PCREL_R
3868 This is a 12-bit pc-relative reloc with
3869 the right 3 bits assumed to be 0. Same
3870 as the previous reloc but on the right side
3875 This is an 18-bit absolute reloc with
3876 the right 3 bits assumed to be 0.
3878 BFD_RELOC_D30V_21_PCREL
3880 This is an 18-bit pc-relative reloc with
3881 the right 3 bits assumed to be 0.
3883 BFD_RELOC_D30V_21_PCREL_R
3885 This is an 18-bit pc-relative reloc with
3886 the right 3 bits assumed to be 0. Same
3887 as the previous reloc but on the right side
3892 This is a 32-bit absolute reloc.
3894 BFD_RELOC_D30V_32_PCREL
3896 This is a 32-bit pc-relative reloc.
3899 BFD_RELOC_DLX_HI16_S
3914 BFD_RELOC_M32C_RL_JUMP
3916 BFD_RELOC_M32C_RL_1ADDR
3918 BFD_RELOC_M32C_RL_2ADDR
3920 Renesas M16C/M32C Relocations.
3925 Renesas M32R (formerly Mitsubishi M32R) relocs.
3926 This is a 24 bit absolute address.
3928 BFD_RELOC_M32R_10_PCREL
3930 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3932 BFD_RELOC_M32R_18_PCREL
3934 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3936 BFD_RELOC_M32R_26_PCREL
3938 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3940 BFD_RELOC_M32R_HI16_ULO
3942 This is a 16-bit reloc containing the high 16 bits of an address
3943 used when the lower 16 bits are treated as unsigned.
3945 BFD_RELOC_M32R_HI16_SLO
3947 This is a 16-bit reloc containing the high 16 bits of an address
3948 used when the lower 16 bits are treated as signed.
3952 This is a 16-bit reloc containing the lower 16 bits of an address.
3954 BFD_RELOC_M32R_SDA16
3956 This is a 16-bit reloc containing the small data area offset for use in
3957 add3, load, and store instructions.
3959 BFD_RELOC_M32R_GOT24
3961 BFD_RELOC_M32R_26_PLTREL
3965 BFD_RELOC_M32R_GLOB_DAT
3967 BFD_RELOC_M32R_JMP_SLOT
3969 BFD_RELOC_M32R_RELATIVE
3971 BFD_RELOC_M32R_GOTOFF
3973 BFD_RELOC_M32R_GOTOFF_HI_ULO
3975 BFD_RELOC_M32R_GOTOFF_HI_SLO
3977 BFD_RELOC_M32R_GOTOFF_LO
3979 BFD_RELOC_M32R_GOTPC24
3981 BFD_RELOC_M32R_GOT16_HI_ULO
3983 BFD_RELOC_M32R_GOT16_HI_SLO
3985 BFD_RELOC_M32R_GOT16_LO
3987 BFD_RELOC_M32R_GOTPC_HI_ULO
3989 BFD_RELOC_M32R_GOTPC_HI_SLO
3991 BFD_RELOC_M32R_GOTPC_LO
4000 This is a 20 bit absolute address.
4002 BFD_RELOC_NDS32_9_PCREL
4004 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4006 BFD_RELOC_NDS32_WORD_9_PCREL
4008 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4010 BFD_RELOC_NDS32_15_PCREL
4012 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4014 BFD_RELOC_NDS32_17_PCREL
4016 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4018 BFD_RELOC_NDS32_25_PCREL
4020 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4022 BFD_RELOC_NDS32_HI20
4024 This is a 20-bit reloc containing the high 20 bits of an address
4025 used with the lower 12 bits
4027 BFD_RELOC_NDS32_LO12S3
4029 This is a 12-bit reloc containing the lower 12 bits of an address
4030 then shift right by 3. This is used with ldi,sdi...
4032 BFD_RELOC_NDS32_LO12S2
4034 This is a 12-bit reloc containing the lower 12 bits of an address
4035 then shift left by 2. This is used with lwi,swi...
4037 BFD_RELOC_NDS32_LO12S1
4039 This is a 12-bit reloc containing the lower 12 bits of an address
4040 then shift left by 1. This is used with lhi,shi...
4042 BFD_RELOC_NDS32_LO12S0
4044 This is a 12-bit reloc containing the lower 12 bits of an address
4045 then shift left by 0. This is used with lbisbi...
4047 BFD_RELOC_NDS32_LO12S0_ORI
4049 This is a 12-bit reloc containing the lower 12 bits of an address
4050 then shift left by 0. This is only used with branch relaxations
4052 BFD_RELOC_NDS32_SDA15S3
4054 This is a 15-bit reloc containing the small data area 18-bit signed offset
4055 and shift left by 3 for use in ldi, sdi...
4057 BFD_RELOC_NDS32_SDA15S2
4059 This is a 15-bit reloc containing the small data area 17-bit signed offset
4060 and shift left by 2 for use in lwi, swi...
4062 BFD_RELOC_NDS32_SDA15S1
4064 This is a 15-bit reloc containing the small data area 16-bit signed offset
4065 and shift left by 1 for use in lhi, shi...
4067 BFD_RELOC_NDS32_SDA15S0
4069 This is a 15-bit reloc containing the small data area 15-bit signed offset
4070 and shift left by 0 for use in lbi, sbi...
4072 BFD_RELOC_NDS32_SDA16S3
4074 This is a 16-bit reloc containing the small data area 16-bit signed offset
4077 BFD_RELOC_NDS32_SDA17S2
4079 This is a 17-bit reloc containing the small data area 17-bit signed offset
4080 and shift left by 2 for use in lwi.gp, swi.gp...
4082 BFD_RELOC_NDS32_SDA18S1
4084 This is a 18-bit reloc containing the small data area 18-bit signed offset
4085 and shift left by 1 for use in lhi.gp, shi.gp...
4087 BFD_RELOC_NDS32_SDA19S0
4089 This is a 19-bit reloc containing the small data area 19-bit signed offset
4090 and shift left by 0 for use in lbi.gp, sbi.gp...
4092 BFD_RELOC_NDS32_GOT20
4094 BFD_RELOC_NDS32_9_PLTREL
4096 BFD_RELOC_NDS32_25_PLTREL
4098 BFD_RELOC_NDS32_COPY
4100 BFD_RELOC_NDS32_GLOB_DAT
4102 BFD_RELOC_NDS32_JMP_SLOT
4104 BFD_RELOC_NDS32_RELATIVE
4106 BFD_RELOC_NDS32_GOTOFF
4108 BFD_RELOC_NDS32_GOTOFF_HI20
4110 BFD_RELOC_NDS32_GOTOFF_LO12
4112 BFD_RELOC_NDS32_GOTPC20
4114 BFD_RELOC_NDS32_GOT_HI20
4116 BFD_RELOC_NDS32_GOT_LO12
4118 BFD_RELOC_NDS32_GOTPC_HI20
4120 BFD_RELOC_NDS32_GOTPC_LO12
4124 BFD_RELOC_NDS32_INSN16
4126 BFD_RELOC_NDS32_LABEL
4128 BFD_RELOC_NDS32_LONGCALL1
4130 BFD_RELOC_NDS32_LONGCALL2
4132 BFD_RELOC_NDS32_LONGCALL3
4134 BFD_RELOC_NDS32_LONGJUMP1
4136 BFD_RELOC_NDS32_LONGJUMP2
4138 BFD_RELOC_NDS32_LONGJUMP3
4140 BFD_RELOC_NDS32_LOADSTORE
4142 BFD_RELOC_NDS32_9_FIXED
4144 BFD_RELOC_NDS32_15_FIXED
4146 BFD_RELOC_NDS32_17_FIXED
4148 BFD_RELOC_NDS32_25_FIXED
4150 BFD_RELOC_NDS32_LONGCALL4
4152 BFD_RELOC_NDS32_LONGCALL5
4154 BFD_RELOC_NDS32_LONGCALL6
4156 BFD_RELOC_NDS32_LONGJUMP4
4158 BFD_RELOC_NDS32_LONGJUMP5
4160 BFD_RELOC_NDS32_LONGJUMP6
4162 BFD_RELOC_NDS32_LONGJUMP7
4166 BFD_RELOC_NDS32_PLTREL_HI20
4168 BFD_RELOC_NDS32_PLTREL_LO12
4170 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4172 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4176 BFD_RELOC_NDS32_SDA12S2_DP
4178 BFD_RELOC_NDS32_SDA12S2_SP
4180 BFD_RELOC_NDS32_LO12S2_DP
4182 BFD_RELOC_NDS32_LO12S2_SP
4186 BFD_RELOC_NDS32_DWARF2_OP1
4188 BFD_RELOC_NDS32_DWARF2_OP2
4190 BFD_RELOC_NDS32_DWARF2_LEB
4192 for dwarf2 debug_line.
4194 BFD_RELOC_NDS32_UPDATE_TA
4196 for eliminate 16-bit instructions
4198 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4200 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4202 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4204 BFD_RELOC_NDS32_GOT_LO15
4206 BFD_RELOC_NDS32_GOT_LO19
4208 BFD_RELOC_NDS32_GOTOFF_LO15
4210 BFD_RELOC_NDS32_GOTOFF_LO19
4212 BFD_RELOC_NDS32_GOT15S2
4214 BFD_RELOC_NDS32_GOT17S2
4216 for PIC object relaxation
4221 This is a 5 bit absolute address.
4223 BFD_RELOC_NDS32_10_UPCREL
4225 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4227 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4229 If fp were omitted, fp can used as another gp.
4231 BFD_RELOC_NDS32_RELAX_ENTRY
4233 BFD_RELOC_NDS32_GOT_SUFF
4235 BFD_RELOC_NDS32_GOTOFF_SUFF
4237 BFD_RELOC_NDS32_PLT_GOT_SUFF
4239 BFD_RELOC_NDS32_MULCALL_SUFF
4243 BFD_RELOC_NDS32_PTR_COUNT
4245 BFD_RELOC_NDS32_PTR_RESOLVED
4247 BFD_RELOC_NDS32_PLTBLOCK
4249 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4251 BFD_RELOC_NDS32_RELAX_REGION_END
4253 BFD_RELOC_NDS32_MINUEND
4255 BFD_RELOC_NDS32_SUBTRAHEND
4257 BFD_RELOC_NDS32_DIFF8
4259 BFD_RELOC_NDS32_DIFF16
4261 BFD_RELOC_NDS32_DIFF32
4263 BFD_RELOC_NDS32_DIFF_ULEB128
4265 BFD_RELOC_NDS32_EMPTY
4267 relaxation relative relocation types
4269 BFD_RELOC_NDS32_25_ABS
4271 This is a 25 bit absolute address.
4273 BFD_RELOC_NDS32_DATA
4275 BFD_RELOC_NDS32_TRAN
4277 BFD_RELOC_NDS32_17IFC_PCREL
4279 BFD_RELOC_NDS32_10IFCU_PCREL
4281 For ex9 and ifc using.
4283 BFD_RELOC_NDS32_TPOFF
4285 BFD_RELOC_NDS32_TLS_LE_HI20
4287 BFD_RELOC_NDS32_TLS_LE_LO12
4289 BFD_RELOC_NDS32_TLS_LE_ADD
4291 BFD_RELOC_NDS32_TLS_LE_LS
4293 BFD_RELOC_NDS32_GOTTPOFF
4295 BFD_RELOC_NDS32_TLS_IE_HI20
4297 BFD_RELOC_NDS32_TLS_IE_LO12S2
4299 BFD_RELOC_NDS32_TLS_TPOFF
4301 BFD_RELOC_NDS32_TLS_LE_20
4303 BFD_RELOC_NDS32_TLS_LE_15S0
4305 BFD_RELOC_NDS32_TLS_LE_15S1
4307 BFD_RELOC_NDS32_TLS_LE_15S2
4313 BFD_RELOC_V850_9_PCREL
4315 This is a 9-bit reloc
4317 BFD_RELOC_V850_22_PCREL
4319 This is a 22-bit reloc
4322 BFD_RELOC_V850_SDA_16_16_OFFSET
4324 This is a 16 bit offset from the short data area pointer.
4326 BFD_RELOC_V850_SDA_15_16_OFFSET
4328 This is a 16 bit offset (of which only 15 bits are used) from the
4329 short data area pointer.
4331 BFD_RELOC_V850_ZDA_16_16_OFFSET
4333 This is a 16 bit offset from the zero data area pointer.
4335 BFD_RELOC_V850_ZDA_15_16_OFFSET
4337 This is a 16 bit offset (of which only 15 bits are used) from the
4338 zero data area pointer.
4340 BFD_RELOC_V850_TDA_6_8_OFFSET
4342 This is an 8 bit offset (of which only 6 bits are used) from the
4343 tiny data area pointer.
4345 BFD_RELOC_V850_TDA_7_8_OFFSET
4347 This is an 8bit offset (of which only 7 bits are used) from the tiny
4350 BFD_RELOC_V850_TDA_7_7_OFFSET
4352 This is a 7 bit offset from the tiny data area pointer.
4354 BFD_RELOC_V850_TDA_16_16_OFFSET
4356 This is a 16 bit offset from the tiny data area pointer.
4359 BFD_RELOC_V850_TDA_4_5_OFFSET
4361 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4364 BFD_RELOC_V850_TDA_4_4_OFFSET
4366 This is a 4 bit offset from the tiny data area pointer.
4368 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4370 This is a 16 bit offset from the short data area pointer, with the
4371 bits placed non-contiguously in the instruction.
4373 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4375 This is a 16 bit offset from the zero data area pointer, with the
4376 bits placed non-contiguously in the instruction.
4378 BFD_RELOC_V850_CALLT_6_7_OFFSET
4380 This is a 6 bit offset from the call table base pointer.
4382 BFD_RELOC_V850_CALLT_16_16_OFFSET
4384 This is a 16 bit offset from the call table base pointer.
4386 BFD_RELOC_V850_LONGCALL
4388 Used for relaxing indirect function calls.
4390 BFD_RELOC_V850_LONGJUMP
4392 Used for relaxing indirect jumps.
4394 BFD_RELOC_V850_ALIGN
4396 Used to maintain alignment whilst relaxing.
4398 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4400 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4403 BFD_RELOC_V850_16_PCREL
4405 This is a 16-bit reloc.
4407 BFD_RELOC_V850_17_PCREL
4409 This is a 17-bit reloc.
4413 This is a 23-bit reloc.
4415 BFD_RELOC_V850_32_PCREL
4417 This is a 32-bit reloc.
4419 BFD_RELOC_V850_32_ABS
4421 This is a 32-bit reloc.
4423 BFD_RELOC_V850_16_SPLIT_OFFSET
4425 This is a 16-bit reloc.
4427 BFD_RELOC_V850_16_S1
4429 This is a 16-bit reloc.
4431 BFD_RELOC_V850_LO16_S1
4433 Low 16 bits. 16 bit shifted by 1.
4435 BFD_RELOC_V850_CALLT_15_16_OFFSET
4437 This is a 16 bit offset from the call table base pointer.
4439 BFD_RELOC_V850_32_GOTPCREL
4443 BFD_RELOC_V850_16_GOT
4447 BFD_RELOC_V850_32_GOT
4451 BFD_RELOC_V850_22_PLT_PCREL
4455 BFD_RELOC_V850_32_PLT_PCREL
4463 BFD_RELOC_V850_GLOB_DAT
4467 BFD_RELOC_V850_JMP_SLOT
4471 BFD_RELOC_V850_RELATIVE
4475 BFD_RELOC_V850_16_GOTOFF
4479 BFD_RELOC_V850_32_GOTOFF
4494 This is a 8bit DP reloc for the tms320c30, where the most
4495 significant 8 bits of a 24 bit word are placed into the least
4496 significant 8 bits of the opcode.
4499 BFD_RELOC_TIC54X_PARTLS7
4501 This is a 7bit reloc for the tms320c54x, where the least
4502 significant 7 bits of a 16 bit word are placed into the least
4503 significant 7 bits of the opcode.
4506 BFD_RELOC_TIC54X_PARTMS9
4508 This is a 9bit DP reloc for the tms320c54x, where the most
4509 significant 9 bits of a 16 bit word are placed into the least
4510 significant 9 bits of the opcode.
4515 This is an extended address 23-bit reloc for the tms320c54x.
4518 BFD_RELOC_TIC54X_16_OF_23
4520 This is a 16-bit reloc for the tms320c54x, where the least
4521 significant 16 bits of a 23-bit extended address are placed into
4525 BFD_RELOC_TIC54X_MS7_OF_23
4527 This is a reloc for the tms320c54x, where the most
4528 significant 7 bits of a 23-bit extended address are placed into
4532 BFD_RELOC_C6000_PCR_S21
4534 BFD_RELOC_C6000_PCR_S12
4536 BFD_RELOC_C6000_PCR_S10
4538 BFD_RELOC_C6000_PCR_S7
4540 BFD_RELOC_C6000_ABS_S16
4542 BFD_RELOC_C6000_ABS_L16
4544 BFD_RELOC_C6000_ABS_H16
4546 BFD_RELOC_C6000_SBR_U15_B
4548 BFD_RELOC_C6000_SBR_U15_H
4550 BFD_RELOC_C6000_SBR_U15_W
4552 BFD_RELOC_C6000_SBR_S16
4554 BFD_RELOC_C6000_SBR_L16_B
4556 BFD_RELOC_C6000_SBR_L16_H
4558 BFD_RELOC_C6000_SBR_L16_W
4560 BFD_RELOC_C6000_SBR_H16_B
4562 BFD_RELOC_C6000_SBR_H16_H
4564 BFD_RELOC_C6000_SBR_H16_W
4566 BFD_RELOC_C6000_SBR_GOT_U15_W
4568 BFD_RELOC_C6000_SBR_GOT_L16_W
4570 BFD_RELOC_C6000_SBR_GOT_H16_W
4572 BFD_RELOC_C6000_DSBT_INDEX
4574 BFD_RELOC_C6000_PREL31
4576 BFD_RELOC_C6000_COPY
4578 BFD_RELOC_C6000_JUMP_SLOT
4580 BFD_RELOC_C6000_EHTYPE
4582 BFD_RELOC_C6000_PCR_H16
4584 BFD_RELOC_C6000_PCR_L16
4586 BFD_RELOC_C6000_ALIGN
4588 BFD_RELOC_C6000_FPHEAD
4590 BFD_RELOC_C6000_NOCMP
4592 TMS320C6000 relocations.
4597 This is a 48 bit reloc for the FR30 that stores 32 bits.
4601 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4604 BFD_RELOC_FR30_6_IN_4
4606 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4609 BFD_RELOC_FR30_8_IN_8
4611 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4614 BFD_RELOC_FR30_9_IN_8
4616 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4619 BFD_RELOC_FR30_10_IN_8
4621 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4624 BFD_RELOC_FR30_9_PCREL
4626 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4627 short offset into 8 bits.
4629 BFD_RELOC_FR30_12_PCREL
4631 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4632 short offset into 11 bits.
4635 BFD_RELOC_MCORE_PCREL_IMM8BY4
4637 BFD_RELOC_MCORE_PCREL_IMM11BY2
4639 BFD_RELOC_MCORE_PCREL_IMM4BY2
4641 BFD_RELOC_MCORE_PCREL_32
4643 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4647 Motorola Mcore relocations.
4656 BFD_RELOC_MEP_PCREL8A2
4658 BFD_RELOC_MEP_PCREL12A2
4660 BFD_RELOC_MEP_PCREL17A2
4662 BFD_RELOC_MEP_PCREL24A2
4664 BFD_RELOC_MEP_PCABS24A2
4676 BFD_RELOC_MEP_TPREL7
4678 BFD_RELOC_MEP_TPREL7A2
4680 BFD_RELOC_MEP_TPREL7A4
4682 BFD_RELOC_MEP_UIMM24
4684 BFD_RELOC_MEP_ADDR24A4
4686 BFD_RELOC_MEP_GNU_VTINHERIT
4688 BFD_RELOC_MEP_GNU_VTENTRY
4690 Toshiba Media Processor Relocations.
4694 BFD_RELOC_METAG_HIADDR16
4696 BFD_RELOC_METAG_LOADDR16
4698 BFD_RELOC_METAG_RELBRANCH
4700 BFD_RELOC_METAG_GETSETOFF
4702 BFD_RELOC_METAG_HIOG
4704 BFD_RELOC_METAG_LOOG
4706 BFD_RELOC_METAG_REL8
4708 BFD_RELOC_METAG_REL16
4710 BFD_RELOC_METAG_HI16_GOTOFF
4712 BFD_RELOC_METAG_LO16_GOTOFF
4714 BFD_RELOC_METAG_GETSET_GOTOFF
4716 BFD_RELOC_METAG_GETSET_GOT
4718 BFD_RELOC_METAG_HI16_GOTPC
4720 BFD_RELOC_METAG_LO16_GOTPC
4722 BFD_RELOC_METAG_HI16_PLT
4724 BFD_RELOC_METAG_LO16_PLT
4726 BFD_RELOC_METAG_RELBRANCH_PLT
4728 BFD_RELOC_METAG_GOTOFF
4732 BFD_RELOC_METAG_COPY
4734 BFD_RELOC_METAG_JMP_SLOT
4736 BFD_RELOC_METAG_RELATIVE
4738 BFD_RELOC_METAG_GLOB_DAT
4740 BFD_RELOC_METAG_TLS_GD
4742 BFD_RELOC_METAG_TLS_LDM
4744 BFD_RELOC_METAG_TLS_LDO_HI16
4746 BFD_RELOC_METAG_TLS_LDO_LO16
4748 BFD_RELOC_METAG_TLS_LDO
4750 BFD_RELOC_METAG_TLS_IE
4752 BFD_RELOC_METAG_TLS_IENONPIC
4754 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4756 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4758 BFD_RELOC_METAG_TLS_TPOFF
4760 BFD_RELOC_METAG_TLS_DTPMOD
4762 BFD_RELOC_METAG_TLS_DTPOFF
4764 BFD_RELOC_METAG_TLS_LE
4766 BFD_RELOC_METAG_TLS_LE_HI16
4768 BFD_RELOC_METAG_TLS_LE_LO16
4770 Imagination Technologies Meta relocations.
4775 BFD_RELOC_MMIX_GETA_1
4777 BFD_RELOC_MMIX_GETA_2
4779 BFD_RELOC_MMIX_GETA_3
4781 These are relocations for the GETA instruction.
4783 BFD_RELOC_MMIX_CBRANCH
4785 BFD_RELOC_MMIX_CBRANCH_J
4787 BFD_RELOC_MMIX_CBRANCH_1
4789 BFD_RELOC_MMIX_CBRANCH_2
4791 BFD_RELOC_MMIX_CBRANCH_3
4793 These are relocations for a conditional branch instruction.
4795 BFD_RELOC_MMIX_PUSHJ
4797 BFD_RELOC_MMIX_PUSHJ_1
4799 BFD_RELOC_MMIX_PUSHJ_2
4801 BFD_RELOC_MMIX_PUSHJ_3
4803 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4805 These are relocations for the PUSHJ instruction.
4809 BFD_RELOC_MMIX_JMP_1
4811 BFD_RELOC_MMIX_JMP_2
4813 BFD_RELOC_MMIX_JMP_3
4815 These are relocations for the JMP instruction.
4817 BFD_RELOC_MMIX_ADDR19
4819 This is a relocation for a relative address as in a GETA instruction or
4822 BFD_RELOC_MMIX_ADDR27
4824 This is a relocation for a relative address as in a JMP instruction.
4826 BFD_RELOC_MMIX_REG_OR_BYTE
4828 This is a relocation for an instruction field that may be a general
4829 register or a value 0..255.
4833 This is a relocation for an instruction field that may be a general
4836 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4838 This is a relocation for two instruction fields holding a register and
4839 an offset, the equivalent of the relocation.
4841 BFD_RELOC_MMIX_LOCAL
4843 This relocation is an assertion that the expression is not allocated as
4844 a global register. It does not modify contents.
4847 BFD_RELOC_AVR_7_PCREL
4849 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4850 short offset into 7 bits.
4852 BFD_RELOC_AVR_13_PCREL
4854 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4855 short offset into 12 bits.
4859 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4860 program memory address) into 16 bits.
4862 BFD_RELOC_AVR_LO8_LDI
4864 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4865 data memory address) into 8 bit immediate value of LDI insn.
4867 BFD_RELOC_AVR_HI8_LDI
4869 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4870 of data memory address) into 8 bit immediate value of LDI insn.
4872 BFD_RELOC_AVR_HH8_LDI
4874 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4875 of program memory address) into 8 bit immediate value of LDI insn.
4877 BFD_RELOC_AVR_MS8_LDI
4879 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4880 of 32 bit value) into 8 bit immediate value of LDI insn.
4882 BFD_RELOC_AVR_LO8_LDI_NEG
4884 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4885 (usually data memory address) into 8 bit immediate value of SUBI insn.
4887 BFD_RELOC_AVR_HI8_LDI_NEG
4889 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4890 (high 8 bit of data memory address) into 8 bit immediate value of
4893 BFD_RELOC_AVR_HH8_LDI_NEG
4895 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4896 (most high 8 bit of program memory address) into 8 bit immediate value
4897 of LDI or SUBI insn.
4899 BFD_RELOC_AVR_MS8_LDI_NEG
4901 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4902 of 32 bit value) into 8 bit immediate value of LDI insn.
4904 BFD_RELOC_AVR_LO8_LDI_PM
4906 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4907 command address) into 8 bit immediate value of LDI insn.
4909 BFD_RELOC_AVR_LO8_LDI_GS
4911 This is a 16 bit reloc for the AVR that stores 8 bit value
4912 (command address) into 8 bit immediate value of LDI insn. If the address
4913 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4916 BFD_RELOC_AVR_HI8_LDI_PM
4918 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4919 of command address) into 8 bit immediate value of LDI insn.
4921 BFD_RELOC_AVR_HI8_LDI_GS
4923 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4924 of command address) into 8 bit immediate value of LDI insn. If the address
4925 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4928 BFD_RELOC_AVR_HH8_LDI_PM
4930 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4931 of command address) into 8 bit immediate value of LDI insn.
4933 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4935 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4936 (usually command address) into 8 bit immediate value of SUBI insn.
4938 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4940 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4941 (high 8 bit of 16 bit command address) into 8 bit immediate value
4944 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4946 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4947 (high 6 bit of 22 bit command address) into 8 bit immediate
4952 This is a 32 bit reloc for the AVR that stores 23 bit value
4957 This is a 16 bit reloc for the AVR that stores all needed bits
4958 for absolute addressing with ldi with overflow check to linktime
4962 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4965 BFD_RELOC_AVR_6_ADIW
4967 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4972 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4973 in .byte lo8(symbol)
4977 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4978 in .byte hi8(symbol)
4982 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4983 in .byte hlo8(symbol)
4987 BFD_RELOC_AVR_DIFF16
4989 BFD_RELOC_AVR_DIFF32
4991 AVR relocations to mark the difference of two local symbols.
4992 These are only needed to support linker relaxation and can be ignored
4993 when not relaxing. The field is set to the value of the difference
4994 assuming no relaxation. The relocation encodes the position of the
4995 second symbol so the linker can determine whether to adjust the field
4998 BFD_RELOC_AVR_LDS_STS_16
5000 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5001 lds and sts instructions supported only tiny core.
5005 This is a 6 bit reloc for the AVR that stores an I/O register
5006 number for the IN and OUT instructions
5010 This is a 5 bit reloc for the AVR that stores an I/O register
5011 number for the SBIC, SBIS, SBI and CBI instructions
5015 BFD_RELOC_RL78_NEG16
5017 BFD_RELOC_RL78_NEG24
5019 BFD_RELOC_RL78_NEG32
5021 BFD_RELOC_RL78_16_OP
5023 BFD_RELOC_RL78_24_OP
5025 BFD_RELOC_RL78_32_OP
5033 BFD_RELOC_RL78_DIR3U_PCREL
5037 BFD_RELOC_RL78_GPRELB
5039 BFD_RELOC_RL78_GPRELW
5041 BFD_RELOC_RL78_GPRELL
5045 BFD_RELOC_RL78_OP_SUBTRACT
5047 BFD_RELOC_RL78_OP_NEG
5049 BFD_RELOC_RL78_OP_AND
5051 BFD_RELOC_RL78_OP_SHRA
5055 BFD_RELOC_RL78_ABS16
5057 BFD_RELOC_RL78_ABS16_REV
5059 BFD_RELOC_RL78_ABS32
5061 BFD_RELOC_RL78_ABS32_REV
5063 BFD_RELOC_RL78_ABS16U
5065 BFD_RELOC_RL78_ABS16UW
5067 BFD_RELOC_RL78_ABS16UL
5069 BFD_RELOC_RL78_RELAX
5079 BFD_RELOC_RL78_SADDR
5081 Renesas RL78 Relocations.
5104 BFD_RELOC_RX_DIR3U_PCREL
5116 BFD_RELOC_RX_OP_SUBTRACT
5124 BFD_RELOC_RX_ABS16_REV
5128 BFD_RELOC_RX_ABS32_REV
5132 BFD_RELOC_RX_ABS16UW
5134 BFD_RELOC_RX_ABS16UL
5138 Renesas RX Relocations.
5151 32 bit PC relative PLT address.
5155 Copy symbol at runtime.
5157 BFD_RELOC_390_GLOB_DAT
5161 BFD_RELOC_390_JMP_SLOT
5165 BFD_RELOC_390_RELATIVE
5167 Adjust by program base.
5171 32 bit PC relative offset to GOT.
5177 BFD_RELOC_390_PC12DBL
5179 PC relative 12 bit shifted by 1.
5181 BFD_RELOC_390_PLT12DBL
5183 12 bit PC rel. PLT shifted by 1.
5185 BFD_RELOC_390_PC16DBL
5187 PC relative 16 bit shifted by 1.
5189 BFD_RELOC_390_PLT16DBL
5191 16 bit PC rel. PLT shifted by 1.
5193 BFD_RELOC_390_PC24DBL
5195 PC relative 24 bit shifted by 1.
5197 BFD_RELOC_390_PLT24DBL
5199 24 bit PC rel. PLT shifted by 1.
5201 BFD_RELOC_390_PC32DBL
5203 PC relative 32 bit shifted by 1.
5205 BFD_RELOC_390_PLT32DBL
5207 32 bit PC rel. PLT shifted by 1.
5209 BFD_RELOC_390_GOTPCDBL
5211 32 bit PC rel. GOT shifted by 1.
5219 64 bit PC relative PLT address.
5221 BFD_RELOC_390_GOTENT
5223 32 bit rel. offset to GOT entry.
5225 BFD_RELOC_390_GOTOFF64
5227 64 bit offset to GOT.
5229 BFD_RELOC_390_GOTPLT12
5231 12-bit offset to symbol-entry within GOT, with PLT handling.
5233 BFD_RELOC_390_GOTPLT16
5235 16-bit offset to symbol-entry within GOT, with PLT handling.
5237 BFD_RELOC_390_GOTPLT32
5239 32-bit offset to symbol-entry within GOT, with PLT handling.
5241 BFD_RELOC_390_GOTPLT64
5243 64-bit offset to symbol-entry within GOT, with PLT handling.
5245 BFD_RELOC_390_GOTPLTENT
5247 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5249 BFD_RELOC_390_PLTOFF16
5251 16-bit rel. offset from the GOT to a PLT entry.
5253 BFD_RELOC_390_PLTOFF32
5255 32-bit rel. offset from the GOT to a PLT entry.
5257 BFD_RELOC_390_PLTOFF64
5259 64-bit rel. offset from the GOT to a PLT entry.
5262 BFD_RELOC_390_TLS_LOAD
5264 BFD_RELOC_390_TLS_GDCALL
5266 BFD_RELOC_390_TLS_LDCALL
5268 BFD_RELOC_390_TLS_GD32
5270 BFD_RELOC_390_TLS_GD64
5272 BFD_RELOC_390_TLS_GOTIE12
5274 BFD_RELOC_390_TLS_GOTIE32
5276 BFD_RELOC_390_TLS_GOTIE64
5278 BFD_RELOC_390_TLS_LDM32
5280 BFD_RELOC_390_TLS_LDM64
5282 BFD_RELOC_390_TLS_IE32
5284 BFD_RELOC_390_TLS_IE64
5286 BFD_RELOC_390_TLS_IEENT
5288 BFD_RELOC_390_TLS_LE32
5290 BFD_RELOC_390_TLS_LE64
5292 BFD_RELOC_390_TLS_LDO32
5294 BFD_RELOC_390_TLS_LDO64
5296 BFD_RELOC_390_TLS_DTPMOD
5298 BFD_RELOC_390_TLS_DTPOFF
5300 BFD_RELOC_390_TLS_TPOFF
5302 s390 tls relocations.
5309 BFD_RELOC_390_GOTPLT20
5311 BFD_RELOC_390_TLS_GOTIE20
5313 Long displacement extension.
5316 BFD_RELOC_390_IRELATIVE
5318 STT_GNU_IFUNC relocation.
5321 BFD_RELOC_SCORE_GPREL15
5324 Low 16 bit for load/store
5326 BFD_RELOC_SCORE_DUMMY2
5330 This is a 24-bit reloc with the right 1 bit assumed to be 0
5332 BFD_RELOC_SCORE_BRANCH
5334 This is a 19-bit reloc with the right 1 bit assumed to be 0
5336 BFD_RELOC_SCORE_IMM30
5338 This is a 32-bit reloc for 48-bit instructions.
5340 BFD_RELOC_SCORE_IMM32
5342 This is a 32-bit reloc for 48-bit instructions.
5344 BFD_RELOC_SCORE16_JMP
5346 This is a 11-bit reloc with the right 1 bit assumed to be 0
5348 BFD_RELOC_SCORE16_BRANCH
5350 This is a 8-bit reloc with the right 1 bit assumed to be 0
5352 BFD_RELOC_SCORE_BCMP
5354 This is a 9-bit reloc with the right 1 bit assumed to be 0
5356 BFD_RELOC_SCORE_GOT15
5358 BFD_RELOC_SCORE_GOT_LO16
5360 BFD_RELOC_SCORE_CALL15
5362 BFD_RELOC_SCORE_DUMMY_HI16
5364 Undocumented Score relocs
5369 Scenix IP2K - 9-bit register number / data address
5373 Scenix IP2K - 4-bit register/data bank number
5375 BFD_RELOC_IP2K_ADDR16CJP
5377 Scenix IP2K - low 13 bits of instruction word address
5379 BFD_RELOC_IP2K_PAGE3
5381 Scenix IP2K - high 3 bits of instruction word address
5383 BFD_RELOC_IP2K_LO8DATA
5385 BFD_RELOC_IP2K_HI8DATA
5387 BFD_RELOC_IP2K_EX8DATA
5389 Scenix IP2K - ext/low/high 8 bits of data address
5391 BFD_RELOC_IP2K_LO8INSN
5393 BFD_RELOC_IP2K_HI8INSN
5395 Scenix IP2K - low/high 8 bits of instruction word address
5397 BFD_RELOC_IP2K_PC_SKIP
5399 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5403 Scenix IP2K - 16 bit word address in text section.
5405 BFD_RELOC_IP2K_FR_OFFSET
5407 Scenix IP2K - 7-bit sp or dp offset
5409 BFD_RELOC_VPE4KMATH_DATA
5411 BFD_RELOC_VPE4KMATH_INSN
5413 Scenix VPE4K coprocessor - data/insn-space addressing
5416 BFD_RELOC_VTABLE_INHERIT
5418 BFD_RELOC_VTABLE_ENTRY
5420 These two relocations are used by the linker to determine which of
5421 the entries in a C++ virtual function table are actually used. When
5422 the --gc-sections option is given, the linker will zero out the entries
5423 that are not used, so that the code for those functions need not be
5424 included in the output.
5426 VTABLE_INHERIT is a zero-space relocation used to describe to the
5427 linker the inheritance tree of a C++ virtual function table. The
5428 relocation's symbol should be the parent class' vtable, and the
5429 relocation should be located at the child vtable.
5431 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5432 virtual function table entry. The reloc's symbol should refer to the
5433 table of the class mentioned in the code. Off of that base, an offset
5434 describes the entry that is being used. For Rela hosts, this offset
5435 is stored in the reloc's addend. For Rel hosts, we are forced to put
5436 this offset in the reloc's section offset.
5439 BFD_RELOC_IA64_IMM14
5441 BFD_RELOC_IA64_IMM22
5443 BFD_RELOC_IA64_IMM64
5445 BFD_RELOC_IA64_DIR32MSB
5447 BFD_RELOC_IA64_DIR32LSB
5449 BFD_RELOC_IA64_DIR64MSB
5451 BFD_RELOC_IA64_DIR64LSB
5453 BFD_RELOC_IA64_GPREL22
5455 BFD_RELOC_IA64_GPREL64I
5457 BFD_RELOC_IA64_GPREL32MSB
5459 BFD_RELOC_IA64_GPREL32LSB
5461 BFD_RELOC_IA64_GPREL64MSB
5463 BFD_RELOC_IA64_GPREL64LSB
5465 BFD_RELOC_IA64_LTOFF22
5467 BFD_RELOC_IA64_LTOFF64I
5469 BFD_RELOC_IA64_PLTOFF22
5471 BFD_RELOC_IA64_PLTOFF64I
5473 BFD_RELOC_IA64_PLTOFF64MSB
5475 BFD_RELOC_IA64_PLTOFF64LSB
5477 BFD_RELOC_IA64_FPTR64I
5479 BFD_RELOC_IA64_FPTR32MSB
5481 BFD_RELOC_IA64_FPTR32LSB
5483 BFD_RELOC_IA64_FPTR64MSB
5485 BFD_RELOC_IA64_FPTR64LSB
5487 BFD_RELOC_IA64_PCREL21B
5489 BFD_RELOC_IA64_PCREL21BI
5491 BFD_RELOC_IA64_PCREL21M
5493 BFD_RELOC_IA64_PCREL21F
5495 BFD_RELOC_IA64_PCREL22
5497 BFD_RELOC_IA64_PCREL60B
5499 BFD_RELOC_IA64_PCREL64I
5501 BFD_RELOC_IA64_PCREL32MSB
5503 BFD_RELOC_IA64_PCREL32LSB
5505 BFD_RELOC_IA64_PCREL64MSB
5507 BFD_RELOC_IA64_PCREL64LSB
5509 BFD_RELOC_IA64_LTOFF_FPTR22
5511 BFD_RELOC_IA64_LTOFF_FPTR64I
5513 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5515 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5517 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5519 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5521 BFD_RELOC_IA64_SEGREL32MSB
5523 BFD_RELOC_IA64_SEGREL32LSB
5525 BFD_RELOC_IA64_SEGREL64MSB
5527 BFD_RELOC_IA64_SEGREL64LSB
5529 BFD_RELOC_IA64_SECREL32MSB
5531 BFD_RELOC_IA64_SECREL32LSB
5533 BFD_RELOC_IA64_SECREL64MSB
5535 BFD_RELOC_IA64_SECREL64LSB
5537 BFD_RELOC_IA64_REL32MSB
5539 BFD_RELOC_IA64_REL32LSB
5541 BFD_RELOC_IA64_REL64MSB
5543 BFD_RELOC_IA64_REL64LSB
5545 BFD_RELOC_IA64_LTV32MSB
5547 BFD_RELOC_IA64_LTV32LSB
5549 BFD_RELOC_IA64_LTV64MSB
5551 BFD_RELOC_IA64_LTV64LSB
5553 BFD_RELOC_IA64_IPLTMSB
5555 BFD_RELOC_IA64_IPLTLSB
5559 BFD_RELOC_IA64_LTOFF22X
5561 BFD_RELOC_IA64_LDXMOV
5563 BFD_RELOC_IA64_TPREL14
5565 BFD_RELOC_IA64_TPREL22
5567 BFD_RELOC_IA64_TPREL64I
5569 BFD_RELOC_IA64_TPREL64MSB
5571 BFD_RELOC_IA64_TPREL64LSB
5573 BFD_RELOC_IA64_LTOFF_TPREL22
5575 BFD_RELOC_IA64_DTPMOD64MSB
5577 BFD_RELOC_IA64_DTPMOD64LSB
5579 BFD_RELOC_IA64_LTOFF_DTPMOD22
5581 BFD_RELOC_IA64_DTPREL14
5583 BFD_RELOC_IA64_DTPREL22
5585 BFD_RELOC_IA64_DTPREL64I
5587 BFD_RELOC_IA64_DTPREL32MSB
5589 BFD_RELOC_IA64_DTPREL32LSB
5591 BFD_RELOC_IA64_DTPREL64MSB
5593 BFD_RELOC_IA64_DTPREL64LSB
5595 BFD_RELOC_IA64_LTOFF_DTPREL22
5597 Intel IA64 Relocations.
5600 BFD_RELOC_M68HC11_HI8
5602 Motorola 68HC11 reloc.
5603 This is the 8 bit high part of an absolute address.
5605 BFD_RELOC_M68HC11_LO8
5607 Motorola 68HC11 reloc.
5608 This is the 8 bit low part of an absolute address.
5610 BFD_RELOC_M68HC11_3B
5612 Motorola 68HC11 reloc.
5613 This is the 3 bit of a value.
5615 BFD_RELOC_M68HC11_RL_JUMP
5617 Motorola 68HC11 reloc.
5618 This reloc marks the beginning of a jump/call instruction.
5619 It is used for linker relaxation to correctly identify beginning
5620 of instruction and change some branches to use PC-relative
5623 BFD_RELOC_M68HC11_RL_GROUP
5625 Motorola 68HC11 reloc.
5626 This reloc marks a group of several instructions that gcc generates
5627 and for which the linker relaxation pass can modify and/or remove
5630 BFD_RELOC_M68HC11_LO16
5632 Motorola 68HC11 reloc.
5633 This is the 16-bit lower part of an address. It is used for 'call'
5634 instruction to specify the symbol address without any special
5635 transformation (due to memory bank window).
5637 BFD_RELOC_M68HC11_PAGE
5639 Motorola 68HC11 reloc.
5640 This is a 8-bit reloc that specifies the page number of an address.
5641 It is used by 'call' instruction to specify the page number of
5644 BFD_RELOC_M68HC11_24
5646 Motorola 68HC11 reloc.
5647 This is a 24-bit reloc that represents the address with a 16-bit
5648 value and a 8-bit page number. The symbol address is transformed
5649 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5651 BFD_RELOC_M68HC12_5B
5653 Motorola 68HC12 reloc.
5654 This is the 5 bits of a value.
5656 BFD_RELOC_XGATE_RL_JUMP
5658 Freescale XGATE reloc.
5659 This reloc marks the beginning of a bra/jal instruction.
5661 BFD_RELOC_XGATE_RL_GROUP
5663 Freescale XGATE reloc.
5664 This reloc marks a group of several instructions that gcc generates
5665 and for which the linker relaxation pass can modify and/or remove
5668 BFD_RELOC_XGATE_LO16
5670 Freescale XGATE reloc.
5671 This is the 16-bit lower part of an address. It is used for the '16-bit'
5674 BFD_RELOC_XGATE_GPAGE
5676 Freescale XGATE reloc.
5680 Freescale XGATE reloc.
5682 BFD_RELOC_XGATE_PCREL_9
5684 Freescale XGATE reloc.
5685 This is a 9-bit pc-relative reloc.
5687 BFD_RELOC_XGATE_PCREL_10
5689 Freescale XGATE reloc.
5690 This is a 10-bit pc-relative reloc.
5692 BFD_RELOC_XGATE_IMM8_LO
5694 Freescale XGATE reloc.
5695 This is the 16-bit lower part of an address. It is used for the '16-bit'
5698 BFD_RELOC_XGATE_IMM8_HI
5700 Freescale XGATE reloc.
5701 This is the 16-bit higher part of an address. It is used for the '16-bit'
5704 BFD_RELOC_XGATE_IMM3
5706 Freescale XGATE reloc.
5707 This is a 3-bit pc-relative reloc.
5709 BFD_RELOC_XGATE_IMM4
5711 Freescale XGATE reloc.
5712 This is a 4-bit pc-relative reloc.
5714 BFD_RELOC_XGATE_IMM5
5716 Freescale XGATE reloc.
5717 This is a 5-bit pc-relative reloc.
5719 BFD_RELOC_M68HC12_9B
5721 Motorola 68HC12 reloc.
5722 This is the 9 bits of a value.
5724 BFD_RELOC_M68HC12_16B
5726 Motorola 68HC12 reloc.
5727 This is the 16 bits of a value.
5729 BFD_RELOC_M68HC12_9_PCREL
5731 Motorola 68HC12/XGATE reloc.
5732 This is a PCREL9 branch.
5734 BFD_RELOC_M68HC12_10_PCREL
5736 Motorola 68HC12/XGATE reloc.
5737 This is a PCREL10 branch.
5739 BFD_RELOC_M68HC12_LO8XG
5741 Motorola 68HC12/XGATE reloc.
5742 This is the 8 bit low part of an absolute address and immediately precedes
5743 a matching HI8XG part.
5745 BFD_RELOC_M68HC12_HI8XG
5747 Motorola 68HC12/XGATE reloc.
5748 This is the 8 bit high part of an absolute address and immediately follows
5749 a matching LO8XG part.
5753 BFD_RELOC_16C_NUM08_C
5757 BFD_RELOC_16C_NUM16_C
5761 BFD_RELOC_16C_NUM32_C
5763 BFD_RELOC_16C_DISP04
5765 BFD_RELOC_16C_DISP04_C
5767 BFD_RELOC_16C_DISP08
5769 BFD_RELOC_16C_DISP08_C
5771 BFD_RELOC_16C_DISP16
5773 BFD_RELOC_16C_DISP16_C
5775 BFD_RELOC_16C_DISP24
5777 BFD_RELOC_16C_DISP24_C
5779 BFD_RELOC_16C_DISP24a
5781 BFD_RELOC_16C_DISP24a_C
5785 BFD_RELOC_16C_REG04_C
5787 BFD_RELOC_16C_REG04a
5789 BFD_RELOC_16C_REG04a_C
5793 BFD_RELOC_16C_REG14_C
5797 BFD_RELOC_16C_REG16_C
5801 BFD_RELOC_16C_REG20_C
5805 BFD_RELOC_16C_ABS20_C
5809 BFD_RELOC_16C_ABS24_C
5813 BFD_RELOC_16C_IMM04_C
5817 BFD_RELOC_16C_IMM16_C
5821 BFD_RELOC_16C_IMM20_C
5825 BFD_RELOC_16C_IMM24_C
5829 BFD_RELOC_16C_IMM32_C
5831 NS CR16C Relocations.
5836 BFD_RELOC_CR16_NUM16
5838 BFD_RELOC_CR16_NUM32
5840 BFD_RELOC_CR16_NUM32a
5842 BFD_RELOC_CR16_REGREL0
5844 BFD_RELOC_CR16_REGREL4
5846 BFD_RELOC_CR16_REGREL4a
5848 BFD_RELOC_CR16_REGREL14
5850 BFD_RELOC_CR16_REGREL14a
5852 BFD_RELOC_CR16_REGREL16
5854 BFD_RELOC_CR16_REGREL20
5856 BFD_RELOC_CR16_REGREL20a
5858 BFD_RELOC_CR16_ABS20
5860 BFD_RELOC_CR16_ABS24
5866 BFD_RELOC_CR16_IMM16
5868 BFD_RELOC_CR16_IMM20
5870 BFD_RELOC_CR16_IMM24
5872 BFD_RELOC_CR16_IMM32
5874 BFD_RELOC_CR16_IMM32a
5876 BFD_RELOC_CR16_DISP4
5878 BFD_RELOC_CR16_DISP8
5880 BFD_RELOC_CR16_DISP16
5882 BFD_RELOC_CR16_DISP20
5884 BFD_RELOC_CR16_DISP24
5886 BFD_RELOC_CR16_DISP24a
5888 BFD_RELOC_CR16_SWITCH8
5890 BFD_RELOC_CR16_SWITCH16
5892 BFD_RELOC_CR16_SWITCH32
5894 BFD_RELOC_CR16_GOT_REGREL20
5896 BFD_RELOC_CR16_GOTC_REGREL20
5898 BFD_RELOC_CR16_GLOB_DAT
5900 NS CR16 Relocations.
5907 BFD_RELOC_CRX_REL8_CMP
5915 BFD_RELOC_CRX_REGREL12
5917 BFD_RELOC_CRX_REGREL22
5919 BFD_RELOC_CRX_REGREL28
5921 BFD_RELOC_CRX_REGREL32
5937 BFD_RELOC_CRX_SWITCH8
5939 BFD_RELOC_CRX_SWITCH16
5941 BFD_RELOC_CRX_SWITCH32
5946 BFD_RELOC_CRIS_BDISP8
5948 BFD_RELOC_CRIS_UNSIGNED_5
5950 BFD_RELOC_CRIS_SIGNED_6
5952 BFD_RELOC_CRIS_UNSIGNED_6
5954 BFD_RELOC_CRIS_SIGNED_8
5956 BFD_RELOC_CRIS_UNSIGNED_8
5958 BFD_RELOC_CRIS_SIGNED_16
5960 BFD_RELOC_CRIS_UNSIGNED_16
5962 BFD_RELOC_CRIS_LAPCQ_OFFSET
5964 BFD_RELOC_CRIS_UNSIGNED_4
5966 These relocs are only used within the CRIS assembler. They are not
5967 (at present) written to any object files.
5971 BFD_RELOC_CRIS_GLOB_DAT
5973 BFD_RELOC_CRIS_JUMP_SLOT
5975 BFD_RELOC_CRIS_RELATIVE
5977 Relocs used in ELF shared libraries for CRIS.
5979 BFD_RELOC_CRIS_32_GOT
5981 32-bit offset to symbol-entry within GOT.
5983 BFD_RELOC_CRIS_16_GOT
5985 16-bit offset to symbol-entry within GOT.
5987 BFD_RELOC_CRIS_32_GOTPLT
5989 32-bit offset to symbol-entry within GOT, with PLT handling.
5991 BFD_RELOC_CRIS_16_GOTPLT
5993 16-bit offset to symbol-entry within GOT, with PLT handling.
5995 BFD_RELOC_CRIS_32_GOTREL
5997 32-bit offset to symbol, relative to GOT.
5999 BFD_RELOC_CRIS_32_PLT_GOTREL
6001 32-bit offset to symbol with PLT entry, relative to GOT.
6003 BFD_RELOC_CRIS_32_PLT_PCREL
6005 32-bit offset to symbol with PLT entry, relative to this relocation.
6008 BFD_RELOC_CRIS_32_GOT_GD
6010 BFD_RELOC_CRIS_16_GOT_GD
6012 BFD_RELOC_CRIS_32_GD
6016 BFD_RELOC_CRIS_32_DTPREL
6018 BFD_RELOC_CRIS_16_DTPREL
6020 BFD_RELOC_CRIS_32_GOT_TPREL
6022 BFD_RELOC_CRIS_16_GOT_TPREL
6024 BFD_RELOC_CRIS_32_TPREL
6026 BFD_RELOC_CRIS_16_TPREL
6028 BFD_RELOC_CRIS_DTPMOD
6030 BFD_RELOC_CRIS_32_IE
6032 Relocs used in TLS code for CRIS.
6037 BFD_RELOC_860_GLOB_DAT
6039 BFD_RELOC_860_JUMP_SLOT
6041 BFD_RELOC_860_RELATIVE
6051 BFD_RELOC_860_SPLIT0
6055 BFD_RELOC_860_SPLIT1
6059 BFD_RELOC_860_SPLIT2
6063 BFD_RELOC_860_LOGOT0
6065 BFD_RELOC_860_SPGOT0
6067 BFD_RELOC_860_LOGOT1
6069 BFD_RELOC_860_SPGOT1
6071 BFD_RELOC_860_LOGOTOFF0
6073 BFD_RELOC_860_SPGOTOFF0
6075 BFD_RELOC_860_LOGOTOFF1
6077 BFD_RELOC_860_SPGOTOFF1
6079 BFD_RELOC_860_LOGOTOFF2
6081 BFD_RELOC_860_LOGOTOFF3
6085 BFD_RELOC_860_HIGHADJ
6089 BFD_RELOC_860_HAGOTOFF
6097 BFD_RELOC_860_HIGOTOFF
6099 Intel i860 Relocations.
6102 BFD_RELOC_OR1K_REL_26
6104 BFD_RELOC_OR1K_GOTPC_HI16
6106 BFD_RELOC_OR1K_GOTPC_LO16
6108 BFD_RELOC_OR1K_GOT16
6110 BFD_RELOC_OR1K_PLT26
6112 BFD_RELOC_OR1K_GOTOFF_HI16
6114 BFD_RELOC_OR1K_GOTOFF_LO16
6118 BFD_RELOC_OR1K_GLOB_DAT
6120 BFD_RELOC_OR1K_JMP_SLOT
6122 BFD_RELOC_OR1K_RELATIVE
6124 BFD_RELOC_OR1K_TLS_GD_HI16
6126 BFD_RELOC_OR1K_TLS_GD_LO16
6128 BFD_RELOC_OR1K_TLS_LDM_HI16
6130 BFD_RELOC_OR1K_TLS_LDM_LO16
6132 BFD_RELOC_OR1K_TLS_LDO_HI16
6134 BFD_RELOC_OR1K_TLS_LDO_LO16
6136 BFD_RELOC_OR1K_TLS_IE_HI16
6138 BFD_RELOC_OR1K_TLS_IE_LO16
6140 BFD_RELOC_OR1K_TLS_LE_HI16
6142 BFD_RELOC_OR1K_TLS_LE_LO16
6144 BFD_RELOC_OR1K_TLS_TPOFF
6146 BFD_RELOC_OR1K_TLS_DTPOFF
6148 BFD_RELOC_OR1K_TLS_DTPMOD
6150 OpenRISC 1000 Relocations.
6153 BFD_RELOC_H8_DIR16A8
6155 BFD_RELOC_H8_DIR16R8
6157 BFD_RELOC_H8_DIR24A8
6159 BFD_RELOC_H8_DIR24R8
6161 BFD_RELOC_H8_DIR32A16
6163 BFD_RELOC_H8_DISP32A16
6168 BFD_RELOC_XSTORMY16_REL_12
6170 BFD_RELOC_XSTORMY16_12
6172 BFD_RELOC_XSTORMY16_24
6174 BFD_RELOC_XSTORMY16_FPTR16
6176 Sony Xstormy16 Relocations.
6181 Self-describing complex relocations.
6193 Infineon Relocations.
6196 BFD_RELOC_VAX_GLOB_DAT
6198 BFD_RELOC_VAX_JMP_SLOT
6200 BFD_RELOC_VAX_RELATIVE
6202 Relocations used by VAX ELF.
6207 Morpho MT - 16 bit immediate relocation.
6211 Morpho MT - Hi 16 bits of an address.
6215 Morpho MT - Low 16 bits of an address.
6217 BFD_RELOC_MT_GNU_VTINHERIT
6219 Morpho MT - Used to tell the linker which vtable entries are used.
6221 BFD_RELOC_MT_GNU_VTENTRY
6223 Morpho MT - Used to tell the linker which vtable entries are used.
6225 BFD_RELOC_MT_PCINSN8
6227 Morpho MT - 8 bit immediate relocation.
6230 BFD_RELOC_MSP430_10_PCREL
6232 BFD_RELOC_MSP430_16_PCREL
6236 BFD_RELOC_MSP430_16_PCREL_BYTE
6238 BFD_RELOC_MSP430_16_BYTE
6240 BFD_RELOC_MSP430_2X_PCREL
6242 BFD_RELOC_MSP430_RL_PCREL
6244 BFD_RELOC_MSP430_ABS8
6246 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6248 BFD_RELOC_MSP430X_PCR20_EXT_DST
6250 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6252 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6254 BFD_RELOC_MSP430X_ABS20_EXT_DST
6256 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6258 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6260 BFD_RELOC_MSP430X_ABS20_ADR_DST
6262 BFD_RELOC_MSP430X_PCR16
6264 BFD_RELOC_MSP430X_PCR20_CALL
6266 BFD_RELOC_MSP430X_ABS16
6268 BFD_RELOC_MSP430_ABS_HI16
6270 BFD_RELOC_MSP430_PREL31
6272 BFD_RELOC_MSP430_SYM_DIFF
6274 msp430 specific relocation codes
6281 BFD_RELOC_NIOS2_CALL26
6283 BFD_RELOC_NIOS2_IMM5
6285 BFD_RELOC_NIOS2_CACHE_OPX
6287 BFD_RELOC_NIOS2_IMM6
6289 BFD_RELOC_NIOS2_IMM8
6291 BFD_RELOC_NIOS2_HI16
6293 BFD_RELOC_NIOS2_LO16
6295 BFD_RELOC_NIOS2_HIADJ16
6297 BFD_RELOC_NIOS2_GPREL
6299 BFD_RELOC_NIOS2_UJMP
6301 BFD_RELOC_NIOS2_CJMP
6303 BFD_RELOC_NIOS2_CALLR
6305 BFD_RELOC_NIOS2_ALIGN
6307 BFD_RELOC_NIOS2_GOT16
6309 BFD_RELOC_NIOS2_CALL16
6311 BFD_RELOC_NIOS2_GOTOFF_LO
6313 BFD_RELOC_NIOS2_GOTOFF_HA
6315 BFD_RELOC_NIOS2_PCREL_LO
6317 BFD_RELOC_NIOS2_PCREL_HA
6319 BFD_RELOC_NIOS2_TLS_GD16
6321 BFD_RELOC_NIOS2_TLS_LDM16
6323 BFD_RELOC_NIOS2_TLS_LDO16
6325 BFD_RELOC_NIOS2_TLS_IE16
6327 BFD_RELOC_NIOS2_TLS_LE16
6329 BFD_RELOC_NIOS2_TLS_DTPMOD
6331 BFD_RELOC_NIOS2_TLS_DTPREL
6333 BFD_RELOC_NIOS2_TLS_TPREL
6335 BFD_RELOC_NIOS2_COPY
6337 BFD_RELOC_NIOS2_GLOB_DAT
6339 BFD_RELOC_NIOS2_JUMP_SLOT
6341 BFD_RELOC_NIOS2_RELATIVE
6343 BFD_RELOC_NIOS2_GOTOFF
6345 BFD_RELOC_NIOS2_CALL26_NOAT
6347 BFD_RELOC_NIOS2_GOT_LO
6349 BFD_RELOC_NIOS2_GOT_HA
6351 BFD_RELOC_NIOS2_CALL_LO
6353 BFD_RELOC_NIOS2_CALL_HA
6355 BFD_RELOC_NIOS2_R2_S12
6357 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6359 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6361 BFD_RELOC_NIOS2_R2_T1I7_2
6363 BFD_RELOC_NIOS2_R2_T2I4
6365 BFD_RELOC_NIOS2_R2_T2I4_1
6367 BFD_RELOC_NIOS2_R2_T2I4_2
6369 BFD_RELOC_NIOS2_R2_X1I7_2
6371 BFD_RELOC_NIOS2_R2_X2L5
6373 BFD_RELOC_NIOS2_R2_F1I5_2
6375 BFD_RELOC_NIOS2_R2_L5I4X1
6377 BFD_RELOC_NIOS2_R2_T1X1I6
6379 BFD_RELOC_NIOS2_R2_T1X1I6_2
6381 Relocations used by the Altera Nios II core.
6384 BFD_RELOC_IQ2000_OFFSET_16
6386 BFD_RELOC_IQ2000_OFFSET_21
6388 BFD_RELOC_IQ2000_UHI16
6393 BFD_RELOC_XTENSA_RTLD
6395 Special Xtensa relocation used only by PLT entries in ELF shared
6396 objects to indicate that the runtime linker should set the value
6397 to one of its own internal functions or data structures.
6399 BFD_RELOC_XTENSA_GLOB_DAT
6401 BFD_RELOC_XTENSA_JMP_SLOT
6403 BFD_RELOC_XTENSA_RELATIVE
6405 Xtensa relocations for ELF shared objects.
6407 BFD_RELOC_XTENSA_PLT
6409 Xtensa relocation used in ELF object files for symbols that may require
6410 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6412 BFD_RELOC_XTENSA_DIFF8
6414 BFD_RELOC_XTENSA_DIFF16
6416 BFD_RELOC_XTENSA_DIFF32
6418 Xtensa relocations to mark the difference of two local symbols.
6419 These are only needed to support linker relaxation and can be ignored
6420 when not relaxing. The field is set to the value of the difference
6421 assuming no relaxation. The relocation encodes the position of the
6422 first symbol so the linker can determine whether to adjust the field
6425 BFD_RELOC_XTENSA_SLOT0_OP
6427 BFD_RELOC_XTENSA_SLOT1_OP
6429 BFD_RELOC_XTENSA_SLOT2_OP
6431 BFD_RELOC_XTENSA_SLOT3_OP
6433 BFD_RELOC_XTENSA_SLOT4_OP
6435 BFD_RELOC_XTENSA_SLOT5_OP
6437 BFD_RELOC_XTENSA_SLOT6_OP
6439 BFD_RELOC_XTENSA_SLOT7_OP
6441 BFD_RELOC_XTENSA_SLOT8_OP
6443 BFD_RELOC_XTENSA_SLOT9_OP
6445 BFD_RELOC_XTENSA_SLOT10_OP
6447 BFD_RELOC_XTENSA_SLOT11_OP
6449 BFD_RELOC_XTENSA_SLOT12_OP
6451 BFD_RELOC_XTENSA_SLOT13_OP
6453 BFD_RELOC_XTENSA_SLOT14_OP
6455 Generic Xtensa relocations for instruction operands. Only the slot
6456 number is encoded in the relocation. The relocation applies to the
6457 last PC-relative immediate operand, or if there are no PC-relative
6458 immediates, to the last immediate operand.
6460 BFD_RELOC_XTENSA_SLOT0_ALT
6462 BFD_RELOC_XTENSA_SLOT1_ALT
6464 BFD_RELOC_XTENSA_SLOT2_ALT
6466 BFD_RELOC_XTENSA_SLOT3_ALT
6468 BFD_RELOC_XTENSA_SLOT4_ALT
6470 BFD_RELOC_XTENSA_SLOT5_ALT
6472 BFD_RELOC_XTENSA_SLOT6_ALT
6474 BFD_RELOC_XTENSA_SLOT7_ALT
6476 BFD_RELOC_XTENSA_SLOT8_ALT
6478 BFD_RELOC_XTENSA_SLOT9_ALT
6480 BFD_RELOC_XTENSA_SLOT10_ALT
6482 BFD_RELOC_XTENSA_SLOT11_ALT
6484 BFD_RELOC_XTENSA_SLOT12_ALT
6486 BFD_RELOC_XTENSA_SLOT13_ALT
6488 BFD_RELOC_XTENSA_SLOT14_ALT
6490 Alternate Xtensa relocations. Only the slot is encoded in the
6491 relocation. The meaning of these relocations is opcode-specific.
6493 BFD_RELOC_XTENSA_OP0
6495 BFD_RELOC_XTENSA_OP1
6497 BFD_RELOC_XTENSA_OP2
6499 Xtensa relocations for backward compatibility. These have all been
6500 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6502 BFD_RELOC_XTENSA_ASM_EXPAND
6504 Xtensa relocation to mark that the assembler expanded the
6505 instructions from an original target. The expansion size is
6506 encoded in the reloc size.
6508 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6510 Xtensa relocation to mark that the linker should simplify
6511 assembler-expanded instructions. This is commonly used
6512 internally by the linker after analysis of a
6513 BFD_RELOC_XTENSA_ASM_EXPAND.
6515 BFD_RELOC_XTENSA_TLSDESC_FN
6517 BFD_RELOC_XTENSA_TLSDESC_ARG
6519 BFD_RELOC_XTENSA_TLS_DTPOFF
6521 BFD_RELOC_XTENSA_TLS_TPOFF
6523 BFD_RELOC_XTENSA_TLS_FUNC
6525 BFD_RELOC_XTENSA_TLS_ARG
6527 BFD_RELOC_XTENSA_TLS_CALL
6529 Xtensa TLS relocations.
6534 8 bit signed offset in (ix+d) or (iy+d).
6552 BFD_RELOC_LM32_BRANCH
6554 BFD_RELOC_LM32_16_GOT
6556 BFD_RELOC_LM32_GOTOFF_HI16
6558 BFD_RELOC_LM32_GOTOFF_LO16
6562 BFD_RELOC_LM32_GLOB_DAT
6564 BFD_RELOC_LM32_JMP_SLOT
6566 BFD_RELOC_LM32_RELATIVE
6568 Lattice Mico32 relocations.
6571 BFD_RELOC_MACH_O_SECTDIFF
6573 Difference between two section addreses. Must be followed by a
6574 BFD_RELOC_MACH_O_PAIR.
6576 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6578 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6580 BFD_RELOC_MACH_O_PAIR
6582 Pair of relocation. Contains the first symbol.
6585 BFD_RELOC_MACH_O_X86_64_BRANCH32
6587 BFD_RELOC_MACH_O_X86_64_BRANCH8
6589 PCREL relocations. They are marked as branch to create PLT entry if
6592 BFD_RELOC_MACH_O_X86_64_GOT
6594 Used when referencing a GOT entry.
6596 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6598 Used when loading a GOT entry with movq. It is specially marked so that
6599 the linker could optimize the movq to a leaq if possible.
6601 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
6603 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6605 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
6607 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6609 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6611 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6613 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6615 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6617 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6619 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6622 BFD_RELOC_MICROBLAZE_32_LO
6624 This is a 32 bit reloc for the microblaze that stores the
6625 low 16 bits of a value
6627 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6629 This is a 32 bit pc-relative reloc for the microblaze that
6630 stores the low 16 bits of a value
6632 BFD_RELOC_MICROBLAZE_32_ROSDA
6634 This is a 32 bit reloc for the microblaze that stores a
6635 value relative to the read-only small data area anchor
6637 BFD_RELOC_MICROBLAZE_32_RWSDA
6639 This is a 32 bit reloc for the microblaze that stores a
6640 value relative to the read-write small data area anchor
6642 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6644 This is a 32 bit reloc for the microblaze to handle
6645 expressions of the form "Symbol Op Symbol"
6647 BFD_RELOC_MICROBLAZE_64_NONE
6649 This is a 64 bit reloc that stores the 32 bit pc relative
6650 value in two words (with an imm instruction). No relocation is
6651 done here - only used for relaxing
6653 BFD_RELOC_MICROBLAZE_64_GOTPC
6655 This is a 64 bit reloc that stores the 32 bit pc relative
6656 value in two words (with an imm instruction). The relocation is
6657 PC-relative GOT offset
6659 BFD_RELOC_MICROBLAZE_64_GOT
6661 This is a 64 bit reloc that stores the 32 bit pc relative
6662 value in two words (with an imm instruction). The relocation is
6665 BFD_RELOC_MICROBLAZE_64_PLT
6667 This is a 64 bit reloc that stores the 32 bit pc relative
6668 value in two words (with an imm instruction). The relocation is
6669 PC-relative offset into PLT
6671 BFD_RELOC_MICROBLAZE_64_GOTOFF
6673 This is a 64 bit reloc that stores the 32 bit GOT relative
6674 value in two words (with an imm instruction). The relocation is
6675 relative offset from _GLOBAL_OFFSET_TABLE_
6677 BFD_RELOC_MICROBLAZE_32_GOTOFF
6679 This is a 32 bit reloc that stores the 32 bit GOT relative
6680 value in a word. The relocation is relative offset from
6681 _GLOBAL_OFFSET_TABLE_
6683 BFD_RELOC_MICROBLAZE_COPY
6685 This is used to tell the dynamic linker to copy the value out of
6686 the dynamic object into the runtime process image.
6688 BFD_RELOC_MICROBLAZE_64_TLS
6692 BFD_RELOC_MICROBLAZE_64_TLSGD
6694 This is a 64 bit reloc that stores the 32 bit GOT relative value
6695 of the GOT TLS GD info entry in two words (with an imm instruction). The
6696 relocation is GOT offset.
6698 BFD_RELOC_MICROBLAZE_64_TLSLD
6700 This is a 64 bit reloc that stores the 32 bit GOT relative value
6701 of the GOT TLS LD info entry in two words (with an imm instruction). The
6702 relocation is GOT offset.
6704 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6706 This is a 32 bit reloc that stores the Module ID to GOT(n).
6708 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6710 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6712 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6714 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6717 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6719 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6720 to two words (uses imm instruction).
6722 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6724 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6725 to two words (uses imm instruction).
6728 BFD_RELOC_AARCH64_RELOC_START
6730 AArch64 pseudo relocation code to mark the start of the AArch64
6731 relocation enumerators. N.B. the order of the enumerators is
6732 important as several tables in the AArch64 bfd backend are indexed
6733 by these enumerators; make sure they are all synced.
6735 BFD_RELOC_AARCH64_NONE
6737 AArch64 null relocation code.
6739 BFD_RELOC_AARCH64_64
6741 BFD_RELOC_AARCH64_32
6743 BFD_RELOC_AARCH64_16
6745 Basic absolute relocations of N bits. These are equivalent to
6746 BFD_RELOC_N and they were added to assist the indexing of the howto
6749 BFD_RELOC_AARCH64_64_PCREL
6751 BFD_RELOC_AARCH64_32_PCREL
6753 BFD_RELOC_AARCH64_16_PCREL
6755 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6756 and they were added to assist the indexing of the howto table.
6758 BFD_RELOC_AARCH64_MOVW_G0
6760 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6761 of an unsigned address/value.
6763 BFD_RELOC_AARCH64_MOVW_G0_NC
6765 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6766 an address/value. No overflow checking.
6768 BFD_RELOC_AARCH64_MOVW_G1
6770 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6771 of an unsigned address/value.
6773 BFD_RELOC_AARCH64_MOVW_G1_NC
6775 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6776 of an address/value. No overflow checking.
6778 BFD_RELOC_AARCH64_MOVW_G2
6780 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6781 of an unsigned address/value.
6783 BFD_RELOC_AARCH64_MOVW_G2_NC
6785 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6786 of an address/value. No overflow checking.
6788 BFD_RELOC_AARCH64_MOVW_G3
6790 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6791 of a signed or unsigned address/value.
6793 BFD_RELOC_AARCH64_MOVW_G0_S
6795 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6796 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6799 BFD_RELOC_AARCH64_MOVW_G1_S
6801 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6802 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6805 BFD_RELOC_AARCH64_MOVW_G2_S
6807 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6808 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6811 BFD_RELOC_AARCH64_LD_LO19_PCREL
6813 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6814 offset. The lowest two bits must be zero and are not stored in the
6815 instruction, giving a 21 bit signed byte offset.
6817 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6819 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6821 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6823 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6824 offset, giving a 4KB aligned page base address.
6826 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6828 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6829 offset, giving a 4KB aligned page base address, but with no overflow
6832 BFD_RELOC_AARCH64_ADD_LO12
6834 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6835 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6837 BFD_RELOC_AARCH64_LDST8_LO12
6839 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6840 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6842 BFD_RELOC_AARCH64_TSTBR14
6844 AArch64 14 bit pc-relative test bit and branch.
6845 The lowest two bits must be zero and are not stored in the instruction,
6846 giving a 16 bit signed byte offset.
6848 BFD_RELOC_AARCH64_BRANCH19
6850 AArch64 19 bit pc-relative conditional branch and compare & branch.
6851 The lowest two bits must be zero and are not stored in the instruction,
6852 giving a 21 bit signed byte offset.
6854 BFD_RELOC_AARCH64_JUMP26
6856 AArch64 26 bit pc-relative unconditional branch.
6857 The lowest two bits must be zero and are not stored in the instruction,
6858 giving a 28 bit signed byte offset.
6860 BFD_RELOC_AARCH64_CALL26
6862 AArch64 26 bit pc-relative unconditional branch and link.
6863 The lowest two bits must be zero and are not stored in the instruction,
6864 giving a 28 bit signed byte offset.
6866 BFD_RELOC_AARCH64_LDST16_LO12
6868 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6869 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6871 BFD_RELOC_AARCH64_LDST32_LO12
6873 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6874 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6876 BFD_RELOC_AARCH64_LDST64_LO12
6878 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6879 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6881 BFD_RELOC_AARCH64_LDST128_LO12
6883 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6884 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6886 BFD_RELOC_AARCH64_GOT_LD_PREL19
6888 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6889 offset of the global offset table entry for a symbol. The lowest two
6890 bits must be zero and are not stored in the instruction, giving a 21
6891 bit signed byte offset. This relocation type requires signed overflow
6894 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6896 Get to the page base of the global offset table entry for a symbol as
6897 part of an ADRP instruction using a 21 bit PC relative value.Used in
6898 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6900 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6902 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6903 the GOT entry for this symbol. Used in conjunction with
6904 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6906 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6908 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6909 the GOT entry for this symbol. Used in conjunction with
6910 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6912 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
6914 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
6915 for this symbol. Valid in LP64 ABI only.
6917 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
6919 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
6920 for this symbol. Valid in LP64 ABI only.
6922 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
6924 Unsigned 15 bit byte offset for 64 bit load/store from the page of
6925 the GOT entry for this symbol. Valid in LP64 ABI only.
6927 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
6929 Scaled 14 bit byte offset to the page base of the global offset table.
6931 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
6933 Scaled 15 bit byte offset to the page base of the global offset table.
6935 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6937 Get to the page base of the global offset table entry for a symbols
6938 tls_index structure as part of an adrp instruction using a 21 bit PC
6939 relative value. Used in conjunction with
6940 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6942 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
6944 AArch64 TLS General Dynamic
6946 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6948 Unsigned 12 bit byte offset to global offset table entry for a symbols
6949 tls_index structure. Used in conjunction with
6950 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6952 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
6954 AArch64 TLS General Dynamic relocation.
6956 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
6958 AArch64 TLS General Dynamic relocation.
6960 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6962 AArch64 TLS INITIAL EXEC relocation.
6964 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6966 AArch64 TLS INITIAL EXEC relocation.
6968 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6970 AArch64 TLS INITIAL EXEC relocation.
6972 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6974 AArch64 TLS INITIAL EXEC relocation.
6976 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6978 AArch64 TLS INITIAL EXEC relocation.
6980 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6982 AArch64 TLS INITIAL EXEC relocation.
6984 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
6986 bit[23:12] of byte offset to module TLS base address.
6988 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
6990 Unsigned 12 bit byte offset to module TLS base address.
6992 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
6994 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
6996 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
6998 Unsigned 12 bit byte offset to global offset table entry for a symbols
6999 tls_index structure. Used in conjunction with
7000 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7002 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7004 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7007 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7009 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7011 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7013 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7016 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7018 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7020 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7022 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7025 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7027 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7029 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7031 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7034 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7036 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7038 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7040 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7043 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7045 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7047 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7049 bit[15:0] of byte offset to module TLS base address.
7051 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7053 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7055 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7057 bit[31:16] of byte offset to module TLS base address.
7059 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7061 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7063 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7065 bit[47:32] of byte offset to module TLS base address.
7067 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7069 AArch64 TLS LOCAL EXEC relocation.
7071 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7073 AArch64 TLS LOCAL EXEC relocation.
7075 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7077 AArch64 TLS LOCAL EXEC relocation.
7079 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7081 AArch64 TLS LOCAL EXEC relocation.
7083 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7085 AArch64 TLS LOCAL EXEC relocation.
7087 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7089 AArch64 TLS LOCAL EXEC relocation.
7091 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7093 AArch64 TLS LOCAL EXEC relocation.
7095 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7097 AArch64 TLS LOCAL EXEC relocation.
7099 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7101 AArch64 TLS DESC relocation.
7103 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7105 AArch64 TLS DESC relocation.
7107 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7109 AArch64 TLS DESC relocation.
7111 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
7113 AArch64 TLS DESC relocation.
7115 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7117 AArch64 TLS DESC relocation.
7119 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
7121 AArch64 TLS DESC relocation.
7123 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7125 AArch64 TLS DESC relocation.
7127 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7129 AArch64 TLS DESC relocation.
7131 BFD_RELOC_AARCH64_TLSDESC_LDR
7133 AArch64 TLS DESC relocation.
7135 BFD_RELOC_AARCH64_TLSDESC_ADD
7137 AArch64 TLS DESC relocation.
7139 BFD_RELOC_AARCH64_TLSDESC_CALL
7141 AArch64 TLS DESC relocation.
7143 BFD_RELOC_AARCH64_COPY
7145 AArch64 TLS relocation.
7147 BFD_RELOC_AARCH64_GLOB_DAT
7149 AArch64 TLS relocation.
7151 BFD_RELOC_AARCH64_JUMP_SLOT
7153 AArch64 TLS relocation.
7155 BFD_RELOC_AARCH64_RELATIVE
7157 AArch64 TLS relocation.
7159 BFD_RELOC_AARCH64_TLS_DTPMOD
7161 AArch64 TLS relocation.
7163 BFD_RELOC_AARCH64_TLS_DTPREL
7165 AArch64 TLS relocation.
7167 BFD_RELOC_AARCH64_TLS_TPREL
7169 AArch64 TLS relocation.
7171 BFD_RELOC_AARCH64_TLSDESC
7173 AArch64 TLS relocation.
7175 BFD_RELOC_AARCH64_IRELATIVE
7177 AArch64 support for STT_GNU_IFUNC.
7179 BFD_RELOC_AARCH64_RELOC_END
7181 AArch64 pseudo relocation code to mark the end of the AArch64
7182 relocation enumerators that have direct mapping to ELF reloc codes.
7183 There are a few more enumerators after this one; those are mainly
7184 used by the AArch64 assembler for the internal fixup or to select
7185 one of the above enumerators.
7187 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7189 AArch64 pseudo relocation code to be used internally by the AArch64
7190 assembler and not (currently) written to any object files.
7192 BFD_RELOC_AARCH64_LDST_LO12
7194 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7195 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7197 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7199 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7200 used internally by the AArch64 assembler and not (currently) written to
7203 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7205 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7207 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7209 AArch64 pseudo relocation code to be used internally by the AArch64
7210 assembler and not (currently) written to any object files.
7212 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7214 AArch64 pseudo relocation code to be used internally by the AArch64
7215 assembler and not (currently) written to any object files.
7217 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7219 AArch64 pseudo relocation code to be used internally by the AArch64
7220 assembler and not (currently) written to any object files.
7222 BFD_RELOC_TILEPRO_COPY
7224 BFD_RELOC_TILEPRO_GLOB_DAT
7226 BFD_RELOC_TILEPRO_JMP_SLOT
7228 BFD_RELOC_TILEPRO_RELATIVE
7230 BFD_RELOC_TILEPRO_BROFF_X1
7232 BFD_RELOC_TILEPRO_JOFFLONG_X1
7234 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7236 BFD_RELOC_TILEPRO_IMM8_X0
7238 BFD_RELOC_TILEPRO_IMM8_Y0
7240 BFD_RELOC_TILEPRO_IMM8_X1
7242 BFD_RELOC_TILEPRO_IMM8_Y1
7244 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7246 BFD_RELOC_TILEPRO_MT_IMM15_X1
7248 BFD_RELOC_TILEPRO_MF_IMM15_X1
7250 BFD_RELOC_TILEPRO_IMM16_X0
7252 BFD_RELOC_TILEPRO_IMM16_X1
7254 BFD_RELOC_TILEPRO_IMM16_X0_LO
7256 BFD_RELOC_TILEPRO_IMM16_X1_LO
7258 BFD_RELOC_TILEPRO_IMM16_X0_HI
7260 BFD_RELOC_TILEPRO_IMM16_X1_HI
7262 BFD_RELOC_TILEPRO_IMM16_X0_HA
7264 BFD_RELOC_TILEPRO_IMM16_X1_HA
7266 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7268 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7270 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7272 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7274 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7276 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7278 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7280 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7282 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7284 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7286 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7288 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7290 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7292 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7294 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7296 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7298 BFD_RELOC_TILEPRO_MMSTART_X0
7300 BFD_RELOC_TILEPRO_MMEND_X0
7302 BFD_RELOC_TILEPRO_MMSTART_X1
7304 BFD_RELOC_TILEPRO_MMEND_X1
7306 BFD_RELOC_TILEPRO_SHAMT_X0
7308 BFD_RELOC_TILEPRO_SHAMT_X1
7310 BFD_RELOC_TILEPRO_SHAMT_Y0
7312 BFD_RELOC_TILEPRO_SHAMT_Y1
7314 BFD_RELOC_TILEPRO_TLS_GD_CALL
7316 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7318 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7320 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7322 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7324 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7326 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7328 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7330 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7332 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7334 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7336 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7338 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7340 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7342 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7344 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7346 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7348 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7350 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7352 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7354 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7356 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7358 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7360 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7362 BFD_RELOC_TILEPRO_TLS_TPOFF32
7364 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7366 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7368 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7370 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7372 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7374 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7376 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7378 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7380 Tilera TILEPro Relocations.
7382 BFD_RELOC_TILEGX_HW0
7384 BFD_RELOC_TILEGX_HW1
7386 BFD_RELOC_TILEGX_HW2
7388 BFD_RELOC_TILEGX_HW3
7390 BFD_RELOC_TILEGX_HW0_LAST
7392 BFD_RELOC_TILEGX_HW1_LAST
7394 BFD_RELOC_TILEGX_HW2_LAST
7396 BFD_RELOC_TILEGX_COPY
7398 BFD_RELOC_TILEGX_GLOB_DAT
7400 BFD_RELOC_TILEGX_JMP_SLOT
7402 BFD_RELOC_TILEGX_RELATIVE
7404 BFD_RELOC_TILEGX_BROFF_X1
7406 BFD_RELOC_TILEGX_JUMPOFF_X1
7408 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7410 BFD_RELOC_TILEGX_IMM8_X0
7412 BFD_RELOC_TILEGX_IMM8_Y0
7414 BFD_RELOC_TILEGX_IMM8_X1
7416 BFD_RELOC_TILEGX_IMM8_Y1
7418 BFD_RELOC_TILEGX_DEST_IMM8_X1
7420 BFD_RELOC_TILEGX_MT_IMM14_X1
7422 BFD_RELOC_TILEGX_MF_IMM14_X1
7424 BFD_RELOC_TILEGX_MMSTART_X0
7426 BFD_RELOC_TILEGX_MMEND_X0
7428 BFD_RELOC_TILEGX_SHAMT_X0
7430 BFD_RELOC_TILEGX_SHAMT_X1
7432 BFD_RELOC_TILEGX_SHAMT_Y0
7434 BFD_RELOC_TILEGX_SHAMT_Y1
7436 BFD_RELOC_TILEGX_IMM16_X0_HW0
7438 BFD_RELOC_TILEGX_IMM16_X1_HW0
7440 BFD_RELOC_TILEGX_IMM16_X0_HW1
7442 BFD_RELOC_TILEGX_IMM16_X1_HW1
7444 BFD_RELOC_TILEGX_IMM16_X0_HW2
7446 BFD_RELOC_TILEGX_IMM16_X1_HW2
7448 BFD_RELOC_TILEGX_IMM16_X0_HW3
7450 BFD_RELOC_TILEGX_IMM16_X1_HW3
7452 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7454 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7456 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7458 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7460 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7462 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7464 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7466 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7468 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7470 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7472 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7474 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7476 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7478 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7480 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7482 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7484 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7486 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7488 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7490 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7492 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7494 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7496 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7498 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7500 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7502 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7504 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7506 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7508 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7510 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7512 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7514 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7516 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7518 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7520 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7522 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7524 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7526 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7528 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7530 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7532 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7534 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7536 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7538 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7540 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7542 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7544 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7546 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7548 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7550 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7552 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7554 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7556 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7558 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7560 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7562 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7564 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7566 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7568 BFD_RELOC_TILEGX_TLS_DTPMOD64
7570 BFD_RELOC_TILEGX_TLS_DTPOFF64
7572 BFD_RELOC_TILEGX_TLS_TPOFF64
7574 BFD_RELOC_TILEGX_TLS_DTPMOD32
7576 BFD_RELOC_TILEGX_TLS_DTPOFF32
7578 BFD_RELOC_TILEGX_TLS_TPOFF32
7580 BFD_RELOC_TILEGX_TLS_GD_CALL
7582 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7584 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7586 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7588 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7590 BFD_RELOC_TILEGX_TLS_IE_LOAD
7592 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7594 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7596 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7598 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7600 Tilera TILE-Gx Relocations.
7603 BFD_RELOC_EPIPHANY_SIMM8
7605 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7607 BFD_RELOC_EPIPHANY_SIMM24
7609 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7611 BFD_RELOC_EPIPHANY_HIGH
7613 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7615 BFD_RELOC_EPIPHANY_LOW
7617 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7619 BFD_RELOC_EPIPHANY_SIMM11
7621 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7623 BFD_RELOC_EPIPHANY_IMM11
7625 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7627 BFD_RELOC_EPIPHANY_IMM8
7629 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7632 BFD_RELOC_VISIUM_HI16
7634 BFD_RELOC_VISIUM_LO16
7636 BFD_RELOC_VISIUM_IM16
7638 BFD_RELOC_VISIUM_REL16
7640 BFD_RELOC_VISIUM_HI16_PCREL
7642 BFD_RELOC_VISIUM_LO16_PCREL
7644 BFD_RELOC_VISIUM_IM16_PCREL
7652 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7657 bfd_reloc_type_lookup
7658 bfd_reloc_name_lookup
7661 reloc_howto_type *bfd_reloc_type_lookup
7662 (bfd *abfd, bfd_reloc_code_real_type code);
7663 reloc_howto_type *bfd_reloc_name_lookup
7664 (bfd *abfd, const char *reloc_name);
7667 Return a pointer to a howto structure which, when
7668 invoked, will perform the relocation @var{code} on data from the
7674 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7676 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7680 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7682 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7685 static reloc_howto_type bfd_howto_32
=
7686 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7690 bfd_default_reloc_type_lookup
7693 reloc_howto_type *bfd_default_reloc_type_lookup
7694 (bfd *abfd, bfd_reloc_code_real_type code);
7697 Provides a default relocation lookup routine for any architecture.
7702 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7706 case BFD_RELOC_CTOR
:
7707 /* The type of reloc used in a ctor, which will be as wide as the
7708 address - so either a 64, 32, or 16 bitter. */
7709 switch (bfd_arch_bits_per_address (abfd
))
7714 return &bfd_howto_32
;
7728 bfd_get_reloc_code_name
7731 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7734 Provides a printable name for the supplied relocation code.
7735 Useful mainly for printing error messages.
7739 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7741 if (code
> BFD_RELOC_UNUSED
)
7743 return bfd_reloc_code_real_names
[code
];
7748 bfd_generic_relax_section
7751 bfd_boolean bfd_generic_relax_section
7754 struct bfd_link_info *,
7758 Provides default handling for relaxing for back ends which
7763 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
7764 asection
*section ATTRIBUTE_UNUSED
,
7765 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
7768 if (bfd_link_relocatable (link_info
))
7769 (*link_info
->callbacks
->einfo
)
7770 (_("%P%F: --relax and -r may not be used together\n"));
7778 bfd_generic_gc_sections
7781 bfd_boolean bfd_generic_gc_sections
7782 (bfd *, struct bfd_link_info *);
7785 Provides default handling for relaxing for back ends which
7786 don't do section gc -- i.e., does nothing.
7790 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7791 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
7798 bfd_generic_lookup_section_flags
7801 bfd_boolean bfd_generic_lookup_section_flags
7802 (struct bfd_link_info *, struct flag_info *, asection *);
7805 Provides default handling for section flags lookup
7806 -- i.e., does nothing.
7807 Returns FALSE if the section should be omitted, otherwise TRUE.
7811 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
7812 struct flag_info
*flaginfo
,
7813 asection
*section ATTRIBUTE_UNUSED
)
7815 if (flaginfo
!= NULL
)
7817 (*_bfd_error_handler
) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7825 bfd_generic_merge_sections
7828 bfd_boolean bfd_generic_merge_sections
7829 (bfd *, struct bfd_link_info *);
7832 Provides default handling for SEC_MERGE section merging for back ends
7833 which don't have SEC_MERGE support -- i.e., does nothing.
7837 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7838 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
7845 bfd_generic_get_relocated_section_contents
7848 bfd_byte *bfd_generic_get_relocated_section_contents
7850 struct bfd_link_info *link_info,
7851 struct bfd_link_order *link_order,
7853 bfd_boolean relocatable,
7857 Provides default handling of relocation effort for back ends
7858 which can't be bothered to do it efficiently.
7863 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
7864 struct bfd_link_info
*link_info
,
7865 struct bfd_link_order
*link_order
,
7867 bfd_boolean relocatable
,
7870 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
7871 asection
*input_section
= link_order
->u
.indirect
.section
;
7873 arelent
**reloc_vector
;
7876 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
7880 /* Read in the section. */
7881 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
7884 if (reloc_size
== 0)
7887 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
7888 if (reloc_vector
== NULL
)
7891 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
7895 if (reloc_count
< 0)
7898 if (reloc_count
> 0)
7901 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
7903 char *error_message
= NULL
;
7905 bfd_reloc_status_type r
;
7907 symbol
= *(*parent
)->sym_ptr_ptr
;
7908 if (symbol
->section
&& discarded_section (symbol
->section
))
7911 static reloc_howto_type none_howto
7912 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
7913 "unused", FALSE
, 0, 0, FALSE
);
7915 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
7916 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
7918 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
7919 (*parent
)->addend
= 0;
7920 (*parent
)->howto
= &none_howto
;
7924 r
= bfd_perform_relocation (input_bfd
,
7928 relocatable
? abfd
: NULL
,
7933 asection
*os
= input_section
->output_section
;
7935 /* A partial link, so keep the relocs. */
7936 os
->orelocation
[os
->reloc_count
] = *parent
;
7940 if (r
!= bfd_reloc_ok
)
7944 case bfd_reloc_undefined
:
7945 if (!((*link_info
->callbacks
->undefined_symbol
)
7946 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7947 input_bfd
, input_section
, (*parent
)->address
,
7951 case bfd_reloc_dangerous
:
7952 BFD_ASSERT (error_message
!= NULL
);
7953 if (!((*link_info
->callbacks
->reloc_dangerous
)
7954 (link_info
, error_message
, input_bfd
, input_section
,
7955 (*parent
)->address
)))
7958 case bfd_reloc_overflow
:
7959 if (!((*link_info
->callbacks
->reloc_overflow
)
7961 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7962 (*parent
)->howto
->name
, (*parent
)->addend
,
7963 input_bfd
, input_section
, (*parent
)->address
)))
7966 case bfd_reloc_outofrange
:
7968 This error can result when processing some partially
7969 complete binaries. Do not abort, but issue an error
7971 link_info
->callbacks
->einfo
7972 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7973 abfd
, input_section
, * parent
);
7976 case bfd_reloc_notsupported
:
7978 This error can result when processing a corrupt binary.
7979 Do not abort. Issue an error message instead. */
7980 link_info
->callbacks
->einfo
7981 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
7982 abfd
, input_section
, * parent
);
7986 /* PR 17512; file: 90c2a92e.
7987 Report unexpected results, without aborting. */
7988 link_info
->callbacks
->einfo
7989 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
7990 abfd
, input_section
, * parent
, r
);
7998 free (reloc_vector
);
8002 free (reloc_vector
);