1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2020 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
54 #include "coff/internal.h"
58 typedef arelent, howto manager, Relocations, Relocations
63 This is the structure of a relocation entry:
67 .typedef enum bfd_reloc_status
69 . {* No errors detected. Note - the value 2 is used so that it
70 . will not be mistaken for the boolean TRUE or FALSE values. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok. If this type is
92 . returned, the error_message argument to bfd_perform_relocation
96 . bfd_reloc_status_type;
98 .typedef const struct reloc_howto_struct reloc_howto_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's idea of
288 . an external reloc number is stored in this field. *}
291 . {* The encoded size of the item to be relocated. This is *not* a
292 . power-of-two measure. Use bfd_get_reloc_size to find the size
293 . of the item in bytes. *}
294 . unsigned int size:3;
296 . {* The number of bits in the field to be relocated. This is used
297 . when doing overflow checking. *}
298 . unsigned int bitsize:7;
300 . {* The value the final relocation is shifted right by. This drops
301 . unwanted data from the relocation. *}
302 . unsigned int rightshift:6;
304 . {* The bit position of the reloc value in the destination.
305 . The relocated value is left shifted by this amount. *}
306 . unsigned int bitpos:6;
308 . {* What type of overflow error should be checked for when
310 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
312 . {* The relocation value should be negated before applying. *}
313 . unsigned int negate:1;
315 . {* The relocation is relative to the item being relocated. *}
316 . unsigned int pc_relative:1;
318 . {* Some formats record a relocation addend in the section contents
319 . rather than with the relocation. For ELF formats this is the
320 . distinction between USE_REL and USE_RELA (though the code checks
321 . for USE_REL == 1/0). The value of this field is TRUE if the
322 . addend is recorded with the section contents; when performing a
323 . partial link (ld -r) the section contents (the data) will be
324 . modified. The value of this field is FALSE if addends are
325 . recorded with the relocation (in arelent.addend); when performing
326 . a partial link the relocation will be modified.
327 . All relocations for all ELF USE_RELA targets should set this field
328 . to FALSE (values of TRUE should be looked on with suspicion).
329 . However, the converse is not true: not all relocations of all ELF
330 . USE_REL targets set this field to TRUE. Why this is so is peculiar
331 . to each particular target. For relocs that aren't used in partial
332 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
333 . unsigned int partial_inplace:1;
335 . {* When some formats create PC relative instructions, they leave
336 . the value of the pc of the place being relocated in the offset
337 . slot of the instruction, so that a PC relative relocation can
338 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
339 . Some formats leave the displacement part of an instruction
340 . empty (e.g., ELF); this flag signals the fact. *}
341 . unsigned int pcrel_offset:1;
343 . {* src_mask selects the part of the instruction (or data) to be used
344 . in the relocation sum. If the target relocations don't have an
345 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
346 . dst_mask to extract the addend from the section contents. If
347 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
348 . field should normally be zero. Non-zero values for ELF USE_RELA
349 . targets should be viewed with suspicion as normally the value in
350 . the dst_mask part of the section contents should be ignored. *}
353 . {* dst_mask selects which parts of the instruction (or data) are
354 . replaced with a relocated value. *}
357 . {* If this field is non null, then the supplied function is
358 . called rather than the normal function. This allows really
359 . strange relocation methods to be accommodated. *}
360 . bfd_reloc_status_type (*special_function)
361 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
364 . {* The textual name of the relocation type. *}
375 The HOWTO macro fills in a reloc_howto_type (a typedef for
376 const struct reloc_howto_struct).
378 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
379 . inplace, src_mask, dst_mask, pcrel_off) \
380 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
381 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
384 This is used to fill in an empty howto entry in an array.
386 .#define EMPTY_HOWTO(C) \
387 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
388 . NULL, FALSE, 0, 0, FALSE)
397 unsigned int bfd_get_reloc_size (reloc_howto_type *);
400 For a reloc_howto_type that operates on a fixed number of bytes,
401 this returns the number of bytes operated on.
405 bfd_get_reloc_size (reloc_howto_type
*howto
)
425 How relocs are tied together in an <<asection>>:
427 .typedef struct relent_chain
430 . struct relent_chain *next;
436 /* N_ONES produces N one bits, without undefined behaviour for N
437 between zero and the number of bits in a bfd_vma. */
438 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
445 bfd_reloc_status_type bfd_check_overflow
446 (enum complain_overflow how,
447 unsigned int bitsize,
448 unsigned int rightshift,
449 unsigned int addrsize,
453 Perform overflow checking on @var{relocation} which has
454 @var{bitsize} significant bits and will be shifted right by
455 @var{rightshift} bits, on a machine with addresses containing
456 @var{addrsize} significant bits. The result is either of
457 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
461 bfd_reloc_status_type
462 bfd_check_overflow (enum complain_overflow how
,
463 unsigned int bitsize
,
464 unsigned int rightshift
,
465 unsigned int addrsize
,
468 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
469 bfd_reloc_status_type flag
= bfd_reloc_ok
;
474 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
475 we'll be permissive: extra bits in the field mask will
476 automatically extend the address mask for purposes of the
478 fieldmask
= N_ONES (bitsize
);
479 signmask
= ~fieldmask
;
480 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
481 a
= (relocation
& addrmask
) >> rightshift
;
485 case complain_overflow_dont
:
488 case complain_overflow_signed
:
489 /* If any sign bits are set, all sign bits must be set. That
490 is, A must be a valid negative address after shifting. */
491 signmask
= ~ (fieldmask
>> 1);
494 case complain_overflow_bitfield
:
495 /* Bitfields are sometimes signed, sometimes unsigned. We
496 explicitly allow an address wrap too, which means a bitfield
497 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
498 if the value has some, but not all, bits set outside the
501 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
502 flag
= bfd_reloc_overflow
;
505 case complain_overflow_unsigned
:
506 /* We have an overflow if the address does not fit in the field. */
507 if ((a
& signmask
) != 0)
508 flag
= bfd_reloc_overflow
;
520 bfd_reloc_offset_in_range
523 bfd_boolean bfd_reloc_offset_in_range
524 (reloc_howto_type *howto,
527 bfd_size_type offset);
530 Returns TRUE if the reloc described by @var{HOWTO} can be
531 applied at @var{OFFSET} octets in @var{SECTION}.
535 /* HOWTO describes a relocation, at offset OCTET. Return whether the
536 relocation field is within SECTION of ABFD. */
539 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
544 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
545 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
547 /* The reloc field must be contained entirely within the section.
548 Allow zero length fields (marker relocs or NONE relocs where no
549 relocation will be performed) at the end of the section. */
550 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
553 /* Read and return the section contents at DATA converted to a host
554 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
557 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
562 return bfd_get_8 (abfd
, data
);
565 return bfd_get_16 (abfd
, data
);
568 return bfd_get_32 (abfd
, data
);
575 return bfd_get_64 (abfd
, data
);
579 return bfd_get_24 (abfd
, data
);
587 /* Convert VAL to target format and write to DATA. The number of
588 bytes written is given by the HOWTO. */
591 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
596 bfd_put_8 (abfd
, val
, data
);
600 bfd_put_16 (abfd
, val
, data
);
604 bfd_put_32 (abfd
, val
, data
);
612 bfd_put_64 (abfd
, val
, data
);
617 bfd_put_24 (abfd
, val
, data
);
625 /* Apply RELOCATION value to target bytes at DATA, according to
629 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
632 bfd_vma val
= read_reloc (abfd
, data
, howto
);
635 relocation
= -relocation
;
637 val
= ((val
& ~howto
->dst_mask
)
638 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
640 write_reloc (abfd
, val
, data
, howto
);
645 bfd_perform_relocation
648 bfd_reloc_status_type bfd_perform_relocation
650 arelent *reloc_entry,
652 asection *input_section,
654 char **error_message);
657 If @var{output_bfd} is supplied to this function, the
658 generated image will be relocatable; the relocations are
659 copied to the output file after they have been changed to
660 reflect the new state of the world. There are two ways of
661 reflecting the results of partial linkage in an output file:
662 by modifying the output data in place, and by modifying the
663 relocation record. Some native formats (e.g., basic a.out and
664 basic coff) have no way of specifying an addend in the
665 relocation type, so the addend has to go in the output data.
666 This is no big deal since in these formats the output data
667 slot will always be big enough for the addend. Complex reloc
668 types with addends were invented to solve just this problem.
669 The @var{error_message} argument is set to an error message if
670 this return @code{bfd_reloc_dangerous}.
674 bfd_reloc_status_type
675 bfd_perform_relocation (bfd
*abfd
,
676 arelent
*reloc_entry
,
678 asection
*input_section
,
680 char **error_message
)
683 bfd_reloc_status_type flag
= bfd_reloc_ok
;
684 bfd_size_type octets
;
685 bfd_vma output_base
= 0;
686 reloc_howto_type
*howto
= reloc_entry
->howto
;
687 asection
*reloc_target_output_section
;
690 symbol
= *(reloc_entry
->sym_ptr_ptr
);
692 /* If we are not producing relocatable output, return an error if
693 the symbol is not defined. An undefined weak symbol is
694 considered to have a value of zero (SVR4 ABI, p. 4-27). */
695 if (bfd_is_und_section (symbol
->section
)
696 && (symbol
->flags
& BSF_WEAK
) == 0
697 && output_bfd
== NULL
)
698 flag
= bfd_reloc_undefined
;
700 /* If there is a function supplied to handle this relocation type,
701 call it. It'll return `bfd_reloc_continue' if further processing
703 if (howto
&& howto
->special_function
)
705 bfd_reloc_status_type cont
;
707 /* Note - we do not call bfd_reloc_offset_in_range here as the
708 reloc_entry->address field might actually be valid for the
709 backend concerned. It is up to the special_function itself
710 to call bfd_reloc_offset_in_range if needed. */
711 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
712 input_section
, output_bfd
,
714 if (cont
!= bfd_reloc_continue
)
718 if (bfd_is_abs_section (symbol
->section
)
719 && output_bfd
!= NULL
)
721 reloc_entry
->address
+= input_section
->output_offset
;
725 /* PR 17512: file: 0f67f69d. */
727 return bfd_reloc_undefined
;
729 /* Is the address of the relocation really within the section? */
730 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
731 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
732 return bfd_reloc_outofrange
;
734 /* Work out which section the relocation is targeted at and the
735 initial relocation command value. */
737 /* Get symbol value. (Common symbols are special.) */
738 if (bfd_is_com_section (symbol
->section
))
741 relocation
= symbol
->value
;
743 reloc_target_output_section
= symbol
->section
->output_section
;
745 /* Convert input-section-relative symbol value to absolute. */
746 if ((output_bfd
&& ! howto
->partial_inplace
)
747 || reloc_target_output_section
== NULL
)
750 output_base
= reloc_target_output_section
->vma
;
752 output_base
+= symbol
->section
->output_offset
;
754 /* If symbol addresses are in octets, convert to bytes. */
755 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
756 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
757 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
759 relocation
+= output_base
;
761 /* Add in supplied addend. */
762 relocation
+= reloc_entry
->addend
;
764 /* Here the variable relocation holds the final address of the
765 symbol we are relocating against, plus any addend. */
767 if (howto
->pc_relative
)
769 /* This is a PC relative relocation. We want to set RELOCATION
770 to the distance between the address of the symbol and the
771 location. RELOCATION is already the address of the symbol.
773 We start by subtracting the address of the section containing
776 If pcrel_offset is set, we must further subtract the position
777 of the location within the section. Some targets arrange for
778 the addend to be the negative of the position of the location
779 within the section; for example, i386-aout does this. For
780 i386-aout, pcrel_offset is FALSE. Some other targets do not
781 include the position of the location; for example, ELF.
782 For those targets, pcrel_offset is TRUE.
784 If we are producing relocatable output, then we must ensure
785 that this reloc will be correctly computed when the final
786 relocation is done. If pcrel_offset is FALSE we want to wind
787 up with the negative of the location within the section,
788 which means we must adjust the existing addend by the change
789 in the location within the section. If pcrel_offset is TRUE
790 we do not want to adjust the existing addend at all.
792 FIXME: This seems logical to me, but for the case of
793 producing relocatable output it is not what the code
794 actually does. I don't want to change it, because it seems
795 far too likely that something will break. */
798 input_section
->output_section
->vma
+ input_section
->output_offset
;
800 if (howto
->pcrel_offset
)
801 relocation
-= reloc_entry
->address
;
804 if (output_bfd
!= NULL
)
806 if (! howto
->partial_inplace
)
808 /* This is a partial relocation, and we want to apply the relocation
809 to the reloc entry rather than the raw data. Modify the reloc
810 inplace to reflect what we now know. */
811 reloc_entry
->addend
= relocation
;
812 reloc_entry
->address
+= input_section
->output_offset
;
817 /* This is a partial relocation, but inplace, so modify the
820 If we've relocated with a symbol with a section, change
821 into a ref to the section belonging to the symbol. */
823 reloc_entry
->address
+= input_section
->output_offset
;
826 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
827 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
828 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
830 /* For m68k-coff, the addend was being subtracted twice during
831 relocation with -r. Removing the line below this comment
832 fixes that problem; see PR 2953.
834 However, Ian wrote the following, regarding removing the line below,
835 which explains why it is still enabled: --djm
837 If you put a patch like that into BFD you need to check all the COFF
838 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
839 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
840 problem in a different way. There may very well be a reason that the
841 code works as it does.
843 Hmmm. The first obvious point is that bfd_perform_relocation should
844 not have any tests that depend upon the flavour. It's seem like
845 entirely the wrong place for such a thing. The second obvious point
846 is that the current code ignores the reloc addend when producing
847 relocatable output for COFF. That's peculiar. In fact, I really
848 have no idea what the point of the line you want to remove is.
850 A typical COFF reloc subtracts the old value of the symbol and adds in
851 the new value to the location in the object file (if it's a pc
852 relative reloc it adds the difference between the symbol value and the
853 location). When relocating we need to preserve that property.
855 BFD handles this by setting the addend to the negative of the old
856 value of the symbol. Unfortunately it handles common symbols in a
857 non-standard way (it doesn't subtract the old value) but that's a
858 different story (we can't change it without losing backward
859 compatibility with old object files) (coff-i386 does subtract the old
860 value, to be compatible with existing coff-i386 targets, like SCO).
862 So everything works fine when not producing relocatable output. When
863 we are producing relocatable output, logically we should do exactly
864 what we do when not producing relocatable output. Therefore, your
865 patch is correct. In fact, it should probably always just set
866 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
867 add the value into the object file. This won't hurt the COFF code,
868 which doesn't use the addend; I'm not sure what it will do to other
869 formats (the thing to check for would be whether any formats both use
870 the addend and set partial_inplace).
872 When I wanted to make coff-i386 produce relocatable output, I ran
873 into the problem that you are running into: I wanted to remove that
874 line. Rather than risk it, I made the coff-i386 relocs use a special
875 function; it's coff_i386_reloc in coff-i386.c. The function
876 specifically adds the addend field into the object file, knowing that
877 bfd_perform_relocation is not going to. If you remove that line, then
878 coff-i386.c will wind up adding the addend field in twice. It's
879 trivial to fix; it just needs to be done.
881 The problem with removing the line is just that it may break some
882 working code. With BFD it's hard to be sure of anything. The right
883 way to deal with this is simply to build and test at least all the
884 supported COFF targets. It should be straightforward if time and disk
885 space consuming. For each target:
887 2) generate some executable, and link it using -r (I would
888 probably use paranoia.o and link against newlib/libc.a, which
889 for all the supported targets would be available in
890 /usr/cygnus/progressive/H-host/target/lib/libc.a).
891 3) make the change to reloc.c
892 4) rebuild the linker
894 6) if the resulting object files are the same, you have at least
896 7) if they are different you have to figure out which version is
899 relocation
-= reloc_entry
->addend
;
900 reloc_entry
->addend
= 0;
904 reloc_entry
->addend
= relocation
;
908 else if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
909 && (input_section
->output_section
->owner
->xvec
->flavour
910 == bfd_target_elf_flavour
)
911 && strcmp (abfd
->xvec
->name
, "pe-x86-64") == 0
912 && strcmp (input_section
->output_section
->owner
->xvec
->name
,
913 "elf64-x86-64") == 0)
915 /* NB: bfd_perform_relocation isn't called to generate PE binary.
916 _bfd_relocate_contents is called instead. When linking PE
917 object files to generate ELF output, _bfd_relocate_contents
918 isn't called and bfd_perform_relocation is used. We need to
919 adjust relocation here. */
920 relocation
-= reloc_entry
->addend
;
921 if (howto
->type
>= R_AMD64_PCRLONG_1
922 && howto
->type
<= R_AMD64_PCRLONG_5
)
923 relocation
-= (bfd_vma
)(howto
->type
- R_AMD64_PCRLONG
);
926 /* FIXME: This overflow checking is incomplete, because the value
927 might have overflowed before we get here. For a correct check we
928 need to compute the value in a size larger than bitsize, but we
929 can't reasonably do that for a reloc the same size as a host
931 FIXME: We should also do overflow checking on the result after
932 adding in the value contained in the object file. */
933 if (howto
->complain_on_overflow
!= complain_overflow_dont
934 && flag
== bfd_reloc_ok
)
935 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
938 bfd_arch_bits_per_address (abfd
),
941 /* Either we are relocating all the way, or we don't want to apply
942 the relocation to the reloc entry (probably because there isn't
943 any room in the output format to describe addends to relocs). */
945 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
946 (OSF version 1.3, compiler version 3.11). It miscompiles the
960 x <<= (unsigned long) s.i0;
964 printf ("succeeded (%lx)\n", x);
968 relocation
>>= (bfd_vma
) howto
->rightshift
;
970 /* Shift everything up to where it's going to be used. */
971 relocation
<<= (bfd_vma
) howto
->bitpos
;
973 /* Wait for the day when all have the mask in them. */
976 i instruction to be left alone
977 o offset within instruction
978 r relocation offset to apply
987 (( i i i i i o o o o o from bfd_get<size>
988 and S S S S S) to get the size offset we want
989 + r r r r r r r r r r) to get the final value to place
990 and D D D D D to chop to right size
991 -----------------------
994 ( i i i i i o o o o o from bfd_get<size>
995 and N N N N N ) get instruction
996 -----------------------
1002 -----------------------
1003 = R R R R R R R R R R put into bfd_put<size>
1006 data
= (bfd_byte
*) data
+ octets
;
1007 apply_reloc (abfd
, data
, howto
, relocation
);
1013 bfd_install_relocation
1016 bfd_reloc_status_type bfd_install_relocation
1018 arelent *reloc_entry,
1019 void *data, bfd_vma data_start,
1020 asection *input_section,
1021 char **error_message);
1024 This looks remarkably like <<bfd_perform_relocation>>, except it
1025 does not expect that the section contents have been filled in.
1026 I.e., it's suitable for use when creating, rather than applying
1029 For now, this function should be considered reserved for the
1033 bfd_reloc_status_type
1034 bfd_install_relocation (bfd
*abfd
,
1035 arelent
*reloc_entry
,
1037 bfd_vma data_start_offset
,
1038 asection
*input_section
,
1039 char **error_message
)
1042 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1043 bfd_size_type octets
;
1044 bfd_vma output_base
= 0;
1045 reloc_howto_type
*howto
= reloc_entry
->howto
;
1046 asection
*reloc_target_output_section
;
1050 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1052 /* If there is a function supplied to handle this relocation type,
1053 call it. It'll return `bfd_reloc_continue' if further processing
1055 if (howto
&& howto
->special_function
)
1057 bfd_reloc_status_type cont
;
1059 /* Note - we do not call bfd_reloc_offset_in_range here as the
1060 reloc_entry->address field might actually be valid for the
1061 backend concerned. It is up to the special_function itself
1062 to call bfd_reloc_offset_in_range if needed. */
1063 /* XXX - The special_function calls haven't been fixed up to deal
1064 with creating new relocations and section contents. */
1065 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1066 /* XXX - Non-portable! */
1067 ((bfd_byte
*) data_start
1068 - data_start_offset
),
1069 input_section
, abfd
, error_message
);
1070 if (cont
!= bfd_reloc_continue
)
1074 if (bfd_is_abs_section (symbol
->section
))
1076 reloc_entry
->address
+= input_section
->output_offset
;
1077 return bfd_reloc_ok
;
1080 /* No need to check for howto != NULL if !bfd_is_abs_section as
1081 it will have been checked in `bfd_perform_relocation already'. */
1083 /* Is the address of the relocation really within the section? */
1084 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1085 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1086 return bfd_reloc_outofrange
;
1088 /* Work out which section the relocation is targeted at and the
1089 initial relocation command value. */
1091 /* Get symbol value. (Common symbols are special.) */
1092 if (bfd_is_com_section (symbol
->section
))
1095 relocation
= symbol
->value
;
1097 reloc_target_output_section
= symbol
->section
->output_section
;
1099 /* Convert input-section-relative symbol value to absolute. */
1100 if (! howto
->partial_inplace
)
1103 output_base
= reloc_target_output_section
->vma
;
1105 output_base
+= symbol
->section
->output_offset
;
1107 /* If symbol addresses are in octets, convert to bytes. */
1108 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1109 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1110 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1112 relocation
+= output_base
;
1114 /* Add in supplied addend. */
1115 relocation
+= reloc_entry
->addend
;
1117 /* Here the variable relocation holds the final address of the
1118 symbol we are relocating against, plus any addend. */
1120 if (howto
->pc_relative
)
1122 /* This is a PC relative relocation. We want to set RELOCATION
1123 to the distance between the address of the symbol and the
1124 location. RELOCATION is already the address of the symbol.
1126 We start by subtracting the address of the section containing
1129 If pcrel_offset is set, we must further subtract the position
1130 of the location within the section. Some targets arrange for
1131 the addend to be the negative of the position of the location
1132 within the section; for example, i386-aout does this. For
1133 i386-aout, pcrel_offset is FALSE. Some other targets do not
1134 include the position of the location; for example, ELF.
1135 For those targets, pcrel_offset is TRUE.
1137 If we are producing relocatable output, then we must ensure
1138 that this reloc will be correctly computed when the final
1139 relocation is done. If pcrel_offset is FALSE we want to wind
1140 up with the negative of the location within the section,
1141 which means we must adjust the existing addend by the change
1142 in the location within the section. If pcrel_offset is TRUE
1143 we do not want to adjust the existing addend at all.
1145 FIXME: This seems logical to me, but for the case of
1146 producing relocatable output it is not what the code
1147 actually does. I don't want to change it, because it seems
1148 far too likely that something will break. */
1151 input_section
->output_section
->vma
+ input_section
->output_offset
;
1153 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1154 relocation
-= reloc_entry
->address
;
1157 if (! howto
->partial_inplace
)
1159 /* This is a partial relocation, and we want to apply the relocation
1160 to the reloc entry rather than the raw data. Modify the reloc
1161 inplace to reflect what we now know. */
1162 reloc_entry
->addend
= relocation
;
1163 reloc_entry
->address
+= input_section
->output_offset
;
1168 /* This is a partial relocation, but inplace, so modify the
1171 If we've relocated with a symbol with a section, change
1172 into a ref to the section belonging to the symbol. */
1173 reloc_entry
->address
+= input_section
->output_offset
;
1176 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1177 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1178 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1181 /* For m68k-coff, the addend was being subtracted twice during
1182 relocation with -r. Removing the line below this comment
1183 fixes that problem; see PR 2953.
1185 However, Ian wrote the following, regarding removing the line below,
1186 which explains why it is still enabled: --djm
1188 If you put a patch like that into BFD you need to check all the COFF
1189 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1190 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1191 problem in a different way. There may very well be a reason that the
1192 code works as it does.
1194 Hmmm. The first obvious point is that bfd_install_relocation should
1195 not have any tests that depend upon the flavour. It's seem like
1196 entirely the wrong place for such a thing. The second obvious point
1197 is that the current code ignores the reloc addend when producing
1198 relocatable output for COFF. That's peculiar. In fact, I really
1199 have no idea what the point of the line you want to remove is.
1201 A typical COFF reloc subtracts the old value of the symbol and adds in
1202 the new value to the location in the object file (if it's a pc
1203 relative reloc it adds the difference between the symbol value and the
1204 location). When relocating we need to preserve that property.
1206 BFD handles this by setting the addend to the negative of the old
1207 value of the symbol. Unfortunately it handles common symbols in a
1208 non-standard way (it doesn't subtract the old value) but that's a
1209 different story (we can't change it without losing backward
1210 compatibility with old object files) (coff-i386 does subtract the old
1211 value, to be compatible with existing coff-i386 targets, like SCO).
1213 So everything works fine when not producing relocatable output. When
1214 we are producing relocatable output, logically we should do exactly
1215 what we do when not producing relocatable output. Therefore, your
1216 patch is correct. In fact, it should probably always just set
1217 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1218 add the value into the object file. This won't hurt the COFF code,
1219 which doesn't use the addend; I'm not sure what it will do to other
1220 formats (the thing to check for would be whether any formats both use
1221 the addend and set partial_inplace).
1223 When I wanted to make coff-i386 produce relocatable output, I ran
1224 into the problem that you are running into: I wanted to remove that
1225 line. Rather than risk it, I made the coff-i386 relocs use a special
1226 function; it's coff_i386_reloc in coff-i386.c. The function
1227 specifically adds the addend field into the object file, knowing that
1228 bfd_install_relocation is not going to. If you remove that line, then
1229 coff-i386.c will wind up adding the addend field in twice. It's
1230 trivial to fix; it just needs to be done.
1232 The problem with removing the line is just that it may break some
1233 working code. With BFD it's hard to be sure of anything. The right
1234 way to deal with this is simply to build and test at least all the
1235 supported COFF targets. It should be straightforward if time and disk
1236 space consuming. For each target:
1238 2) generate some executable, and link it using -r (I would
1239 probably use paranoia.o and link against newlib/libc.a, which
1240 for all the supported targets would be available in
1241 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1242 3) make the change to reloc.c
1243 4) rebuild the linker
1245 6) if the resulting object files are the same, you have at least
1247 7) if they are different you have to figure out which version is
1249 relocation
-= reloc_entry
->addend
;
1250 /* FIXME: There should be no target specific code here... */
1251 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1252 reloc_entry
->addend
= 0;
1256 reloc_entry
->addend
= relocation
;
1260 /* FIXME: This overflow checking is incomplete, because the value
1261 might have overflowed before we get here. For a correct check we
1262 need to compute the value in a size larger than bitsize, but we
1263 can't reasonably do that for a reloc the same size as a host
1265 FIXME: We should also do overflow checking on the result after
1266 adding in the value contained in the object file. */
1267 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1268 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1271 bfd_arch_bits_per_address (abfd
),
1274 /* Either we are relocating all the way, or we don't want to apply
1275 the relocation to the reloc entry (probably because there isn't
1276 any room in the output format to describe addends to relocs). */
1278 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1279 (OSF version 1.3, compiler version 3.11). It miscompiles the
1293 x <<= (unsigned long) s.i0;
1295 printf ("failed\n");
1297 printf ("succeeded (%lx)\n", x);
1301 relocation
>>= (bfd_vma
) howto
->rightshift
;
1303 /* Shift everything up to where it's going to be used. */
1304 relocation
<<= (bfd_vma
) howto
->bitpos
;
1306 /* Wait for the day when all have the mask in them. */
1309 i instruction to be left alone
1310 o offset within instruction
1311 r relocation offset to apply
1320 (( i i i i i o o o o o from bfd_get<size>
1321 and S S S S S) to get the size offset we want
1322 + r r r r r r r r r r) to get the final value to place
1323 and D D D D D to chop to right size
1324 -----------------------
1327 ( i i i i i o o o o o from bfd_get<size>
1328 and N N N N N ) get instruction
1329 -----------------------
1335 -----------------------
1336 = R R R R R R R R R R put into bfd_put<size>
1339 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1340 apply_reloc (abfd
, data
, howto
, relocation
);
1344 /* This relocation routine is used by some of the backend linkers.
1345 They do not construct asymbol or arelent structures, so there is no
1346 reason for them to use bfd_perform_relocation. Also,
1347 bfd_perform_relocation is so hacked up it is easier to write a new
1348 function than to try to deal with it.
1350 This routine does a final relocation. Whether it is useful for a
1351 relocatable link depends upon how the object format defines
1354 FIXME: This routine ignores any special_function in the HOWTO,
1355 since the existing special_function values have been written for
1356 bfd_perform_relocation.
1358 HOWTO is the reloc howto information.
1359 INPUT_BFD is the BFD which the reloc applies to.
1360 INPUT_SECTION is the section which the reloc applies to.
1361 CONTENTS is the contents of the section.
1362 ADDRESS is the address of the reloc within INPUT_SECTION.
1363 VALUE is the value of the symbol the reloc refers to.
1364 ADDEND is the addend of the reloc. */
1366 bfd_reloc_status_type
1367 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1369 asection
*input_section
,
1376 bfd_size_type octets
= (address
1377 * bfd_octets_per_byte (input_bfd
, input_section
));
1379 /* Sanity check the address. */
1380 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1381 return bfd_reloc_outofrange
;
1383 /* This function assumes that we are dealing with a basic relocation
1384 against a symbol. We want to compute the value of the symbol to
1385 relocate to. This is just VALUE, the value of the symbol, plus
1386 ADDEND, any addend associated with the reloc. */
1387 relocation
= value
+ addend
;
1389 /* If the relocation is PC relative, we want to set RELOCATION to
1390 the distance between the symbol (currently in RELOCATION) and the
1391 location we are relocating. Some targets (e.g., i386-aout)
1392 arrange for the contents of the section to be the negative of the
1393 offset of the location within the section; for such targets
1394 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1395 the contents of the section as zero; for such targets
1396 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1397 subtract out the offset of the location within the section (which
1398 is just ADDRESS). */
1399 if (howto
->pc_relative
)
1401 relocation
-= (input_section
->output_section
->vma
1402 + input_section
->output_offset
);
1403 if (howto
->pcrel_offset
)
1404 relocation
-= address
;
1407 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1411 /* Relocate a given location using a given value and howto. */
1413 bfd_reloc_status_type
1414 _bfd_relocate_contents (reloc_howto_type
*howto
,
1420 bfd_reloc_status_type flag
;
1421 unsigned int rightshift
= howto
->rightshift
;
1422 unsigned int bitpos
= howto
->bitpos
;
1425 relocation
= -relocation
;
1427 /* Get the value we are going to relocate. */
1428 x
= read_reloc (input_bfd
, location
, howto
);
1430 /* Check for overflow. FIXME: We may drop bits during the addition
1431 which we don't check for. We must either check at every single
1432 operation, which would be tedious, or we must do the computations
1433 in a type larger than bfd_vma, which would be inefficient. */
1434 flag
= bfd_reloc_ok
;
1435 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1437 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1440 /* Get the values to be added together. For signed and unsigned
1441 relocations, we assume that all values should be truncated to
1442 the size of an address. For bitfields, all the bits matter.
1443 See also bfd_check_overflow. */
1444 fieldmask
= N_ONES (howto
->bitsize
);
1445 signmask
= ~fieldmask
;
1446 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1447 | (fieldmask
<< rightshift
));
1448 a
= (relocation
& addrmask
) >> rightshift
;
1449 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1450 addrmask
>>= rightshift
;
1452 switch (howto
->complain_on_overflow
)
1454 case complain_overflow_signed
:
1455 /* If any sign bits are set, all sign bits must be set.
1456 That is, A must be a valid negative address after
1458 signmask
= ~(fieldmask
>> 1);
1461 case complain_overflow_bitfield
:
1462 /* Much like the signed check, but for a field one bit
1463 wider. We allow a bitfield to represent numbers in the
1464 range -2**n to 2**n-1, where n is the number of bits in the
1465 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1466 can't overflow, which is exactly what we want. */
1468 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1469 flag
= bfd_reloc_overflow
;
1471 /* We only need this next bit of code if the sign bit of B
1472 is below the sign bit of A. This would only happen if
1473 SRC_MASK had fewer bits than BITSIZE. Note that if
1474 SRC_MASK has more bits than BITSIZE, we can get into
1475 trouble; we would need to verify that B is in range, as
1476 we do for A above. */
1477 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1480 /* Set all the bits above the sign bit. */
1483 /* Now we can do the addition. */
1486 /* See if the result has the correct sign. Bits above the
1487 sign bit are junk now; ignore them. If the sum is
1488 positive, make sure we did not have all negative inputs;
1489 if the sum is negative, make sure we did not have all
1490 positive inputs. The test below looks only at the sign
1491 bits, and it really just
1492 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1494 We mask with addrmask here to explicitly allow an address
1495 wrap-around. The Linux kernel relies on it, and it is
1496 the only way to write assembler code which can run when
1497 loaded at a location 0x80000000 away from the location at
1498 which it is linked. */
1499 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1500 flag
= bfd_reloc_overflow
;
1503 case complain_overflow_unsigned
:
1504 /* Checking for an unsigned overflow is relatively easy:
1505 trim the addresses and add, and trim the result as well.
1506 Overflow is normally indicated when the result does not
1507 fit in the field. However, we also need to consider the
1508 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1509 input is 0x80000000, and bfd_vma is only 32 bits; then we
1510 will get sum == 0, but there is an overflow, since the
1511 inputs did not fit in the field. Instead of doing a
1512 separate test, we can check for this by or-ing in the
1513 operands when testing for the sum overflowing its final
1515 sum
= (a
+ b
) & addrmask
;
1516 if ((a
| b
| sum
) & signmask
)
1517 flag
= bfd_reloc_overflow
;
1525 /* Put RELOCATION in the right bits. */
1526 relocation
>>= (bfd_vma
) rightshift
;
1527 relocation
<<= (bfd_vma
) bitpos
;
1529 /* Add RELOCATION to the right bits of X. */
1530 x
= ((x
& ~howto
->dst_mask
)
1531 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1533 /* Put the relocated value back in the object file. */
1534 write_reloc (input_bfd
, x
, location
, howto
);
1538 /* Clear a given location using a given howto, by applying a fixed relocation
1539 value and discarding any in-place addend. This is used for fixed-up
1540 relocations against discarded symbols, to make ignorable debug or unwind
1541 information more obvious. */
1543 bfd_reloc_status_type
1544 _bfd_clear_contents (reloc_howto_type
*howto
,
1546 asection
*input_section
,
1553 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1554 return bfd_reloc_outofrange
;
1556 /* Get the value we are going to relocate. */
1557 location
= buf
+ off
;
1558 x
= read_reloc (input_bfd
, location
, howto
);
1560 /* Zero out the unwanted bits of X. */
1561 x
&= ~howto
->dst_mask
;
1563 /* For a range list, use 1 instead of 0 as placeholder. 0
1564 would terminate the list, hiding any later entries. */
1565 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1566 && (howto
->dst_mask
& 1) != 0)
1569 /* Put the relocated value back in the object file. */
1570 write_reloc (input_bfd
, x
, location
, howto
);
1571 return bfd_reloc_ok
;
1577 howto manager, , typedef arelent, Relocations
1582 When an application wants to create a relocation, but doesn't
1583 know what the target machine might call it, it can find out by
1584 using this bit of code.
1593 The insides of a reloc code. The idea is that, eventually, there
1594 will be one enumerator for every type of relocation we ever do.
1595 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1596 return a howto pointer.
1598 This does mean that the application must determine the correct
1599 enumerator value; you can't get a howto pointer from a random set
1620 Basic absolute relocations of N bits.
1635 PC-relative relocations. Sometimes these are relative to the address
1636 of the relocation itself; sometimes they are relative to the start of
1637 the section containing the relocation. It depends on the specific target.
1642 Section relative relocations. Some targets need this for DWARF2.
1645 BFD_RELOC_32_GOT_PCREL
1647 BFD_RELOC_16_GOT_PCREL
1649 BFD_RELOC_8_GOT_PCREL
1655 BFD_RELOC_LO16_GOTOFF
1657 BFD_RELOC_HI16_GOTOFF
1659 BFD_RELOC_HI16_S_GOTOFF
1663 BFD_RELOC_64_PLT_PCREL
1665 BFD_RELOC_32_PLT_PCREL
1667 BFD_RELOC_24_PLT_PCREL
1669 BFD_RELOC_16_PLT_PCREL
1671 BFD_RELOC_8_PLT_PCREL
1679 BFD_RELOC_LO16_PLTOFF
1681 BFD_RELOC_HI16_PLTOFF
1683 BFD_RELOC_HI16_S_PLTOFF
1697 BFD_RELOC_68K_GLOB_DAT
1699 BFD_RELOC_68K_JMP_SLOT
1701 BFD_RELOC_68K_RELATIVE
1703 BFD_RELOC_68K_TLS_GD32
1705 BFD_RELOC_68K_TLS_GD16
1707 BFD_RELOC_68K_TLS_GD8
1709 BFD_RELOC_68K_TLS_LDM32
1711 BFD_RELOC_68K_TLS_LDM16
1713 BFD_RELOC_68K_TLS_LDM8
1715 BFD_RELOC_68K_TLS_LDO32
1717 BFD_RELOC_68K_TLS_LDO16
1719 BFD_RELOC_68K_TLS_LDO8
1721 BFD_RELOC_68K_TLS_IE32
1723 BFD_RELOC_68K_TLS_IE16
1725 BFD_RELOC_68K_TLS_IE8
1727 BFD_RELOC_68K_TLS_LE32
1729 BFD_RELOC_68K_TLS_LE16
1731 BFD_RELOC_68K_TLS_LE8
1733 Relocations used by 68K ELF.
1736 BFD_RELOC_32_BASEREL
1738 BFD_RELOC_16_BASEREL
1740 BFD_RELOC_LO16_BASEREL
1742 BFD_RELOC_HI16_BASEREL
1744 BFD_RELOC_HI16_S_BASEREL
1750 Linkage-table relative.
1755 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1758 BFD_RELOC_32_PCREL_S2
1760 BFD_RELOC_16_PCREL_S2
1762 BFD_RELOC_23_PCREL_S2
1764 These PC-relative relocations are stored as word displacements --
1765 i.e., byte displacements shifted right two bits. The 30-bit word
1766 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1767 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1768 signed 16-bit displacement is used on the MIPS, and the 23-bit
1769 displacement is used on the Alpha.
1776 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1777 the target word. These are used on the SPARC.
1784 For systems that allocate a Global Pointer register, these are
1785 displacements off that register. These relocation types are
1786 handled specially, because the value the register will have is
1787 decided relatively late.
1792 BFD_RELOC_SPARC_WDISP22
1798 BFD_RELOC_SPARC_GOT10
1800 BFD_RELOC_SPARC_GOT13
1802 BFD_RELOC_SPARC_GOT22
1804 BFD_RELOC_SPARC_PC10
1806 BFD_RELOC_SPARC_PC22
1808 BFD_RELOC_SPARC_WPLT30
1810 BFD_RELOC_SPARC_COPY
1812 BFD_RELOC_SPARC_GLOB_DAT
1814 BFD_RELOC_SPARC_JMP_SLOT
1816 BFD_RELOC_SPARC_RELATIVE
1818 BFD_RELOC_SPARC_UA16
1820 BFD_RELOC_SPARC_UA32
1822 BFD_RELOC_SPARC_UA64
1824 BFD_RELOC_SPARC_GOTDATA_HIX22
1826 BFD_RELOC_SPARC_GOTDATA_LOX10
1828 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1830 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1832 BFD_RELOC_SPARC_GOTDATA_OP
1834 BFD_RELOC_SPARC_JMP_IREL
1836 BFD_RELOC_SPARC_IRELATIVE
1838 SPARC ELF relocations. There is probably some overlap with other
1839 relocation types already defined.
1842 BFD_RELOC_SPARC_BASE13
1844 BFD_RELOC_SPARC_BASE22
1846 I think these are specific to SPARC a.out (e.g., Sun 4).
1856 BFD_RELOC_SPARC_OLO10
1858 BFD_RELOC_SPARC_HH22
1860 BFD_RELOC_SPARC_HM10
1862 BFD_RELOC_SPARC_LM22
1864 BFD_RELOC_SPARC_PC_HH22
1866 BFD_RELOC_SPARC_PC_HM10
1868 BFD_RELOC_SPARC_PC_LM22
1870 BFD_RELOC_SPARC_WDISP16
1872 BFD_RELOC_SPARC_WDISP19
1880 BFD_RELOC_SPARC_DISP64
1883 BFD_RELOC_SPARC_PLT32
1885 BFD_RELOC_SPARC_PLT64
1887 BFD_RELOC_SPARC_HIX22
1889 BFD_RELOC_SPARC_LOX10
1897 BFD_RELOC_SPARC_REGISTER
1901 BFD_RELOC_SPARC_SIZE32
1903 BFD_RELOC_SPARC_SIZE64
1905 BFD_RELOC_SPARC_WDISP10
1910 BFD_RELOC_SPARC_REV32
1912 SPARC little endian relocation
1914 BFD_RELOC_SPARC_TLS_GD_HI22
1916 BFD_RELOC_SPARC_TLS_GD_LO10
1918 BFD_RELOC_SPARC_TLS_GD_ADD
1920 BFD_RELOC_SPARC_TLS_GD_CALL
1922 BFD_RELOC_SPARC_TLS_LDM_HI22
1924 BFD_RELOC_SPARC_TLS_LDM_LO10
1926 BFD_RELOC_SPARC_TLS_LDM_ADD
1928 BFD_RELOC_SPARC_TLS_LDM_CALL
1930 BFD_RELOC_SPARC_TLS_LDO_HIX22
1932 BFD_RELOC_SPARC_TLS_LDO_LOX10
1934 BFD_RELOC_SPARC_TLS_LDO_ADD
1936 BFD_RELOC_SPARC_TLS_IE_HI22
1938 BFD_RELOC_SPARC_TLS_IE_LO10
1940 BFD_RELOC_SPARC_TLS_IE_LD
1942 BFD_RELOC_SPARC_TLS_IE_LDX
1944 BFD_RELOC_SPARC_TLS_IE_ADD
1946 BFD_RELOC_SPARC_TLS_LE_HIX22
1948 BFD_RELOC_SPARC_TLS_LE_LOX10
1950 BFD_RELOC_SPARC_TLS_DTPMOD32
1952 BFD_RELOC_SPARC_TLS_DTPMOD64
1954 BFD_RELOC_SPARC_TLS_DTPOFF32
1956 BFD_RELOC_SPARC_TLS_DTPOFF64
1958 BFD_RELOC_SPARC_TLS_TPOFF32
1960 BFD_RELOC_SPARC_TLS_TPOFF64
1962 SPARC TLS relocations
1971 BFD_RELOC_SPU_IMM10W
1975 BFD_RELOC_SPU_IMM16W
1979 BFD_RELOC_SPU_PCREL9a
1981 BFD_RELOC_SPU_PCREL9b
1983 BFD_RELOC_SPU_PCREL16
1993 BFD_RELOC_SPU_ADD_PIC
1998 BFD_RELOC_ALPHA_GPDISP_HI16
2000 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2001 "addend" in some special way.
2002 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2003 writing; when reading, it will be the absolute section symbol. The
2004 addend is the displacement in bytes of the "lda" instruction from
2005 the "ldah" instruction (which is at the address of this reloc).
2007 BFD_RELOC_ALPHA_GPDISP_LO16
2009 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2010 with GPDISP_HI16 relocs. The addend is ignored when writing the
2011 relocations out, and is filled in with the file's GP value on
2012 reading, for convenience.
2015 BFD_RELOC_ALPHA_GPDISP
2017 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2018 relocation except that there is no accompanying GPDISP_LO16
2022 BFD_RELOC_ALPHA_LITERAL
2024 BFD_RELOC_ALPHA_ELF_LITERAL
2026 BFD_RELOC_ALPHA_LITUSE
2028 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2029 the assembler turns it into a LDQ instruction to load the address of
2030 the symbol, and then fills in a register in the real instruction.
2032 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2033 section symbol. The addend is ignored when writing, but is filled
2034 in with the file's GP value on reading, for convenience, as with the
2037 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2038 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2039 but it generates output not based on the position within the .got
2040 section, but relative to the GP value chosen for the file during the
2043 The LITUSE reloc, on the instruction using the loaded address, gives
2044 information to the linker that it might be able to use to optimize
2045 away some literal section references. The symbol is ignored (read
2046 as the absolute section symbol), and the "addend" indicates the type
2047 of instruction using the register:
2048 1 - "memory" fmt insn
2049 2 - byte-manipulation (byte offset reg)
2050 3 - jsr (target of branch)
2053 BFD_RELOC_ALPHA_HINT
2055 The HINT relocation indicates a value that should be filled into the
2056 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2057 prediction logic which may be provided on some processors.
2060 BFD_RELOC_ALPHA_LINKAGE
2062 The LINKAGE relocation outputs a linkage pair in the object file,
2063 which is filled by the linker.
2066 BFD_RELOC_ALPHA_CODEADDR
2068 The CODEADDR relocation outputs a STO_CA in the object file,
2069 which is filled by the linker.
2072 BFD_RELOC_ALPHA_GPREL_HI16
2074 BFD_RELOC_ALPHA_GPREL_LO16
2076 The GPREL_HI/LO relocations together form a 32-bit offset from the
2080 BFD_RELOC_ALPHA_BRSGP
2082 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2083 share a common GP, and the target address is adjusted for
2084 STO_ALPHA_STD_GPLOAD.
2089 The NOP relocation outputs a NOP if the longword displacement
2090 between two procedure entry points is < 2^21.
2095 The BSR relocation outputs a BSR if the longword displacement
2096 between two procedure entry points is < 2^21.
2101 The LDA relocation outputs a LDA if the longword displacement
2102 between two procedure entry points is < 2^16.
2107 The BOH relocation outputs a BSR if the longword displacement
2108 between two procedure entry points is < 2^21, or else a hint.
2111 BFD_RELOC_ALPHA_TLSGD
2113 BFD_RELOC_ALPHA_TLSLDM
2115 BFD_RELOC_ALPHA_DTPMOD64
2117 BFD_RELOC_ALPHA_GOTDTPREL16
2119 BFD_RELOC_ALPHA_DTPREL64
2121 BFD_RELOC_ALPHA_DTPREL_HI16
2123 BFD_RELOC_ALPHA_DTPREL_LO16
2125 BFD_RELOC_ALPHA_DTPREL16
2127 BFD_RELOC_ALPHA_GOTTPREL16
2129 BFD_RELOC_ALPHA_TPREL64
2131 BFD_RELOC_ALPHA_TPREL_HI16
2133 BFD_RELOC_ALPHA_TPREL_LO16
2135 BFD_RELOC_ALPHA_TPREL16
2137 Alpha thread-local storage relocations.
2142 BFD_RELOC_MICROMIPS_JMP
2144 The MIPS jump instruction.
2147 BFD_RELOC_MIPS16_JMP
2149 The MIPS16 jump instruction.
2152 BFD_RELOC_MIPS16_GPREL
2154 MIPS16 GP relative reloc.
2159 High 16 bits of 32-bit value; simple reloc.
2164 High 16 bits of 32-bit value but the low 16 bits will be sign
2165 extended and added to form the final result. If the low 16
2166 bits form a negative number, we need to add one to the high value
2167 to compensate for the borrow when the low bits are added.
2175 BFD_RELOC_HI16_PCREL
2177 High 16 bits of 32-bit pc-relative value
2179 BFD_RELOC_HI16_S_PCREL
2181 High 16 bits of 32-bit pc-relative value, adjusted
2183 BFD_RELOC_LO16_PCREL
2185 Low 16 bits of pc-relative value
2188 BFD_RELOC_MIPS16_GOT16
2190 BFD_RELOC_MIPS16_CALL16
2192 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2193 16-bit immediate fields
2195 BFD_RELOC_MIPS16_HI16
2197 MIPS16 high 16 bits of 32-bit value.
2199 BFD_RELOC_MIPS16_HI16_S
2201 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2202 extended and added to form the final result. If the low 16
2203 bits form a negative number, we need to add one to the high value
2204 to compensate for the borrow when the low bits are added.
2206 BFD_RELOC_MIPS16_LO16
2211 BFD_RELOC_MIPS16_TLS_GD
2213 BFD_RELOC_MIPS16_TLS_LDM
2215 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2217 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2219 BFD_RELOC_MIPS16_TLS_GOTTPREL
2221 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2223 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2225 MIPS16 TLS relocations
2228 BFD_RELOC_MIPS_LITERAL
2230 BFD_RELOC_MICROMIPS_LITERAL
2232 Relocation against a MIPS literal section.
2235 BFD_RELOC_MICROMIPS_7_PCREL_S1
2237 BFD_RELOC_MICROMIPS_10_PCREL_S1
2239 BFD_RELOC_MICROMIPS_16_PCREL_S1
2241 microMIPS PC-relative relocations.
2244 BFD_RELOC_MIPS16_16_PCREL_S1
2246 MIPS16 PC-relative relocation.
2249 BFD_RELOC_MIPS_21_PCREL_S2
2251 BFD_RELOC_MIPS_26_PCREL_S2
2253 BFD_RELOC_MIPS_18_PCREL_S3
2255 BFD_RELOC_MIPS_19_PCREL_S2
2257 MIPS PC-relative relocations.
2260 BFD_RELOC_MICROMIPS_GPREL16
2262 BFD_RELOC_MICROMIPS_HI16
2264 BFD_RELOC_MICROMIPS_HI16_S
2266 BFD_RELOC_MICROMIPS_LO16
2268 microMIPS versions of generic BFD relocs.
2271 BFD_RELOC_MIPS_GOT16
2273 BFD_RELOC_MICROMIPS_GOT16
2275 BFD_RELOC_MIPS_CALL16
2277 BFD_RELOC_MICROMIPS_CALL16
2279 BFD_RELOC_MIPS_GOT_HI16
2281 BFD_RELOC_MICROMIPS_GOT_HI16
2283 BFD_RELOC_MIPS_GOT_LO16
2285 BFD_RELOC_MICROMIPS_GOT_LO16
2287 BFD_RELOC_MIPS_CALL_HI16
2289 BFD_RELOC_MICROMIPS_CALL_HI16
2291 BFD_RELOC_MIPS_CALL_LO16
2293 BFD_RELOC_MICROMIPS_CALL_LO16
2297 BFD_RELOC_MICROMIPS_SUB
2299 BFD_RELOC_MIPS_GOT_PAGE
2301 BFD_RELOC_MICROMIPS_GOT_PAGE
2303 BFD_RELOC_MIPS_GOT_OFST
2305 BFD_RELOC_MICROMIPS_GOT_OFST
2307 BFD_RELOC_MIPS_GOT_DISP
2309 BFD_RELOC_MICROMIPS_GOT_DISP
2311 BFD_RELOC_MIPS_SHIFT5
2313 BFD_RELOC_MIPS_SHIFT6
2315 BFD_RELOC_MIPS_INSERT_A
2317 BFD_RELOC_MIPS_INSERT_B
2319 BFD_RELOC_MIPS_DELETE
2321 BFD_RELOC_MIPS_HIGHEST
2323 BFD_RELOC_MICROMIPS_HIGHEST
2325 BFD_RELOC_MIPS_HIGHER
2327 BFD_RELOC_MICROMIPS_HIGHER
2329 BFD_RELOC_MIPS_SCN_DISP
2331 BFD_RELOC_MICROMIPS_SCN_DISP
2333 BFD_RELOC_MIPS_REL16
2335 BFD_RELOC_MIPS_RELGOT
2339 BFD_RELOC_MICROMIPS_JALR
2341 BFD_RELOC_MIPS_TLS_DTPMOD32
2343 BFD_RELOC_MIPS_TLS_DTPREL32
2345 BFD_RELOC_MIPS_TLS_DTPMOD64
2347 BFD_RELOC_MIPS_TLS_DTPREL64
2349 BFD_RELOC_MIPS_TLS_GD
2351 BFD_RELOC_MICROMIPS_TLS_GD
2353 BFD_RELOC_MIPS_TLS_LDM
2355 BFD_RELOC_MICROMIPS_TLS_LDM
2357 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2359 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2361 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2363 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2365 BFD_RELOC_MIPS_TLS_GOTTPREL
2367 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2369 BFD_RELOC_MIPS_TLS_TPREL32
2371 BFD_RELOC_MIPS_TLS_TPREL64
2373 BFD_RELOC_MIPS_TLS_TPREL_HI16
2375 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2377 BFD_RELOC_MIPS_TLS_TPREL_LO16
2379 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2383 MIPS ELF relocations.
2389 BFD_RELOC_MIPS_JUMP_SLOT
2391 MIPS ELF relocations (VxWorks and PLT extensions).
2395 BFD_RELOC_MOXIE_10_PCREL
2397 Moxie ELF relocations.
2409 BFD_RELOC_FT32_RELAX
2417 BFD_RELOC_FT32_DIFF32
2419 FT32 ELF relocations.
2423 BFD_RELOC_FRV_LABEL16
2425 BFD_RELOC_FRV_LABEL24
2431 BFD_RELOC_FRV_GPREL12
2433 BFD_RELOC_FRV_GPRELU12
2435 BFD_RELOC_FRV_GPREL32
2437 BFD_RELOC_FRV_GPRELHI
2439 BFD_RELOC_FRV_GPRELLO
2447 BFD_RELOC_FRV_FUNCDESC
2449 BFD_RELOC_FRV_FUNCDESC_GOT12
2451 BFD_RELOC_FRV_FUNCDESC_GOTHI
2453 BFD_RELOC_FRV_FUNCDESC_GOTLO
2455 BFD_RELOC_FRV_FUNCDESC_VALUE
2457 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2459 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2461 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2463 BFD_RELOC_FRV_GOTOFF12
2465 BFD_RELOC_FRV_GOTOFFHI
2467 BFD_RELOC_FRV_GOTOFFLO
2469 BFD_RELOC_FRV_GETTLSOFF
2471 BFD_RELOC_FRV_TLSDESC_VALUE
2473 BFD_RELOC_FRV_GOTTLSDESC12
2475 BFD_RELOC_FRV_GOTTLSDESCHI
2477 BFD_RELOC_FRV_GOTTLSDESCLO
2479 BFD_RELOC_FRV_TLSMOFF12
2481 BFD_RELOC_FRV_TLSMOFFHI
2483 BFD_RELOC_FRV_TLSMOFFLO
2485 BFD_RELOC_FRV_GOTTLSOFF12
2487 BFD_RELOC_FRV_GOTTLSOFFHI
2489 BFD_RELOC_FRV_GOTTLSOFFLO
2491 BFD_RELOC_FRV_TLSOFF
2493 BFD_RELOC_FRV_TLSDESC_RELAX
2495 BFD_RELOC_FRV_GETTLSOFF_RELAX
2497 BFD_RELOC_FRV_TLSOFF_RELAX
2499 BFD_RELOC_FRV_TLSMOFF
2501 Fujitsu Frv Relocations.
2505 BFD_RELOC_MN10300_GOTOFF24
2507 This is a 24bit GOT-relative reloc for the mn10300.
2509 BFD_RELOC_MN10300_GOT32
2511 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2514 BFD_RELOC_MN10300_GOT24
2516 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2519 BFD_RELOC_MN10300_GOT16
2521 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2524 BFD_RELOC_MN10300_COPY
2526 Copy symbol at runtime.
2528 BFD_RELOC_MN10300_GLOB_DAT
2532 BFD_RELOC_MN10300_JMP_SLOT
2536 BFD_RELOC_MN10300_RELATIVE
2538 Adjust by program base.
2540 BFD_RELOC_MN10300_SYM_DIFF
2542 Together with another reloc targeted at the same location,
2543 allows for a value that is the difference of two symbols
2544 in the same section.
2546 BFD_RELOC_MN10300_ALIGN
2548 The addend of this reloc is an alignment power that must
2549 be honoured at the offset's location, regardless of linker
2552 BFD_RELOC_MN10300_TLS_GD
2554 BFD_RELOC_MN10300_TLS_LD
2556 BFD_RELOC_MN10300_TLS_LDO
2558 BFD_RELOC_MN10300_TLS_GOTIE
2560 BFD_RELOC_MN10300_TLS_IE
2562 BFD_RELOC_MN10300_TLS_LE
2564 BFD_RELOC_MN10300_TLS_DTPMOD
2566 BFD_RELOC_MN10300_TLS_DTPOFF
2568 BFD_RELOC_MN10300_TLS_TPOFF
2570 Various TLS-related relocations.
2572 BFD_RELOC_MN10300_32_PCREL
2574 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2577 BFD_RELOC_MN10300_16_PCREL
2579 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2590 BFD_RELOC_386_GLOB_DAT
2592 BFD_RELOC_386_JUMP_SLOT
2594 BFD_RELOC_386_RELATIVE
2596 BFD_RELOC_386_GOTOFF
2600 BFD_RELOC_386_TLS_TPOFF
2602 BFD_RELOC_386_TLS_IE
2604 BFD_RELOC_386_TLS_GOTIE
2606 BFD_RELOC_386_TLS_LE
2608 BFD_RELOC_386_TLS_GD
2610 BFD_RELOC_386_TLS_LDM
2612 BFD_RELOC_386_TLS_LDO_32
2614 BFD_RELOC_386_TLS_IE_32
2616 BFD_RELOC_386_TLS_LE_32
2618 BFD_RELOC_386_TLS_DTPMOD32
2620 BFD_RELOC_386_TLS_DTPOFF32
2622 BFD_RELOC_386_TLS_TPOFF32
2624 BFD_RELOC_386_TLS_GOTDESC
2626 BFD_RELOC_386_TLS_DESC_CALL
2628 BFD_RELOC_386_TLS_DESC
2630 BFD_RELOC_386_IRELATIVE
2632 BFD_RELOC_386_GOT32X
2634 i386/elf relocations
2637 BFD_RELOC_X86_64_GOT32
2639 BFD_RELOC_X86_64_PLT32
2641 BFD_RELOC_X86_64_COPY
2643 BFD_RELOC_X86_64_GLOB_DAT
2645 BFD_RELOC_X86_64_JUMP_SLOT
2647 BFD_RELOC_X86_64_RELATIVE
2649 BFD_RELOC_X86_64_GOTPCREL
2651 BFD_RELOC_X86_64_32S
2653 BFD_RELOC_X86_64_DTPMOD64
2655 BFD_RELOC_X86_64_DTPOFF64
2657 BFD_RELOC_X86_64_TPOFF64
2659 BFD_RELOC_X86_64_TLSGD
2661 BFD_RELOC_X86_64_TLSLD
2663 BFD_RELOC_X86_64_DTPOFF32
2665 BFD_RELOC_X86_64_GOTTPOFF
2667 BFD_RELOC_X86_64_TPOFF32
2669 BFD_RELOC_X86_64_GOTOFF64
2671 BFD_RELOC_X86_64_GOTPC32
2673 BFD_RELOC_X86_64_GOT64
2675 BFD_RELOC_X86_64_GOTPCREL64
2677 BFD_RELOC_X86_64_GOTPC64
2679 BFD_RELOC_X86_64_GOTPLT64
2681 BFD_RELOC_X86_64_PLTOFF64
2683 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2685 BFD_RELOC_X86_64_TLSDESC_CALL
2687 BFD_RELOC_X86_64_TLSDESC
2689 BFD_RELOC_X86_64_IRELATIVE
2691 BFD_RELOC_X86_64_PC32_BND
2693 BFD_RELOC_X86_64_PLT32_BND
2695 BFD_RELOC_X86_64_GOTPCRELX
2697 BFD_RELOC_X86_64_REX_GOTPCRELX
2699 x86-64/elf relocations
2702 BFD_RELOC_NS32K_IMM_8
2704 BFD_RELOC_NS32K_IMM_16
2706 BFD_RELOC_NS32K_IMM_32
2708 BFD_RELOC_NS32K_IMM_8_PCREL
2710 BFD_RELOC_NS32K_IMM_16_PCREL
2712 BFD_RELOC_NS32K_IMM_32_PCREL
2714 BFD_RELOC_NS32K_DISP_8
2716 BFD_RELOC_NS32K_DISP_16
2718 BFD_RELOC_NS32K_DISP_32
2720 BFD_RELOC_NS32K_DISP_8_PCREL
2722 BFD_RELOC_NS32K_DISP_16_PCREL
2724 BFD_RELOC_NS32K_DISP_32_PCREL
2729 BFD_RELOC_PDP11_DISP_8_PCREL
2731 BFD_RELOC_PDP11_DISP_6_PCREL
2736 BFD_RELOC_PJ_CODE_HI16
2738 BFD_RELOC_PJ_CODE_LO16
2740 BFD_RELOC_PJ_CODE_DIR16
2742 BFD_RELOC_PJ_CODE_DIR32
2744 BFD_RELOC_PJ_CODE_REL16
2746 BFD_RELOC_PJ_CODE_REL32
2748 Picojava relocs. Not all of these appear in object files.
2759 BFD_RELOC_PPC_B16_BRTAKEN
2761 BFD_RELOC_PPC_B16_BRNTAKEN
2765 BFD_RELOC_PPC_BA16_BRTAKEN
2767 BFD_RELOC_PPC_BA16_BRNTAKEN
2771 BFD_RELOC_PPC_GLOB_DAT
2773 BFD_RELOC_PPC_JMP_SLOT
2775 BFD_RELOC_PPC_RELATIVE
2777 BFD_RELOC_PPC_LOCAL24PC
2779 BFD_RELOC_PPC_EMB_NADDR32
2781 BFD_RELOC_PPC_EMB_NADDR16
2783 BFD_RELOC_PPC_EMB_NADDR16_LO
2785 BFD_RELOC_PPC_EMB_NADDR16_HI
2787 BFD_RELOC_PPC_EMB_NADDR16_HA
2789 BFD_RELOC_PPC_EMB_SDAI16
2791 BFD_RELOC_PPC_EMB_SDA2I16
2793 BFD_RELOC_PPC_EMB_SDA2REL
2795 BFD_RELOC_PPC_EMB_SDA21
2797 BFD_RELOC_PPC_EMB_MRKREF
2799 BFD_RELOC_PPC_EMB_RELSEC16
2801 BFD_RELOC_PPC_EMB_RELST_LO
2803 BFD_RELOC_PPC_EMB_RELST_HI
2805 BFD_RELOC_PPC_EMB_RELST_HA
2807 BFD_RELOC_PPC_EMB_BIT_FLD
2809 BFD_RELOC_PPC_EMB_RELSDA
2811 BFD_RELOC_PPC_VLE_REL8
2813 BFD_RELOC_PPC_VLE_REL15
2815 BFD_RELOC_PPC_VLE_REL24
2817 BFD_RELOC_PPC_VLE_LO16A
2819 BFD_RELOC_PPC_VLE_LO16D
2821 BFD_RELOC_PPC_VLE_HI16A
2823 BFD_RELOC_PPC_VLE_HI16D
2825 BFD_RELOC_PPC_VLE_HA16A
2827 BFD_RELOC_PPC_VLE_HA16D
2829 BFD_RELOC_PPC_VLE_SDA21
2831 BFD_RELOC_PPC_VLE_SDA21_LO
2833 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2835 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2837 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2839 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2841 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2843 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2845 BFD_RELOC_PPC_16DX_HA
2847 BFD_RELOC_PPC_REL16DX_HA
2849 BFD_RELOC_PPC64_HIGHER
2851 BFD_RELOC_PPC64_HIGHER_S
2853 BFD_RELOC_PPC64_HIGHEST
2855 BFD_RELOC_PPC64_HIGHEST_S
2857 BFD_RELOC_PPC64_TOC16_LO
2859 BFD_RELOC_PPC64_TOC16_HI
2861 BFD_RELOC_PPC64_TOC16_HA
2865 BFD_RELOC_PPC64_PLTGOT16
2867 BFD_RELOC_PPC64_PLTGOT16_LO
2869 BFD_RELOC_PPC64_PLTGOT16_HI
2871 BFD_RELOC_PPC64_PLTGOT16_HA
2873 BFD_RELOC_PPC64_ADDR16_DS
2875 BFD_RELOC_PPC64_ADDR16_LO_DS
2877 BFD_RELOC_PPC64_GOT16_DS
2879 BFD_RELOC_PPC64_GOT16_LO_DS
2881 BFD_RELOC_PPC64_PLT16_LO_DS
2883 BFD_RELOC_PPC64_SECTOFF_DS
2885 BFD_RELOC_PPC64_SECTOFF_LO_DS
2887 BFD_RELOC_PPC64_TOC16_DS
2889 BFD_RELOC_PPC64_TOC16_LO_DS
2891 BFD_RELOC_PPC64_PLTGOT16_DS
2893 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2895 BFD_RELOC_PPC64_ADDR16_HIGH
2897 BFD_RELOC_PPC64_ADDR16_HIGHA
2899 BFD_RELOC_PPC64_REL16_HIGH
2901 BFD_RELOC_PPC64_REL16_HIGHA
2903 BFD_RELOC_PPC64_REL16_HIGHER
2905 BFD_RELOC_PPC64_REL16_HIGHERA
2907 BFD_RELOC_PPC64_REL16_HIGHEST
2909 BFD_RELOC_PPC64_REL16_HIGHESTA
2911 BFD_RELOC_PPC64_ADDR64_LOCAL
2913 BFD_RELOC_PPC64_ENTRY
2915 BFD_RELOC_PPC64_REL24_NOTOC
2919 BFD_RELOC_PPC64_D34_LO
2921 BFD_RELOC_PPC64_D34_HI30
2923 BFD_RELOC_PPC64_D34_HA30
2925 BFD_RELOC_PPC64_PCREL34
2927 BFD_RELOC_PPC64_GOT_PCREL34
2929 BFD_RELOC_PPC64_PLT_PCREL34
2931 BFD_RELOC_PPC64_ADDR16_HIGHER34
2933 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2935 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2937 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2939 BFD_RELOC_PPC64_REL16_HIGHER34
2941 BFD_RELOC_PPC64_REL16_HIGHERA34
2943 BFD_RELOC_PPC64_REL16_HIGHEST34
2945 BFD_RELOC_PPC64_REL16_HIGHESTA34
2949 BFD_RELOC_PPC64_PCREL28
2951 Power(rs6000) and PowerPC relocations.
2960 BFD_RELOC_PPC_DTPMOD
2962 BFD_RELOC_PPC_TPREL16
2964 BFD_RELOC_PPC_TPREL16_LO
2966 BFD_RELOC_PPC_TPREL16_HI
2968 BFD_RELOC_PPC_TPREL16_HA
2972 BFD_RELOC_PPC_DTPREL16
2974 BFD_RELOC_PPC_DTPREL16_LO
2976 BFD_RELOC_PPC_DTPREL16_HI
2978 BFD_RELOC_PPC_DTPREL16_HA
2980 BFD_RELOC_PPC_DTPREL
2982 BFD_RELOC_PPC_GOT_TLSGD16
2984 BFD_RELOC_PPC_GOT_TLSGD16_LO
2986 BFD_RELOC_PPC_GOT_TLSGD16_HI
2988 BFD_RELOC_PPC_GOT_TLSGD16_HA
2990 BFD_RELOC_PPC_GOT_TLSLD16
2992 BFD_RELOC_PPC_GOT_TLSLD16_LO
2994 BFD_RELOC_PPC_GOT_TLSLD16_HI
2996 BFD_RELOC_PPC_GOT_TLSLD16_HA
2998 BFD_RELOC_PPC_GOT_TPREL16
3000 BFD_RELOC_PPC_GOT_TPREL16_LO
3002 BFD_RELOC_PPC_GOT_TPREL16_HI
3004 BFD_RELOC_PPC_GOT_TPREL16_HA
3006 BFD_RELOC_PPC_GOT_DTPREL16
3008 BFD_RELOC_PPC_GOT_DTPREL16_LO
3010 BFD_RELOC_PPC_GOT_DTPREL16_HI
3012 BFD_RELOC_PPC_GOT_DTPREL16_HA
3014 BFD_RELOC_PPC64_TPREL16_DS
3016 BFD_RELOC_PPC64_TPREL16_LO_DS
3018 BFD_RELOC_PPC64_TPREL16_HIGH
3020 BFD_RELOC_PPC64_TPREL16_HIGHA
3022 BFD_RELOC_PPC64_TPREL16_HIGHER
3024 BFD_RELOC_PPC64_TPREL16_HIGHERA
3026 BFD_RELOC_PPC64_TPREL16_HIGHEST
3028 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3030 BFD_RELOC_PPC64_DTPREL16_DS
3032 BFD_RELOC_PPC64_DTPREL16_LO_DS
3034 BFD_RELOC_PPC64_DTPREL16_HIGH
3036 BFD_RELOC_PPC64_DTPREL16_HIGHA
3038 BFD_RELOC_PPC64_DTPREL16_HIGHER
3040 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3042 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3044 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3046 BFD_RELOC_PPC64_TPREL34
3048 BFD_RELOC_PPC64_DTPREL34
3050 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
3052 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
3054 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
3056 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
3058 BFD_RELOC_PPC64_TLS_PCREL
3060 PowerPC and PowerPC64 thread-local storage relocations.
3065 IBM 370/390 relocations
3070 The type of reloc used to build a constructor table - at the moment
3071 probably a 32 bit wide absolute relocation, but the target can choose.
3072 It generally does map to one of the other relocation types.
3075 BFD_RELOC_ARM_PCREL_BRANCH
3077 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3078 not stored in the instruction.
3080 BFD_RELOC_ARM_PCREL_BLX
3082 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3083 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3084 field in the instruction.
3086 BFD_RELOC_THUMB_PCREL_BLX
3088 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3089 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3090 field in the instruction.
3092 BFD_RELOC_ARM_PCREL_CALL
3094 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3096 BFD_RELOC_ARM_PCREL_JUMP
3098 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3101 BFD_RELOC_THUMB_PCREL_BRANCH5
3103 ARM 5-bit pc-relative branch for Branch Future instructions.
3106 BFD_RELOC_THUMB_PCREL_BFCSEL
3108 ARM 6-bit pc-relative branch for BFCSEL instruction.
3111 BFD_RELOC_ARM_THUMB_BF17
3113 ARM 17-bit pc-relative branch for Branch Future instructions.
3116 BFD_RELOC_ARM_THUMB_BF13
3118 ARM 13-bit pc-relative branch for BFCSEL instruction.
3121 BFD_RELOC_ARM_THUMB_BF19
3123 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3126 BFD_RELOC_ARM_THUMB_LOOP12
3128 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3131 BFD_RELOC_THUMB_PCREL_BRANCH7
3133 BFD_RELOC_THUMB_PCREL_BRANCH9
3135 BFD_RELOC_THUMB_PCREL_BRANCH12
3137 BFD_RELOC_THUMB_PCREL_BRANCH20
3139 BFD_RELOC_THUMB_PCREL_BRANCH23
3141 BFD_RELOC_THUMB_PCREL_BRANCH25
3143 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3144 The lowest bit must be zero and is not stored in the instruction.
3145 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3146 "nn" one smaller in all cases. Note further that BRANCH23
3147 corresponds to R_ARM_THM_CALL.
3150 BFD_RELOC_ARM_OFFSET_IMM
3152 12-bit immediate offset, used in ARM-format ldr and str instructions.
3155 BFD_RELOC_ARM_THUMB_OFFSET
3157 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3160 BFD_RELOC_ARM_TARGET1
3162 Pc-relative or absolute relocation depending on target. Used for
3163 entries in .init_array sections.
3165 BFD_RELOC_ARM_ROSEGREL32
3167 Read-only segment base relative address.
3169 BFD_RELOC_ARM_SBREL32
3171 Data segment base relative address.
3173 BFD_RELOC_ARM_TARGET2
3175 This reloc is used for references to RTTI data from exception handling
3176 tables. The actual definition depends on the target. It may be a
3177 pc-relative or some form of GOT-indirect relocation.
3179 BFD_RELOC_ARM_PREL31
3181 31-bit PC relative address.
3187 BFD_RELOC_ARM_MOVW_PCREL
3189 BFD_RELOC_ARM_MOVT_PCREL
3191 BFD_RELOC_ARM_THUMB_MOVW
3193 BFD_RELOC_ARM_THUMB_MOVT
3195 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3197 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3199 Low and High halfword relocations for MOVW and MOVT instructions.
3202 BFD_RELOC_ARM_GOTFUNCDESC
3204 BFD_RELOC_ARM_GOTOFFFUNCDESC
3206 BFD_RELOC_ARM_FUNCDESC
3208 BFD_RELOC_ARM_FUNCDESC_VALUE
3210 BFD_RELOC_ARM_TLS_GD32_FDPIC
3212 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3214 BFD_RELOC_ARM_TLS_IE32_FDPIC
3216 ARM FDPIC specific relocations.
3219 BFD_RELOC_ARM_JUMP_SLOT
3221 BFD_RELOC_ARM_GLOB_DAT
3227 BFD_RELOC_ARM_RELATIVE
3229 BFD_RELOC_ARM_GOTOFF
3233 BFD_RELOC_ARM_GOT_PREL
3235 Relocations for setting up GOTs and PLTs for shared libraries.
3238 BFD_RELOC_ARM_TLS_GD32
3240 BFD_RELOC_ARM_TLS_LDO32
3242 BFD_RELOC_ARM_TLS_LDM32
3244 BFD_RELOC_ARM_TLS_DTPOFF32
3246 BFD_RELOC_ARM_TLS_DTPMOD32
3248 BFD_RELOC_ARM_TLS_TPOFF32
3250 BFD_RELOC_ARM_TLS_IE32
3252 BFD_RELOC_ARM_TLS_LE32
3254 BFD_RELOC_ARM_TLS_GOTDESC
3256 BFD_RELOC_ARM_TLS_CALL
3258 BFD_RELOC_ARM_THM_TLS_CALL
3260 BFD_RELOC_ARM_TLS_DESCSEQ
3262 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3264 BFD_RELOC_ARM_TLS_DESC
3266 ARM thread-local storage relocations.
3269 BFD_RELOC_ARM_ALU_PC_G0_NC
3271 BFD_RELOC_ARM_ALU_PC_G0
3273 BFD_RELOC_ARM_ALU_PC_G1_NC
3275 BFD_RELOC_ARM_ALU_PC_G1
3277 BFD_RELOC_ARM_ALU_PC_G2
3279 BFD_RELOC_ARM_LDR_PC_G0
3281 BFD_RELOC_ARM_LDR_PC_G1
3283 BFD_RELOC_ARM_LDR_PC_G2
3285 BFD_RELOC_ARM_LDRS_PC_G0
3287 BFD_RELOC_ARM_LDRS_PC_G1
3289 BFD_RELOC_ARM_LDRS_PC_G2
3291 BFD_RELOC_ARM_LDC_PC_G0
3293 BFD_RELOC_ARM_LDC_PC_G1
3295 BFD_RELOC_ARM_LDC_PC_G2
3297 BFD_RELOC_ARM_ALU_SB_G0_NC
3299 BFD_RELOC_ARM_ALU_SB_G0
3301 BFD_RELOC_ARM_ALU_SB_G1_NC
3303 BFD_RELOC_ARM_ALU_SB_G1
3305 BFD_RELOC_ARM_ALU_SB_G2
3307 BFD_RELOC_ARM_LDR_SB_G0
3309 BFD_RELOC_ARM_LDR_SB_G1
3311 BFD_RELOC_ARM_LDR_SB_G2
3313 BFD_RELOC_ARM_LDRS_SB_G0
3315 BFD_RELOC_ARM_LDRS_SB_G1
3317 BFD_RELOC_ARM_LDRS_SB_G2
3319 BFD_RELOC_ARM_LDC_SB_G0
3321 BFD_RELOC_ARM_LDC_SB_G1
3323 BFD_RELOC_ARM_LDC_SB_G2
3325 ARM group relocations.
3330 Annotation of BX instructions.
3333 BFD_RELOC_ARM_IRELATIVE
3335 ARM support for STT_GNU_IFUNC.
3338 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3340 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3342 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3344 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3346 Thumb1 relocations to support execute-only code.
3349 BFD_RELOC_ARM_IMMEDIATE
3351 BFD_RELOC_ARM_ADRL_IMMEDIATE
3353 BFD_RELOC_ARM_T32_IMMEDIATE
3355 BFD_RELOC_ARM_T32_ADD_IMM
3357 BFD_RELOC_ARM_T32_IMM12
3359 BFD_RELOC_ARM_T32_ADD_PC12
3361 BFD_RELOC_ARM_SHIFT_IMM
3371 BFD_RELOC_ARM_CP_OFF_IMM
3373 BFD_RELOC_ARM_CP_OFF_IMM_S2
3375 BFD_RELOC_ARM_T32_CP_OFF_IMM
3377 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3379 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3381 BFD_RELOC_ARM_ADR_IMM
3383 BFD_RELOC_ARM_LDR_IMM
3385 BFD_RELOC_ARM_LITERAL
3387 BFD_RELOC_ARM_IN_POOL
3389 BFD_RELOC_ARM_OFFSET_IMM8
3391 BFD_RELOC_ARM_T32_OFFSET_U8
3393 BFD_RELOC_ARM_T32_OFFSET_IMM
3395 BFD_RELOC_ARM_HWLITERAL
3397 BFD_RELOC_ARM_THUMB_ADD
3399 BFD_RELOC_ARM_THUMB_IMM
3401 BFD_RELOC_ARM_THUMB_SHIFT
3403 These relocs are only used within the ARM assembler. They are not
3404 (at present) written to any object files.
3407 BFD_RELOC_SH_PCDISP8BY2
3409 BFD_RELOC_SH_PCDISP12BY2
3417 BFD_RELOC_SH_DISP12BY2
3419 BFD_RELOC_SH_DISP12BY4
3421 BFD_RELOC_SH_DISP12BY8
3425 BFD_RELOC_SH_DISP20BY8
3429 BFD_RELOC_SH_IMM4BY2
3431 BFD_RELOC_SH_IMM4BY4
3435 BFD_RELOC_SH_IMM8BY2
3437 BFD_RELOC_SH_IMM8BY4
3439 BFD_RELOC_SH_PCRELIMM8BY2
3441 BFD_RELOC_SH_PCRELIMM8BY4
3443 BFD_RELOC_SH_SWITCH16
3445 BFD_RELOC_SH_SWITCH32
3459 BFD_RELOC_SH_LOOP_START
3461 BFD_RELOC_SH_LOOP_END
3465 BFD_RELOC_SH_GLOB_DAT
3467 BFD_RELOC_SH_JMP_SLOT
3469 BFD_RELOC_SH_RELATIVE
3473 BFD_RELOC_SH_GOT_LOW16
3475 BFD_RELOC_SH_GOT_MEDLOW16
3477 BFD_RELOC_SH_GOT_MEDHI16
3479 BFD_RELOC_SH_GOT_HI16
3481 BFD_RELOC_SH_GOTPLT_LOW16
3483 BFD_RELOC_SH_GOTPLT_MEDLOW16
3485 BFD_RELOC_SH_GOTPLT_MEDHI16
3487 BFD_RELOC_SH_GOTPLT_HI16
3489 BFD_RELOC_SH_PLT_LOW16
3491 BFD_RELOC_SH_PLT_MEDLOW16
3493 BFD_RELOC_SH_PLT_MEDHI16
3495 BFD_RELOC_SH_PLT_HI16
3497 BFD_RELOC_SH_GOTOFF_LOW16
3499 BFD_RELOC_SH_GOTOFF_MEDLOW16
3501 BFD_RELOC_SH_GOTOFF_MEDHI16
3503 BFD_RELOC_SH_GOTOFF_HI16
3505 BFD_RELOC_SH_GOTPC_LOW16
3507 BFD_RELOC_SH_GOTPC_MEDLOW16
3509 BFD_RELOC_SH_GOTPC_MEDHI16
3511 BFD_RELOC_SH_GOTPC_HI16
3515 BFD_RELOC_SH_GLOB_DAT64
3517 BFD_RELOC_SH_JMP_SLOT64
3519 BFD_RELOC_SH_RELATIVE64
3521 BFD_RELOC_SH_GOT10BY4
3523 BFD_RELOC_SH_GOT10BY8
3525 BFD_RELOC_SH_GOTPLT10BY4
3527 BFD_RELOC_SH_GOTPLT10BY8
3529 BFD_RELOC_SH_GOTPLT32
3531 BFD_RELOC_SH_SHMEDIA_CODE
3537 BFD_RELOC_SH_IMMS6BY32
3543 BFD_RELOC_SH_IMMS10BY2
3545 BFD_RELOC_SH_IMMS10BY4
3547 BFD_RELOC_SH_IMMS10BY8
3553 BFD_RELOC_SH_IMM_LOW16
3555 BFD_RELOC_SH_IMM_LOW16_PCREL
3557 BFD_RELOC_SH_IMM_MEDLOW16
3559 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3561 BFD_RELOC_SH_IMM_MEDHI16
3563 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3565 BFD_RELOC_SH_IMM_HI16
3567 BFD_RELOC_SH_IMM_HI16_PCREL
3571 BFD_RELOC_SH_TLS_GD_32
3573 BFD_RELOC_SH_TLS_LD_32
3575 BFD_RELOC_SH_TLS_LDO_32
3577 BFD_RELOC_SH_TLS_IE_32
3579 BFD_RELOC_SH_TLS_LE_32
3581 BFD_RELOC_SH_TLS_DTPMOD32
3583 BFD_RELOC_SH_TLS_DTPOFF32
3585 BFD_RELOC_SH_TLS_TPOFF32
3589 BFD_RELOC_SH_GOTOFF20
3591 BFD_RELOC_SH_GOTFUNCDESC
3593 BFD_RELOC_SH_GOTFUNCDESC20
3595 BFD_RELOC_SH_GOTOFFFUNCDESC
3597 BFD_RELOC_SH_GOTOFFFUNCDESC20
3599 BFD_RELOC_SH_FUNCDESC
3601 Renesas / SuperH SH relocs. Not all of these appear in object files.
3624 BFD_RELOC_ARC_SECTOFF
3626 BFD_RELOC_ARC_S21H_PCREL
3628 BFD_RELOC_ARC_S21W_PCREL
3630 BFD_RELOC_ARC_S25H_PCREL
3632 BFD_RELOC_ARC_S25W_PCREL
3636 BFD_RELOC_ARC_SDA_LDST
3638 BFD_RELOC_ARC_SDA_LDST1
3640 BFD_RELOC_ARC_SDA_LDST2
3642 BFD_RELOC_ARC_SDA16_LD
3644 BFD_RELOC_ARC_SDA16_LD1
3646 BFD_RELOC_ARC_SDA16_LD2
3648 BFD_RELOC_ARC_S13_PCREL
3654 BFD_RELOC_ARC_32_ME_S
3656 BFD_RELOC_ARC_N32_ME
3658 BFD_RELOC_ARC_SECTOFF_ME
3660 BFD_RELOC_ARC_SDA32_ME
3664 BFD_RELOC_AC_SECTOFF_U8
3666 BFD_RELOC_AC_SECTOFF_U8_1
3668 BFD_RELOC_AC_SECTOFF_U8_2
3670 BFD_RELOC_AC_SECTOFF_S9
3672 BFD_RELOC_AC_SECTOFF_S9_1
3674 BFD_RELOC_AC_SECTOFF_S9_2
3676 BFD_RELOC_ARC_SECTOFF_ME_1
3678 BFD_RELOC_ARC_SECTOFF_ME_2
3680 BFD_RELOC_ARC_SECTOFF_1
3682 BFD_RELOC_ARC_SECTOFF_2
3684 BFD_RELOC_ARC_SDA_12
3686 BFD_RELOC_ARC_SDA16_ST2
3688 BFD_RELOC_ARC_32_PCREL
3694 BFD_RELOC_ARC_GOTPC32
3700 BFD_RELOC_ARC_GLOB_DAT
3702 BFD_RELOC_ARC_JMP_SLOT
3704 BFD_RELOC_ARC_RELATIVE
3706 BFD_RELOC_ARC_GOTOFF
3710 BFD_RELOC_ARC_S21W_PCREL_PLT
3712 BFD_RELOC_ARC_S25H_PCREL_PLT
3714 BFD_RELOC_ARC_TLS_DTPMOD
3716 BFD_RELOC_ARC_TLS_TPOFF
3718 BFD_RELOC_ARC_TLS_GD_GOT
3720 BFD_RELOC_ARC_TLS_GD_LD
3722 BFD_RELOC_ARC_TLS_GD_CALL
3724 BFD_RELOC_ARC_TLS_IE_GOT
3726 BFD_RELOC_ARC_TLS_DTPOFF
3728 BFD_RELOC_ARC_TLS_DTPOFF_S9
3730 BFD_RELOC_ARC_TLS_LE_S9
3732 BFD_RELOC_ARC_TLS_LE_32
3734 BFD_RELOC_ARC_S25W_PCREL_PLT
3736 BFD_RELOC_ARC_S21H_PCREL_PLT
3738 BFD_RELOC_ARC_NPS_CMEM16
3740 BFD_RELOC_ARC_JLI_SECTOFF
3745 BFD_RELOC_BFIN_16_IMM
3747 ADI Blackfin 16 bit immediate absolute reloc.
3749 BFD_RELOC_BFIN_16_HIGH
3751 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3753 BFD_RELOC_BFIN_4_PCREL
3755 ADI Blackfin 'a' part of LSETUP.
3757 BFD_RELOC_BFIN_5_PCREL
3761 BFD_RELOC_BFIN_16_LOW
3763 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3765 BFD_RELOC_BFIN_10_PCREL
3769 BFD_RELOC_BFIN_11_PCREL
3771 ADI Blackfin 'b' part of LSETUP.
3773 BFD_RELOC_BFIN_12_PCREL_JUMP
3777 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3779 ADI Blackfin Short jump, pcrel.
3781 BFD_RELOC_BFIN_24_PCREL_CALL_X
3783 ADI Blackfin Call.x not implemented.
3785 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3787 ADI Blackfin Long Jump pcrel.
3789 BFD_RELOC_BFIN_GOT17M4
3791 BFD_RELOC_BFIN_GOTHI
3793 BFD_RELOC_BFIN_GOTLO
3795 BFD_RELOC_BFIN_FUNCDESC
3797 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3799 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3801 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3803 BFD_RELOC_BFIN_FUNCDESC_VALUE
3805 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3807 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3809 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3811 BFD_RELOC_BFIN_GOTOFF17M4
3813 BFD_RELOC_BFIN_GOTOFFHI
3815 BFD_RELOC_BFIN_GOTOFFLO
3817 ADI Blackfin FD-PIC relocations.
3821 ADI Blackfin GOT relocation.
3823 BFD_RELOC_BFIN_PLTPC
3825 ADI Blackfin PLTPC relocation.
3827 BFD_ARELOC_BFIN_PUSH
3829 ADI Blackfin arithmetic relocation.
3831 BFD_ARELOC_BFIN_CONST
3833 ADI Blackfin arithmetic relocation.
3837 ADI Blackfin arithmetic relocation.
3841 ADI Blackfin arithmetic relocation.
3843 BFD_ARELOC_BFIN_MULT
3845 ADI Blackfin arithmetic relocation.
3849 ADI Blackfin arithmetic relocation.
3853 ADI Blackfin arithmetic relocation.
3855 BFD_ARELOC_BFIN_LSHIFT
3857 ADI Blackfin arithmetic relocation.
3859 BFD_ARELOC_BFIN_RSHIFT
3861 ADI Blackfin arithmetic relocation.
3865 ADI Blackfin arithmetic relocation.
3869 ADI Blackfin arithmetic relocation.
3873 ADI Blackfin arithmetic relocation.
3875 BFD_ARELOC_BFIN_LAND
3877 ADI Blackfin arithmetic relocation.
3881 ADI Blackfin arithmetic relocation.
3885 ADI Blackfin arithmetic relocation.
3889 ADI Blackfin arithmetic relocation.
3891 BFD_ARELOC_BFIN_COMP
3893 ADI Blackfin arithmetic relocation.
3895 BFD_ARELOC_BFIN_PAGE
3897 ADI Blackfin arithmetic relocation.
3899 BFD_ARELOC_BFIN_HWPAGE
3901 ADI Blackfin arithmetic relocation.
3903 BFD_ARELOC_BFIN_ADDR
3905 ADI Blackfin arithmetic relocation.
3908 BFD_RELOC_D10V_10_PCREL_R
3910 Mitsubishi D10V relocs.
3911 This is a 10-bit reloc with the right 2 bits
3914 BFD_RELOC_D10V_10_PCREL_L
3916 Mitsubishi D10V relocs.
3917 This is a 10-bit reloc with the right 2 bits
3918 assumed to be 0. This is the same as the previous reloc
3919 except it is in the left container, i.e.,
3920 shifted left 15 bits.
3924 This is an 18-bit reloc with the right 2 bits
3927 BFD_RELOC_D10V_18_PCREL
3929 This is an 18-bit reloc with the right 2 bits
3935 Mitsubishi D30V relocs.
3936 This is a 6-bit absolute reloc.
3938 BFD_RELOC_D30V_9_PCREL
3940 This is a 6-bit pc-relative reloc with
3941 the right 3 bits assumed to be 0.
3943 BFD_RELOC_D30V_9_PCREL_R
3945 This is a 6-bit pc-relative reloc with
3946 the right 3 bits assumed to be 0. Same
3947 as the previous reloc but on the right side
3952 This is a 12-bit absolute reloc with the
3953 right 3 bitsassumed to be 0.
3955 BFD_RELOC_D30V_15_PCREL
3957 This is a 12-bit pc-relative reloc with
3958 the right 3 bits assumed to be 0.
3960 BFD_RELOC_D30V_15_PCREL_R
3962 This is a 12-bit pc-relative reloc with
3963 the right 3 bits assumed to be 0. Same
3964 as the previous reloc but on the right side
3969 This is an 18-bit absolute reloc with
3970 the right 3 bits assumed to be 0.
3972 BFD_RELOC_D30V_21_PCREL
3974 This is an 18-bit pc-relative reloc with
3975 the right 3 bits assumed to be 0.
3977 BFD_RELOC_D30V_21_PCREL_R
3979 This is an 18-bit pc-relative reloc with
3980 the right 3 bits assumed to be 0. Same
3981 as the previous reloc but on the right side
3986 This is a 32-bit absolute reloc.
3988 BFD_RELOC_D30V_32_PCREL
3990 This is a 32-bit pc-relative reloc.
3993 BFD_RELOC_DLX_HI16_S
4008 BFD_RELOC_M32C_RL_JUMP
4010 BFD_RELOC_M32C_RL_1ADDR
4012 BFD_RELOC_M32C_RL_2ADDR
4014 Renesas M16C/M32C Relocations.
4019 Renesas M32R (formerly Mitsubishi M32R) relocs.
4020 This is a 24 bit absolute address.
4022 BFD_RELOC_M32R_10_PCREL
4024 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4026 BFD_RELOC_M32R_18_PCREL
4028 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4030 BFD_RELOC_M32R_26_PCREL
4032 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4034 BFD_RELOC_M32R_HI16_ULO
4036 This is a 16-bit reloc containing the high 16 bits of an address
4037 used when the lower 16 bits are treated as unsigned.
4039 BFD_RELOC_M32R_HI16_SLO
4041 This is a 16-bit reloc containing the high 16 bits of an address
4042 used when the lower 16 bits are treated as signed.
4046 This is a 16-bit reloc containing the lower 16 bits of an address.
4048 BFD_RELOC_M32R_SDA16
4050 This is a 16-bit reloc containing the small data area offset for use in
4051 add3, load, and store instructions.
4053 BFD_RELOC_M32R_GOT24
4055 BFD_RELOC_M32R_26_PLTREL
4059 BFD_RELOC_M32R_GLOB_DAT
4061 BFD_RELOC_M32R_JMP_SLOT
4063 BFD_RELOC_M32R_RELATIVE
4065 BFD_RELOC_M32R_GOTOFF
4067 BFD_RELOC_M32R_GOTOFF_HI_ULO
4069 BFD_RELOC_M32R_GOTOFF_HI_SLO
4071 BFD_RELOC_M32R_GOTOFF_LO
4073 BFD_RELOC_M32R_GOTPC24
4075 BFD_RELOC_M32R_GOT16_HI_ULO
4077 BFD_RELOC_M32R_GOT16_HI_SLO
4079 BFD_RELOC_M32R_GOT16_LO
4081 BFD_RELOC_M32R_GOTPC_HI_ULO
4083 BFD_RELOC_M32R_GOTPC_HI_SLO
4085 BFD_RELOC_M32R_GOTPC_LO
4094 This is a 20 bit absolute address.
4096 BFD_RELOC_NDS32_9_PCREL
4098 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4100 BFD_RELOC_NDS32_WORD_9_PCREL
4102 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4104 BFD_RELOC_NDS32_15_PCREL
4106 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4108 BFD_RELOC_NDS32_17_PCREL
4110 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4112 BFD_RELOC_NDS32_25_PCREL
4114 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4116 BFD_RELOC_NDS32_HI20
4118 This is a 20-bit reloc containing the high 20 bits of an address
4119 used with the lower 12 bits
4121 BFD_RELOC_NDS32_LO12S3
4123 This is a 12-bit reloc containing the lower 12 bits of an address
4124 then shift right by 3. This is used with ldi,sdi...
4126 BFD_RELOC_NDS32_LO12S2
4128 This is a 12-bit reloc containing the lower 12 bits of an address
4129 then shift left by 2. This is used with lwi,swi...
4131 BFD_RELOC_NDS32_LO12S1
4133 This is a 12-bit reloc containing the lower 12 bits of an address
4134 then shift left by 1. This is used with lhi,shi...
4136 BFD_RELOC_NDS32_LO12S0
4138 This is a 12-bit reloc containing the lower 12 bits of an address
4139 then shift left by 0. This is used with lbisbi...
4141 BFD_RELOC_NDS32_LO12S0_ORI
4143 This is a 12-bit reloc containing the lower 12 bits of an address
4144 then shift left by 0. This is only used with branch relaxations
4146 BFD_RELOC_NDS32_SDA15S3
4148 This is a 15-bit reloc containing the small data area 18-bit signed offset
4149 and shift left by 3 for use in ldi, sdi...
4151 BFD_RELOC_NDS32_SDA15S2
4153 This is a 15-bit reloc containing the small data area 17-bit signed offset
4154 and shift left by 2 for use in lwi, swi...
4156 BFD_RELOC_NDS32_SDA15S1
4158 This is a 15-bit reloc containing the small data area 16-bit signed offset
4159 and shift left by 1 for use in lhi, shi...
4161 BFD_RELOC_NDS32_SDA15S0
4163 This is a 15-bit reloc containing the small data area 15-bit signed offset
4164 and shift left by 0 for use in lbi, sbi...
4166 BFD_RELOC_NDS32_SDA16S3
4168 This is a 16-bit reloc containing the small data area 16-bit signed offset
4171 BFD_RELOC_NDS32_SDA17S2
4173 This is a 17-bit reloc containing the small data area 17-bit signed offset
4174 and shift left by 2 for use in lwi.gp, swi.gp...
4176 BFD_RELOC_NDS32_SDA18S1
4178 This is a 18-bit reloc containing the small data area 18-bit signed offset
4179 and shift left by 1 for use in lhi.gp, shi.gp...
4181 BFD_RELOC_NDS32_SDA19S0
4183 This is a 19-bit reloc containing the small data area 19-bit signed offset
4184 and shift left by 0 for use in lbi.gp, sbi.gp...
4186 BFD_RELOC_NDS32_GOT20
4188 BFD_RELOC_NDS32_9_PLTREL
4190 BFD_RELOC_NDS32_25_PLTREL
4192 BFD_RELOC_NDS32_COPY
4194 BFD_RELOC_NDS32_GLOB_DAT
4196 BFD_RELOC_NDS32_JMP_SLOT
4198 BFD_RELOC_NDS32_RELATIVE
4200 BFD_RELOC_NDS32_GOTOFF
4202 BFD_RELOC_NDS32_GOTOFF_HI20
4204 BFD_RELOC_NDS32_GOTOFF_LO12
4206 BFD_RELOC_NDS32_GOTPC20
4208 BFD_RELOC_NDS32_GOT_HI20
4210 BFD_RELOC_NDS32_GOT_LO12
4212 BFD_RELOC_NDS32_GOTPC_HI20
4214 BFD_RELOC_NDS32_GOTPC_LO12
4218 BFD_RELOC_NDS32_INSN16
4220 BFD_RELOC_NDS32_LABEL
4222 BFD_RELOC_NDS32_LONGCALL1
4224 BFD_RELOC_NDS32_LONGCALL2
4226 BFD_RELOC_NDS32_LONGCALL3
4228 BFD_RELOC_NDS32_LONGJUMP1
4230 BFD_RELOC_NDS32_LONGJUMP2
4232 BFD_RELOC_NDS32_LONGJUMP3
4234 BFD_RELOC_NDS32_LOADSTORE
4236 BFD_RELOC_NDS32_9_FIXED
4238 BFD_RELOC_NDS32_15_FIXED
4240 BFD_RELOC_NDS32_17_FIXED
4242 BFD_RELOC_NDS32_25_FIXED
4244 BFD_RELOC_NDS32_LONGCALL4
4246 BFD_RELOC_NDS32_LONGCALL5
4248 BFD_RELOC_NDS32_LONGCALL6
4250 BFD_RELOC_NDS32_LONGJUMP4
4252 BFD_RELOC_NDS32_LONGJUMP5
4254 BFD_RELOC_NDS32_LONGJUMP6
4256 BFD_RELOC_NDS32_LONGJUMP7
4260 BFD_RELOC_NDS32_PLTREL_HI20
4262 BFD_RELOC_NDS32_PLTREL_LO12
4264 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4266 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4270 BFD_RELOC_NDS32_SDA12S2_DP
4272 BFD_RELOC_NDS32_SDA12S2_SP
4274 BFD_RELOC_NDS32_LO12S2_DP
4276 BFD_RELOC_NDS32_LO12S2_SP
4280 BFD_RELOC_NDS32_DWARF2_OP1
4282 BFD_RELOC_NDS32_DWARF2_OP2
4284 BFD_RELOC_NDS32_DWARF2_LEB
4286 for dwarf2 debug_line.
4288 BFD_RELOC_NDS32_UPDATE_TA
4290 for eliminate 16-bit instructions
4292 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4294 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4296 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4298 BFD_RELOC_NDS32_GOT_LO15
4300 BFD_RELOC_NDS32_GOT_LO19
4302 BFD_RELOC_NDS32_GOTOFF_LO15
4304 BFD_RELOC_NDS32_GOTOFF_LO19
4306 BFD_RELOC_NDS32_GOT15S2
4308 BFD_RELOC_NDS32_GOT17S2
4310 for PIC object relaxation
4315 This is a 5 bit absolute address.
4317 BFD_RELOC_NDS32_10_UPCREL
4319 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4321 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4323 If fp were omitted, fp can used as another gp.
4325 BFD_RELOC_NDS32_RELAX_ENTRY
4327 BFD_RELOC_NDS32_GOT_SUFF
4329 BFD_RELOC_NDS32_GOTOFF_SUFF
4331 BFD_RELOC_NDS32_PLT_GOT_SUFF
4333 BFD_RELOC_NDS32_MULCALL_SUFF
4337 BFD_RELOC_NDS32_PTR_COUNT
4339 BFD_RELOC_NDS32_PTR_RESOLVED
4341 BFD_RELOC_NDS32_PLTBLOCK
4343 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4345 BFD_RELOC_NDS32_RELAX_REGION_END
4347 BFD_RELOC_NDS32_MINUEND
4349 BFD_RELOC_NDS32_SUBTRAHEND
4351 BFD_RELOC_NDS32_DIFF8
4353 BFD_RELOC_NDS32_DIFF16
4355 BFD_RELOC_NDS32_DIFF32
4357 BFD_RELOC_NDS32_DIFF_ULEB128
4359 BFD_RELOC_NDS32_EMPTY
4361 relaxation relative relocation types
4363 BFD_RELOC_NDS32_25_ABS
4365 This is a 25 bit absolute address.
4367 BFD_RELOC_NDS32_DATA
4369 BFD_RELOC_NDS32_TRAN
4371 BFD_RELOC_NDS32_17IFC_PCREL
4373 BFD_RELOC_NDS32_10IFCU_PCREL
4375 For ex9 and ifc using.
4377 BFD_RELOC_NDS32_TPOFF
4379 BFD_RELOC_NDS32_GOTTPOFF
4381 BFD_RELOC_NDS32_TLS_LE_HI20
4383 BFD_RELOC_NDS32_TLS_LE_LO12
4385 BFD_RELOC_NDS32_TLS_LE_20
4387 BFD_RELOC_NDS32_TLS_LE_15S0
4389 BFD_RELOC_NDS32_TLS_LE_15S1
4391 BFD_RELOC_NDS32_TLS_LE_15S2
4393 BFD_RELOC_NDS32_TLS_LE_ADD
4395 BFD_RELOC_NDS32_TLS_LE_LS
4397 BFD_RELOC_NDS32_TLS_IE_HI20
4399 BFD_RELOC_NDS32_TLS_IE_LO12
4401 BFD_RELOC_NDS32_TLS_IE_LO12S2
4403 BFD_RELOC_NDS32_TLS_IEGP_HI20
4405 BFD_RELOC_NDS32_TLS_IEGP_LO12
4407 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4409 BFD_RELOC_NDS32_TLS_IEGP_LW
4411 BFD_RELOC_NDS32_TLS_DESC
4413 BFD_RELOC_NDS32_TLS_DESC_HI20
4415 BFD_RELOC_NDS32_TLS_DESC_LO12
4417 BFD_RELOC_NDS32_TLS_DESC_20
4419 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4421 BFD_RELOC_NDS32_TLS_DESC_ADD
4423 BFD_RELOC_NDS32_TLS_DESC_FUNC
4425 BFD_RELOC_NDS32_TLS_DESC_CALL
4427 BFD_RELOC_NDS32_TLS_DESC_MEM
4429 BFD_RELOC_NDS32_REMOVE
4431 BFD_RELOC_NDS32_GROUP
4437 For floating load store relaxation.
4441 BFD_RELOC_V850_9_PCREL
4443 This is a 9-bit reloc
4445 BFD_RELOC_V850_22_PCREL
4447 This is a 22-bit reloc
4450 BFD_RELOC_V850_SDA_16_16_OFFSET
4452 This is a 16 bit offset from the short data area pointer.
4454 BFD_RELOC_V850_SDA_15_16_OFFSET
4456 This is a 16 bit offset (of which only 15 bits are used) from the
4457 short data area pointer.
4459 BFD_RELOC_V850_ZDA_16_16_OFFSET
4461 This is a 16 bit offset from the zero data area pointer.
4463 BFD_RELOC_V850_ZDA_15_16_OFFSET
4465 This is a 16 bit offset (of which only 15 bits are used) from the
4466 zero data area pointer.
4468 BFD_RELOC_V850_TDA_6_8_OFFSET
4470 This is an 8 bit offset (of which only 6 bits are used) from the
4471 tiny data area pointer.
4473 BFD_RELOC_V850_TDA_7_8_OFFSET
4475 This is an 8bit offset (of which only 7 bits are used) from the tiny
4478 BFD_RELOC_V850_TDA_7_7_OFFSET
4480 This is a 7 bit offset from the tiny data area pointer.
4482 BFD_RELOC_V850_TDA_16_16_OFFSET
4484 This is a 16 bit offset from the tiny data area pointer.
4487 BFD_RELOC_V850_TDA_4_5_OFFSET
4489 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4492 BFD_RELOC_V850_TDA_4_4_OFFSET
4494 This is a 4 bit offset from the tiny data area pointer.
4496 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4498 This is a 16 bit offset from the short data area pointer, with the
4499 bits placed non-contiguously in the instruction.
4501 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4503 This is a 16 bit offset from the zero data area pointer, with the
4504 bits placed non-contiguously in the instruction.
4506 BFD_RELOC_V850_CALLT_6_7_OFFSET
4508 This is a 6 bit offset from the call table base pointer.
4510 BFD_RELOC_V850_CALLT_16_16_OFFSET
4512 This is a 16 bit offset from the call table base pointer.
4514 BFD_RELOC_V850_LONGCALL
4516 Used for relaxing indirect function calls.
4518 BFD_RELOC_V850_LONGJUMP
4520 Used for relaxing indirect jumps.
4522 BFD_RELOC_V850_ALIGN
4524 Used to maintain alignment whilst relaxing.
4526 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4528 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4531 BFD_RELOC_V850_16_PCREL
4533 This is a 16-bit reloc.
4535 BFD_RELOC_V850_17_PCREL
4537 This is a 17-bit reloc.
4541 This is a 23-bit reloc.
4543 BFD_RELOC_V850_32_PCREL
4545 This is a 32-bit reloc.
4547 BFD_RELOC_V850_32_ABS
4549 This is a 32-bit reloc.
4551 BFD_RELOC_V850_16_SPLIT_OFFSET
4553 This is a 16-bit reloc.
4555 BFD_RELOC_V850_16_S1
4557 This is a 16-bit reloc.
4559 BFD_RELOC_V850_LO16_S1
4561 Low 16 bits. 16 bit shifted by 1.
4563 BFD_RELOC_V850_CALLT_15_16_OFFSET
4565 This is a 16 bit offset from the call table base pointer.
4567 BFD_RELOC_V850_32_GOTPCREL
4571 BFD_RELOC_V850_16_GOT
4575 BFD_RELOC_V850_32_GOT
4579 BFD_RELOC_V850_22_PLT_PCREL
4583 BFD_RELOC_V850_32_PLT_PCREL
4591 BFD_RELOC_V850_GLOB_DAT
4595 BFD_RELOC_V850_JMP_SLOT
4599 BFD_RELOC_V850_RELATIVE
4603 BFD_RELOC_V850_16_GOTOFF
4607 BFD_RELOC_V850_32_GOTOFF
4622 This is a 8bit DP reloc for the tms320c30, where the most
4623 significant 8 bits of a 24 bit word are placed into the least
4624 significant 8 bits of the opcode.
4627 BFD_RELOC_TIC54X_PARTLS7
4629 This is a 7bit reloc for the tms320c54x, where the least
4630 significant 7 bits of a 16 bit word are placed into the least
4631 significant 7 bits of the opcode.
4634 BFD_RELOC_TIC54X_PARTMS9
4636 This is a 9bit DP reloc for the tms320c54x, where the most
4637 significant 9 bits of a 16 bit word are placed into the least
4638 significant 9 bits of the opcode.
4643 This is an extended address 23-bit reloc for the tms320c54x.
4646 BFD_RELOC_TIC54X_16_OF_23
4648 This is a 16-bit reloc for the tms320c54x, where the least
4649 significant 16 bits of a 23-bit extended address are placed into
4653 BFD_RELOC_TIC54X_MS7_OF_23
4655 This is a reloc for the tms320c54x, where the most
4656 significant 7 bits of a 23-bit extended address are placed into
4660 BFD_RELOC_C6000_PCR_S21
4662 BFD_RELOC_C6000_PCR_S12
4664 BFD_RELOC_C6000_PCR_S10
4666 BFD_RELOC_C6000_PCR_S7
4668 BFD_RELOC_C6000_ABS_S16
4670 BFD_RELOC_C6000_ABS_L16
4672 BFD_RELOC_C6000_ABS_H16
4674 BFD_RELOC_C6000_SBR_U15_B
4676 BFD_RELOC_C6000_SBR_U15_H
4678 BFD_RELOC_C6000_SBR_U15_W
4680 BFD_RELOC_C6000_SBR_S16
4682 BFD_RELOC_C6000_SBR_L16_B
4684 BFD_RELOC_C6000_SBR_L16_H
4686 BFD_RELOC_C6000_SBR_L16_W
4688 BFD_RELOC_C6000_SBR_H16_B
4690 BFD_RELOC_C6000_SBR_H16_H
4692 BFD_RELOC_C6000_SBR_H16_W
4694 BFD_RELOC_C6000_SBR_GOT_U15_W
4696 BFD_RELOC_C6000_SBR_GOT_L16_W
4698 BFD_RELOC_C6000_SBR_GOT_H16_W
4700 BFD_RELOC_C6000_DSBT_INDEX
4702 BFD_RELOC_C6000_PREL31
4704 BFD_RELOC_C6000_COPY
4706 BFD_RELOC_C6000_JUMP_SLOT
4708 BFD_RELOC_C6000_EHTYPE
4710 BFD_RELOC_C6000_PCR_H16
4712 BFD_RELOC_C6000_PCR_L16
4714 BFD_RELOC_C6000_ALIGN
4716 BFD_RELOC_C6000_FPHEAD
4718 BFD_RELOC_C6000_NOCMP
4720 TMS320C6000 relocations.
4725 This is a 48 bit reloc for the FR30 that stores 32 bits.
4729 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4732 BFD_RELOC_FR30_6_IN_4
4734 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4737 BFD_RELOC_FR30_8_IN_8
4739 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4742 BFD_RELOC_FR30_9_IN_8
4744 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4747 BFD_RELOC_FR30_10_IN_8
4749 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4752 BFD_RELOC_FR30_9_PCREL
4754 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4755 short offset into 8 bits.
4757 BFD_RELOC_FR30_12_PCREL
4759 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4760 short offset into 11 bits.
4763 BFD_RELOC_MCORE_PCREL_IMM8BY4
4765 BFD_RELOC_MCORE_PCREL_IMM11BY2
4767 BFD_RELOC_MCORE_PCREL_IMM4BY2
4769 BFD_RELOC_MCORE_PCREL_32
4771 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4775 Motorola Mcore relocations.
4784 BFD_RELOC_MEP_PCREL8A2
4786 BFD_RELOC_MEP_PCREL12A2
4788 BFD_RELOC_MEP_PCREL17A2
4790 BFD_RELOC_MEP_PCREL24A2
4792 BFD_RELOC_MEP_PCABS24A2
4804 BFD_RELOC_MEP_TPREL7
4806 BFD_RELOC_MEP_TPREL7A2
4808 BFD_RELOC_MEP_TPREL7A4
4810 BFD_RELOC_MEP_UIMM24
4812 BFD_RELOC_MEP_ADDR24A4
4814 BFD_RELOC_MEP_GNU_VTINHERIT
4816 BFD_RELOC_MEP_GNU_VTENTRY
4818 Toshiba Media Processor Relocations.
4822 BFD_RELOC_METAG_HIADDR16
4824 BFD_RELOC_METAG_LOADDR16
4826 BFD_RELOC_METAG_RELBRANCH
4828 BFD_RELOC_METAG_GETSETOFF
4830 BFD_RELOC_METAG_HIOG
4832 BFD_RELOC_METAG_LOOG
4834 BFD_RELOC_METAG_REL8
4836 BFD_RELOC_METAG_REL16
4838 BFD_RELOC_METAG_HI16_GOTOFF
4840 BFD_RELOC_METAG_LO16_GOTOFF
4842 BFD_RELOC_METAG_GETSET_GOTOFF
4844 BFD_RELOC_METAG_GETSET_GOT
4846 BFD_RELOC_METAG_HI16_GOTPC
4848 BFD_RELOC_METAG_LO16_GOTPC
4850 BFD_RELOC_METAG_HI16_PLT
4852 BFD_RELOC_METAG_LO16_PLT
4854 BFD_RELOC_METAG_RELBRANCH_PLT
4856 BFD_RELOC_METAG_GOTOFF
4860 BFD_RELOC_METAG_COPY
4862 BFD_RELOC_METAG_JMP_SLOT
4864 BFD_RELOC_METAG_RELATIVE
4866 BFD_RELOC_METAG_GLOB_DAT
4868 BFD_RELOC_METAG_TLS_GD
4870 BFD_RELOC_METAG_TLS_LDM
4872 BFD_RELOC_METAG_TLS_LDO_HI16
4874 BFD_RELOC_METAG_TLS_LDO_LO16
4876 BFD_RELOC_METAG_TLS_LDO
4878 BFD_RELOC_METAG_TLS_IE
4880 BFD_RELOC_METAG_TLS_IENONPIC
4882 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4884 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4886 BFD_RELOC_METAG_TLS_TPOFF
4888 BFD_RELOC_METAG_TLS_DTPMOD
4890 BFD_RELOC_METAG_TLS_DTPOFF
4892 BFD_RELOC_METAG_TLS_LE
4894 BFD_RELOC_METAG_TLS_LE_HI16
4896 BFD_RELOC_METAG_TLS_LE_LO16
4898 Imagination Technologies Meta relocations.
4903 BFD_RELOC_MMIX_GETA_1
4905 BFD_RELOC_MMIX_GETA_2
4907 BFD_RELOC_MMIX_GETA_3
4909 These are relocations for the GETA instruction.
4911 BFD_RELOC_MMIX_CBRANCH
4913 BFD_RELOC_MMIX_CBRANCH_J
4915 BFD_RELOC_MMIX_CBRANCH_1
4917 BFD_RELOC_MMIX_CBRANCH_2
4919 BFD_RELOC_MMIX_CBRANCH_3
4921 These are relocations for a conditional branch instruction.
4923 BFD_RELOC_MMIX_PUSHJ
4925 BFD_RELOC_MMIX_PUSHJ_1
4927 BFD_RELOC_MMIX_PUSHJ_2
4929 BFD_RELOC_MMIX_PUSHJ_3
4931 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4933 These are relocations for the PUSHJ instruction.
4937 BFD_RELOC_MMIX_JMP_1
4939 BFD_RELOC_MMIX_JMP_2
4941 BFD_RELOC_MMIX_JMP_3
4943 These are relocations for the JMP instruction.
4945 BFD_RELOC_MMIX_ADDR19
4947 This is a relocation for a relative address as in a GETA instruction or
4950 BFD_RELOC_MMIX_ADDR27
4952 This is a relocation for a relative address as in a JMP instruction.
4954 BFD_RELOC_MMIX_REG_OR_BYTE
4956 This is a relocation for an instruction field that may be a general
4957 register or a value 0..255.
4961 This is a relocation for an instruction field that may be a general
4964 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4966 This is a relocation for two instruction fields holding a register and
4967 an offset, the equivalent of the relocation.
4969 BFD_RELOC_MMIX_LOCAL
4971 This relocation is an assertion that the expression is not allocated as
4972 a global register. It does not modify contents.
4975 BFD_RELOC_AVR_7_PCREL
4977 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4978 short offset into 7 bits.
4980 BFD_RELOC_AVR_13_PCREL
4982 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4983 short offset into 12 bits.
4987 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4988 program memory address) into 16 bits.
4990 BFD_RELOC_AVR_LO8_LDI
4992 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4993 data memory address) into 8 bit immediate value of LDI insn.
4995 BFD_RELOC_AVR_HI8_LDI
4997 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4998 of data memory address) into 8 bit immediate value of LDI insn.
5000 BFD_RELOC_AVR_HH8_LDI
5002 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5003 of program memory address) into 8 bit immediate value of LDI insn.
5005 BFD_RELOC_AVR_MS8_LDI
5007 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5008 of 32 bit value) into 8 bit immediate value of LDI insn.
5010 BFD_RELOC_AVR_LO8_LDI_NEG
5012 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5013 (usually data memory address) into 8 bit immediate value of SUBI insn.
5015 BFD_RELOC_AVR_HI8_LDI_NEG
5017 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5018 (high 8 bit of data memory address) into 8 bit immediate value of
5021 BFD_RELOC_AVR_HH8_LDI_NEG
5023 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5024 (most high 8 bit of program memory address) into 8 bit immediate value
5025 of LDI or SUBI insn.
5027 BFD_RELOC_AVR_MS8_LDI_NEG
5029 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5030 of 32 bit value) into 8 bit immediate value of LDI insn.
5032 BFD_RELOC_AVR_LO8_LDI_PM
5034 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5035 command address) into 8 bit immediate value of LDI insn.
5037 BFD_RELOC_AVR_LO8_LDI_GS
5039 This is a 16 bit reloc for the AVR that stores 8 bit value
5040 (command address) into 8 bit immediate value of LDI insn. If the address
5041 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5044 BFD_RELOC_AVR_HI8_LDI_PM
5046 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5047 of command address) into 8 bit immediate value of LDI insn.
5049 BFD_RELOC_AVR_HI8_LDI_GS
5051 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5052 of command address) into 8 bit immediate value of LDI insn. If the address
5053 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5056 BFD_RELOC_AVR_HH8_LDI_PM
5058 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5059 of command address) into 8 bit immediate value of LDI insn.
5061 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5063 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5064 (usually command address) into 8 bit immediate value of SUBI insn.
5066 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5068 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5069 (high 8 bit of 16 bit command address) into 8 bit immediate value
5072 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5074 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5075 (high 6 bit of 22 bit command address) into 8 bit immediate
5080 This is a 32 bit reloc for the AVR that stores 23 bit value
5085 This is a 16 bit reloc for the AVR that stores all needed bits
5086 for absolute addressing with ldi with overflow check to linktime
5090 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5093 BFD_RELOC_AVR_6_ADIW
5095 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5100 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5101 in .byte lo8(symbol)
5105 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5106 in .byte hi8(symbol)
5110 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5111 in .byte hlo8(symbol)
5115 BFD_RELOC_AVR_DIFF16
5117 BFD_RELOC_AVR_DIFF32
5119 AVR relocations to mark the difference of two local symbols.
5120 These are only needed to support linker relaxation and can be ignored
5121 when not relaxing. The field is set to the value of the difference
5122 assuming no relaxation. The relocation encodes the position of the
5123 second symbol so the linker can determine whether to adjust the field
5126 BFD_RELOC_AVR_LDS_STS_16
5128 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5129 lds and sts instructions supported only tiny core.
5133 This is a 6 bit reloc for the AVR that stores an I/O register
5134 number for the IN and OUT instructions
5138 This is a 5 bit reloc for the AVR that stores an I/O register
5139 number for the SBIC, SBIS, SBI and CBI instructions
5142 BFD_RELOC_RISCV_HI20
5144 BFD_RELOC_RISCV_PCREL_HI20
5146 BFD_RELOC_RISCV_PCREL_LO12_I
5148 BFD_RELOC_RISCV_PCREL_LO12_S
5150 BFD_RELOC_RISCV_LO12_I
5152 BFD_RELOC_RISCV_LO12_S
5154 BFD_RELOC_RISCV_GPREL12_I
5156 BFD_RELOC_RISCV_GPREL12_S
5158 BFD_RELOC_RISCV_TPREL_HI20
5160 BFD_RELOC_RISCV_TPREL_LO12_I
5162 BFD_RELOC_RISCV_TPREL_LO12_S
5164 BFD_RELOC_RISCV_TPREL_ADD
5166 BFD_RELOC_RISCV_CALL
5168 BFD_RELOC_RISCV_CALL_PLT
5170 BFD_RELOC_RISCV_ADD8
5172 BFD_RELOC_RISCV_ADD16
5174 BFD_RELOC_RISCV_ADD32
5176 BFD_RELOC_RISCV_ADD64
5178 BFD_RELOC_RISCV_SUB8
5180 BFD_RELOC_RISCV_SUB16
5182 BFD_RELOC_RISCV_SUB32
5184 BFD_RELOC_RISCV_SUB64
5186 BFD_RELOC_RISCV_GOT_HI20
5188 BFD_RELOC_RISCV_TLS_GOT_HI20
5190 BFD_RELOC_RISCV_TLS_GD_HI20
5194 BFD_RELOC_RISCV_TLS_DTPMOD32
5196 BFD_RELOC_RISCV_TLS_DTPREL32
5198 BFD_RELOC_RISCV_TLS_DTPMOD64
5200 BFD_RELOC_RISCV_TLS_DTPREL64
5202 BFD_RELOC_RISCV_TLS_TPREL32
5204 BFD_RELOC_RISCV_TLS_TPREL64
5206 BFD_RELOC_RISCV_ALIGN
5208 BFD_RELOC_RISCV_RVC_BRANCH
5210 BFD_RELOC_RISCV_RVC_JUMP
5212 BFD_RELOC_RISCV_RVC_LUI
5214 BFD_RELOC_RISCV_GPREL_I
5216 BFD_RELOC_RISCV_GPREL_S
5218 BFD_RELOC_RISCV_TPREL_I
5220 BFD_RELOC_RISCV_TPREL_S
5222 BFD_RELOC_RISCV_RELAX
5226 BFD_RELOC_RISCV_SUB6
5228 BFD_RELOC_RISCV_SET6
5230 BFD_RELOC_RISCV_SET8
5232 BFD_RELOC_RISCV_SET16
5234 BFD_RELOC_RISCV_SET32
5236 BFD_RELOC_RISCV_32_PCREL
5243 BFD_RELOC_RL78_NEG16
5245 BFD_RELOC_RL78_NEG24
5247 BFD_RELOC_RL78_NEG32
5249 BFD_RELOC_RL78_16_OP
5251 BFD_RELOC_RL78_24_OP
5253 BFD_RELOC_RL78_32_OP
5261 BFD_RELOC_RL78_DIR3U_PCREL
5265 BFD_RELOC_RL78_GPRELB
5267 BFD_RELOC_RL78_GPRELW
5269 BFD_RELOC_RL78_GPRELL
5273 BFD_RELOC_RL78_OP_SUBTRACT
5275 BFD_RELOC_RL78_OP_NEG
5277 BFD_RELOC_RL78_OP_AND
5279 BFD_RELOC_RL78_OP_SHRA
5283 BFD_RELOC_RL78_ABS16
5285 BFD_RELOC_RL78_ABS16_REV
5287 BFD_RELOC_RL78_ABS32
5289 BFD_RELOC_RL78_ABS32_REV
5291 BFD_RELOC_RL78_ABS16U
5293 BFD_RELOC_RL78_ABS16UW
5295 BFD_RELOC_RL78_ABS16UL
5297 BFD_RELOC_RL78_RELAX
5307 BFD_RELOC_RL78_SADDR
5309 Renesas RL78 Relocations.
5332 BFD_RELOC_RX_DIR3U_PCREL
5344 BFD_RELOC_RX_OP_SUBTRACT
5352 BFD_RELOC_RX_ABS16_REV
5356 BFD_RELOC_RX_ABS32_REV
5360 BFD_RELOC_RX_ABS16UW
5362 BFD_RELOC_RX_ABS16UL
5366 Renesas RX Relocations.
5379 32 bit PC relative PLT address.
5383 Copy symbol at runtime.
5385 BFD_RELOC_390_GLOB_DAT
5389 BFD_RELOC_390_JMP_SLOT
5393 BFD_RELOC_390_RELATIVE
5395 Adjust by program base.
5399 32 bit PC relative offset to GOT.
5405 BFD_RELOC_390_PC12DBL
5407 PC relative 12 bit shifted by 1.
5409 BFD_RELOC_390_PLT12DBL
5411 12 bit PC rel. PLT shifted by 1.
5413 BFD_RELOC_390_PC16DBL
5415 PC relative 16 bit shifted by 1.
5417 BFD_RELOC_390_PLT16DBL
5419 16 bit PC rel. PLT shifted by 1.
5421 BFD_RELOC_390_PC24DBL
5423 PC relative 24 bit shifted by 1.
5425 BFD_RELOC_390_PLT24DBL
5427 24 bit PC rel. PLT shifted by 1.
5429 BFD_RELOC_390_PC32DBL
5431 PC relative 32 bit shifted by 1.
5433 BFD_RELOC_390_PLT32DBL
5435 32 bit PC rel. PLT shifted by 1.
5437 BFD_RELOC_390_GOTPCDBL
5439 32 bit PC rel. GOT shifted by 1.
5447 64 bit PC relative PLT address.
5449 BFD_RELOC_390_GOTENT
5451 32 bit rel. offset to GOT entry.
5453 BFD_RELOC_390_GOTOFF64
5455 64 bit offset to GOT.
5457 BFD_RELOC_390_GOTPLT12
5459 12-bit offset to symbol-entry within GOT, with PLT handling.
5461 BFD_RELOC_390_GOTPLT16
5463 16-bit offset to symbol-entry within GOT, with PLT handling.
5465 BFD_RELOC_390_GOTPLT32
5467 32-bit offset to symbol-entry within GOT, with PLT handling.
5469 BFD_RELOC_390_GOTPLT64
5471 64-bit offset to symbol-entry within GOT, with PLT handling.
5473 BFD_RELOC_390_GOTPLTENT
5475 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5477 BFD_RELOC_390_PLTOFF16
5479 16-bit rel. offset from the GOT to a PLT entry.
5481 BFD_RELOC_390_PLTOFF32
5483 32-bit rel. offset from the GOT to a PLT entry.
5485 BFD_RELOC_390_PLTOFF64
5487 64-bit rel. offset from the GOT to a PLT entry.
5490 BFD_RELOC_390_TLS_LOAD
5492 BFD_RELOC_390_TLS_GDCALL
5494 BFD_RELOC_390_TLS_LDCALL
5496 BFD_RELOC_390_TLS_GD32
5498 BFD_RELOC_390_TLS_GD64
5500 BFD_RELOC_390_TLS_GOTIE12
5502 BFD_RELOC_390_TLS_GOTIE32
5504 BFD_RELOC_390_TLS_GOTIE64
5506 BFD_RELOC_390_TLS_LDM32
5508 BFD_RELOC_390_TLS_LDM64
5510 BFD_RELOC_390_TLS_IE32
5512 BFD_RELOC_390_TLS_IE64
5514 BFD_RELOC_390_TLS_IEENT
5516 BFD_RELOC_390_TLS_LE32
5518 BFD_RELOC_390_TLS_LE64
5520 BFD_RELOC_390_TLS_LDO32
5522 BFD_RELOC_390_TLS_LDO64
5524 BFD_RELOC_390_TLS_DTPMOD
5526 BFD_RELOC_390_TLS_DTPOFF
5528 BFD_RELOC_390_TLS_TPOFF
5530 s390 tls relocations.
5537 BFD_RELOC_390_GOTPLT20
5539 BFD_RELOC_390_TLS_GOTIE20
5541 Long displacement extension.
5544 BFD_RELOC_390_IRELATIVE
5546 STT_GNU_IFUNC relocation.
5549 BFD_RELOC_SCORE_GPREL15
5552 Low 16 bit for load/store
5554 BFD_RELOC_SCORE_DUMMY2
5558 This is a 24-bit reloc with the right 1 bit assumed to be 0
5560 BFD_RELOC_SCORE_BRANCH
5562 This is a 19-bit reloc with the right 1 bit assumed to be 0
5564 BFD_RELOC_SCORE_IMM30
5566 This is a 32-bit reloc for 48-bit instructions.
5568 BFD_RELOC_SCORE_IMM32
5570 This is a 32-bit reloc for 48-bit instructions.
5572 BFD_RELOC_SCORE16_JMP
5574 This is a 11-bit reloc with the right 1 bit assumed to be 0
5576 BFD_RELOC_SCORE16_BRANCH
5578 This is a 8-bit reloc with the right 1 bit assumed to be 0
5580 BFD_RELOC_SCORE_BCMP
5582 This is a 9-bit reloc with the right 1 bit assumed to be 0
5584 BFD_RELOC_SCORE_GOT15
5586 BFD_RELOC_SCORE_GOT_LO16
5588 BFD_RELOC_SCORE_CALL15
5590 BFD_RELOC_SCORE_DUMMY_HI16
5592 Undocumented Score relocs
5597 Scenix IP2K - 9-bit register number / data address
5601 Scenix IP2K - 4-bit register/data bank number
5603 BFD_RELOC_IP2K_ADDR16CJP
5605 Scenix IP2K - low 13 bits of instruction word address
5607 BFD_RELOC_IP2K_PAGE3
5609 Scenix IP2K - high 3 bits of instruction word address
5611 BFD_RELOC_IP2K_LO8DATA
5613 BFD_RELOC_IP2K_HI8DATA
5615 BFD_RELOC_IP2K_EX8DATA
5617 Scenix IP2K - ext/low/high 8 bits of data address
5619 BFD_RELOC_IP2K_LO8INSN
5621 BFD_RELOC_IP2K_HI8INSN
5623 Scenix IP2K - low/high 8 bits of instruction word address
5625 BFD_RELOC_IP2K_PC_SKIP
5627 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5631 Scenix IP2K - 16 bit word address in text section.
5633 BFD_RELOC_IP2K_FR_OFFSET
5635 Scenix IP2K - 7-bit sp or dp offset
5637 BFD_RELOC_VPE4KMATH_DATA
5639 BFD_RELOC_VPE4KMATH_INSN
5641 Scenix VPE4K coprocessor - data/insn-space addressing
5644 BFD_RELOC_VTABLE_INHERIT
5646 BFD_RELOC_VTABLE_ENTRY
5648 These two relocations are used by the linker to determine which of
5649 the entries in a C++ virtual function table are actually used. When
5650 the --gc-sections option is given, the linker will zero out the entries
5651 that are not used, so that the code for those functions need not be
5652 included in the output.
5654 VTABLE_INHERIT is a zero-space relocation used to describe to the
5655 linker the inheritance tree of a C++ virtual function table. The
5656 relocation's symbol should be the parent class' vtable, and the
5657 relocation should be located at the child vtable.
5659 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5660 virtual function table entry. The reloc's symbol should refer to the
5661 table of the class mentioned in the code. Off of that base, an offset
5662 describes the entry that is being used. For Rela hosts, this offset
5663 is stored in the reloc's addend. For Rel hosts, we are forced to put
5664 this offset in the reloc's section offset.
5667 BFD_RELOC_IA64_IMM14
5669 BFD_RELOC_IA64_IMM22
5671 BFD_RELOC_IA64_IMM64
5673 BFD_RELOC_IA64_DIR32MSB
5675 BFD_RELOC_IA64_DIR32LSB
5677 BFD_RELOC_IA64_DIR64MSB
5679 BFD_RELOC_IA64_DIR64LSB
5681 BFD_RELOC_IA64_GPREL22
5683 BFD_RELOC_IA64_GPREL64I
5685 BFD_RELOC_IA64_GPREL32MSB
5687 BFD_RELOC_IA64_GPREL32LSB
5689 BFD_RELOC_IA64_GPREL64MSB
5691 BFD_RELOC_IA64_GPREL64LSB
5693 BFD_RELOC_IA64_LTOFF22
5695 BFD_RELOC_IA64_LTOFF64I
5697 BFD_RELOC_IA64_PLTOFF22
5699 BFD_RELOC_IA64_PLTOFF64I
5701 BFD_RELOC_IA64_PLTOFF64MSB
5703 BFD_RELOC_IA64_PLTOFF64LSB
5705 BFD_RELOC_IA64_FPTR64I
5707 BFD_RELOC_IA64_FPTR32MSB
5709 BFD_RELOC_IA64_FPTR32LSB
5711 BFD_RELOC_IA64_FPTR64MSB
5713 BFD_RELOC_IA64_FPTR64LSB
5715 BFD_RELOC_IA64_PCREL21B
5717 BFD_RELOC_IA64_PCREL21BI
5719 BFD_RELOC_IA64_PCREL21M
5721 BFD_RELOC_IA64_PCREL21F
5723 BFD_RELOC_IA64_PCREL22
5725 BFD_RELOC_IA64_PCREL60B
5727 BFD_RELOC_IA64_PCREL64I
5729 BFD_RELOC_IA64_PCREL32MSB
5731 BFD_RELOC_IA64_PCREL32LSB
5733 BFD_RELOC_IA64_PCREL64MSB
5735 BFD_RELOC_IA64_PCREL64LSB
5737 BFD_RELOC_IA64_LTOFF_FPTR22
5739 BFD_RELOC_IA64_LTOFF_FPTR64I
5741 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5743 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5745 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5747 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5749 BFD_RELOC_IA64_SEGREL32MSB
5751 BFD_RELOC_IA64_SEGREL32LSB
5753 BFD_RELOC_IA64_SEGREL64MSB
5755 BFD_RELOC_IA64_SEGREL64LSB
5757 BFD_RELOC_IA64_SECREL32MSB
5759 BFD_RELOC_IA64_SECREL32LSB
5761 BFD_RELOC_IA64_SECREL64MSB
5763 BFD_RELOC_IA64_SECREL64LSB
5765 BFD_RELOC_IA64_REL32MSB
5767 BFD_RELOC_IA64_REL32LSB
5769 BFD_RELOC_IA64_REL64MSB
5771 BFD_RELOC_IA64_REL64LSB
5773 BFD_RELOC_IA64_LTV32MSB
5775 BFD_RELOC_IA64_LTV32LSB
5777 BFD_RELOC_IA64_LTV64MSB
5779 BFD_RELOC_IA64_LTV64LSB
5781 BFD_RELOC_IA64_IPLTMSB
5783 BFD_RELOC_IA64_IPLTLSB
5787 BFD_RELOC_IA64_LTOFF22X
5789 BFD_RELOC_IA64_LDXMOV
5791 BFD_RELOC_IA64_TPREL14
5793 BFD_RELOC_IA64_TPREL22
5795 BFD_RELOC_IA64_TPREL64I
5797 BFD_RELOC_IA64_TPREL64MSB
5799 BFD_RELOC_IA64_TPREL64LSB
5801 BFD_RELOC_IA64_LTOFF_TPREL22
5803 BFD_RELOC_IA64_DTPMOD64MSB
5805 BFD_RELOC_IA64_DTPMOD64LSB
5807 BFD_RELOC_IA64_LTOFF_DTPMOD22
5809 BFD_RELOC_IA64_DTPREL14
5811 BFD_RELOC_IA64_DTPREL22
5813 BFD_RELOC_IA64_DTPREL64I
5815 BFD_RELOC_IA64_DTPREL32MSB
5817 BFD_RELOC_IA64_DTPREL32LSB
5819 BFD_RELOC_IA64_DTPREL64MSB
5821 BFD_RELOC_IA64_DTPREL64LSB
5823 BFD_RELOC_IA64_LTOFF_DTPREL22
5825 Intel IA64 Relocations.
5828 BFD_RELOC_M68HC11_HI8
5830 Motorola 68HC11 reloc.
5831 This is the 8 bit high part of an absolute address.
5833 BFD_RELOC_M68HC11_LO8
5835 Motorola 68HC11 reloc.
5836 This is the 8 bit low part of an absolute address.
5838 BFD_RELOC_M68HC11_3B
5840 Motorola 68HC11 reloc.
5841 This is the 3 bit of a value.
5843 BFD_RELOC_M68HC11_RL_JUMP
5845 Motorola 68HC11 reloc.
5846 This reloc marks the beginning of a jump/call instruction.
5847 It is used for linker relaxation to correctly identify beginning
5848 of instruction and change some branches to use PC-relative
5851 BFD_RELOC_M68HC11_RL_GROUP
5853 Motorola 68HC11 reloc.
5854 This reloc marks a group of several instructions that gcc generates
5855 and for which the linker relaxation pass can modify and/or remove
5858 BFD_RELOC_M68HC11_LO16
5860 Motorola 68HC11 reloc.
5861 This is the 16-bit lower part of an address. It is used for 'call'
5862 instruction to specify the symbol address without any special
5863 transformation (due to memory bank window).
5865 BFD_RELOC_M68HC11_PAGE
5867 Motorola 68HC11 reloc.
5868 This is a 8-bit reloc that specifies the page number of an address.
5869 It is used by 'call' instruction to specify the page number of
5872 BFD_RELOC_M68HC11_24
5874 Motorola 68HC11 reloc.
5875 This is a 24-bit reloc that represents the address with a 16-bit
5876 value and a 8-bit page number. The symbol address is transformed
5877 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5879 BFD_RELOC_M68HC12_5B
5881 Motorola 68HC12 reloc.
5882 This is the 5 bits of a value.
5884 BFD_RELOC_XGATE_RL_JUMP
5886 Freescale XGATE reloc.
5887 This reloc marks the beginning of a bra/jal instruction.
5889 BFD_RELOC_XGATE_RL_GROUP
5891 Freescale XGATE reloc.
5892 This reloc marks a group of several instructions that gcc generates
5893 and for which the linker relaxation pass can modify and/or remove
5896 BFD_RELOC_XGATE_LO16
5898 Freescale XGATE reloc.
5899 This is the 16-bit lower part of an address. It is used for the '16-bit'
5902 BFD_RELOC_XGATE_GPAGE
5904 Freescale XGATE reloc.
5908 Freescale XGATE reloc.
5910 BFD_RELOC_XGATE_PCREL_9
5912 Freescale XGATE reloc.
5913 This is a 9-bit pc-relative reloc.
5915 BFD_RELOC_XGATE_PCREL_10
5917 Freescale XGATE reloc.
5918 This is a 10-bit pc-relative reloc.
5920 BFD_RELOC_XGATE_IMM8_LO
5922 Freescale XGATE reloc.
5923 This is the 16-bit lower part of an address. It is used for the '16-bit'
5926 BFD_RELOC_XGATE_IMM8_HI
5928 Freescale XGATE reloc.
5929 This is the 16-bit higher part of an address. It is used for the '16-bit'
5932 BFD_RELOC_XGATE_IMM3
5934 Freescale XGATE reloc.
5935 This is a 3-bit pc-relative reloc.
5937 BFD_RELOC_XGATE_IMM4
5939 Freescale XGATE reloc.
5940 This is a 4-bit pc-relative reloc.
5942 BFD_RELOC_XGATE_IMM5
5944 Freescale XGATE reloc.
5945 This is a 5-bit pc-relative reloc.
5947 BFD_RELOC_M68HC12_9B
5949 Motorola 68HC12 reloc.
5950 This is the 9 bits of a value.
5952 BFD_RELOC_M68HC12_16B
5954 Motorola 68HC12 reloc.
5955 This is the 16 bits of a value.
5957 BFD_RELOC_M68HC12_9_PCREL
5959 Motorola 68HC12/XGATE reloc.
5960 This is a PCREL9 branch.
5962 BFD_RELOC_M68HC12_10_PCREL
5964 Motorola 68HC12/XGATE reloc.
5965 This is a PCREL10 branch.
5967 BFD_RELOC_M68HC12_LO8XG
5969 Motorola 68HC12/XGATE reloc.
5970 This is the 8 bit low part of an absolute address and immediately precedes
5971 a matching HI8XG part.
5973 BFD_RELOC_M68HC12_HI8XG
5975 Motorola 68HC12/XGATE reloc.
5976 This is the 8 bit high part of an absolute address and immediately follows
5977 a matching LO8XG part.
5979 BFD_RELOC_S12Z_15_PCREL
5981 Freescale S12Z reloc.
5982 This is a 15 bit relative address. If the most significant bits are all zero
5983 then it may be truncated to 8 bits.
5988 BFD_RELOC_CR16_NUM16
5990 BFD_RELOC_CR16_NUM32
5992 BFD_RELOC_CR16_NUM32a
5994 BFD_RELOC_CR16_REGREL0
5996 BFD_RELOC_CR16_REGREL4
5998 BFD_RELOC_CR16_REGREL4a
6000 BFD_RELOC_CR16_REGREL14
6002 BFD_RELOC_CR16_REGREL14a
6004 BFD_RELOC_CR16_REGREL16
6006 BFD_RELOC_CR16_REGREL20
6008 BFD_RELOC_CR16_REGREL20a
6010 BFD_RELOC_CR16_ABS20
6012 BFD_RELOC_CR16_ABS24
6018 BFD_RELOC_CR16_IMM16
6020 BFD_RELOC_CR16_IMM20
6022 BFD_RELOC_CR16_IMM24
6024 BFD_RELOC_CR16_IMM32
6026 BFD_RELOC_CR16_IMM32a
6028 BFD_RELOC_CR16_DISP4
6030 BFD_RELOC_CR16_DISP8
6032 BFD_RELOC_CR16_DISP16
6034 BFD_RELOC_CR16_DISP20
6036 BFD_RELOC_CR16_DISP24
6038 BFD_RELOC_CR16_DISP24a
6040 BFD_RELOC_CR16_SWITCH8
6042 BFD_RELOC_CR16_SWITCH16
6044 BFD_RELOC_CR16_SWITCH32
6046 BFD_RELOC_CR16_GOT_REGREL20
6048 BFD_RELOC_CR16_GOTC_REGREL20
6050 BFD_RELOC_CR16_GLOB_DAT
6052 NS CR16 Relocations.
6059 BFD_RELOC_CRX_REL8_CMP
6067 BFD_RELOC_CRX_REGREL12
6069 BFD_RELOC_CRX_REGREL22
6071 BFD_RELOC_CRX_REGREL28
6073 BFD_RELOC_CRX_REGREL32
6089 BFD_RELOC_CRX_SWITCH8
6091 BFD_RELOC_CRX_SWITCH16
6093 BFD_RELOC_CRX_SWITCH32
6098 BFD_RELOC_CRIS_BDISP8
6100 BFD_RELOC_CRIS_UNSIGNED_5
6102 BFD_RELOC_CRIS_SIGNED_6
6104 BFD_RELOC_CRIS_UNSIGNED_6
6106 BFD_RELOC_CRIS_SIGNED_8
6108 BFD_RELOC_CRIS_UNSIGNED_8
6110 BFD_RELOC_CRIS_SIGNED_16
6112 BFD_RELOC_CRIS_UNSIGNED_16
6114 BFD_RELOC_CRIS_LAPCQ_OFFSET
6116 BFD_RELOC_CRIS_UNSIGNED_4
6118 These relocs are only used within the CRIS assembler. They are not
6119 (at present) written to any object files.
6123 BFD_RELOC_CRIS_GLOB_DAT
6125 BFD_RELOC_CRIS_JUMP_SLOT
6127 BFD_RELOC_CRIS_RELATIVE
6129 Relocs used in ELF shared libraries for CRIS.
6131 BFD_RELOC_CRIS_32_GOT
6133 32-bit offset to symbol-entry within GOT.
6135 BFD_RELOC_CRIS_16_GOT
6137 16-bit offset to symbol-entry within GOT.
6139 BFD_RELOC_CRIS_32_GOTPLT
6141 32-bit offset to symbol-entry within GOT, with PLT handling.
6143 BFD_RELOC_CRIS_16_GOTPLT
6145 16-bit offset to symbol-entry within GOT, with PLT handling.
6147 BFD_RELOC_CRIS_32_GOTREL
6149 32-bit offset to symbol, relative to GOT.
6151 BFD_RELOC_CRIS_32_PLT_GOTREL
6153 32-bit offset to symbol with PLT entry, relative to GOT.
6155 BFD_RELOC_CRIS_32_PLT_PCREL
6157 32-bit offset to symbol with PLT entry, relative to this relocation.
6160 BFD_RELOC_CRIS_32_GOT_GD
6162 BFD_RELOC_CRIS_16_GOT_GD
6164 BFD_RELOC_CRIS_32_GD
6168 BFD_RELOC_CRIS_32_DTPREL
6170 BFD_RELOC_CRIS_16_DTPREL
6172 BFD_RELOC_CRIS_32_GOT_TPREL
6174 BFD_RELOC_CRIS_16_GOT_TPREL
6176 BFD_RELOC_CRIS_32_TPREL
6178 BFD_RELOC_CRIS_16_TPREL
6180 BFD_RELOC_CRIS_DTPMOD
6182 BFD_RELOC_CRIS_32_IE
6184 Relocs used in TLS code for CRIS.
6187 BFD_RELOC_OR1K_REL_26
6189 BFD_RELOC_OR1K_SLO16
6191 BFD_RELOC_OR1K_PCREL_PG21
6195 BFD_RELOC_OR1K_SLO13
6197 BFD_RELOC_OR1K_GOTPC_HI16
6199 BFD_RELOC_OR1K_GOTPC_LO16
6201 BFD_RELOC_OR1K_GOT16
6203 BFD_RELOC_OR1K_GOT_PG21
6205 BFD_RELOC_OR1K_GOT_LO13
6207 BFD_RELOC_OR1K_PLT26
6209 BFD_RELOC_OR1K_PLTA26
6211 BFD_RELOC_OR1K_GOTOFF_SLO16
6215 BFD_RELOC_OR1K_GLOB_DAT
6217 BFD_RELOC_OR1K_JMP_SLOT
6219 BFD_RELOC_OR1K_RELATIVE
6221 BFD_RELOC_OR1K_TLS_GD_HI16
6223 BFD_RELOC_OR1K_TLS_GD_LO16
6225 BFD_RELOC_OR1K_TLS_GD_PG21
6227 BFD_RELOC_OR1K_TLS_GD_LO13
6229 BFD_RELOC_OR1K_TLS_LDM_HI16
6231 BFD_RELOC_OR1K_TLS_LDM_LO16
6233 BFD_RELOC_OR1K_TLS_LDM_PG21
6235 BFD_RELOC_OR1K_TLS_LDM_LO13
6237 BFD_RELOC_OR1K_TLS_LDO_HI16
6239 BFD_RELOC_OR1K_TLS_LDO_LO16
6241 BFD_RELOC_OR1K_TLS_IE_HI16
6243 BFD_RELOC_OR1K_TLS_IE_AHI16
6245 BFD_RELOC_OR1K_TLS_IE_LO16
6247 BFD_RELOC_OR1K_TLS_IE_PG21
6249 BFD_RELOC_OR1K_TLS_IE_LO13
6251 BFD_RELOC_OR1K_TLS_LE_HI16
6253 BFD_RELOC_OR1K_TLS_LE_AHI16
6255 BFD_RELOC_OR1K_TLS_LE_LO16
6257 BFD_RELOC_OR1K_TLS_LE_SLO16
6259 BFD_RELOC_OR1K_TLS_TPOFF
6261 BFD_RELOC_OR1K_TLS_DTPOFF
6263 BFD_RELOC_OR1K_TLS_DTPMOD
6265 OpenRISC 1000 Relocations.
6268 BFD_RELOC_H8_DIR16A8
6270 BFD_RELOC_H8_DIR16R8
6272 BFD_RELOC_H8_DIR24A8
6274 BFD_RELOC_H8_DIR24R8
6276 BFD_RELOC_H8_DIR32A16
6278 BFD_RELOC_H8_DISP32A16
6283 BFD_RELOC_XSTORMY16_REL_12
6285 BFD_RELOC_XSTORMY16_12
6287 BFD_RELOC_XSTORMY16_24
6289 BFD_RELOC_XSTORMY16_FPTR16
6291 Sony Xstormy16 Relocations.
6296 Self-describing complex relocations.
6308 Infineon Relocations.
6311 BFD_RELOC_VAX_GLOB_DAT
6313 BFD_RELOC_VAX_JMP_SLOT
6315 BFD_RELOC_VAX_RELATIVE
6317 Relocations used by VAX ELF.
6322 Morpho MT - 16 bit immediate relocation.
6326 Morpho MT - Hi 16 bits of an address.
6330 Morpho MT - Low 16 bits of an address.
6332 BFD_RELOC_MT_GNU_VTINHERIT
6334 Morpho MT - Used to tell the linker which vtable entries are used.
6336 BFD_RELOC_MT_GNU_VTENTRY
6338 Morpho MT - Used to tell the linker which vtable entries are used.
6340 BFD_RELOC_MT_PCINSN8
6342 Morpho MT - 8 bit immediate relocation.
6345 BFD_RELOC_MSP430_10_PCREL
6347 BFD_RELOC_MSP430_16_PCREL
6351 BFD_RELOC_MSP430_16_PCREL_BYTE
6353 BFD_RELOC_MSP430_16_BYTE
6355 BFD_RELOC_MSP430_2X_PCREL
6357 BFD_RELOC_MSP430_RL_PCREL
6359 BFD_RELOC_MSP430_ABS8
6361 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6363 BFD_RELOC_MSP430X_PCR20_EXT_DST
6365 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6367 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6369 BFD_RELOC_MSP430X_ABS20_EXT_DST
6371 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6373 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6375 BFD_RELOC_MSP430X_ABS20_ADR_DST
6377 BFD_RELOC_MSP430X_PCR16
6379 BFD_RELOC_MSP430X_PCR20_CALL
6381 BFD_RELOC_MSP430X_ABS16
6383 BFD_RELOC_MSP430_ABS_HI16
6385 BFD_RELOC_MSP430_PREL31
6387 BFD_RELOC_MSP430_SYM_DIFF
6389 BFD_RELOC_MSP430_SET_ULEB128
6391 BFD_RELOC_MSP430_SUB_ULEB128
6394 msp430 specific relocation codes
6401 BFD_RELOC_NIOS2_CALL26
6403 BFD_RELOC_NIOS2_IMM5
6405 BFD_RELOC_NIOS2_CACHE_OPX
6407 BFD_RELOC_NIOS2_IMM6
6409 BFD_RELOC_NIOS2_IMM8
6411 BFD_RELOC_NIOS2_HI16
6413 BFD_RELOC_NIOS2_LO16
6415 BFD_RELOC_NIOS2_HIADJ16
6417 BFD_RELOC_NIOS2_GPREL
6419 BFD_RELOC_NIOS2_UJMP
6421 BFD_RELOC_NIOS2_CJMP
6423 BFD_RELOC_NIOS2_CALLR
6425 BFD_RELOC_NIOS2_ALIGN
6427 BFD_RELOC_NIOS2_GOT16
6429 BFD_RELOC_NIOS2_CALL16
6431 BFD_RELOC_NIOS2_GOTOFF_LO
6433 BFD_RELOC_NIOS2_GOTOFF_HA
6435 BFD_RELOC_NIOS2_PCREL_LO
6437 BFD_RELOC_NIOS2_PCREL_HA
6439 BFD_RELOC_NIOS2_TLS_GD16
6441 BFD_RELOC_NIOS2_TLS_LDM16
6443 BFD_RELOC_NIOS2_TLS_LDO16
6445 BFD_RELOC_NIOS2_TLS_IE16
6447 BFD_RELOC_NIOS2_TLS_LE16
6449 BFD_RELOC_NIOS2_TLS_DTPMOD
6451 BFD_RELOC_NIOS2_TLS_DTPREL
6453 BFD_RELOC_NIOS2_TLS_TPREL
6455 BFD_RELOC_NIOS2_COPY
6457 BFD_RELOC_NIOS2_GLOB_DAT
6459 BFD_RELOC_NIOS2_JUMP_SLOT
6461 BFD_RELOC_NIOS2_RELATIVE
6463 BFD_RELOC_NIOS2_GOTOFF
6465 BFD_RELOC_NIOS2_CALL26_NOAT
6467 BFD_RELOC_NIOS2_GOT_LO
6469 BFD_RELOC_NIOS2_GOT_HA
6471 BFD_RELOC_NIOS2_CALL_LO
6473 BFD_RELOC_NIOS2_CALL_HA
6475 BFD_RELOC_NIOS2_R2_S12
6477 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6479 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6481 BFD_RELOC_NIOS2_R2_T1I7_2
6483 BFD_RELOC_NIOS2_R2_T2I4
6485 BFD_RELOC_NIOS2_R2_T2I4_1
6487 BFD_RELOC_NIOS2_R2_T2I4_2
6489 BFD_RELOC_NIOS2_R2_X1I7_2
6491 BFD_RELOC_NIOS2_R2_X2L5
6493 BFD_RELOC_NIOS2_R2_F1I5_2
6495 BFD_RELOC_NIOS2_R2_L5I4X1
6497 BFD_RELOC_NIOS2_R2_T1X1I6
6499 BFD_RELOC_NIOS2_R2_T1X1I6_2
6501 Relocations used by the Altera Nios II core.
6506 PRU LDI 16-bit unsigned data-memory relocation.
6508 BFD_RELOC_PRU_U16_PMEMIMM
6510 PRU LDI 16-bit unsigned instruction-memory relocation.
6514 PRU relocation for two consecutive LDI load instructions that load a
6515 32 bit value into a register. If the higher bits are all zero, then
6516 the second instruction may be relaxed.
6518 BFD_RELOC_PRU_S10_PCREL
6520 PRU QBBx 10-bit signed PC-relative relocation.
6522 BFD_RELOC_PRU_U8_PCREL
6524 PRU 8-bit unsigned relocation used for the LOOP instruction.
6526 BFD_RELOC_PRU_32_PMEM
6528 BFD_RELOC_PRU_16_PMEM
6530 PRU Program Memory relocations. Used to convert from byte addressing to
6531 32-bit word addressing.
6533 BFD_RELOC_PRU_GNU_DIFF8
6535 BFD_RELOC_PRU_GNU_DIFF16
6537 BFD_RELOC_PRU_GNU_DIFF32
6539 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6541 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6543 PRU relocations to mark the difference of two local symbols.
6544 These are only needed to support linker relaxation and can be ignored
6545 when not relaxing. The field is set to the value of the difference
6546 assuming no relaxation. The relocation encodes the position of the
6547 second symbol so the linker can determine whether to adjust the field
6548 value. The PMEM variants encode the word difference, instead of byte
6549 difference between symbols.
6552 BFD_RELOC_IQ2000_OFFSET_16
6554 BFD_RELOC_IQ2000_OFFSET_21
6556 BFD_RELOC_IQ2000_UHI16
6561 BFD_RELOC_XTENSA_RTLD
6563 Special Xtensa relocation used only by PLT entries in ELF shared
6564 objects to indicate that the runtime linker should set the value
6565 to one of its own internal functions or data structures.
6567 BFD_RELOC_XTENSA_GLOB_DAT
6569 BFD_RELOC_XTENSA_JMP_SLOT
6571 BFD_RELOC_XTENSA_RELATIVE
6573 Xtensa relocations for ELF shared objects.
6575 BFD_RELOC_XTENSA_PLT
6577 Xtensa relocation used in ELF object files for symbols that may require
6578 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6580 BFD_RELOC_XTENSA_DIFF8
6582 BFD_RELOC_XTENSA_DIFF16
6584 BFD_RELOC_XTENSA_DIFF32
6586 Xtensa relocations for backward compatibility. These have been replaced
6587 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6588 Xtensa relocations to mark the difference of two local symbols.
6589 These are only needed to support linker relaxation and can be ignored
6590 when not relaxing. The field is set to the value of the difference
6591 assuming no relaxation. The relocation encodes the position of the
6592 first symbol so the linker can determine whether to adjust the field
6595 BFD_RELOC_XTENSA_SLOT0_OP
6597 BFD_RELOC_XTENSA_SLOT1_OP
6599 BFD_RELOC_XTENSA_SLOT2_OP
6601 BFD_RELOC_XTENSA_SLOT3_OP
6603 BFD_RELOC_XTENSA_SLOT4_OP
6605 BFD_RELOC_XTENSA_SLOT5_OP
6607 BFD_RELOC_XTENSA_SLOT6_OP
6609 BFD_RELOC_XTENSA_SLOT7_OP
6611 BFD_RELOC_XTENSA_SLOT8_OP
6613 BFD_RELOC_XTENSA_SLOT9_OP
6615 BFD_RELOC_XTENSA_SLOT10_OP
6617 BFD_RELOC_XTENSA_SLOT11_OP
6619 BFD_RELOC_XTENSA_SLOT12_OP
6621 BFD_RELOC_XTENSA_SLOT13_OP
6623 BFD_RELOC_XTENSA_SLOT14_OP
6625 Generic Xtensa relocations for instruction operands. Only the slot
6626 number is encoded in the relocation. The relocation applies to the
6627 last PC-relative immediate operand, or if there are no PC-relative
6628 immediates, to the last immediate operand.
6630 BFD_RELOC_XTENSA_SLOT0_ALT
6632 BFD_RELOC_XTENSA_SLOT1_ALT
6634 BFD_RELOC_XTENSA_SLOT2_ALT
6636 BFD_RELOC_XTENSA_SLOT3_ALT
6638 BFD_RELOC_XTENSA_SLOT4_ALT
6640 BFD_RELOC_XTENSA_SLOT5_ALT
6642 BFD_RELOC_XTENSA_SLOT6_ALT
6644 BFD_RELOC_XTENSA_SLOT7_ALT
6646 BFD_RELOC_XTENSA_SLOT8_ALT
6648 BFD_RELOC_XTENSA_SLOT9_ALT
6650 BFD_RELOC_XTENSA_SLOT10_ALT
6652 BFD_RELOC_XTENSA_SLOT11_ALT
6654 BFD_RELOC_XTENSA_SLOT12_ALT
6656 BFD_RELOC_XTENSA_SLOT13_ALT
6658 BFD_RELOC_XTENSA_SLOT14_ALT
6660 Alternate Xtensa relocations. Only the slot is encoded in the
6661 relocation. The meaning of these relocations is opcode-specific.
6663 BFD_RELOC_XTENSA_OP0
6665 BFD_RELOC_XTENSA_OP1
6667 BFD_RELOC_XTENSA_OP2
6669 Xtensa relocations for backward compatibility. These have all been
6670 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6672 BFD_RELOC_XTENSA_ASM_EXPAND
6674 Xtensa relocation to mark that the assembler expanded the
6675 instructions from an original target. The expansion size is
6676 encoded in the reloc size.
6678 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6680 Xtensa relocation to mark that the linker should simplify
6681 assembler-expanded instructions. This is commonly used
6682 internally by the linker after analysis of a
6683 BFD_RELOC_XTENSA_ASM_EXPAND.
6685 BFD_RELOC_XTENSA_TLSDESC_FN
6687 BFD_RELOC_XTENSA_TLSDESC_ARG
6689 BFD_RELOC_XTENSA_TLS_DTPOFF
6691 BFD_RELOC_XTENSA_TLS_TPOFF
6693 BFD_RELOC_XTENSA_TLS_FUNC
6695 BFD_RELOC_XTENSA_TLS_ARG
6697 BFD_RELOC_XTENSA_TLS_CALL
6699 Xtensa TLS relocations.
6701 BFD_RELOC_XTENSA_PDIFF8
6703 BFD_RELOC_XTENSA_PDIFF16
6705 BFD_RELOC_XTENSA_PDIFF32
6707 BFD_RELOC_XTENSA_NDIFF8
6709 BFD_RELOC_XTENSA_NDIFF16
6711 BFD_RELOC_XTENSA_NDIFF32
6713 Xtensa relocations to mark the difference of two local symbols.
6714 These are only needed to support linker relaxation and can be ignored
6715 when not relaxing. The field is set to the value of the difference
6716 assuming no relaxation. The relocation encodes the position of the
6717 subtracted symbol so the linker can determine whether to adjust the field
6718 value. PDIFF relocations are used for positive differences, NDIFF
6719 relocations are used for negative differences. The difference value
6720 is treated as unsigned with these relocation types, giving full
6726 8 bit signed offset in (ix+d) or (iy+d).
6730 First 8 bits of multibyte (32, 24 or 16 bit) value.
6734 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6738 Third 8 bits of multibyte (32 or 24 bit) value.
6742 Fourth 8 bits of multibyte (32 bit) value.
6746 Lowest 16 bits of multibyte (32 or 24 bit) value.
6750 Highest 16 bits of multibyte (32 or 24 bit) value.
6754 Like BFD_RELOC_16 but big-endian.
6772 BFD_RELOC_LM32_BRANCH
6774 BFD_RELOC_LM32_16_GOT
6776 BFD_RELOC_LM32_GOTOFF_HI16
6778 BFD_RELOC_LM32_GOTOFF_LO16
6782 BFD_RELOC_LM32_GLOB_DAT
6784 BFD_RELOC_LM32_JMP_SLOT
6786 BFD_RELOC_LM32_RELATIVE
6788 Lattice Mico32 relocations.
6791 BFD_RELOC_MACH_O_SECTDIFF
6793 Difference between two section addreses. Must be followed by a
6794 BFD_RELOC_MACH_O_PAIR.
6796 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6798 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6800 BFD_RELOC_MACH_O_PAIR
6802 Pair of relocation. Contains the first symbol.
6804 BFD_RELOC_MACH_O_SUBTRACTOR32
6806 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6808 BFD_RELOC_MACH_O_SUBTRACTOR64
6810 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6813 BFD_RELOC_MACH_O_X86_64_BRANCH32
6815 BFD_RELOC_MACH_O_X86_64_BRANCH8
6817 PCREL relocations. They are marked as branch to create PLT entry if
6820 BFD_RELOC_MACH_O_X86_64_GOT
6822 Used when referencing a GOT entry.
6824 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6826 Used when loading a GOT entry with movq. It is specially marked so that
6827 the linker could optimize the movq to a leaq if possible.
6829 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6831 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6833 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6835 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6837 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6839 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6841 BFD_RELOC_MACH_O_X86_64_TLV
6843 Used when referencing a TLV entry.
6847 BFD_RELOC_MACH_O_ARM64_ADDEND
6849 Addend for PAGE or PAGEOFF.
6851 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6853 Relative offset to page of GOT slot.
6855 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6857 Relative offset within page of GOT slot.
6859 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6861 Address of a GOT entry.
6864 BFD_RELOC_MICROBLAZE_32_LO
6866 This is a 32 bit reloc for the microblaze that stores the
6867 low 16 bits of a value
6869 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6871 This is a 32 bit pc-relative reloc for the microblaze that
6872 stores the low 16 bits of a value
6874 BFD_RELOC_MICROBLAZE_32_ROSDA
6876 This is a 32 bit reloc for the microblaze that stores a
6877 value relative to the read-only small data area anchor
6879 BFD_RELOC_MICROBLAZE_32_RWSDA
6881 This is a 32 bit reloc for the microblaze that stores a
6882 value relative to the read-write small data area anchor
6884 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6886 This is a 32 bit reloc for the microblaze to handle
6887 expressions of the form "Symbol Op Symbol"
6889 BFD_RELOC_MICROBLAZE_64_NONE
6891 This is a 64 bit reloc that stores the 32 bit pc relative
6892 value in two words (with an imm instruction). No relocation is
6893 done here - only used for relaxing
6895 BFD_RELOC_MICROBLAZE_64_GOTPC
6897 This is a 64 bit reloc that stores the 32 bit pc relative
6898 value in two words (with an imm instruction). The relocation is
6899 PC-relative GOT offset
6901 BFD_RELOC_MICROBLAZE_64_GOT
6903 This is a 64 bit reloc that stores the 32 bit pc relative
6904 value in two words (with an imm instruction). The relocation is
6907 BFD_RELOC_MICROBLAZE_64_PLT
6909 This is a 64 bit reloc that stores the 32 bit pc relative
6910 value in two words (with an imm instruction). The relocation is
6911 PC-relative offset into PLT
6913 BFD_RELOC_MICROBLAZE_64_GOTOFF
6915 This is a 64 bit reloc that stores the 32 bit GOT relative
6916 value in two words (with an imm instruction). The relocation is
6917 relative offset from _GLOBAL_OFFSET_TABLE_
6919 BFD_RELOC_MICROBLAZE_32_GOTOFF
6921 This is a 32 bit reloc that stores the 32 bit GOT relative
6922 value in a word. The relocation is relative offset from
6923 _GLOBAL_OFFSET_TABLE_
6925 BFD_RELOC_MICROBLAZE_COPY
6927 This is used to tell the dynamic linker to copy the value out of
6928 the dynamic object into the runtime process image.
6930 BFD_RELOC_MICROBLAZE_64_TLS
6934 BFD_RELOC_MICROBLAZE_64_TLSGD
6936 This is a 64 bit reloc that stores the 32 bit GOT relative value
6937 of the GOT TLS GD info entry in two words (with an imm instruction). The
6938 relocation is GOT offset.
6940 BFD_RELOC_MICROBLAZE_64_TLSLD
6942 This is a 64 bit reloc that stores the 32 bit GOT relative value
6943 of the GOT TLS LD info entry in two words (with an imm instruction). The
6944 relocation is GOT offset.
6946 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6948 This is a 32 bit reloc that stores the Module ID to GOT(n).
6950 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6952 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6954 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6956 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6959 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6961 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6962 to two words (uses imm instruction).
6964 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6966 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6967 to two words (uses imm instruction).
6969 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6971 This is a 64 bit reloc that stores the 32 bit pc relative
6972 value in two words (with an imm instruction). The relocation is
6973 PC-relative offset from start of TEXT.
6975 BFD_RELOC_MICROBLAZE_64_TEXTREL
6977 This is a 64 bit reloc that stores the 32 bit offset
6978 value in two words (with an imm instruction). The relocation is
6979 relative offset from start of TEXT.
6982 BFD_RELOC_AARCH64_RELOC_START
6984 AArch64 pseudo relocation code to mark the start of the AArch64
6985 relocation enumerators. N.B. the order of the enumerators is
6986 important as several tables in the AArch64 bfd backend are indexed
6987 by these enumerators; make sure they are all synced.
6989 BFD_RELOC_AARCH64_NULL
6991 Deprecated AArch64 null relocation code.
6993 BFD_RELOC_AARCH64_NONE
6995 AArch64 null relocation code.
6997 BFD_RELOC_AARCH64_64
6999 BFD_RELOC_AARCH64_32
7001 BFD_RELOC_AARCH64_16
7003 Basic absolute relocations of N bits. These are equivalent to
7004 BFD_RELOC_N and they were added to assist the indexing of the howto
7007 BFD_RELOC_AARCH64_64_PCREL
7009 BFD_RELOC_AARCH64_32_PCREL
7011 BFD_RELOC_AARCH64_16_PCREL
7013 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
7014 and they were added to assist the indexing of the howto table.
7016 BFD_RELOC_AARCH64_MOVW_G0
7018 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7019 of an unsigned address/value.
7021 BFD_RELOC_AARCH64_MOVW_G0_NC
7023 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7024 an address/value. No overflow checking.
7026 BFD_RELOC_AARCH64_MOVW_G1
7028 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7029 of an unsigned address/value.
7031 BFD_RELOC_AARCH64_MOVW_G1_NC
7033 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7034 of an address/value. No overflow checking.
7036 BFD_RELOC_AARCH64_MOVW_G2
7038 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7039 of an unsigned address/value.
7041 BFD_RELOC_AARCH64_MOVW_G2_NC
7043 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7044 of an address/value. No overflow checking.
7046 BFD_RELOC_AARCH64_MOVW_G3
7048 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7049 of a signed or unsigned address/value.
7051 BFD_RELOC_AARCH64_MOVW_G0_S
7053 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7054 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7057 BFD_RELOC_AARCH64_MOVW_G1_S
7059 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7060 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7063 BFD_RELOC_AARCH64_MOVW_G2_S
7065 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7066 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7069 BFD_RELOC_AARCH64_MOVW_PREL_G0
7071 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7072 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7075 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7077 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7078 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7081 BFD_RELOC_AARCH64_MOVW_PREL_G1
7083 AArch64 MOVK instruction with most significant bits 16 to 31
7086 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7088 AArch64 MOVK instruction with most significant bits 16 to 31
7091 BFD_RELOC_AARCH64_MOVW_PREL_G2
7093 AArch64 MOVK instruction with most significant bits 32 to 47
7096 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7098 AArch64 MOVK instruction with most significant bits 32 to 47
7101 BFD_RELOC_AARCH64_MOVW_PREL_G3
7103 AArch64 MOVK instruction with most significant bits 47 to 63
7106 BFD_RELOC_AARCH64_LD_LO19_PCREL
7108 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7109 offset. The lowest two bits must be zero and are not stored in the
7110 instruction, giving a 21 bit signed byte offset.
7112 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7114 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7116 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7118 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7119 offset, giving a 4KB aligned page base address.
7121 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7123 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7124 offset, giving a 4KB aligned page base address, but with no overflow
7127 BFD_RELOC_AARCH64_ADD_LO12
7129 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7130 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7132 BFD_RELOC_AARCH64_LDST8_LO12
7134 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7135 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7137 BFD_RELOC_AARCH64_TSTBR14
7139 AArch64 14 bit pc-relative test bit and branch.
7140 The lowest two bits must be zero and are not stored in the instruction,
7141 giving a 16 bit signed byte offset.
7143 BFD_RELOC_AARCH64_BRANCH19
7145 AArch64 19 bit pc-relative conditional branch and compare & branch.
7146 The lowest two bits must be zero and are not stored in the instruction,
7147 giving a 21 bit signed byte offset.
7149 BFD_RELOC_AARCH64_JUMP26
7151 AArch64 26 bit pc-relative unconditional branch.
7152 The lowest two bits must be zero and are not stored in the instruction,
7153 giving a 28 bit signed byte offset.
7155 BFD_RELOC_AARCH64_CALL26
7157 AArch64 26 bit pc-relative unconditional branch and link.
7158 The lowest two bits must be zero and are not stored in the instruction,
7159 giving a 28 bit signed byte offset.
7161 BFD_RELOC_AARCH64_LDST16_LO12
7163 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7164 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7166 BFD_RELOC_AARCH64_LDST32_LO12
7168 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7169 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7171 BFD_RELOC_AARCH64_LDST64_LO12
7173 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7174 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7176 BFD_RELOC_AARCH64_LDST128_LO12
7178 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7179 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7181 BFD_RELOC_AARCH64_GOT_LD_PREL19
7183 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7184 offset of the global offset table entry for a symbol. The lowest two
7185 bits must be zero and are not stored in the instruction, giving a 21
7186 bit signed byte offset. This relocation type requires signed overflow
7189 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7191 Get to the page base of the global offset table entry for a symbol as
7192 part of an ADRP instruction using a 21 bit PC relative value.Used in
7193 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7195 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7197 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7198 the GOT entry for this symbol. Used in conjunction with
7199 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7201 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7203 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7204 the GOT entry for this symbol. Used in conjunction with
7205 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7207 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7209 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7210 for this symbol. Valid in LP64 ABI only.
7212 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7214 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7215 for this symbol. Valid in LP64 ABI only.
7217 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7219 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7220 the GOT entry for this symbol. Valid in LP64 ABI only.
7222 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7224 Scaled 14 bit byte offset to the page base of the global offset table.
7226 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7228 Scaled 15 bit byte offset to the page base of the global offset table.
7230 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7232 Get to the page base of the global offset table entry for a symbols
7233 tls_index structure as part of an adrp instruction using a 21 bit PC
7234 relative value. Used in conjunction with
7235 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7237 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7239 AArch64 TLS General Dynamic
7241 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7243 Unsigned 12 bit byte offset to global offset table entry for a symbols
7244 tls_index structure. Used in conjunction with
7245 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7247 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7249 AArch64 TLS General Dynamic relocation.
7251 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7253 AArch64 TLS General Dynamic relocation.
7255 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7257 AArch64 TLS INITIAL EXEC relocation.
7259 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7261 AArch64 TLS INITIAL EXEC relocation.
7263 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7265 AArch64 TLS INITIAL EXEC relocation.
7267 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7269 AArch64 TLS INITIAL EXEC relocation.
7271 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7273 AArch64 TLS INITIAL EXEC relocation.
7275 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7277 AArch64 TLS INITIAL EXEC relocation.
7279 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7281 bit[23:12] of byte offset to module TLS base address.
7283 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7285 Unsigned 12 bit byte offset to module TLS base address.
7287 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7289 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7291 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7293 Unsigned 12 bit byte offset to global offset table entry for a symbols
7294 tls_index structure. Used in conjunction with
7295 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7297 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7299 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7302 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7304 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7306 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7308 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7311 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7313 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7315 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7317 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7320 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7322 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7324 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7326 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7329 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7331 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7333 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7335 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7338 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7340 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7342 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7344 bit[15:0] of byte offset to module TLS base address.
7346 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7348 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7350 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7352 bit[31:16] of byte offset to module TLS base address.
7354 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7356 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7358 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7360 bit[47:32] of byte offset to module TLS base address.
7362 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7364 AArch64 TLS LOCAL EXEC relocation.
7366 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7368 AArch64 TLS LOCAL EXEC relocation.
7370 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7372 AArch64 TLS LOCAL EXEC relocation.
7374 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7376 AArch64 TLS LOCAL EXEC relocation.
7378 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7380 AArch64 TLS LOCAL EXEC relocation.
7382 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7384 AArch64 TLS LOCAL EXEC relocation.
7386 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7388 AArch64 TLS LOCAL EXEC relocation.
7390 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7392 AArch64 TLS LOCAL EXEC relocation.
7394 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7396 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7399 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7401 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7403 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7405 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7408 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7410 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7412 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7414 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7417 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7419 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7421 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7423 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7426 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7428 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7430 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7432 AArch64 TLS DESC relocation.
7434 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7436 AArch64 TLS DESC relocation.
7438 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7440 AArch64 TLS DESC relocation.
7442 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7444 AArch64 TLS DESC relocation.
7446 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7448 AArch64 TLS DESC relocation.
7450 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7452 AArch64 TLS DESC relocation.
7454 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7456 AArch64 TLS DESC relocation.
7458 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7460 AArch64 TLS DESC relocation.
7462 BFD_RELOC_AARCH64_TLSDESC_LDR
7464 AArch64 TLS DESC relocation.
7466 BFD_RELOC_AARCH64_TLSDESC_ADD
7468 AArch64 TLS DESC relocation.
7470 BFD_RELOC_AARCH64_TLSDESC_CALL
7472 AArch64 TLS DESC relocation.
7474 BFD_RELOC_AARCH64_COPY
7476 AArch64 TLS relocation.
7478 BFD_RELOC_AARCH64_GLOB_DAT
7480 AArch64 TLS relocation.
7482 BFD_RELOC_AARCH64_JUMP_SLOT
7484 AArch64 TLS relocation.
7486 BFD_RELOC_AARCH64_RELATIVE
7488 AArch64 TLS relocation.
7490 BFD_RELOC_AARCH64_TLS_DTPMOD
7492 AArch64 TLS relocation.
7494 BFD_RELOC_AARCH64_TLS_DTPREL
7496 AArch64 TLS relocation.
7498 BFD_RELOC_AARCH64_TLS_TPREL
7500 AArch64 TLS relocation.
7502 BFD_RELOC_AARCH64_TLSDESC
7504 AArch64 TLS relocation.
7506 BFD_RELOC_AARCH64_IRELATIVE
7508 AArch64 support for STT_GNU_IFUNC.
7510 BFD_RELOC_AARCH64_RELOC_END
7512 AArch64 pseudo relocation code to mark the end of the AArch64
7513 relocation enumerators that have direct mapping to ELF reloc codes.
7514 There are a few more enumerators after this one; those are mainly
7515 used by the AArch64 assembler for the internal fixup or to select
7516 one of the above enumerators.
7518 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7520 AArch64 pseudo relocation code to be used internally by the AArch64
7521 assembler and not (currently) written to any object files.
7523 BFD_RELOC_AARCH64_LDST_LO12
7525 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7526 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7528 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7530 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7531 used internally by the AArch64 assembler and not (currently) written to
7534 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7536 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7538 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7540 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7541 used internally by the AArch64 assembler and not (currently) written to
7544 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7546 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7548 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7550 AArch64 pseudo relocation code to be used internally by the AArch64
7551 assembler and not (currently) written to any object files.
7553 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7555 AArch64 pseudo relocation code to be used internally by the AArch64
7556 assembler and not (currently) written to any object files.
7558 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7560 AArch64 pseudo relocation code to be used internally by the AArch64
7561 assembler and not (currently) written to any object files.
7563 BFD_RELOC_TILEPRO_COPY
7565 BFD_RELOC_TILEPRO_GLOB_DAT
7567 BFD_RELOC_TILEPRO_JMP_SLOT
7569 BFD_RELOC_TILEPRO_RELATIVE
7571 BFD_RELOC_TILEPRO_BROFF_X1
7573 BFD_RELOC_TILEPRO_JOFFLONG_X1
7575 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7577 BFD_RELOC_TILEPRO_IMM8_X0
7579 BFD_RELOC_TILEPRO_IMM8_Y0
7581 BFD_RELOC_TILEPRO_IMM8_X1
7583 BFD_RELOC_TILEPRO_IMM8_Y1
7585 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7587 BFD_RELOC_TILEPRO_MT_IMM15_X1
7589 BFD_RELOC_TILEPRO_MF_IMM15_X1
7591 BFD_RELOC_TILEPRO_IMM16_X0
7593 BFD_RELOC_TILEPRO_IMM16_X1
7595 BFD_RELOC_TILEPRO_IMM16_X0_LO
7597 BFD_RELOC_TILEPRO_IMM16_X1_LO
7599 BFD_RELOC_TILEPRO_IMM16_X0_HI
7601 BFD_RELOC_TILEPRO_IMM16_X1_HI
7603 BFD_RELOC_TILEPRO_IMM16_X0_HA
7605 BFD_RELOC_TILEPRO_IMM16_X1_HA
7607 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7609 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7611 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7613 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7615 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7617 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7619 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7621 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7623 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7625 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7627 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7629 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7631 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7633 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7635 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7637 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7639 BFD_RELOC_TILEPRO_MMSTART_X0
7641 BFD_RELOC_TILEPRO_MMEND_X0
7643 BFD_RELOC_TILEPRO_MMSTART_X1
7645 BFD_RELOC_TILEPRO_MMEND_X1
7647 BFD_RELOC_TILEPRO_SHAMT_X0
7649 BFD_RELOC_TILEPRO_SHAMT_X1
7651 BFD_RELOC_TILEPRO_SHAMT_Y0
7653 BFD_RELOC_TILEPRO_SHAMT_Y1
7655 BFD_RELOC_TILEPRO_TLS_GD_CALL
7657 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7659 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7661 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7663 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7665 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7667 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7669 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7671 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7673 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7675 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7677 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7679 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7681 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7683 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7685 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7687 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7689 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7691 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7693 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7695 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7697 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7699 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7701 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7703 BFD_RELOC_TILEPRO_TLS_TPOFF32
7705 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7707 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7709 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7711 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7713 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7715 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7717 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7719 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7721 Tilera TILEPro Relocations.
7723 BFD_RELOC_TILEGX_HW0
7725 BFD_RELOC_TILEGX_HW1
7727 BFD_RELOC_TILEGX_HW2
7729 BFD_RELOC_TILEGX_HW3
7731 BFD_RELOC_TILEGX_HW0_LAST
7733 BFD_RELOC_TILEGX_HW1_LAST
7735 BFD_RELOC_TILEGX_HW2_LAST
7737 BFD_RELOC_TILEGX_COPY
7739 BFD_RELOC_TILEGX_GLOB_DAT
7741 BFD_RELOC_TILEGX_JMP_SLOT
7743 BFD_RELOC_TILEGX_RELATIVE
7745 BFD_RELOC_TILEGX_BROFF_X1
7747 BFD_RELOC_TILEGX_JUMPOFF_X1
7749 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7751 BFD_RELOC_TILEGX_IMM8_X0
7753 BFD_RELOC_TILEGX_IMM8_Y0
7755 BFD_RELOC_TILEGX_IMM8_X1
7757 BFD_RELOC_TILEGX_IMM8_Y1
7759 BFD_RELOC_TILEGX_DEST_IMM8_X1
7761 BFD_RELOC_TILEGX_MT_IMM14_X1
7763 BFD_RELOC_TILEGX_MF_IMM14_X1
7765 BFD_RELOC_TILEGX_MMSTART_X0
7767 BFD_RELOC_TILEGX_MMEND_X0
7769 BFD_RELOC_TILEGX_SHAMT_X0
7771 BFD_RELOC_TILEGX_SHAMT_X1
7773 BFD_RELOC_TILEGX_SHAMT_Y0
7775 BFD_RELOC_TILEGX_SHAMT_Y1
7777 BFD_RELOC_TILEGX_IMM16_X0_HW0
7779 BFD_RELOC_TILEGX_IMM16_X1_HW0
7781 BFD_RELOC_TILEGX_IMM16_X0_HW1
7783 BFD_RELOC_TILEGX_IMM16_X1_HW1
7785 BFD_RELOC_TILEGX_IMM16_X0_HW2
7787 BFD_RELOC_TILEGX_IMM16_X1_HW2
7789 BFD_RELOC_TILEGX_IMM16_X0_HW3
7791 BFD_RELOC_TILEGX_IMM16_X1_HW3
7793 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7795 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7797 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7799 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7801 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7803 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7805 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7817 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7819 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7821 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7823 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7825 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7827 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7829 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7831 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7833 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7835 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7837 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7839 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7841 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7843 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7845 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7847 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7849 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7851 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7853 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7855 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7857 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7859 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7861 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7863 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7865 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7867 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7869 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7871 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7873 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7875 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7877 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7879 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7881 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7883 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7885 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7887 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7889 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7891 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7893 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7895 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7897 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7899 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7901 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7903 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7905 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7907 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7909 BFD_RELOC_TILEGX_TLS_DTPMOD64
7911 BFD_RELOC_TILEGX_TLS_DTPOFF64
7913 BFD_RELOC_TILEGX_TLS_TPOFF64
7915 BFD_RELOC_TILEGX_TLS_DTPMOD32
7917 BFD_RELOC_TILEGX_TLS_DTPOFF32
7919 BFD_RELOC_TILEGX_TLS_TPOFF32
7921 BFD_RELOC_TILEGX_TLS_GD_CALL
7923 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7925 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7927 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7929 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7931 BFD_RELOC_TILEGX_TLS_IE_LOAD
7933 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7935 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7937 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7939 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7941 Tilera TILE-Gx Relocations.
7950 BFD_RELOC_BPF_DISP16
7952 BFD_RELOC_BPF_DISP32
7954 Linux eBPF relocations.
7957 BFD_RELOC_EPIPHANY_SIMM8
7959 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7961 BFD_RELOC_EPIPHANY_SIMM24
7963 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7965 BFD_RELOC_EPIPHANY_HIGH
7967 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7969 BFD_RELOC_EPIPHANY_LOW
7971 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7973 BFD_RELOC_EPIPHANY_SIMM11
7975 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7977 BFD_RELOC_EPIPHANY_IMM11
7979 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7981 BFD_RELOC_EPIPHANY_IMM8
7983 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7986 BFD_RELOC_VISIUM_HI16
7988 BFD_RELOC_VISIUM_LO16
7990 BFD_RELOC_VISIUM_IM16
7992 BFD_RELOC_VISIUM_REL16
7994 BFD_RELOC_VISIUM_HI16_PCREL
7996 BFD_RELOC_VISIUM_LO16_PCREL
7998 BFD_RELOC_VISIUM_IM16_PCREL
8003 BFD_RELOC_WASM32_LEB128
8005 BFD_RELOC_WASM32_LEB128_GOT
8007 BFD_RELOC_WASM32_LEB128_GOT_CODE
8009 BFD_RELOC_WASM32_LEB128_PLT
8011 BFD_RELOC_WASM32_PLT_INDEX
8013 BFD_RELOC_WASM32_ABS32_CODE
8015 BFD_RELOC_WASM32_COPY
8017 BFD_RELOC_WASM32_CODE_POINTER
8019 BFD_RELOC_WASM32_INDEX
8021 BFD_RELOC_WASM32_PLT_SIG
8023 WebAssembly relocations.
8026 BFD_RELOC_CKCORE_NONE
8028 BFD_RELOC_CKCORE_ADDR32
8030 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8032 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8034 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8036 BFD_RELOC_CKCORE_PCREL32
8038 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8040 BFD_RELOC_CKCORE_GNU_VTINHERIT
8042 BFD_RELOC_CKCORE_GNU_VTENTRY
8044 BFD_RELOC_CKCORE_RELATIVE
8046 BFD_RELOC_CKCORE_COPY
8048 BFD_RELOC_CKCORE_GLOB_DAT
8050 BFD_RELOC_CKCORE_JUMP_SLOT
8052 BFD_RELOC_CKCORE_GOTOFF
8054 BFD_RELOC_CKCORE_GOTPC
8056 BFD_RELOC_CKCORE_GOT32
8058 BFD_RELOC_CKCORE_PLT32
8060 BFD_RELOC_CKCORE_ADDRGOT
8062 BFD_RELOC_CKCORE_ADDRPLT
8064 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8066 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8068 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8070 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8072 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8074 BFD_RELOC_CKCORE_ADDR_HI16
8076 BFD_RELOC_CKCORE_ADDR_LO16
8078 BFD_RELOC_CKCORE_GOTPC_HI16
8080 BFD_RELOC_CKCORE_GOTPC_LO16
8082 BFD_RELOC_CKCORE_GOTOFF_HI16
8084 BFD_RELOC_CKCORE_GOTOFF_LO16
8086 BFD_RELOC_CKCORE_GOT12
8088 BFD_RELOC_CKCORE_GOT_HI16
8090 BFD_RELOC_CKCORE_GOT_LO16
8092 BFD_RELOC_CKCORE_PLT12
8094 BFD_RELOC_CKCORE_PLT_HI16
8096 BFD_RELOC_CKCORE_PLT_LO16
8098 BFD_RELOC_CKCORE_ADDRGOT_HI16
8100 BFD_RELOC_CKCORE_ADDRGOT_LO16
8102 BFD_RELOC_CKCORE_ADDRPLT_HI16
8104 BFD_RELOC_CKCORE_ADDRPLT_LO16
8106 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8108 BFD_RELOC_CKCORE_TOFFSET_LO16
8110 BFD_RELOC_CKCORE_DOFFSET_LO16
8112 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8114 BFD_RELOC_CKCORE_DOFFSET_IMM18
8116 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8118 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8120 BFD_RELOC_CKCORE_GOTOFF_IMM18
8122 BFD_RELOC_CKCORE_GOT_IMM18BY4
8124 BFD_RELOC_CKCORE_PLT_IMM18BY4
8126 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8128 BFD_RELOC_CKCORE_TLS_LE32
8130 BFD_RELOC_CKCORE_TLS_IE32
8132 BFD_RELOC_CKCORE_TLS_GD32
8134 BFD_RELOC_CKCORE_TLS_LDM32
8136 BFD_RELOC_CKCORE_TLS_LDO32
8138 BFD_RELOC_CKCORE_TLS_DTPMOD32
8140 BFD_RELOC_CKCORE_TLS_DTPOFF32
8142 BFD_RELOC_CKCORE_TLS_TPOFF32
8144 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8146 BFD_RELOC_CKCORE_NOJSRI
8148 BFD_RELOC_CKCORE_CALLGRAPH
8150 BFD_RELOC_CKCORE_IRELATIVE
8152 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8154 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8167 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8172 bfd_reloc_type_lookup
8173 bfd_reloc_name_lookup
8176 reloc_howto_type *bfd_reloc_type_lookup
8177 (bfd *abfd, bfd_reloc_code_real_type code);
8178 reloc_howto_type *bfd_reloc_name_lookup
8179 (bfd *abfd, const char *reloc_name);
8182 Return a pointer to a howto structure which, when
8183 invoked, will perform the relocation @var{code} on data from the
8189 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8191 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8195 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8197 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8200 static reloc_howto_type bfd_howto_32
=
8201 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8205 bfd_default_reloc_type_lookup
8208 reloc_howto_type *bfd_default_reloc_type_lookup
8209 (bfd *abfd, bfd_reloc_code_real_type code);
8212 Provides a default relocation lookup routine for any architecture.
8217 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8219 /* Very limited support is provided for relocs in generic targets
8220 such as elf32-little. FIXME: Should we always return NULL? */
8221 if (code
== BFD_RELOC_CTOR
8222 && bfd_arch_bits_per_address (abfd
) == 32)
8223 return &bfd_howto_32
;
8229 bfd_get_reloc_code_name
8232 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8235 Provides a printable name for the supplied relocation code.
8236 Useful mainly for printing error messages.
8240 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8242 if (code
> BFD_RELOC_UNUSED
)
8244 return bfd_reloc_code_real_names
[code
];
8249 bfd_generic_relax_section
8252 bfd_boolean bfd_generic_relax_section
8255 struct bfd_link_info *,
8259 Provides default handling for relaxing for back ends which
8264 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8265 asection
*section ATTRIBUTE_UNUSED
,
8266 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8269 if (bfd_link_relocatable (link_info
))
8270 (*link_info
->callbacks
->einfo
)
8271 (_("%P%F: --relax and -r may not be used together\n"));
8279 bfd_generic_gc_sections
8282 bfd_boolean bfd_generic_gc_sections
8283 (bfd *, struct bfd_link_info *);
8286 Provides default handling for relaxing for back ends which
8287 don't do section gc -- i.e., does nothing.
8291 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8292 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8299 bfd_generic_lookup_section_flags
8302 bfd_boolean bfd_generic_lookup_section_flags
8303 (struct bfd_link_info *, struct flag_info *, asection *);
8306 Provides default handling for section flags lookup
8307 -- i.e., does nothing.
8308 Returns FALSE if the section should be omitted, otherwise TRUE.
8312 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8313 struct flag_info
*flaginfo
,
8314 asection
*section ATTRIBUTE_UNUSED
)
8316 if (flaginfo
!= NULL
)
8318 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8326 bfd_generic_merge_sections
8329 bfd_boolean bfd_generic_merge_sections
8330 (bfd *, struct bfd_link_info *);
8333 Provides default handling for SEC_MERGE section merging for back ends
8334 which don't have SEC_MERGE support -- i.e., does nothing.
8338 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8339 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8346 bfd_generic_get_relocated_section_contents
8349 bfd_byte *bfd_generic_get_relocated_section_contents
8351 struct bfd_link_info *link_info,
8352 struct bfd_link_order *link_order,
8354 bfd_boolean relocatable,
8358 Provides default handling of relocation effort for back ends
8359 which can't be bothered to do it efficiently.
8364 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8365 struct bfd_link_info
*link_info
,
8366 struct bfd_link_order
*link_order
,
8368 bfd_boolean relocatable
,
8371 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8372 asection
*input_section
= link_order
->u
.indirect
.section
;
8374 arelent
**reloc_vector
;
8377 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8381 /* Read in the section. */
8382 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8388 if (reloc_size
== 0)
8391 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8392 if (reloc_vector
== NULL
)
8395 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8399 if (reloc_count
< 0)
8402 if (reloc_count
> 0)
8406 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8408 char *error_message
= NULL
;
8410 bfd_reloc_status_type r
;
8412 symbol
= *(*parent
)->sym_ptr_ptr
;
8413 /* PR ld/19628: A specially crafted input file
8414 can result in a NULL symbol pointer here. */
8417 link_info
->callbacks
->einfo
8418 /* xgettext:c-format */
8419 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8420 abfd
, input_section
, (* parent
)->address
);
8424 /* Zap reloc field when the symbol is from a discarded
8425 section, ignoring any addend. Do the same when called
8426 from bfd_simple_get_relocated_section_contents for
8427 undefined symbols in debug sections. This is to keep
8428 debug info reasonably sane, in particular so that
8429 DW_FORM_ref_addr to another file's .debug_info isn't
8430 confused with an offset into the current file's
8432 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8433 || (symbol
->section
== bfd_und_section_ptr
8434 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8435 && link_info
->input_bfds
== link_info
->output_bfd
))
8438 static reloc_howto_type none_howto
8439 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8440 "unused", FALSE
, 0, 0, FALSE
);
8442 off
= ((*parent
)->address
8443 * bfd_octets_per_byte (input_bfd
, input_section
));
8444 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8445 input_section
, data
, off
);
8446 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8447 (*parent
)->addend
= 0;
8448 (*parent
)->howto
= &none_howto
;
8452 r
= bfd_perform_relocation (input_bfd
,
8456 relocatable
? abfd
: NULL
,
8461 asection
*os
= input_section
->output_section
;
8463 /* A partial link, so keep the relocs. */
8464 os
->orelocation
[os
->reloc_count
] = *parent
;
8468 if (r
!= bfd_reloc_ok
)
8472 case bfd_reloc_undefined
:
8473 (*link_info
->callbacks
->undefined_symbol
)
8474 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8475 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8477 case bfd_reloc_dangerous
:
8478 BFD_ASSERT (error_message
!= NULL
);
8479 (*link_info
->callbacks
->reloc_dangerous
)
8480 (link_info
, error_message
,
8481 input_bfd
, input_section
, (*parent
)->address
);
8483 case bfd_reloc_overflow
:
8484 (*link_info
->callbacks
->reloc_overflow
)
8486 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8487 (*parent
)->howto
->name
, (*parent
)->addend
,
8488 input_bfd
, input_section
, (*parent
)->address
);
8490 case bfd_reloc_outofrange
:
8492 This error can result when processing some partially
8493 complete binaries. Do not abort, but issue an error
8495 link_info
->callbacks
->einfo
8496 /* xgettext:c-format */
8497 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8498 abfd
, input_section
, * parent
);
8501 case bfd_reloc_notsupported
:
8503 This error can result when processing a corrupt binary.
8504 Do not abort. Issue an error message instead. */
8505 link_info
->callbacks
->einfo
8506 /* xgettext:c-format */
8507 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8508 abfd
, input_section
, * parent
);
8512 /* PR 17512; file: 90c2a92e.
8513 Report unexpected results, without aborting. */
8514 link_info
->callbacks
->einfo
8515 /* xgettext:c-format */
8516 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8517 abfd
, input_section
, * parent
, r
);
8525 free (reloc_vector
);
8529 free (reloc_vector
);
8535 _bfd_generic_set_reloc
8538 void _bfd_generic_set_reloc
8542 unsigned int count);
8545 Installs a new set of internal relocations in SECTION.
8549 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8554 section
->orelocation
= relptr
;
8555 section
->reloc_count
= count
;
8560 _bfd_unrecognized_reloc
8563 bfd_boolean _bfd_unrecognized_reloc
8566 unsigned int r_type);
8569 Reports an unrecognized reloc.
8570 Written as a function in order to reduce code duplication.
8571 Returns FALSE so that it can be called from a return statement.
8575 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8577 /* xgettext:c-format */
8578 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8579 abfd
, r_type
, section
);
8581 /* PR 21803: Suggest the most likely cause of this error. */
8582 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8583 BFD_VERSION_STRING
);
8585 bfd_set_error (bfd_error_bad_value
);
8590 _bfd_norelocs_bfd_reloc_type_lookup
8592 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8594 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8598 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8599 const char *reloc_name ATTRIBUTE_UNUSED
)
8601 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8605 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8606 arelent
**relp ATTRIBUTE_UNUSED
,
8607 asymbol
**symp ATTRIBUTE_UNUSED
)
8609 return _bfd_long_bfd_n1_error (abfd
);