1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2017 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
452 How relocs are tied together in an <<asection>>:
454 .typedef struct relent_chain
457 . struct relent_chain *next;
463 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
464 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
471 bfd_reloc_status_type bfd_check_overflow
472 (enum complain_overflow how,
473 unsigned int bitsize,
474 unsigned int rightshift,
475 unsigned int addrsize,
479 Perform overflow checking on @var{relocation} which has
480 @var{bitsize} significant bits and will be shifted right by
481 @var{rightshift} bits, on a machine with addresses containing
482 @var{addrsize} significant bits. The result is either of
483 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
487 bfd_reloc_status_type
488 bfd_check_overflow (enum complain_overflow how
,
489 unsigned int bitsize
,
490 unsigned int rightshift
,
491 unsigned int addrsize
,
494 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
495 bfd_reloc_status_type flag
= bfd_reloc_ok
;
497 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
498 we'll be permissive: extra bits in the field mask will
499 automatically extend the address mask for purposes of the
501 fieldmask
= N_ONES (bitsize
);
502 signmask
= ~fieldmask
;
503 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
504 a
= (relocation
& addrmask
) >> rightshift
;
508 case complain_overflow_dont
:
511 case complain_overflow_signed
:
512 /* If any sign bits are set, all sign bits must be set. That
513 is, A must be a valid negative address after shifting. */
514 signmask
= ~ (fieldmask
>> 1);
517 case complain_overflow_bitfield
:
518 /* Bitfields are sometimes signed, sometimes unsigned. We
519 explicitly allow an address wrap too, which means a bitfield
520 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
521 if the value has some, but not all, bits set outside the
524 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
525 flag
= bfd_reloc_overflow
;
528 case complain_overflow_unsigned
:
529 /* We have an overflow if the address does not fit in the field. */
530 if ((a
& signmask
) != 0)
531 flag
= bfd_reloc_overflow
;
543 bfd_perform_relocation
546 bfd_reloc_status_type bfd_perform_relocation
548 arelent *reloc_entry,
550 asection *input_section,
552 char **error_message);
555 If @var{output_bfd} is supplied to this function, the
556 generated image will be relocatable; the relocations are
557 copied to the output file after they have been changed to
558 reflect the new state of the world. There are two ways of
559 reflecting the results of partial linkage in an output file:
560 by modifying the output data in place, and by modifying the
561 relocation record. Some native formats (e.g., basic a.out and
562 basic coff) have no way of specifying an addend in the
563 relocation type, so the addend has to go in the output data.
564 This is no big deal since in these formats the output data
565 slot will always be big enough for the addend. Complex reloc
566 types with addends were invented to solve just this problem.
567 The @var{error_message} argument is set to an error message if
568 this return @code{bfd_reloc_dangerous}.
572 bfd_reloc_status_type
573 bfd_perform_relocation (bfd
*abfd
,
574 arelent
*reloc_entry
,
576 asection
*input_section
,
578 char **error_message
)
581 bfd_reloc_status_type flag
= bfd_reloc_ok
;
582 bfd_size_type octets
;
583 bfd_vma output_base
= 0;
584 reloc_howto_type
*howto
= reloc_entry
->howto
;
585 asection
*reloc_target_output_section
;
588 symbol
= *(reloc_entry
->sym_ptr_ptr
);
590 /* If we are not producing relocatable output, return an error if
591 the symbol is not defined. An undefined weak symbol is
592 considered to have a value of zero (SVR4 ABI, p. 4-27). */
593 if (bfd_is_und_section (symbol
->section
)
594 && (symbol
->flags
& BSF_WEAK
) == 0
595 && output_bfd
== NULL
)
596 flag
= bfd_reloc_undefined
;
598 /* If there is a function supplied to handle this relocation type,
599 call it. It'll return `bfd_reloc_continue' if further processing
601 if (howto
&& howto
->special_function
)
603 bfd_reloc_status_type cont
;
604 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
605 input_section
, output_bfd
,
607 if (cont
!= bfd_reloc_continue
)
611 if (bfd_is_abs_section (symbol
->section
)
612 && output_bfd
!= NULL
)
614 reloc_entry
->address
+= input_section
->output_offset
;
618 /* PR 17512: file: 0f67f69d. */
620 return bfd_reloc_undefined
;
622 /* Is the address of the relocation really within the section?
623 Include the size of the reloc in the test for out of range addresses.
624 PR 17512: file: c146ab8b, 46dff27f, 38e53ebf. */
625 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
626 if (octets
+ bfd_get_reloc_size (howto
)
627 > bfd_get_section_limit_octets (abfd
, input_section
)
628 /* Check for an overly large offset which
629 masquerades as a negative value too. */
630 || (octets
+ bfd_get_reloc_size (howto
) < bfd_get_reloc_size (howto
)))
631 return bfd_reloc_outofrange
;
633 /* Work out which section the relocation is targeted at and the
634 initial relocation command value. */
636 /* Get symbol value. (Common symbols are special.) */
637 if (bfd_is_com_section (symbol
->section
))
640 relocation
= symbol
->value
;
642 reloc_target_output_section
= symbol
->section
->output_section
;
644 /* Convert input-section-relative symbol value to absolute. */
645 if ((output_bfd
&& ! howto
->partial_inplace
)
646 || reloc_target_output_section
== NULL
)
649 output_base
= reloc_target_output_section
->vma
;
651 relocation
+= output_base
+ symbol
->section
->output_offset
;
653 /* Add in supplied addend. */
654 relocation
+= reloc_entry
->addend
;
656 /* Here the variable relocation holds the final address of the
657 symbol we are relocating against, plus any addend. */
659 if (howto
->pc_relative
)
661 /* This is a PC relative relocation. We want to set RELOCATION
662 to the distance between the address of the symbol and the
663 location. RELOCATION is already the address of the symbol.
665 We start by subtracting the address of the section containing
668 If pcrel_offset is set, we must further subtract the position
669 of the location within the section. Some targets arrange for
670 the addend to be the negative of the position of the location
671 within the section; for example, i386-aout does this. For
672 i386-aout, pcrel_offset is FALSE. Some other targets do not
673 include the position of the location; for example, m88kbcs,
674 or ELF. For those targets, pcrel_offset is TRUE.
676 If we are producing relocatable output, then we must ensure
677 that this reloc will be correctly computed when the final
678 relocation is done. If pcrel_offset is FALSE we want to wind
679 up with the negative of the location within the section,
680 which means we must adjust the existing addend by the change
681 in the location within the section. If pcrel_offset is TRUE
682 we do not want to adjust the existing addend at all.
684 FIXME: This seems logical to me, but for the case of
685 producing relocatable output it is not what the code
686 actually does. I don't want to change it, because it seems
687 far too likely that something will break. */
690 input_section
->output_section
->vma
+ input_section
->output_offset
;
692 if (howto
->pcrel_offset
)
693 relocation
-= reloc_entry
->address
;
696 if (output_bfd
!= NULL
)
698 if (! howto
->partial_inplace
)
700 /* This is a partial relocation, and we want to apply the relocation
701 to the reloc entry rather than the raw data. Modify the reloc
702 inplace to reflect what we now know. */
703 reloc_entry
->addend
= relocation
;
704 reloc_entry
->address
+= input_section
->output_offset
;
709 /* This is a partial relocation, but inplace, so modify the
712 If we've relocated with a symbol with a section, change
713 into a ref to the section belonging to the symbol. */
715 reloc_entry
->address
+= input_section
->output_offset
;
718 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
719 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
720 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
722 /* For m68k-coff, the addend was being subtracted twice during
723 relocation with -r. Removing the line below this comment
724 fixes that problem; see PR 2953.
726 However, Ian wrote the following, regarding removing the line below,
727 which explains why it is still enabled: --djm
729 If you put a patch like that into BFD you need to check all the COFF
730 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
731 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
732 problem in a different way. There may very well be a reason that the
733 code works as it does.
735 Hmmm. The first obvious point is that bfd_perform_relocation should
736 not have any tests that depend upon the flavour. It's seem like
737 entirely the wrong place for such a thing. The second obvious point
738 is that the current code ignores the reloc addend when producing
739 relocatable output for COFF. That's peculiar. In fact, I really
740 have no idea what the point of the line you want to remove is.
742 A typical COFF reloc subtracts the old value of the symbol and adds in
743 the new value to the location in the object file (if it's a pc
744 relative reloc it adds the difference between the symbol value and the
745 location). When relocating we need to preserve that property.
747 BFD handles this by setting the addend to the negative of the old
748 value of the symbol. Unfortunately it handles common symbols in a
749 non-standard way (it doesn't subtract the old value) but that's a
750 different story (we can't change it without losing backward
751 compatibility with old object files) (coff-i386 does subtract the old
752 value, to be compatible with existing coff-i386 targets, like SCO).
754 So everything works fine when not producing relocatable output. When
755 we are producing relocatable output, logically we should do exactly
756 what we do when not producing relocatable output. Therefore, your
757 patch is correct. In fact, it should probably always just set
758 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
759 add the value into the object file. This won't hurt the COFF code,
760 which doesn't use the addend; I'm not sure what it will do to other
761 formats (the thing to check for would be whether any formats both use
762 the addend and set partial_inplace).
764 When I wanted to make coff-i386 produce relocatable output, I ran
765 into the problem that you are running into: I wanted to remove that
766 line. Rather than risk it, I made the coff-i386 relocs use a special
767 function; it's coff_i386_reloc in coff-i386.c. The function
768 specifically adds the addend field into the object file, knowing that
769 bfd_perform_relocation is not going to. If you remove that line, then
770 coff-i386.c will wind up adding the addend field in twice. It's
771 trivial to fix; it just needs to be done.
773 The problem with removing the line is just that it may break some
774 working code. With BFD it's hard to be sure of anything. The right
775 way to deal with this is simply to build and test at least all the
776 supported COFF targets. It should be straightforward if time and disk
777 space consuming. For each target:
779 2) generate some executable, and link it using -r (I would
780 probably use paranoia.o and link against newlib/libc.a, which
781 for all the supported targets would be available in
782 /usr/cygnus/progressive/H-host/target/lib/libc.a).
783 3) make the change to reloc.c
784 4) rebuild the linker
786 6) if the resulting object files are the same, you have at least
788 7) if they are different you have to figure out which version is
791 relocation
-= reloc_entry
->addend
;
792 reloc_entry
->addend
= 0;
796 reloc_entry
->addend
= relocation
;
801 /* FIXME: This overflow checking is incomplete, because the value
802 might have overflowed before we get here. For a correct check we
803 need to compute the value in a size larger than bitsize, but we
804 can't reasonably do that for a reloc the same size as a host
806 FIXME: We should also do overflow checking on the result after
807 adding in the value contained in the object file. */
808 if (howto
->complain_on_overflow
!= complain_overflow_dont
809 && flag
== bfd_reloc_ok
)
810 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
813 bfd_arch_bits_per_address (abfd
),
816 /* Either we are relocating all the way, or we don't want to apply
817 the relocation to the reloc entry (probably because there isn't
818 any room in the output format to describe addends to relocs). */
820 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
821 (OSF version 1.3, compiler version 3.11). It miscompiles the
835 x <<= (unsigned long) s.i0;
839 printf ("succeeded (%lx)\n", x);
843 relocation
>>= (bfd_vma
) howto
->rightshift
;
845 /* Shift everything up to where it's going to be used. */
846 relocation
<<= (bfd_vma
) howto
->bitpos
;
848 /* Wait for the day when all have the mask in them. */
851 i instruction to be left alone
852 o offset within instruction
853 r relocation offset to apply
862 (( i i i i i o o o o o from bfd_get<size>
863 and S S S S S) to get the size offset we want
864 + r r r r r r r r r r) to get the final value to place
865 and D D D D D to chop to right size
866 -----------------------
869 ( i i i i i o o o o o from bfd_get<size>
870 and N N N N N ) get instruction
871 -----------------------
877 -----------------------
878 = R R R R R R R R R R put into bfd_put<size>
882 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
888 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
890 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
896 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
898 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
903 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
905 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
910 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
911 relocation
= -relocation
;
913 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
919 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
920 relocation
= -relocation
;
922 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
933 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
935 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
942 return bfd_reloc_other
;
950 bfd_install_relocation
953 bfd_reloc_status_type bfd_install_relocation
955 arelent *reloc_entry,
956 void *data, bfd_vma data_start,
957 asection *input_section,
958 char **error_message);
961 This looks remarkably like <<bfd_perform_relocation>>, except it
962 does not expect that the section contents have been filled in.
963 I.e., it's suitable for use when creating, rather than applying
966 For now, this function should be considered reserved for the
970 bfd_reloc_status_type
971 bfd_install_relocation (bfd
*abfd
,
972 arelent
*reloc_entry
,
974 bfd_vma data_start_offset
,
975 asection
*input_section
,
976 char **error_message
)
979 bfd_reloc_status_type flag
= bfd_reloc_ok
;
980 bfd_size_type octets
;
981 bfd_vma output_base
= 0;
982 reloc_howto_type
*howto
= reloc_entry
->howto
;
983 asection
*reloc_target_output_section
;
987 symbol
= *(reloc_entry
->sym_ptr_ptr
);
989 /* If there is a function supplied to handle this relocation type,
990 call it. It'll return `bfd_reloc_continue' if further processing
992 if (howto
&& howto
->special_function
)
994 bfd_reloc_status_type cont
;
996 /* XXX - The special_function calls haven't been fixed up to deal
997 with creating new relocations and section contents. */
998 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
999 /* XXX - Non-portable! */
1000 ((bfd_byte
*) data_start
1001 - data_start_offset
),
1002 input_section
, abfd
, error_message
);
1003 if (cont
!= bfd_reloc_continue
)
1007 if (bfd_is_abs_section (symbol
->section
))
1009 reloc_entry
->address
+= input_section
->output_offset
;
1010 return bfd_reloc_ok
;
1013 /* No need to check for howto != NULL if !bfd_is_abs_section as
1014 it will have been checked in `bfd_perform_relocation already'. */
1016 /* Is the address of the relocation really within the section? */
1017 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1018 if (octets
+ bfd_get_reloc_size (howto
)
1019 > bfd_get_section_limit_octets (abfd
, input_section
))
1020 return bfd_reloc_outofrange
;
1022 /* Work out which section the relocation is targeted at and the
1023 initial relocation command value. */
1025 /* Get symbol value. (Common symbols are special.) */
1026 if (bfd_is_com_section (symbol
->section
))
1029 relocation
= symbol
->value
;
1031 reloc_target_output_section
= symbol
->section
->output_section
;
1033 /* Convert input-section-relative symbol value to absolute. */
1034 if (! howto
->partial_inplace
)
1037 output_base
= reloc_target_output_section
->vma
;
1039 relocation
+= output_base
+ symbol
->section
->output_offset
;
1041 /* Add in supplied addend. */
1042 relocation
+= reloc_entry
->addend
;
1044 /* Here the variable relocation holds the final address of the
1045 symbol we are relocating against, plus any addend. */
1047 if (howto
->pc_relative
)
1049 /* This is a PC relative relocation. We want to set RELOCATION
1050 to the distance between the address of the symbol and the
1051 location. RELOCATION is already the address of the symbol.
1053 We start by subtracting the address of the section containing
1056 If pcrel_offset is set, we must further subtract the position
1057 of the location within the section. Some targets arrange for
1058 the addend to be the negative of the position of the location
1059 within the section; for example, i386-aout does this. For
1060 i386-aout, pcrel_offset is FALSE. Some other targets do not
1061 include the position of the location; for example, m88kbcs,
1062 or ELF. For those targets, pcrel_offset is TRUE.
1064 If we are producing relocatable output, then we must ensure
1065 that this reloc will be correctly computed when the final
1066 relocation is done. If pcrel_offset is FALSE we want to wind
1067 up with the negative of the location within the section,
1068 which means we must adjust the existing addend by the change
1069 in the location within the section. If pcrel_offset is TRUE
1070 we do not want to adjust the existing addend at all.
1072 FIXME: This seems logical to me, but for the case of
1073 producing relocatable output it is not what the code
1074 actually does. I don't want to change it, because it seems
1075 far too likely that something will break. */
1078 input_section
->output_section
->vma
+ input_section
->output_offset
;
1080 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1081 relocation
-= reloc_entry
->address
;
1084 if (! howto
->partial_inplace
)
1086 /* This is a partial relocation, and we want to apply the relocation
1087 to the reloc entry rather than the raw data. Modify the reloc
1088 inplace to reflect what we now know. */
1089 reloc_entry
->addend
= relocation
;
1090 reloc_entry
->address
+= input_section
->output_offset
;
1095 /* This is a partial relocation, but inplace, so modify the
1098 If we've relocated with a symbol with a section, change
1099 into a ref to the section belonging to the symbol. */
1100 reloc_entry
->address
+= input_section
->output_offset
;
1103 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1104 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1105 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1108 /* For m68k-coff, the addend was being subtracted twice during
1109 relocation with -r. Removing the line below this comment
1110 fixes that problem; see PR 2953.
1112 However, Ian wrote the following, regarding removing the line below,
1113 which explains why it is still enabled: --djm
1115 If you put a patch like that into BFD you need to check all the COFF
1116 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1117 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1118 problem in a different way. There may very well be a reason that the
1119 code works as it does.
1121 Hmmm. The first obvious point is that bfd_install_relocation should
1122 not have any tests that depend upon the flavour. It's seem like
1123 entirely the wrong place for such a thing. The second obvious point
1124 is that the current code ignores the reloc addend when producing
1125 relocatable output for COFF. That's peculiar. In fact, I really
1126 have no idea what the point of the line you want to remove is.
1128 A typical COFF reloc subtracts the old value of the symbol and adds in
1129 the new value to the location in the object file (if it's a pc
1130 relative reloc it adds the difference between the symbol value and the
1131 location). When relocating we need to preserve that property.
1133 BFD handles this by setting the addend to the negative of the old
1134 value of the symbol. Unfortunately it handles common symbols in a
1135 non-standard way (it doesn't subtract the old value) but that's a
1136 different story (we can't change it without losing backward
1137 compatibility with old object files) (coff-i386 does subtract the old
1138 value, to be compatible with existing coff-i386 targets, like SCO).
1140 So everything works fine when not producing relocatable output. When
1141 we are producing relocatable output, logically we should do exactly
1142 what we do when not producing relocatable output. Therefore, your
1143 patch is correct. In fact, it should probably always just set
1144 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1145 add the value into the object file. This won't hurt the COFF code,
1146 which doesn't use the addend; I'm not sure what it will do to other
1147 formats (the thing to check for would be whether any formats both use
1148 the addend and set partial_inplace).
1150 When I wanted to make coff-i386 produce relocatable output, I ran
1151 into the problem that you are running into: I wanted to remove that
1152 line. Rather than risk it, I made the coff-i386 relocs use a special
1153 function; it's coff_i386_reloc in coff-i386.c. The function
1154 specifically adds the addend field into the object file, knowing that
1155 bfd_install_relocation is not going to. If you remove that line, then
1156 coff-i386.c will wind up adding the addend field in twice. It's
1157 trivial to fix; it just needs to be done.
1159 The problem with removing the line is just that it may break some
1160 working code. With BFD it's hard to be sure of anything. The right
1161 way to deal with this is simply to build and test at least all the
1162 supported COFF targets. It should be straightforward if time and disk
1163 space consuming. For each target:
1165 2) generate some executable, and link it using -r (I would
1166 probably use paranoia.o and link against newlib/libc.a, which
1167 for all the supported targets would be available in
1168 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1169 3) make the change to reloc.c
1170 4) rebuild the linker
1172 6) if the resulting object files are the same, you have at least
1174 7) if they are different you have to figure out which version is
1176 relocation
-= reloc_entry
->addend
;
1177 /* FIXME: There should be no target specific code here... */
1178 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1179 reloc_entry
->addend
= 0;
1183 reloc_entry
->addend
= relocation
;
1187 /* FIXME: This overflow checking is incomplete, because the value
1188 might have overflowed before we get here. For a correct check we
1189 need to compute the value in a size larger than bitsize, but we
1190 can't reasonably do that for a reloc the same size as a host
1192 FIXME: We should also do overflow checking on the result after
1193 adding in the value contained in the object file. */
1194 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1195 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1198 bfd_arch_bits_per_address (abfd
),
1201 /* Either we are relocating all the way, or we don't want to apply
1202 the relocation to the reloc entry (probably because there isn't
1203 any room in the output format to describe addends to relocs). */
1205 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1206 (OSF version 1.3, compiler version 3.11). It miscompiles the
1220 x <<= (unsigned long) s.i0;
1222 printf ("failed\n");
1224 printf ("succeeded (%lx)\n", x);
1228 relocation
>>= (bfd_vma
) howto
->rightshift
;
1230 /* Shift everything up to where it's going to be used. */
1231 relocation
<<= (bfd_vma
) howto
->bitpos
;
1233 /* Wait for the day when all have the mask in them. */
1236 i instruction to be left alone
1237 o offset within instruction
1238 r relocation offset to apply
1247 (( i i i i i o o o o o from bfd_get<size>
1248 and S S S S S) to get the size offset we want
1249 + r r r r r r r r r r) to get the final value to place
1250 and D D D D D to chop to right size
1251 -----------------------
1254 ( i i i i i o o o o o from bfd_get<size>
1255 and N N N N N ) get instruction
1256 -----------------------
1262 -----------------------
1263 = R R R R R R R R R R put into bfd_put<size>
1267 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1269 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1271 switch (howto
->size
)
1275 char x
= bfd_get_8 (abfd
, data
);
1277 bfd_put_8 (abfd
, x
, data
);
1283 short x
= bfd_get_16 (abfd
, data
);
1285 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1290 long x
= bfd_get_32 (abfd
, data
);
1292 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1297 long x
= bfd_get_32 (abfd
, data
);
1298 relocation
= -relocation
;
1300 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1310 bfd_vma x
= bfd_get_64 (abfd
, data
);
1312 bfd_put_64 (abfd
, x
, data
);
1316 return bfd_reloc_other
;
1322 /* This relocation routine is used by some of the backend linkers.
1323 They do not construct asymbol or arelent structures, so there is no
1324 reason for them to use bfd_perform_relocation. Also,
1325 bfd_perform_relocation is so hacked up it is easier to write a new
1326 function than to try to deal with it.
1328 This routine does a final relocation. Whether it is useful for a
1329 relocatable link depends upon how the object format defines
1332 FIXME: This routine ignores any special_function in the HOWTO,
1333 since the existing special_function values have been written for
1334 bfd_perform_relocation.
1336 HOWTO is the reloc howto information.
1337 INPUT_BFD is the BFD which the reloc applies to.
1338 INPUT_SECTION is the section which the reloc applies to.
1339 CONTENTS is the contents of the section.
1340 ADDRESS is the address of the reloc within INPUT_SECTION.
1341 VALUE is the value of the symbol the reloc refers to.
1342 ADDEND is the addend of the reloc. */
1344 bfd_reloc_status_type
1345 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1347 asection
*input_section
,
1354 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1356 /* Sanity check the address. */
1357 if (octets
+ bfd_get_reloc_size (howto
)
1358 > bfd_get_section_limit_octets (input_bfd
, input_section
))
1359 return bfd_reloc_outofrange
;
1361 /* This function assumes that we are dealing with a basic relocation
1362 against a symbol. We want to compute the value of the symbol to
1363 relocate to. This is just VALUE, the value of the symbol, plus
1364 ADDEND, any addend associated with the reloc. */
1365 relocation
= value
+ addend
;
1367 /* If the relocation is PC relative, we want to set RELOCATION to
1368 the distance between the symbol (currently in RELOCATION) and the
1369 location we are relocating. Some targets (e.g., i386-aout)
1370 arrange for the contents of the section to be the negative of the
1371 offset of the location within the section; for such targets
1372 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1373 simply leave the contents of the section as zero; for such
1374 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1375 need to subtract out the offset of the location within the
1376 section (which is just ADDRESS). */
1377 if (howto
->pc_relative
)
1379 relocation
-= (input_section
->output_section
->vma
1380 + input_section
->output_offset
);
1381 if (howto
->pcrel_offset
)
1382 relocation
-= address
;
1385 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1387 + address
* bfd_octets_per_byte (input_bfd
));
1390 /* Relocate a given location using a given value and howto. */
1392 bfd_reloc_status_type
1393 _bfd_relocate_contents (reloc_howto_type
*howto
,
1400 bfd_reloc_status_type flag
;
1401 unsigned int rightshift
= howto
->rightshift
;
1402 unsigned int bitpos
= howto
->bitpos
;
1404 /* If the size is negative, negate RELOCATION. This isn't very
1406 if (howto
->size
< 0)
1407 relocation
= -relocation
;
1409 /* Get the value we are going to relocate. */
1410 size
= bfd_get_reloc_size (howto
);
1416 return bfd_reloc_ok
;
1418 x
= bfd_get_8 (input_bfd
, location
);
1421 x
= bfd_get_16 (input_bfd
, location
);
1424 x
= bfd_get_32 (input_bfd
, location
);
1428 x
= bfd_get_64 (input_bfd
, location
);
1435 /* Check for overflow. FIXME: We may drop bits during the addition
1436 which we don't check for. We must either check at every single
1437 operation, which would be tedious, or we must do the computations
1438 in a type larger than bfd_vma, which would be inefficient. */
1439 flag
= bfd_reloc_ok
;
1440 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1442 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1445 /* Get the values to be added together. For signed and unsigned
1446 relocations, we assume that all values should be truncated to
1447 the size of an address. For bitfields, all the bits matter.
1448 See also bfd_check_overflow. */
1449 fieldmask
= N_ONES (howto
->bitsize
);
1450 signmask
= ~fieldmask
;
1451 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1452 | (fieldmask
<< rightshift
));
1453 a
= (relocation
& addrmask
) >> rightshift
;
1454 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1455 addrmask
>>= rightshift
;
1457 switch (howto
->complain_on_overflow
)
1459 case complain_overflow_signed
:
1460 /* If any sign bits are set, all sign bits must be set.
1461 That is, A must be a valid negative address after
1463 signmask
= ~(fieldmask
>> 1);
1466 case complain_overflow_bitfield
:
1467 /* Much like the signed check, but for a field one bit
1468 wider. We allow a bitfield to represent numbers in the
1469 range -2**n to 2**n-1, where n is the number of bits in the
1470 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1471 can't overflow, which is exactly what we want. */
1473 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1474 flag
= bfd_reloc_overflow
;
1476 /* We only need this next bit of code if the sign bit of B
1477 is below the sign bit of A. This would only happen if
1478 SRC_MASK had fewer bits than BITSIZE. Note that if
1479 SRC_MASK has more bits than BITSIZE, we can get into
1480 trouble; we would need to verify that B is in range, as
1481 we do for A above. */
1482 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1485 /* Set all the bits above the sign bit. */
1488 /* Now we can do the addition. */
1491 /* See if the result has the correct sign. Bits above the
1492 sign bit are junk now; ignore them. If the sum is
1493 positive, make sure we did not have all negative inputs;
1494 if the sum is negative, make sure we did not have all
1495 positive inputs. The test below looks only at the sign
1496 bits, and it really just
1497 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1499 We mask with addrmask here to explicitly allow an address
1500 wrap-around. The Linux kernel relies on it, and it is
1501 the only way to write assembler code which can run when
1502 loaded at a location 0x80000000 away from the location at
1503 which it is linked. */
1504 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1505 flag
= bfd_reloc_overflow
;
1508 case complain_overflow_unsigned
:
1509 /* Checking for an unsigned overflow is relatively easy:
1510 trim the addresses and add, and trim the result as well.
1511 Overflow is normally indicated when the result does not
1512 fit in the field. However, we also need to consider the
1513 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1514 input is 0x80000000, and bfd_vma is only 32 bits; then we
1515 will get sum == 0, but there is an overflow, since the
1516 inputs did not fit in the field. Instead of doing a
1517 separate test, we can check for this by or-ing in the
1518 operands when testing for the sum overflowing its final
1520 sum
= (a
+ b
) & addrmask
;
1521 if ((a
| b
| sum
) & signmask
)
1522 flag
= bfd_reloc_overflow
;
1530 /* Put RELOCATION in the right bits. */
1531 relocation
>>= (bfd_vma
) rightshift
;
1532 relocation
<<= (bfd_vma
) bitpos
;
1534 /* Add RELOCATION to the right bits of X. */
1535 x
= ((x
& ~howto
->dst_mask
)
1536 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1538 /* Put the relocated value back in the object file. */
1544 bfd_put_8 (input_bfd
, x
, location
);
1547 bfd_put_16 (input_bfd
, x
, location
);
1550 bfd_put_32 (input_bfd
, x
, location
);
1554 bfd_put_64 (input_bfd
, x
, location
);
1564 /* Clear a given location using a given howto, by applying a fixed relocation
1565 value and discarding any in-place addend. This is used for fixed-up
1566 relocations against discarded symbols, to make ignorable debug or unwind
1567 information more obvious. */
1570 _bfd_clear_contents (reloc_howto_type
*howto
,
1572 asection
*input_section
,
1578 /* Get the value we are going to relocate. */
1579 size
= bfd_get_reloc_size (howto
);
1587 x
= bfd_get_8 (input_bfd
, location
);
1590 x
= bfd_get_16 (input_bfd
, location
);
1593 x
= bfd_get_32 (input_bfd
, location
);
1597 x
= bfd_get_64 (input_bfd
, location
);
1604 /* Zero out the unwanted bits of X. */
1605 x
&= ~howto
->dst_mask
;
1607 /* For a range list, use 1 instead of 0 as placeholder. 0
1608 would terminate the list, hiding any later entries. */
1609 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1610 ".debug_ranges") == 0
1611 && (howto
->dst_mask
& 1) != 0)
1614 /* Put the relocated value back in the object file. */
1621 bfd_put_8 (input_bfd
, x
, location
);
1624 bfd_put_16 (input_bfd
, x
, location
);
1627 bfd_put_32 (input_bfd
, x
, location
);
1631 bfd_put_64 (input_bfd
, x
, location
);
1642 howto manager, , typedef arelent, Relocations
1647 When an application wants to create a relocation, but doesn't
1648 know what the target machine might call it, it can find out by
1649 using this bit of code.
1658 The insides of a reloc code. The idea is that, eventually, there
1659 will be one enumerator for every type of relocation we ever do.
1660 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1661 return a howto pointer.
1663 This does mean that the application must determine the correct
1664 enumerator value; you can't get a howto pointer from a random set
1685 Basic absolute relocations of N bits.
1700 PC-relative relocations. Sometimes these are relative to the address
1701 of the relocation itself; sometimes they are relative to the start of
1702 the section containing the relocation. It depends on the specific target.
1704 The 24-bit relocation is used in some Intel 960 configurations.
1709 Section relative relocations. Some targets need this for DWARF2.
1712 BFD_RELOC_32_GOT_PCREL
1714 BFD_RELOC_16_GOT_PCREL
1716 BFD_RELOC_8_GOT_PCREL
1722 BFD_RELOC_LO16_GOTOFF
1724 BFD_RELOC_HI16_GOTOFF
1726 BFD_RELOC_HI16_S_GOTOFF
1730 BFD_RELOC_64_PLT_PCREL
1732 BFD_RELOC_32_PLT_PCREL
1734 BFD_RELOC_24_PLT_PCREL
1736 BFD_RELOC_16_PLT_PCREL
1738 BFD_RELOC_8_PLT_PCREL
1746 BFD_RELOC_LO16_PLTOFF
1748 BFD_RELOC_HI16_PLTOFF
1750 BFD_RELOC_HI16_S_PLTOFF
1764 BFD_RELOC_68K_GLOB_DAT
1766 BFD_RELOC_68K_JMP_SLOT
1768 BFD_RELOC_68K_RELATIVE
1770 BFD_RELOC_68K_TLS_GD32
1772 BFD_RELOC_68K_TLS_GD16
1774 BFD_RELOC_68K_TLS_GD8
1776 BFD_RELOC_68K_TLS_LDM32
1778 BFD_RELOC_68K_TLS_LDM16
1780 BFD_RELOC_68K_TLS_LDM8
1782 BFD_RELOC_68K_TLS_LDO32
1784 BFD_RELOC_68K_TLS_LDO16
1786 BFD_RELOC_68K_TLS_LDO8
1788 BFD_RELOC_68K_TLS_IE32
1790 BFD_RELOC_68K_TLS_IE16
1792 BFD_RELOC_68K_TLS_IE8
1794 BFD_RELOC_68K_TLS_LE32
1796 BFD_RELOC_68K_TLS_LE16
1798 BFD_RELOC_68K_TLS_LE8
1800 Relocations used by 68K ELF.
1803 BFD_RELOC_32_BASEREL
1805 BFD_RELOC_16_BASEREL
1807 BFD_RELOC_LO16_BASEREL
1809 BFD_RELOC_HI16_BASEREL
1811 BFD_RELOC_HI16_S_BASEREL
1817 Linkage-table relative.
1822 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1825 BFD_RELOC_32_PCREL_S2
1827 BFD_RELOC_16_PCREL_S2
1829 BFD_RELOC_23_PCREL_S2
1831 These PC-relative relocations are stored as word displacements --
1832 i.e., byte displacements shifted right two bits. The 30-bit word
1833 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1834 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1835 signed 16-bit displacement is used on the MIPS, and the 23-bit
1836 displacement is used on the Alpha.
1843 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1844 the target word. These are used on the SPARC.
1851 For systems that allocate a Global Pointer register, these are
1852 displacements off that register. These relocation types are
1853 handled specially, because the value the register will have is
1854 decided relatively late.
1857 BFD_RELOC_I960_CALLJ
1859 Reloc types used for i960/b.out.
1864 BFD_RELOC_SPARC_WDISP22
1870 BFD_RELOC_SPARC_GOT10
1872 BFD_RELOC_SPARC_GOT13
1874 BFD_RELOC_SPARC_GOT22
1876 BFD_RELOC_SPARC_PC10
1878 BFD_RELOC_SPARC_PC22
1880 BFD_RELOC_SPARC_WPLT30
1882 BFD_RELOC_SPARC_COPY
1884 BFD_RELOC_SPARC_GLOB_DAT
1886 BFD_RELOC_SPARC_JMP_SLOT
1888 BFD_RELOC_SPARC_RELATIVE
1890 BFD_RELOC_SPARC_UA16
1892 BFD_RELOC_SPARC_UA32
1894 BFD_RELOC_SPARC_UA64
1896 BFD_RELOC_SPARC_GOTDATA_HIX22
1898 BFD_RELOC_SPARC_GOTDATA_LOX10
1900 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1902 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1904 BFD_RELOC_SPARC_GOTDATA_OP
1906 BFD_RELOC_SPARC_JMP_IREL
1908 BFD_RELOC_SPARC_IRELATIVE
1910 SPARC ELF relocations. There is probably some overlap with other
1911 relocation types already defined.
1914 BFD_RELOC_SPARC_BASE13
1916 BFD_RELOC_SPARC_BASE22
1918 I think these are specific to SPARC a.out (e.g., Sun 4).
1928 BFD_RELOC_SPARC_OLO10
1930 BFD_RELOC_SPARC_HH22
1932 BFD_RELOC_SPARC_HM10
1934 BFD_RELOC_SPARC_LM22
1936 BFD_RELOC_SPARC_PC_HH22
1938 BFD_RELOC_SPARC_PC_HM10
1940 BFD_RELOC_SPARC_PC_LM22
1942 BFD_RELOC_SPARC_WDISP16
1944 BFD_RELOC_SPARC_WDISP19
1952 BFD_RELOC_SPARC_DISP64
1955 BFD_RELOC_SPARC_PLT32
1957 BFD_RELOC_SPARC_PLT64
1959 BFD_RELOC_SPARC_HIX22
1961 BFD_RELOC_SPARC_LOX10
1969 BFD_RELOC_SPARC_REGISTER
1973 BFD_RELOC_SPARC_SIZE32
1975 BFD_RELOC_SPARC_SIZE64
1977 BFD_RELOC_SPARC_WDISP10
1982 BFD_RELOC_SPARC_REV32
1984 SPARC little endian relocation
1986 BFD_RELOC_SPARC_TLS_GD_HI22
1988 BFD_RELOC_SPARC_TLS_GD_LO10
1990 BFD_RELOC_SPARC_TLS_GD_ADD
1992 BFD_RELOC_SPARC_TLS_GD_CALL
1994 BFD_RELOC_SPARC_TLS_LDM_HI22
1996 BFD_RELOC_SPARC_TLS_LDM_LO10
1998 BFD_RELOC_SPARC_TLS_LDM_ADD
2000 BFD_RELOC_SPARC_TLS_LDM_CALL
2002 BFD_RELOC_SPARC_TLS_LDO_HIX22
2004 BFD_RELOC_SPARC_TLS_LDO_LOX10
2006 BFD_RELOC_SPARC_TLS_LDO_ADD
2008 BFD_RELOC_SPARC_TLS_IE_HI22
2010 BFD_RELOC_SPARC_TLS_IE_LO10
2012 BFD_RELOC_SPARC_TLS_IE_LD
2014 BFD_RELOC_SPARC_TLS_IE_LDX
2016 BFD_RELOC_SPARC_TLS_IE_ADD
2018 BFD_RELOC_SPARC_TLS_LE_HIX22
2020 BFD_RELOC_SPARC_TLS_LE_LOX10
2022 BFD_RELOC_SPARC_TLS_DTPMOD32
2024 BFD_RELOC_SPARC_TLS_DTPMOD64
2026 BFD_RELOC_SPARC_TLS_DTPOFF32
2028 BFD_RELOC_SPARC_TLS_DTPOFF64
2030 BFD_RELOC_SPARC_TLS_TPOFF32
2032 BFD_RELOC_SPARC_TLS_TPOFF64
2034 SPARC TLS relocations
2043 BFD_RELOC_SPU_IMM10W
2047 BFD_RELOC_SPU_IMM16W
2051 BFD_RELOC_SPU_PCREL9a
2053 BFD_RELOC_SPU_PCREL9b
2055 BFD_RELOC_SPU_PCREL16
2065 BFD_RELOC_SPU_ADD_PIC
2070 BFD_RELOC_ALPHA_GPDISP_HI16
2072 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2073 "addend" in some special way.
2074 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2075 writing; when reading, it will be the absolute section symbol. The
2076 addend is the displacement in bytes of the "lda" instruction from
2077 the "ldah" instruction (which is at the address of this reloc).
2079 BFD_RELOC_ALPHA_GPDISP_LO16
2081 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2082 with GPDISP_HI16 relocs. The addend is ignored when writing the
2083 relocations out, and is filled in with the file's GP value on
2084 reading, for convenience.
2087 BFD_RELOC_ALPHA_GPDISP
2089 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2090 relocation except that there is no accompanying GPDISP_LO16
2094 BFD_RELOC_ALPHA_LITERAL
2096 BFD_RELOC_ALPHA_ELF_LITERAL
2098 BFD_RELOC_ALPHA_LITUSE
2100 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2101 the assembler turns it into a LDQ instruction to load the address of
2102 the symbol, and then fills in a register in the real instruction.
2104 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2105 section symbol. The addend is ignored when writing, but is filled
2106 in with the file's GP value on reading, for convenience, as with the
2109 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2110 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2111 but it generates output not based on the position within the .got
2112 section, but relative to the GP value chosen for the file during the
2115 The LITUSE reloc, on the instruction using the loaded address, gives
2116 information to the linker that it might be able to use to optimize
2117 away some literal section references. The symbol is ignored (read
2118 as the absolute section symbol), and the "addend" indicates the type
2119 of instruction using the register:
2120 1 - "memory" fmt insn
2121 2 - byte-manipulation (byte offset reg)
2122 3 - jsr (target of branch)
2125 BFD_RELOC_ALPHA_HINT
2127 The HINT relocation indicates a value that should be filled into the
2128 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2129 prediction logic which may be provided on some processors.
2132 BFD_RELOC_ALPHA_LINKAGE
2134 The LINKAGE relocation outputs a linkage pair in the object file,
2135 which is filled by the linker.
2138 BFD_RELOC_ALPHA_CODEADDR
2140 The CODEADDR relocation outputs a STO_CA in the object file,
2141 which is filled by the linker.
2144 BFD_RELOC_ALPHA_GPREL_HI16
2146 BFD_RELOC_ALPHA_GPREL_LO16
2148 The GPREL_HI/LO relocations together form a 32-bit offset from the
2152 BFD_RELOC_ALPHA_BRSGP
2154 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2155 share a common GP, and the target address is adjusted for
2156 STO_ALPHA_STD_GPLOAD.
2161 The NOP relocation outputs a NOP if the longword displacement
2162 between two procedure entry points is < 2^21.
2167 The BSR relocation outputs a BSR if the longword displacement
2168 between two procedure entry points is < 2^21.
2173 The LDA relocation outputs a LDA if the longword displacement
2174 between two procedure entry points is < 2^16.
2179 The BOH relocation outputs a BSR if the longword displacement
2180 between two procedure entry points is < 2^21, or else a hint.
2183 BFD_RELOC_ALPHA_TLSGD
2185 BFD_RELOC_ALPHA_TLSLDM
2187 BFD_RELOC_ALPHA_DTPMOD64
2189 BFD_RELOC_ALPHA_GOTDTPREL16
2191 BFD_RELOC_ALPHA_DTPREL64
2193 BFD_RELOC_ALPHA_DTPREL_HI16
2195 BFD_RELOC_ALPHA_DTPREL_LO16
2197 BFD_RELOC_ALPHA_DTPREL16
2199 BFD_RELOC_ALPHA_GOTTPREL16
2201 BFD_RELOC_ALPHA_TPREL64
2203 BFD_RELOC_ALPHA_TPREL_HI16
2205 BFD_RELOC_ALPHA_TPREL_LO16
2207 BFD_RELOC_ALPHA_TPREL16
2209 Alpha thread-local storage relocations.
2214 BFD_RELOC_MICROMIPS_JMP
2216 The MIPS jump instruction.
2219 BFD_RELOC_MIPS16_JMP
2221 The MIPS16 jump instruction.
2224 BFD_RELOC_MIPS16_GPREL
2226 MIPS16 GP relative reloc.
2231 High 16 bits of 32-bit value; simple reloc.
2236 High 16 bits of 32-bit value but the low 16 bits will be sign
2237 extended and added to form the final result. If the low 16
2238 bits form a negative number, we need to add one to the high value
2239 to compensate for the borrow when the low bits are added.
2247 BFD_RELOC_HI16_PCREL
2249 High 16 bits of 32-bit pc-relative value
2251 BFD_RELOC_HI16_S_PCREL
2253 High 16 bits of 32-bit pc-relative value, adjusted
2255 BFD_RELOC_LO16_PCREL
2257 Low 16 bits of pc-relative value
2260 BFD_RELOC_MIPS16_GOT16
2262 BFD_RELOC_MIPS16_CALL16
2264 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2265 16-bit immediate fields
2267 BFD_RELOC_MIPS16_HI16
2269 MIPS16 high 16 bits of 32-bit value.
2271 BFD_RELOC_MIPS16_HI16_S
2273 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2274 extended and added to form the final result. If the low 16
2275 bits form a negative number, we need to add one to the high value
2276 to compensate for the borrow when the low bits are added.
2278 BFD_RELOC_MIPS16_LO16
2283 BFD_RELOC_MIPS16_TLS_GD
2285 BFD_RELOC_MIPS16_TLS_LDM
2287 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2289 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2291 BFD_RELOC_MIPS16_TLS_GOTTPREL
2293 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2295 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2297 MIPS16 TLS relocations
2300 BFD_RELOC_MIPS_LITERAL
2302 BFD_RELOC_MICROMIPS_LITERAL
2304 Relocation against a MIPS literal section.
2307 BFD_RELOC_MICROMIPS_7_PCREL_S1
2309 BFD_RELOC_MICROMIPS_10_PCREL_S1
2311 BFD_RELOC_MICROMIPS_16_PCREL_S1
2313 microMIPS PC-relative relocations.
2316 BFD_RELOC_MIPS16_16_PCREL_S1
2318 MIPS16 PC-relative relocation.
2321 BFD_RELOC_MIPS_21_PCREL_S2
2323 BFD_RELOC_MIPS_26_PCREL_S2
2325 BFD_RELOC_MIPS_18_PCREL_S3
2327 BFD_RELOC_MIPS_19_PCREL_S2
2329 MIPS PC-relative relocations.
2332 BFD_RELOC_MICROMIPS_GPREL16
2334 BFD_RELOC_MICROMIPS_HI16
2336 BFD_RELOC_MICROMIPS_HI16_S
2338 BFD_RELOC_MICROMIPS_LO16
2340 microMIPS versions of generic BFD relocs.
2343 BFD_RELOC_MIPS_GOT16
2345 BFD_RELOC_MICROMIPS_GOT16
2347 BFD_RELOC_MIPS_CALL16
2349 BFD_RELOC_MICROMIPS_CALL16
2351 BFD_RELOC_MIPS_GOT_HI16
2353 BFD_RELOC_MICROMIPS_GOT_HI16
2355 BFD_RELOC_MIPS_GOT_LO16
2357 BFD_RELOC_MICROMIPS_GOT_LO16
2359 BFD_RELOC_MIPS_CALL_HI16
2361 BFD_RELOC_MICROMIPS_CALL_HI16
2363 BFD_RELOC_MIPS_CALL_LO16
2365 BFD_RELOC_MICROMIPS_CALL_LO16
2369 BFD_RELOC_MICROMIPS_SUB
2371 BFD_RELOC_MIPS_GOT_PAGE
2373 BFD_RELOC_MICROMIPS_GOT_PAGE
2375 BFD_RELOC_MIPS_GOT_OFST
2377 BFD_RELOC_MICROMIPS_GOT_OFST
2379 BFD_RELOC_MIPS_GOT_DISP
2381 BFD_RELOC_MICROMIPS_GOT_DISP
2383 BFD_RELOC_MIPS_SHIFT5
2385 BFD_RELOC_MIPS_SHIFT6
2387 BFD_RELOC_MIPS_INSERT_A
2389 BFD_RELOC_MIPS_INSERT_B
2391 BFD_RELOC_MIPS_DELETE
2393 BFD_RELOC_MIPS_HIGHEST
2395 BFD_RELOC_MICROMIPS_HIGHEST
2397 BFD_RELOC_MIPS_HIGHER
2399 BFD_RELOC_MICROMIPS_HIGHER
2401 BFD_RELOC_MIPS_SCN_DISP
2403 BFD_RELOC_MICROMIPS_SCN_DISP
2405 BFD_RELOC_MIPS_REL16
2407 BFD_RELOC_MIPS_RELGOT
2411 BFD_RELOC_MICROMIPS_JALR
2413 BFD_RELOC_MIPS_TLS_DTPMOD32
2415 BFD_RELOC_MIPS_TLS_DTPREL32
2417 BFD_RELOC_MIPS_TLS_DTPMOD64
2419 BFD_RELOC_MIPS_TLS_DTPREL64
2421 BFD_RELOC_MIPS_TLS_GD
2423 BFD_RELOC_MICROMIPS_TLS_GD
2425 BFD_RELOC_MIPS_TLS_LDM
2427 BFD_RELOC_MICROMIPS_TLS_LDM
2429 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2431 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2433 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2435 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2437 BFD_RELOC_MIPS_TLS_GOTTPREL
2439 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2441 BFD_RELOC_MIPS_TLS_TPREL32
2443 BFD_RELOC_MIPS_TLS_TPREL64
2445 BFD_RELOC_MIPS_TLS_TPREL_HI16
2447 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2449 BFD_RELOC_MIPS_TLS_TPREL_LO16
2451 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2455 MIPS ELF relocations.
2461 BFD_RELOC_MIPS_JUMP_SLOT
2463 MIPS ELF relocations (VxWorks and PLT extensions).
2467 BFD_RELOC_MOXIE_10_PCREL
2469 Moxie ELF relocations.
2481 FT32 ELF relocations.
2485 BFD_RELOC_FRV_LABEL16
2487 BFD_RELOC_FRV_LABEL24
2493 BFD_RELOC_FRV_GPREL12
2495 BFD_RELOC_FRV_GPRELU12
2497 BFD_RELOC_FRV_GPREL32
2499 BFD_RELOC_FRV_GPRELHI
2501 BFD_RELOC_FRV_GPRELLO
2509 BFD_RELOC_FRV_FUNCDESC
2511 BFD_RELOC_FRV_FUNCDESC_GOT12
2513 BFD_RELOC_FRV_FUNCDESC_GOTHI
2515 BFD_RELOC_FRV_FUNCDESC_GOTLO
2517 BFD_RELOC_FRV_FUNCDESC_VALUE
2519 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2521 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2523 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2525 BFD_RELOC_FRV_GOTOFF12
2527 BFD_RELOC_FRV_GOTOFFHI
2529 BFD_RELOC_FRV_GOTOFFLO
2531 BFD_RELOC_FRV_GETTLSOFF
2533 BFD_RELOC_FRV_TLSDESC_VALUE
2535 BFD_RELOC_FRV_GOTTLSDESC12
2537 BFD_RELOC_FRV_GOTTLSDESCHI
2539 BFD_RELOC_FRV_GOTTLSDESCLO
2541 BFD_RELOC_FRV_TLSMOFF12
2543 BFD_RELOC_FRV_TLSMOFFHI
2545 BFD_RELOC_FRV_TLSMOFFLO
2547 BFD_RELOC_FRV_GOTTLSOFF12
2549 BFD_RELOC_FRV_GOTTLSOFFHI
2551 BFD_RELOC_FRV_GOTTLSOFFLO
2553 BFD_RELOC_FRV_TLSOFF
2555 BFD_RELOC_FRV_TLSDESC_RELAX
2557 BFD_RELOC_FRV_GETTLSOFF_RELAX
2559 BFD_RELOC_FRV_TLSOFF_RELAX
2561 BFD_RELOC_FRV_TLSMOFF
2563 Fujitsu Frv Relocations.
2567 BFD_RELOC_MN10300_GOTOFF24
2569 This is a 24bit GOT-relative reloc for the mn10300.
2571 BFD_RELOC_MN10300_GOT32
2573 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2576 BFD_RELOC_MN10300_GOT24
2578 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2581 BFD_RELOC_MN10300_GOT16
2583 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2586 BFD_RELOC_MN10300_COPY
2588 Copy symbol at runtime.
2590 BFD_RELOC_MN10300_GLOB_DAT
2594 BFD_RELOC_MN10300_JMP_SLOT
2598 BFD_RELOC_MN10300_RELATIVE
2600 Adjust by program base.
2602 BFD_RELOC_MN10300_SYM_DIFF
2604 Together with another reloc targeted at the same location,
2605 allows for a value that is the difference of two symbols
2606 in the same section.
2608 BFD_RELOC_MN10300_ALIGN
2610 The addend of this reloc is an alignment power that must
2611 be honoured at the offset's location, regardless of linker
2614 BFD_RELOC_MN10300_TLS_GD
2616 BFD_RELOC_MN10300_TLS_LD
2618 BFD_RELOC_MN10300_TLS_LDO
2620 BFD_RELOC_MN10300_TLS_GOTIE
2622 BFD_RELOC_MN10300_TLS_IE
2624 BFD_RELOC_MN10300_TLS_LE
2626 BFD_RELOC_MN10300_TLS_DTPMOD
2628 BFD_RELOC_MN10300_TLS_DTPOFF
2630 BFD_RELOC_MN10300_TLS_TPOFF
2632 Various TLS-related relocations.
2634 BFD_RELOC_MN10300_32_PCREL
2636 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2639 BFD_RELOC_MN10300_16_PCREL
2641 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2652 BFD_RELOC_386_GLOB_DAT
2654 BFD_RELOC_386_JUMP_SLOT
2656 BFD_RELOC_386_RELATIVE
2658 BFD_RELOC_386_GOTOFF
2662 BFD_RELOC_386_TLS_TPOFF
2664 BFD_RELOC_386_TLS_IE
2666 BFD_RELOC_386_TLS_GOTIE
2668 BFD_RELOC_386_TLS_LE
2670 BFD_RELOC_386_TLS_GD
2672 BFD_RELOC_386_TLS_LDM
2674 BFD_RELOC_386_TLS_LDO_32
2676 BFD_RELOC_386_TLS_IE_32
2678 BFD_RELOC_386_TLS_LE_32
2680 BFD_RELOC_386_TLS_DTPMOD32
2682 BFD_RELOC_386_TLS_DTPOFF32
2684 BFD_RELOC_386_TLS_TPOFF32
2686 BFD_RELOC_386_TLS_GOTDESC
2688 BFD_RELOC_386_TLS_DESC_CALL
2690 BFD_RELOC_386_TLS_DESC
2692 BFD_RELOC_386_IRELATIVE
2694 BFD_RELOC_386_GOT32X
2696 i386/elf relocations
2699 BFD_RELOC_X86_64_GOT32
2701 BFD_RELOC_X86_64_PLT32
2703 BFD_RELOC_X86_64_COPY
2705 BFD_RELOC_X86_64_GLOB_DAT
2707 BFD_RELOC_X86_64_JUMP_SLOT
2709 BFD_RELOC_X86_64_RELATIVE
2711 BFD_RELOC_X86_64_GOTPCREL
2713 BFD_RELOC_X86_64_32S
2715 BFD_RELOC_X86_64_DTPMOD64
2717 BFD_RELOC_X86_64_DTPOFF64
2719 BFD_RELOC_X86_64_TPOFF64
2721 BFD_RELOC_X86_64_TLSGD
2723 BFD_RELOC_X86_64_TLSLD
2725 BFD_RELOC_X86_64_DTPOFF32
2727 BFD_RELOC_X86_64_GOTTPOFF
2729 BFD_RELOC_X86_64_TPOFF32
2731 BFD_RELOC_X86_64_GOTOFF64
2733 BFD_RELOC_X86_64_GOTPC32
2735 BFD_RELOC_X86_64_GOT64
2737 BFD_RELOC_X86_64_GOTPCREL64
2739 BFD_RELOC_X86_64_GOTPC64
2741 BFD_RELOC_X86_64_GOTPLT64
2743 BFD_RELOC_X86_64_PLTOFF64
2745 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2747 BFD_RELOC_X86_64_TLSDESC_CALL
2749 BFD_RELOC_X86_64_TLSDESC
2751 BFD_RELOC_X86_64_IRELATIVE
2753 BFD_RELOC_X86_64_PC32_BND
2755 BFD_RELOC_X86_64_PLT32_BND
2757 BFD_RELOC_X86_64_GOTPCRELX
2759 BFD_RELOC_X86_64_REX_GOTPCRELX
2761 x86-64/elf relocations
2764 BFD_RELOC_NS32K_IMM_8
2766 BFD_RELOC_NS32K_IMM_16
2768 BFD_RELOC_NS32K_IMM_32
2770 BFD_RELOC_NS32K_IMM_8_PCREL
2772 BFD_RELOC_NS32K_IMM_16_PCREL
2774 BFD_RELOC_NS32K_IMM_32_PCREL
2776 BFD_RELOC_NS32K_DISP_8
2778 BFD_RELOC_NS32K_DISP_16
2780 BFD_RELOC_NS32K_DISP_32
2782 BFD_RELOC_NS32K_DISP_8_PCREL
2784 BFD_RELOC_NS32K_DISP_16_PCREL
2786 BFD_RELOC_NS32K_DISP_32_PCREL
2791 BFD_RELOC_PDP11_DISP_8_PCREL
2793 BFD_RELOC_PDP11_DISP_6_PCREL
2798 BFD_RELOC_PJ_CODE_HI16
2800 BFD_RELOC_PJ_CODE_LO16
2802 BFD_RELOC_PJ_CODE_DIR16
2804 BFD_RELOC_PJ_CODE_DIR32
2806 BFD_RELOC_PJ_CODE_REL16
2808 BFD_RELOC_PJ_CODE_REL32
2810 Picojava relocs. Not all of these appear in object files.
2821 BFD_RELOC_PPC_B16_BRTAKEN
2823 BFD_RELOC_PPC_B16_BRNTAKEN
2827 BFD_RELOC_PPC_BA16_BRTAKEN
2829 BFD_RELOC_PPC_BA16_BRNTAKEN
2833 BFD_RELOC_PPC_GLOB_DAT
2835 BFD_RELOC_PPC_JMP_SLOT
2837 BFD_RELOC_PPC_RELATIVE
2839 BFD_RELOC_PPC_LOCAL24PC
2841 BFD_RELOC_PPC_EMB_NADDR32
2843 BFD_RELOC_PPC_EMB_NADDR16
2845 BFD_RELOC_PPC_EMB_NADDR16_LO
2847 BFD_RELOC_PPC_EMB_NADDR16_HI
2849 BFD_RELOC_PPC_EMB_NADDR16_HA
2851 BFD_RELOC_PPC_EMB_SDAI16
2853 BFD_RELOC_PPC_EMB_SDA2I16
2855 BFD_RELOC_PPC_EMB_SDA2REL
2857 BFD_RELOC_PPC_EMB_SDA21
2859 BFD_RELOC_PPC_EMB_MRKREF
2861 BFD_RELOC_PPC_EMB_RELSEC16
2863 BFD_RELOC_PPC_EMB_RELST_LO
2865 BFD_RELOC_PPC_EMB_RELST_HI
2867 BFD_RELOC_PPC_EMB_RELST_HA
2869 BFD_RELOC_PPC_EMB_BIT_FLD
2871 BFD_RELOC_PPC_EMB_RELSDA
2873 BFD_RELOC_PPC_VLE_REL8
2875 BFD_RELOC_PPC_VLE_REL15
2877 BFD_RELOC_PPC_VLE_REL24
2879 BFD_RELOC_PPC_VLE_LO16A
2881 BFD_RELOC_PPC_VLE_LO16D
2883 BFD_RELOC_PPC_VLE_HI16A
2885 BFD_RELOC_PPC_VLE_HI16D
2887 BFD_RELOC_PPC_VLE_HA16A
2889 BFD_RELOC_PPC_VLE_HA16D
2891 BFD_RELOC_PPC_VLE_SDA21
2893 BFD_RELOC_PPC_VLE_SDA21_LO
2895 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2897 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2899 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2901 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2903 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2905 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2907 BFD_RELOC_PPC_16DX_HA
2909 BFD_RELOC_PPC_REL16DX_HA
2911 BFD_RELOC_PPC64_HIGHER
2913 BFD_RELOC_PPC64_HIGHER_S
2915 BFD_RELOC_PPC64_HIGHEST
2917 BFD_RELOC_PPC64_HIGHEST_S
2919 BFD_RELOC_PPC64_TOC16_LO
2921 BFD_RELOC_PPC64_TOC16_HI
2923 BFD_RELOC_PPC64_TOC16_HA
2927 BFD_RELOC_PPC64_PLTGOT16
2929 BFD_RELOC_PPC64_PLTGOT16_LO
2931 BFD_RELOC_PPC64_PLTGOT16_HI
2933 BFD_RELOC_PPC64_PLTGOT16_HA
2935 BFD_RELOC_PPC64_ADDR16_DS
2937 BFD_RELOC_PPC64_ADDR16_LO_DS
2939 BFD_RELOC_PPC64_GOT16_DS
2941 BFD_RELOC_PPC64_GOT16_LO_DS
2943 BFD_RELOC_PPC64_PLT16_LO_DS
2945 BFD_RELOC_PPC64_SECTOFF_DS
2947 BFD_RELOC_PPC64_SECTOFF_LO_DS
2949 BFD_RELOC_PPC64_TOC16_DS
2951 BFD_RELOC_PPC64_TOC16_LO_DS
2953 BFD_RELOC_PPC64_PLTGOT16_DS
2955 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2957 BFD_RELOC_PPC64_ADDR16_HIGH
2959 BFD_RELOC_PPC64_ADDR16_HIGHA
2961 BFD_RELOC_PPC64_ADDR64_LOCAL
2963 BFD_RELOC_PPC64_ENTRY
2965 Power(rs6000) and PowerPC relocations.
2974 BFD_RELOC_PPC_DTPMOD
2976 BFD_RELOC_PPC_TPREL16
2978 BFD_RELOC_PPC_TPREL16_LO
2980 BFD_RELOC_PPC_TPREL16_HI
2982 BFD_RELOC_PPC_TPREL16_HA
2986 BFD_RELOC_PPC_DTPREL16
2988 BFD_RELOC_PPC_DTPREL16_LO
2990 BFD_RELOC_PPC_DTPREL16_HI
2992 BFD_RELOC_PPC_DTPREL16_HA
2994 BFD_RELOC_PPC_DTPREL
2996 BFD_RELOC_PPC_GOT_TLSGD16
2998 BFD_RELOC_PPC_GOT_TLSGD16_LO
3000 BFD_RELOC_PPC_GOT_TLSGD16_HI
3002 BFD_RELOC_PPC_GOT_TLSGD16_HA
3004 BFD_RELOC_PPC_GOT_TLSLD16
3006 BFD_RELOC_PPC_GOT_TLSLD16_LO
3008 BFD_RELOC_PPC_GOT_TLSLD16_HI
3010 BFD_RELOC_PPC_GOT_TLSLD16_HA
3012 BFD_RELOC_PPC_GOT_TPREL16
3014 BFD_RELOC_PPC_GOT_TPREL16_LO
3016 BFD_RELOC_PPC_GOT_TPREL16_HI
3018 BFD_RELOC_PPC_GOT_TPREL16_HA
3020 BFD_RELOC_PPC_GOT_DTPREL16
3022 BFD_RELOC_PPC_GOT_DTPREL16_LO
3024 BFD_RELOC_PPC_GOT_DTPREL16_HI
3026 BFD_RELOC_PPC_GOT_DTPREL16_HA
3028 BFD_RELOC_PPC64_TPREL16_DS
3030 BFD_RELOC_PPC64_TPREL16_LO_DS
3032 BFD_RELOC_PPC64_TPREL16_HIGHER
3034 BFD_RELOC_PPC64_TPREL16_HIGHERA
3036 BFD_RELOC_PPC64_TPREL16_HIGHEST
3038 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3040 BFD_RELOC_PPC64_DTPREL16_DS
3042 BFD_RELOC_PPC64_DTPREL16_LO_DS
3044 BFD_RELOC_PPC64_DTPREL16_HIGHER
3046 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3048 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3050 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3052 BFD_RELOC_PPC64_TPREL16_HIGH
3054 BFD_RELOC_PPC64_TPREL16_HIGHA
3056 BFD_RELOC_PPC64_DTPREL16_HIGH
3058 BFD_RELOC_PPC64_DTPREL16_HIGHA
3060 PowerPC and PowerPC64 thread-local storage relocations.
3065 IBM 370/390 relocations
3070 The type of reloc used to build a constructor table - at the moment
3071 probably a 32 bit wide absolute relocation, but the target can choose.
3072 It generally does map to one of the other relocation types.
3075 BFD_RELOC_ARM_PCREL_BRANCH
3077 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3078 not stored in the instruction.
3080 BFD_RELOC_ARM_PCREL_BLX
3082 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3083 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3084 field in the instruction.
3086 BFD_RELOC_THUMB_PCREL_BLX
3088 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3089 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3090 field in the instruction.
3092 BFD_RELOC_ARM_PCREL_CALL
3094 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3096 BFD_RELOC_ARM_PCREL_JUMP
3098 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3101 BFD_RELOC_THUMB_PCREL_BRANCH7
3103 BFD_RELOC_THUMB_PCREL_BRANCH9
3105 BFD_RELOC_THUMB_PCREL_BRANCH12
3107 BFD_RELOC_THUMB_PCREL_BRANCH20
3109 BFD_RELOC_THUMB_PCREL_BRANCH23
3111 BFD_RELOC_THUMB_PCREL_BRANCH25
3113 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3114 The lowest bit must be zero and is not stored in the instruction.
3115 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3116 "nn" one smaller in all cases. Note further that BRANCH23
3117 corresponds to R_ARM_THM_CALL.
3120 BFD_RELOC_ARM_OFFSET_IMM
3122 12-bit immediate offset, used in ARM-format ldr and str instructions.
3125 BFD_RELOC_ARM_THUMB_OFFSET
3127 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3130 BFD_RELOC_ARM_TARGET1
3132 Pc-relative or absolute relocation depending on target. Used for
3133 entries in .init_array sections.
3135 BFD_RELOC_ARM_ROSEGREL32
3137 Read-only segment base relative address.
3139 BFD_RELOC_ARM_SBREL32
3141 Data segment base relative address.
3143 BFD_RELOC_ARM_TARGET2
3145 This reloc is used for references to RTTI data from exception handling
3146 tables. The actual definition depends on the target. It may be a
3147 pc-relative or some form of GOT-indirect relocation.
3149 BFD_RELOC_ARM_PREL31
3151 31-bit PC relative address.
3157 BFD_RELOC_ARM_MOVW_PCREL
3159 BFD_RELOC_ARM_MOVT_PCREL
3161 BFD_RELOC_ARM_THUMB_MOVW
3163 BFD_RELOC_ARM_THUMB_MOVT
3165 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3167 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3169 Low and High halfword relocations for MOVW and MOVT instructions.
3172 BFD_RELOC_ARM_JUMP_SLOT
3174 BFD_RELOC_ARM_GLOB_DAT
3180 BFD_RELOC_ARM_RELATIVE
3182 BFD_RELOC_ARM_GOTOFF
3186 BFD_RELOC_ARM_GOT_PREL
3188 Relocations for setting up GOTs and PLTs for shared libraries.
3191 BFD_RELOC_ARM_TLS_GD32
3193 BFD_RELOC_ARM_TLS_LDO32
3195 BFD_RELOC_ARM_TLS_LDM32
3197 BFD_RELOC_ARM_TLS_DTPOFF32
3199 BFD_RELOC_ARM_TLS_DTPMOD32
3201 BFD_RELOC_ARM_TLS_TPOFF32
3203 BFD_RELOC_ARM_TLS_IE32
3205 BFD_RELOC_ARM_TLS_LE32
3207 BFD_RELOC_ARM_TLS_GOTDESC
3209 BFD_RELOC_ARM_TLS_CALL
3211 BFD_RELOC_ARM_THM_TLS_CALL
3213 BFD_RELOC_ARM_TLS_DESCSEQ
3215 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3217 BFD_RELOC_ARM_TLS_DESC
3219 ARM thread-local storage relocations.
3222 BFD_RELOC_ARM_ALU_PC_G0_NC
3224 BFD_RELOC_ARM_ALU_PC_G0
3226 BFD_RELOC_ARM_ALU_PC_G1_NC
3228 BFD_RELOC_ARM_ALU_PC_G1
3230 BFD_RELOC_ARM_ALU_PC_G2
3232 BFD_RELOC_ARM_LDR_PC_G0
3234 BFD_RELOC_ARM_LDR_PC_G1
3236 BFD_RELOC_ARM_LDR_PC_G2
3238 BFD_RELOC_ARM_LDRS_PC_G0
3240 BFD_RELOC_ARM_LDRS_PC_G1
3242 BFD_RELOC_ARM_LDRS_PC_G2
3244 BFD_RELOC_ARM_LDC_PC_G0
3246 BFD_RELOC_ARM_LDC_PC_G1
3248 BFD_RELOC_ARM_LDC_PC_G2
3250 BFD_RELOC_ARM_ALU_SB_G0_NC
3252 BFD_RELOC_ARM_ALU_SB_G0
3254 BFD_RELOC_ARM_ALU_SB_G1_NC
3256 BFD_RELOC_ARM_ALU_SB_G1
3258 BFD_RELOC_ARM_ALU_SB_G2
3260 BFD_RELOC_ARM_LDR_SB_G0
3262 BFD_RELOC_ARM_LDR_SB_G1
3264 BFD_RELOC_ARM_LDR_SB_G2
3266 BFD_RELOC_ARM_LDRS_SB_G0
3268 BFD_RELOC_ARM_LDRS_SB_G1
3270 BFD_RELOC_ARM_LDRS_SB_G2
3272 BFD_RELOC_ARM_LDC_SB_G0
3274 BFD_RELOC_ARM_LDC_SB_G1
3276 BFD_RELOC_ARM_LDC_SB_G2
3278 ARM group relocations.
3283 Annotation of BX instructions.
3286 BFD_RELOC_ARM_IRELATIVE
3288 ARM support for STT_GNU_IFUNC.
3291 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3293 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3295 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3297 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3299 Thumb1 relocations to support execute-only code.
3302 BFD_RELOC_ARM_IMMEDIATE
3304 BFD_RELOC_ARM_ADRL_IMMEDIATE
3306 BFD_RELOC_ARM_T32_IMMEDIATE
3308 BFD_RELOC_ARM_T32_ADD_IMM
3310 BFD_RELOC_ARM_T32_IMM12
3312 BFD_RELOC_ARM_T32_ADD_PC12
3314 BFD_RELOC_ARM_SHIFT_IMM
3324 BFD_RELOC_ARM_CP_OFF_IMM
3326 BFD_RELOC_ARM_CP_OFF_IMM_S2
3328 BFD_RELOC_ARM_T32_CP_OFF_IMM
3330 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3332 BFD_RELOC_ARM_ADR_IMM
3334 BFD_RELOC_ARM_LDR_IMM
3336 BFD_RELOC_ARM_LITERAL
3338 BFD_RELOC_ARM_IN_POOL
3340 BFD_RELOC_ARM_OFFSET_IMM8
3342 BFD_RELOC_ARM_T32_OFFSET_U8
3344 BFD_RELOC_ARM_T32_OFFSET_IMM
3346 BFD_RELOC_ARM_HWLITERAL
3348 BFD_RELOC_ARM_THUMB_ADD
3350 BFD_RELOC_ARM_THUMB_IMM
3352 BFD_RELOC_ARM_THUMB_SHIFT
3354 These relocs are only used within the ARM assembler. They are not
3355 (at present) written to any object files.
3358 BFD_RELOC_SH_PCDISP8BY2
3360 BFD_RELOC_SH_PCDISP12BY2
3368 BFD_RELOC_SH_DISP12BY2
3370 BFD_RELOC_SH_DISP12BY4
3372 BFD_RELOC_SH_DISP12BY8
3376 BFD_RELOC_SH_DISP20BY8
3380 BFD_RELOC_SH_IMM4BY2
3382 BFD_RELOC_SH_IMM4BY4
3386 BFD_RELOC_SH_IMM8BY2
3388 BFD_RELOC_SH_IMM8BY4
3390 BFD_RELOC_SH_PCRELIMM8BY2
3392 BFD_RELOC_SH_PCRELIMM8BY4
3394 BFD_RELOC_SH_SWITCH16
3396 BFD_RELOC_SH_SWITCH32
3410 BFD_RELOC_SH_LOOP_START
3412 BFD_RELOC_SH_LOOP_END
3416 BFD_RELOC_SH_GLOB_DAT
3418 BFD_RELOC_SH_JMP_SLOT
3420 BFD_RELOC_SH_RELATIVE
3424 BFD_RELOC_SH_GOT_LOW16
3426 BFD_RELOC_SH_GOT_MEDLOW16
3428 BFD_RELOC_SH_GOT_MEDHI16
3430 BFD_RELOC_SH_GOT_HI16
3432 BFD_RELOC_SH_GOTPLT_LOW16
3434 BFD_RELOC_SH_GOTPLT_MEDLOW16
3436 BFD_RELOC_SH_GOTPLT_MEDHI16
3438 BFD_RELOC_SH_GOTPLT_HI16
3440 BFD_RELOC_SH_PLT_LOW16
3442 BFD_RELOC_SH_PLT_MEDLOW16
3444 BFD_RELOC_SH_PLT_MEDHI16
3446 BFD_RELOC_SH_PLT_HI16
3448 BFD_RELOC_SH_GOTOFF_LOW16
3450 BFD_RELOC_SH_GOTOFF_MEDLOW16
3452 BFD_RELOC_SH_GOTOFF_MEDHI16
3454 BFD_RELOC_SH_GOTOFF_HI16
3456 BFD_RELOC_SH_GOTPC_LOW16
3458 BFD_RELOC_SH_GOTPC_MEDLOW16
3460 BFD_RELOC_SH_GOTPC_MEDHI16
3462 BFD_RELOC_SH_GOTPC_HI16
3466 BFD_RELOC_SH_GLOB_DAT64
3468 BFD_RELOC_SH_JMP_SLOT64
3470 BFD_RELOC_SH_RELATIVE64
3472 BFD_RELOC_SH_GOT10BY4
3474 BFD_RELOC_SH_GOT10BY8
3476 BFD_RELOC_SH_GOTPLT10BY4
3478 BFD_RELOC_SH_GOTPLT10BY8
3480 BFD_RELOC_SH_GOTPLT32
3482 BFD_RELOC_SH_SHMEDIA_CODE
3488 BFD_RELOC_SH_IMMS6BY32
3494 BFD_RELOC_SH_IMMS10BY2
3496 BFD_RELOC_SH_IMMS10BY4
3498 BFD_RELOC_SH_IMMS10BY8
3504 BFD_RELOC_SH_IMM_LOW16
3506 BFD_RELOC_SH_IMM_LOW16_PCREL
3508 BFD_RELOC_SH_IMM_MEDLOW16
3510 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3512 BFD_RELOC_SH_IMM_MEDHI16
3514 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3516 BFD_RELOC_SH_IMM_HI16
3518 BFD_RELOC_SH_IMM_HI16_PCREL
3522 BFD_RELOC_SH_TLS_GD_32
3524 BFD_RELOC_SH_TLS_LD_32
3526 BFD_RELOC_SH_TLS_LDO_32
3528 BFD_RELOC_SH_TLS_IE_32
3530 BFD_RELOC_SH_TLS_LE_32
3532 BFD_RELOC_SH_TLS_DTPMOD32
3534 BFD_RELOC_SH_TLS_DTPOFF32
3536 BFD_RELOC_SH_TLS_TPOFF32
3540 BFD_RELOC_SH_GOTOFF20
3542 BFD_RELOC_SH_GOTFUNCDESC
3544 BFD_RELOC_SH_GOTFUNCDESC20
3546 BFD_RELOC_SH_GOTOFFFUNCDESC
3548 BFD_RELOC_SH_GOTOFFFUNCDESC20
3550 BFD_RELOC_SH_FUNCDESC
3552 Renesas / SuperH SH relocs. Not all of these appear in object files.
3575 BFD_RELOC_ARC_SECTOFF
3577 BFD_RELOC_ARC_S21H_PCREL
3579 BFD_RELOC_ARC_S21W_PCREL
3581 BFD_RELOC_ARC_S25H_PCREL
3583 BFD_RELOC_ARC_S25W_PCREL
3587 BFD_RELOC_ARC_SDA_LDST
3589 BFD_RELOC_ARC_SDA_LDST1
3591 BFD_RELOC_ARC_SDA_LDST2
3593 BFD_RELOC_ARC_SDA16_LD
3595 BFD_RELOC_ARC_SDA16_LD1
3597 BFD_RELOC_ARC_SDA16_LD2
3599 BFD_RELOC_ARC_S13_PCREL
3605 BFD_RELOC_ARC_32_ME_S
3607 BFD_RELOC_ARC_N32_ME
3609 BFD_RELOC_ARC_SECTOFF_ME
3611 BFD_RELOC_ARC_SDA32_ME
3615 BFD_RELOC_AC_SECTOFF_U8
3617 BFD_RELOC_AC_SECTOFF_U8_1
3619 BFD_RELOC_AC_SECTOFF_U8_2
3621 BFD_RELOC_AC_SECTOFF_S9
3623 BFD_RELOC_AC_SECTOFF_S9_1
3625 BFD_RELOC_AC_SECTOFF_S9_2
3627 BFD_RELOC_ARC_SECTOFF_ME_1
3629 BFD_RELOC_ARC_SECTOFF_ME_2
3631 BFD_RELOC_ARC_SECTOFF_1
3633 BFD_RELOC_ARC_SECTOFF_2
3635 BFD_RELOC_ARC_SDA_12
3637 BFD_RELOC_ARC_SDA16_ST2
3639 BFD_RELOC_ARC_32_PCREL
3645 BFD_RELOC_ARC_GOTPC32
3651 BFD_RELOC_ARC_GLOB_DAT
3653 BFD_RELOC_ARC_JMP_SLOT
3655 BFD_RELOC_ARC_RELATIVE
3657 BFD_RELOC_ARC_GOTOFF
3661 BFD_RELOC_ARC_S21W_PCREL_PLT
3663 BFD_RELOC_ARC_S25H_PCREL_PLT
3665 BFD_RELOC_ARC_TLS_DTPMOD
3667 BFD_RELOC_ARC_TLS_TPOFF
3669 BFD_RELOC_ARC_TLS_GD_GOT
3671 BFD_RELOC_ARC_TLS_GD_LD
3673 BFD_RELOC_ARC_TLS_GD_CALL
3675 BFD_RELOC_ARC_TLS_IE_GOT
3677 BFD_RELOC_ARC_TLS_DTPOFF
3679 BFD_RELOC_ARC_TLS_DTPOFF_S9
3681 BFD_RELOC_ARC_TLS_LE_S9
3683 BFD_RELOC_ARC_TLS_LE_32
3685 BFD_RELOC_ARC_S25W_PCREL_PLT
3687 BFD_RELOC_ARC_S21H_PCREL_PLT
3689 BFD_RELOC_ARC_NPS_CMEM16
3694 BFD_RELOC_BFIN_16_IMM
3696 ADI Blackfin 16 bit immediate absolute reloc.
3698 BFD_RELOC_BFIN_16_HIGH
3700 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3702 BFD_RELOC_BFIN_4_PCREL
3704 ADI Blackfin 'a' part of LSETUP.
3706 BFD_RELOC_BFIN_5_PCREL
3710 BFD_RELOC_BFIN_16_LOW
3712 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3714 BFD_RELOC_BFIN_10_PCREL
3718 BFD_RELOC_BFIN_11_PCREL
3720 ADI Blackfin 'b' part of LSETUP.
3722 BFD_RELOC_BFIN_12_PCREL_JUMP
3726 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3728 ADI Blackfin Short jump, pcrel.
3730 BFD_RELOC_BFIN_24_PCREL_CALL_X
3732 ADI Blackfin Call.x not implemented.
3734 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3736 ADI Blackfin Long Jump pcrel.
3738 BFD_RELOC_BFIN_GOT17M4
3740 BFD_RELOC_BFIN_GOTHI
3742 BFD_RELOC_BFIN_GOTLO
3744 BFD_RELOC_BFIN_FUNCDESC
3746 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3748 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3750 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3752 BFD_RELOC_BFIN_FUNCDESC_VALUE
3754 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3756 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3758 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3760 BFD_RELOC_BFIN_GOTOFF17M4
3762 BFD_RELOC_BFIN_GOTOFFHI
3764 BFD_RELOC_BFIN_GOTOFFLO
3766 ADI Blackfin FD-PIC relocations.
3770 ADI Blackfin GOT relocation.
3772 BFD_RELOC_BFIN_PLTPC
3774 ADI Blackfin PLTPC relocation.
3776 BFD_ARELOC_BFIN_PUSH
3778 ADI Blackfin arithmetic relocation.
3780 BFD_ARELOC_BFIN_CONST
3782 ADI Blackfin arithmetic relocation.
3786 ADI Blackfin arithmetic relocation.
3790 ADI Blackfin arithmetic relocation.
3792 BFD_ARELOC_BFIN_MULT
3794 ADI Blackfin arithmetic relocation.
3798 ADI Blackfin arithmetic relocation.
3802 ADI Blackfin arithmetic relocation.
3804 BFD_ARELOC_BFIN_LSHIFT
3806 ADI Blackfin arithmetic relocation.
3808 BFD_ARELOC_BFIN_RSHIFT
3810 ADI Blackfin arithmetic relocation.
3814 ADI Blackfin arithmetic relocation.
3818 ADI Blackfin arithmetic relocation.
3822 ADI Blackfin arithmetic relocation.
3824 BFD_ARELOC_BFIN_LAND
3826 ADI Blackfin arithmetic relocation.
3830 ADI Blackfin arithmetic relocation.
3834 ADI Blackfin arithmetic relocation.
3838 ADI Blackfin arithmetic relocation.
3840 BFD_ARELOC_BFIN_COMP
3842 ADI Blackfin arithmetic relocation.
3844 BFD_ARELOC_BFIN_PAGE
3846 ADI Blackfin arithmetic relocation.
3848 BFD_ARELOC_BFIN_HWPAGE
3850 ADI Blackfin arithmetic relocation.
3852 BFD_ARELOC_BFIN_ADDR
3854 ADI Blackfin arithmetic relocation.
3857 BFD_RELOC_D10V_10_PCREL_R
3859 Mitsubishi D10V relocs.
3860 This is a 10-bit reloc with the right 2 bits
3863 BFD_RELOC_D10V_10_PCREL_L
3865 Mitsubishi D10V relocs.
3866 This is a 10-bit reloc with the right 2 bits
3867 assumed to be 0. This is the same as the previous reloc
3868 except it is in the left container, i.e.,
3869 shifted left 15 bits.
3873 This is an 18-bit reloc with the right 2 bits
3876 BFD_RELOC_D10V_18_PCREL
3878 This is an 18-bit reloc with the right 2 bits
3884 Mitsubishi D30V relocs.
3885 This is a 6-bit absolute reloc.
3887 BFD_RELOC_D30V_9_PCREL
3889 This is a 6-bit pc-relative reloc with
3890 the right 3 bits assumed to be 0.
3892 BFD_RELOC_D30V_9_PCREL_R
3894 This is a 6-bit pc-relative reloc with
3895 the right 3 bits assumed to be 0. Same
3896 as the previous reloc but on the right side
3901 This is a 12-bit absolute reloc with the
3902 right 3 bitsassumed to be 0.
3904 BFD_RELOC_D30V_15_PCREL
3906 This is a 12-bit pc-relative reloc with
3907 the right 3 bits assumed to be 0.
3909 BFD_RELOC_D30V_15_PCREL_R
3911 This is a 12-bit pc-relative reloc with
3912 the right 3 bits assumed to be 0. Same
3913 as the previous reloc but on the right side
3918 This is an 18-bit absolute reloc with
3919 the right 3 bits assumed to be 0.
3921 BFD_RELOC_D30V_21_PCREL
3923 This is an 18-bit pc-relative reloc with
3924 the right 3 bits assumed to be 0.
3926 BFD_RELOC_D30V_21_PCREL_R
3928 This is an 18-bit pc-relative reloc with
3929 the right 3 bits assumed to be 0. Same
3930 as the previous reloc but on the right side
3935 This is a 32-bit absolute reloc.
3937 BFD_RELOC_D30V_32_PCREL
3939 This is a 32-bit pc-relative reloc.
3942 BFD_RELOC_DLX_HI16_S
3957 BFD_RELOC_M32C_RL_JUMP
3959 BFD_RELOC_M32C_RL_1ADDR
3961 BFD_RELOC_M32C_RL_2ADDR
3963 Renesas M16C/M32C Relocations.
3968 Renesas M32R (formerly Mitsubishi M32R) relocs.
3969 This is a 24 bit absolute address.
3971 BFD_RELOC_M32R_10_PCREL
3973 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3975 BFD_RELOC_M32R_18_PCREL
3977 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3979 BFD_RELOC_M32R_26_PCREL
3981 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3983 BFD_RELOC_M32R_HI16_ULO
3985 This is a 16-bit reloc containing the high 16 bits of an address
3986 used when the lower 16 bits are treated as unsigned.
3988 BFD_RELOC_M32R_HI16_SLO
3990 This is a 16-bit reloc containing the high 16 bits of an address
3991 used when the lower 16 bits are treated as signed.
3995 This is a 16-bit reloc containing the lower 16 bits of an address.
3997 BFD_RELOC_M32R_SDA16
3999 This is a 16-bit reloc containing the small data area offset for use in
4000 add3, load, and store instructions.
4002 BFD_RELOC_M32R_GOT24
4004 BFD_RELOC_M32R_26_PLTREL
4008 BFD_RELOC_M32R_GLOB_DAT
4010 BFD_RELOC_M32R_JMP_SLOT
4012 BFD_RELOC_M32R_RELATIVE
4014 BFD_RELOC_M32R_GOTOFF
4016 BFD_RELOC_M32R_GOTOFF_HI_ULO
4018 BFD_RELOC_M32R_GOTOFF_HI_SLO
4020 BFD_RELOC_M32R_GOTOFF_LO
4022 BFD_RELOC_M32R_GOTPC24
4024 BFD_RELOC_M32R_GOT16_HI_ULO
4026 BFD_RELOC_M32R_GOT16_HI_SLO
4028 BFD_RELOC_M32R_GOT16_LO
4030 BFD_RELOC_M32R_GOTPC_HI_ULO
4032 BFD_RELOC_M32R_GOTPC_HI_SLO
4034 BFD_RELOC_M32R_GOTPC_LO
4043 This is a 20 bit absolute address.
4045 BFD_RELOC_NDS32_9_PCREL
4047 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4049 BFD_RELOC_NDS32_WORD_9_PCREL
4051 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4053 BFD_RELOC_NDS32_15_PCREL
4055 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4057 BFD_RELOC_NDS32_17_PCREL
4059 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4061 BFD_RELOC_NDS32_25_PCREL
4063 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4065 BFD_RELOC_NDS32_HI20
4067 This is a 20-bit reloc containing the high 20 bits of an address
4068 used with the lower 12 bits
4070 BFD_RELOC_NDS32_LO12S3
4072 This is a 12-bit reloc containing the lower 12 bits of an address
4073 then shift right by 3. This is used with ldi,sdi...
4075 BFD_RELOC_NDS32_LO12S2
4077 This is a 12-bit reloc containing the lower 12 bits of an address
4078 then shift left by 2. This is used with lwi,swi...
4080 BFD_RELOC_NDS32_LO12S1
4082 This is a 12-bit reloc containing the lower 12 bits of an address
4083 then shift left by 1. This is used with lhi,shi...
4085 BFD_RELOC_NDS32_LO12S0
4087 This is a 12-bit reloc containing the lower 12 bits of an address
4088 then shift left by 0. This is used with lbisbi...
4090 BFD_RELOC_NDS32_LO12S0_ORI
4092 This is a 12-bit reloc containing the lower 12 bits of an address
4093 then shift left by 0. This is only used with branch relaxations
4095 BFD_RELOC_NDS32_SDA15S3
4097 This is a 15-bit reloc containing the small data area 18-bit signed offset
4098 and shift left by 3 for use in ldi, sdi...
4100 BFD_RELOC_NDS32_SDA15S2
4102 This is a 15-bit reloc containing the small data area 17-bit signed offset
4103 and shift left by 2 for use in lwi, swi...
4105 BFD_RELOC_NDS32_SDA15S1
4107 This is a 15-bit reloc containing the small data area 16-bit signed offset
4108 and shift left by 1 for use in lhi, shi...
4110 BFD_RELOC_NDS32_SDA15S0
4112 This is a 15-bit reloc containing the small data area 15-bit signed offset
4113 and shift left by 0 for use in lbi, sbi...
4115 BFD_RELOC_NDS32_SDA16S3
4117 This is a 16-bit reloc containing the small data area 16-bit signed offset
4120 BFD_RELOC_NDS32_SDA17S2
4122 This is a 17-bit reloc containing the small data area 17-bit signed offset
4123 and shift left by 2 for use in lwi.gp, swi.gp...
4125 BFD_RELOC_NDS32_SDA18S1
4127 This is a 18-bit reloc containing the small data area 18-bit signed offset
4128 and shift left by 1 for use in lhi.gp, shi.gp...
4130 BFD_RELOC_NDS32_SDA19S0
4132 This is a 19-bit reloc containing the small data area 19-bit signed offset
4133 and shift left by 0 for use in lbi.gp, sbi.gp...
4135 BFD_RELOC_NDS32_GOT20
4137 BFD_RELOC_NDS32_9_PLTREL
4139 BFD_RELOC_NDS32_25_PLTREL
4141 BFD_RELOC_NDS32_COPY
4143 BFD_RELOC_NDS32_GLOB_DAT
4145 BFD_RELOC_NDS32_JMP_SLOT
4147 BFD_RELOC_NDS32_RELATIVE
4149 BFD_RELOC_NDS32_GOTOFF
4151 BFD_RELOC_NDS32_GOTOFF_HI20
4153 BFD_RELOC_NDS32_GOTOFF_LO12
4155 BFD_RELOC_NDS32_GOTPC20
4157 BFD_RELOC_NDS32_GOT_HI20
4159 BFD_RELOC_NDS32_GOT_LO12
4161 BFD_RELOC_NDS32_GOTPC_HI20
4163 BFD_RELOC_NDS32_GOTPC_LO12
4167 BFD_RELOC_NDS32_INSN16
4169 BFD_RELOC_NDS32_LABEL
4171 BFD_RELOC_NDS32_LONGCALL1
4173 BFD_RELOC_NDS32_LONGCALL2
4175 BFD_RELOC_NDS32_LONGCALL3
4177 BFD_RELOC_NDS32_LONGJUMP1
4179 BFD_RELOC_NDS32_LONGJUMP2
4181 BFD_RELOC_NDS32_LONGJUMP3
4183 BFD_RELOC_NDS32_LOADSTORE
4185 BFD_RELOC_NDS32_9_FIXED
4187 BFD_RELOC_NDS32_15_FIXED
4189 BFD_RELOC_NDS32_17_FIXED
4191 BFD_RELOC_NDS32_25_FIXED
4193 BFD_RELOC_NDS32_LONGCALL4
4195 BFD_RELOC_NDS32_LONGCALL5
4197 BFD_RELOC_NDS32_LONGCALL6
4199 BFD_RELOC_NDS32_LONGJUMP4
4201 BFD_RELOC_NDS32_LONGJUMP5
4203 BFD_RELOC_NDS32_LONGJUMP6
4205 BFD_RELOC_NDS32_LONGJUMP7
4209 BFD_RELOC_NDS32_PLTREL_HI20
4211 BFD_RELOC_NDS32_PLTREL_LO12
4213 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4215 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4219 BFD_RELOC_NDS32_SDA12S2_DP
4221 BFD_RELOC_NDS32_SDA12S2_SP
4223 BFD_RELOC_NDS32_LO12S2_DP
4225 BFD_RELOC_NDS32_LO12S2_SP
4229 BFD_RELOC_NDS32_DWARF2_OP1
4231 BFD_RELOC_NDS32_DWARF2_OP2
4233 BFD_RELOC_NDS32_DWARF2_LEB
4235 for dwarf2 debug_line.
4237 BFD_RELOC_NDS32_UPDATE_TA
4239 for eliminate 16-bit instructions
4241 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4243 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4245 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4247 BFD_RELOC_NDS32_GOT_LO15
4249 BFD_RELOC_NDS32_GOT_LO19
4251 BFD_RELOC_NDS32_GOTOFF_LO15
4253 BFD_RELOC_NDS32_GOTOFF_LO19
4255 BFD_RELOC_NDS32_GOT15S2
4257 BFD_RELOC_NDS32_GOT17S2
4259 for PIC object relaxation
4264 This is a 5 bit absolute address.
4266 BFD_RELOC_NDS32_10_UPCREL
4268 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4270 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4272 If fp were omitted, fp can used as another gp.
4274 BFD_RELOC_NDS32_RELAX_ENTRY
4276 BFD_RELOC_NDS32_GOT_SUFF
4278 BFD_RELOC_NDS32_GOTOFF_SUFF
4280 BFD_RELOC_NDS32_PLT_GOT_SUFF
4282 BFD_RELOC_NDS32_MULCALL_SUFF
4286 BFD_RELOC_NDS32_PTR_COUNT
4288 BFD_RELOC_NDS32_PTR_RESOLVED
4290 BFD_RELOC_NDS32_PLTBLOCK
4292 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4294 BFD_RELOC_NDS32_RELAX_REGION_END
4296 BFD_RELOC_NDS32_MINUEND
4298 BFD_RELOC_NDS32_SUBTRAHEND
4300 BFD_RELOC_NDS32_DIFF8
4302 BFD_RELOC_NDS32_DIFF16
4304 BFD_RELOC_NDS32_DIFF32
4306 BFD_RELOC_NDS32_DIFF_ULEB128
4308 BFD_RELOC_NDS32_EMPTY
4310 relaxation relative relocation types
4312 BFD_RELOC_NDS32_25_ABS
4314 This is a 25 bit absolute address.
4316 BFD_RELOC_NDS32_DATA
4318 BFD_RELOC_NDS32_TRAN
4320 BFD_RELOC_NDS32_17IFC_PCREL
4322 BFD_RELOC_NDS32_10IFCU_PCREL
4324 For ex9 and ifc using.
4326 BFD_RELOC_NDS32_TPOFF
4328 BFD_RELOC_NDS32_TLS_LE_HI20
4330 BFD_RELOC_NDS32_TLS_LE_LO12
4332 BFD_RELOC_NDS32_TLS_LE_ADD
4334 BFD_RELOC_NDS32_TLS_LE_LS
4336 BFD_RELOC_NDS32_GOTTPOFF
4338 BFD_RELOC_NDS32_TLS_IE_HI20
4340 BFD_RELOC_NDS32_TLS_IE_LO12S2
4342 BFD_RELOC_NDS32_TLS_TPOFF
4344 BFD_RELOC_NDS32_TLS_LE_20
4346 BFD_RELOC_NDS32_TLS_LE_15S0
4348 BFD_RELOC_NDS32_TLS_LE_15S1
4350 BFD_RELOC_NDS32_TLS_LE_15S2
4356 BFD_RELOC_V850_9_PCREL
4358 This is a 9-bit reloc
4360 BFD_RELOC_V850_22_PCREL
4362 This is a 22-bit reloc
4365 BFD_RELOC_V850_SDA_16_16_OFFSET
4367 This is a 16 bit offset from the short data area pointer.
4369 BFD_RELOC_V850_SDA_15_16_OFFSET
4371 This is a 16 bit offset (of which only 15 bits are used) from the
4372 short data area pointer.
4374 BFD_RELOC_V850_ZDA_16_16_OFFSET
4376 This is a 16 bit offset from the zero data area pointer.
4378 BFD_RELOC_V850_ZDA_15_16_OFFSET
4380 This is a 16 bit offset (of which only 15 bits are used) from the
4381 zero data area pointer.
4383 BFD_RELOC_V850_TDA_6_8_OFFSET
4385 This is an 8 bit offset (of which only 6 bits are used) from the
4386 tiny data area pointer.
4388 BFD_RELOC_V850_TDA_7_8_OFFSET
4390 This is an 8bit offset (of which only 7 bits are used) from the tiny
4393 BFD_RELOC_V850_TDA_7_7_OFFSET
4395 This is a 7 bit offset from the tiny data area pointer.
4397 BFD_RELOC_V850_TDA_16_16_OFFSET
4399 This is a 16 bit offset from the tiny data area pointer.
4402 BFD_RELOC_V850_TDA_4_5_OFFSET
4404 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4407 BFD_RELOC_V850_TDA_4_4_OFFSET
4409 This is a 4 bit offset from the tiny data area pointer.
4411 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4413 This is a 16 bit offset from the short data area pointer, with the
4414 bits placed non-contiguously in the instruction.
4416 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4418 This is a 16 bit offset from the zero data area pointer, with the
4419 bits placed non-contiguously in the instruction.
4421 BFD_RELOC_V850_CALLT_6_7_OFFSET
4423 This is a 6 bit offset from the call table base pointer.
4425 BFD_RELOC_V850_CALLT_16_16_OFFSET
4427 This is a 16 bit offset from the call table base pointer.
4429 BFD_RELOC_V850_LONGCALL
4431 Used for relaxing indirect function calls.
4433 BFD_RELOC_V850_LONGJUMP
4435 Used for relaxing indirect jumps.
4437 BFD_RELOC_V850_ALIGN
4439 Used to maintain alignment whilst relaxing.
4441 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4443 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4446 BFD_RELOC_V850_16_PCREL
4448 This is a 16-bit reloc.
4450 BFD_RELOC_V850_17_PCREL
4452 This is a 17-bit reloc.
4456 This is a 23-bit reloc.
4458 BFD_RELOC_V850_32_PCREL
4460 This is a 32-bit reloc.
4462 BFD_RELOC_V850_32_ABS
4464 This is a 32-bit reloc.
4466 BFD_RELOC_V850_16_SPLIT_OFFSET
4468 This is a 16-bit reloc.
4470 BFD_RELOC_V850_16_S1
4472 This is a 16-bit reloc.
4474 BFD_RELOC_V850_LO16_S1
4476 Low 16 bits. 16 bit shifted by 1.
4478 BFD_RELOC_V850_CALLT_15_16_OFFSET
4480 This is a 16 bit offset from the call table base pointer.
4482 BFD_RELOC_V850_32_GOTPCREL
4486 BFD_RELOC_V850_16_GOT
4490 BFD_RELOC_V850_32_GOT
4494 BFD_RELOC_V850_22_PLT_PCREL
4498 BFD_RELOC_V850_32_PLT_PCREL
4506 BFD_RELOC_V850_GLOB_DAT
4510 BFD_RELOC_V850_JMP_SLOT
4514 BFD_RELOC_V850_RELATIVE
4518 BFD_RELOC_V850_16_GOTOFF
4522 BFD_RELOC_V850_32_GOTOFF
4537 This is a 8bit DP reloc for the tms320c30, where the most
4538 significant 8 bits of a 24 bit word are placed into the least
4539 significant 8 bits of the opcode.
4542 BFD_RELOC_TIC54X_PARTLS7
4544 This is a 7bit reloc for the tms320c54x, where the least
4545 significant 7 bits of a 16 bit word are placed into the least
4546 significant 7 bits of the opcode.
4549 BFD_RELOC_TIC54X_PARTMS9
4551 This is a 9bit DP reloc for the tms320c54x, where the most
4552 significant 9 bits of a 16 bit word are placed into the least
4553 significant 9 bits of the opcode.
4558 This is an extended address 23-bit reloc for the tms320c54x.
4561 BFD_RELOC_TIC54X_16_OF_23
4563 This is a 16-bit reloc for the tms320c54x, where the least
4564 significant 16 bits of a 23-bit extended address are placed into
4568 BFD_RELOC_TIC54X_MS7_OF_23
4570 This is a reloc for the tms320c54x, where the most
4571 significant 7 bits of a 23-bit extended address are placed into
4575 BFD_RELOC_C6000_PCR_S21
4577 BFD_RELOC_C6000_PCR_S12
4579 BFD_RELOC_C6000_PCR_S10
4581 BFD_RELOC_C6000_PCR_S7
4583 BFD_RELOC_C6000_ABS_S16
4585 BFD_RELOC_C6000_ABS_L16
4587 BFD_RELOC_C6000_ABS_H16
4589 BFD_RELOC_C6000_SBR_U15_B
4591 BFD_RELOC_C6000_SBR_U15_H
4593 BFD_RELOC_C6000_SBR_U15_W
4595 BFD_RELOC_C6000_SBR_S16
4597 BFD_RELOC_C6000_SBR_L16_B
4599 BFD_RELOC_C6000_SBR_L16_H
4601 BFD_RELOC_C6000_SBR_L16_W
4603 BFD_RELOC_C6000_SBR_H16_B
4605 BFD_RELOC_C6000_SBR_H16_H
4607 BFD_RELOC_C6000_SBR_H16_W
4609 BFD_RELOC_C6000_SBR_GOT_U15_W
4611 BFD_RELOC_C6000_SBR_GOT_L16_W
4613 BFD_RELOC_C6000_SBR_GOT_H16_W
4615 BFD_RELOC_C6000_DSBT_INDEX
4617 BFD_RELOC_C6000_PREL31
4619 BFD_RELOC_C6000_COPY
4621 BFD_RELOC_C6000_JUMP_SLOT
4623 BFD_RELOC_C6000_EHTYPE
4625 BFD_RELOC_C6000_PCR_H16
4627 BFD_RELOC_C6000_PCR_L16
4629 BFD_RELOC_C6000_ALIGN
4631 BFD_RELOC_C6000_FPHEAD
4633 BFD_RELOC_C6000_NOCMP
4635 TMS320C6000 relocations.
4640 This is a 48 bit reloc for the FR30 that stores 32 bits.
4644 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4647 BFD_RELOC_FR30_6_IN_4
4649 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4652 BFD_RELOC_FR30_8_IN_8
4654 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4657 BFD_RELOC_FR30_9_IN_8
4659 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4662 BFD_RELOC_FR30_10_IN_8
4664 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4667 BFD_RELOC_FR30_9_PCREL
4669 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4670 short offset into 8 bits.
4672 BFD_RELOC_FR30_12_PCREL
4674 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4675 short offset into 11 bits.
4678 BFD_RELOC_MCORE_PCREL_IMM8BY4
4680 BFD_RELOC_MCORE_PCREL_IMM11BY2
4682 BFD_RELOC_MCORE_PCREL_IMM4BY2
4684 BFD_RELOC_MCORE_PCREL_32
4686 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4690 Motorola Mcore relocations.
4699 BFD_RELOC_MEP_PCREL8A2
4701 BFD_RELOC_MEP_PCREL12A2
4703 BFD_RELOC_MEP_PCREL17A2
4705 BFD_RELOC_MEP_PCREL24A2
4707 BFD_RELOC_MEP_PCABS24A2
4719 BFD_RELOC_MEP_TPREL7
4721 BFD_RELOC_MEP_TPREL7A2
4723 BFD_RELOC_MEP_TPREL7A4
4725 BFD_RELOC_MEP_UIMM24
4727 BFD_RELOC_MEP_ADDR24A4
4729 BFD_RELOC_MEP_GNU_VTINHERIT
4731 BFD_RELOC_MEP_GNU_VTENTRY
4733 Toshiba Media Processor Relocations.
4737 BFD_RELOC_METAG_HIADDR16
4739 BFD_RELOC_METAG_LOADDR16
4741 BFD_RELOC_METAG_RELBRANCH
4743 BFD_RELOC_METAG_GETSETOFF
4745 BFD_RELOC_METAG_HIOG
4747 BFD_RELOC_METAG_LOOG
4749 BFD_RELOC_METAG_REL8
4751 BFD_RELOC_METAG_REL16
4753 BFD_RELOC_METAG_HI16_GOTOFF
4755 BFD_RELOC_METAG_LO16_GOTOFF
4757 BFD_RELOC_METAG_GETSET_GOTOFF
4759 BFD_RELOC_METAG_GETSET_GOT
4761 BFD_RELOC_METAG_HI16_GOTPC
4763 BFD_RELOC_METAG_LO16_GOTPC
4765 BFD_RELOC_METAG_HI16_PLT
4767 BFD_RELOC_METAG_LO16_PLT
4769 BFD_RELOC_METAG_RELBRANCH_PLT
4771 BFD_RELOC_METAG_GOTOFF
4775 BFD_RELOC_METAG_COPY
4777 BFD_RELOC_METAG_JMP_SLOT
4779 BFD_RELOC_METAG_RELATIVE
4781 BFD_RELOC_METAG_GLOB_DAT
4783 BFD_RELOC_METAG_TLS_GD
4785 BFD_RELOC_METAG_TLS_LDM
4787 BFD_RELOC_METAG_TLS_LDO_HI16
4789 BFD_RELOC_METAG_TLS_LDO_LO16
4791 BFD_RELOC_METAG_TLS_LDO
4793 BFD_RELOC_METAG_TLS_IE
4795 BFD_RELOC_METAG_TLS_IENONPIC
4797 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4799 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4801 BFD_RELOC_METAG_TLS_TPOFF
4803 BFD_RELOC_METAG_TLS_DTPMOD
4805 BFD_RELOC_METAG_TLS_DTPOFF
4807 BFD_RELOC_METAG_TLS_LE
4809 BFD_RELOC_METAG_TLS_LE_HI16
4811 BFD_RELOC_METAG_TLS_LE_LO16
4813 Imagination Technologies Meta relocations.
4818 BFD_RELOC_MMIX_GETA_1
4820 BFD_RELOC_MMIX_GETA_2
4822 BFD_RELOC_MMIX_GETA_3
4824 These are relocations for the GETA instruction.
4826 BFD_RELOC_MMIX_CBRANCH
4828 BFD_RELOC_MMIX_CBRANCH_J
4830 BFD_RELOC_MMIX_CBRANCH_1
4832 BFD_RELOC_MMIX_CBRANCH_2
4834 BFD_RELOC_MMIX_CBRANCH_3
4836 These are relocations for a conditional branch instruction.
4838 BFD_RELOC_MMIX_PUSHJ
4840 BFD_RELOC_MMIX_PUSHJ_1
4842 BFD_RELOC_MMIX_PUSHJ_2
4844 BFD_RELOC_MMIX_PUSHJ_3
4846 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4848 These are relocations for the PUSHJ instruction.
4852 BFD_RELOC_MMIX_JMP_1
4854 BFD_RELOC_MMIX_JMP_2
4856 BFD_RELOC_MMIX_JMP_3
4858 These are relocations for the JMP instruction.
4860 BFD_RELOC_MMIX_ADDR19
4862 This is a relocation for a relative address as in a GETA instruction or
4865 BFD_RELOC_MMIX_ADDR27
4867 This is a relocation for a relative address as in a JMP instruction.
4869 BFD_RELOC_MMIX_REG_OR_BYTE
4871 This is a relocation for an instruction field that may be a general
4872 register or a value 0..255.
4876 This is a relocation for an instruction field that may be a general
4879 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4881 This is a relocation for two instruction fields holding a register and
4882 an offset, the equivalent of the relocation.
4884 BFD_RELOC_MMIX_LOCAL
4886 This relocation is an assertion that the expression is not allocated as
4887 a global register. It does not modify contents.
4890 BFD_RELOC_AVR_7_PCREL
4892 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4893 short offset into 7 bits.
4895 BFD_RELOC_AVR_13_PCREL
4897 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4898 short offset into 12 bits.
4902 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4903 program memory address) into 16 bits.
4905 BFD_RELOC_AVR_LO8_LDI
4907 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4908 data memory address) into 8 bit immediate value of LDI insn.
4910 BFD_RELOC_AVR_HI8_LDI
4912 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4913 of data memory address) into 8 bit immediate value of LDI insn.
4915 BFD_RELOC_AVR_HH8_LDI
4917 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4918 of program memory address) into 8 bit immediate value of LDI insn.
4920 BFD_RELOC_AVR_MS8_LDI
4922 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4923 of 32 bit value) into 8 bit immediate value of LDI insn.
4925 BFD_RELOC_AVR_LO8_LDI_NEG
4927 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4928 (usually data memory address) into 8 bit immediate value of SUBI insn.
4930 BFD_RELOC_AVR_HI8_LDI_NEG
4932 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4933 (high 8 bit of data memory address) into 8 bit immediate value of
4936 BFD_RELOC_AVR_HH8_LDI_NEG
4938 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4939 (most high 8 bit of program memory address) into 8 bit immediate value
4940 of LDI or SUBI insn.
4942 BFD_RELOC_AVR_MS8_LDI_NEG
4944 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4945 of 32 bit value) into 8 bit immediate value of LDI insn.
4947 BFD_RELOC_AVR_LO8_LDI_PM
4949 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4950 command address) into 8 bit immediate value of LDI insn.
4952 BFD_RELOC_AVR_LO8_LDI_GS
4954 This is a 16 bit reloc for the AVR that stores 8 bit value
4955 (command address) into 8 bit immediate value of LDI insn. If the address
4956 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4959 BFD_RELOC_AVR_HI8_LDI_PM
4961 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4962 of command address) into 8 bit immediate value of LDI insn.
4964 BFD_RELOC_AVR_HI8_LDI_GS
4966 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4967 of command address) into 8 bit immediate value of LDI insn. If the address
4968 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4971 BFD_RELOC_AVR_HH8_LDI_PM
4973 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4974 of command address) into 8 bit immediate value of LDI insn.
4976 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4978 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4979 (usually command address) into 8 bit immediate value of SUBI insn.
4981 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4983 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4984 (high 8 bit of 16 bit command address) into 8 bit immediate value
4987 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4989 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4990 (high 6 bit of 22 bit command address) into 8 bit immediate
4995 This is a 32 bit reloc for the AVR that stores 23 bit value
5000 This is a 16 bit reloc for the AVR that stores all needed bits
5001 for absolute addressing with ldi with overflow check to linktime
5005 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5008 BFD_RELOC_AVR_6_ADIW
5010 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5015 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5016 in .byte lo8(symbol)
5020 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5021 in .byte hi8(symbol)
5025 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5026 in .byte hlo8(symbol)
5030 BFD_RELOC_AVR_DIFF16
5032 BFD_RELOC_AVR_DIFF32
5034 AVR relocations to mark the difference of two local symbols.
5035 These are only needed to support linker relaxation and can be ignored
5036 when not relaxing. The field is set to the value of the difference
5037 assuming no relaxation. The relocation encodes the position of the
5038 second symbol so the linker can determine whether to adjust the field
5041 BFD_RELOC_AVR_LDS_STS_16
5043 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5044 lds and sts instructions supported only tiny core.
5048 This is a 6 bit reloc for the AVR that stores an I/O register
5049 number for the IN and OUT instructions
5053 This is a 5 bit reloc for the AVR that stores an I/O register
5054 number for the SBIC, SBIS, SBI and CBI instructions
5057 BFD_RELOC_RISCV_HI20
5059 BFD_RELOC_RISCV_PCREL_HI20
5061 BFD_RELOC_RISCV_PCREL_LO12_I
5063 BFD_RELOC_RISCV_PCREL_LO12_S
5065 BFD_RELOC_RISCV_LO12_I
5067 BFD_RELOC_RISCV_LO12_S
5069 BFD_RELOC_RISCV_GPREL12_I
5071 BFD_RELOC_RISCV_GPREL12_S
5073 BFD_RELOC_RISCV_TPREL_HI20
5075 BFD_RELOC_RISCV_TPREL_LO12_I
5077 BFD_RELOC_RISCV_TPREL_LO12_S
5079 BFD_RELOC_RISCV_TPREL_ADD
5081 BFD_RELOC_RISCV_CALL
5083 BFD_RELOC_RISCV_CALL_PLT
5085 BFD_RELOC_RISCV_ADD8
5087 BFD_RELOC_RISCV_ADD16
5089 BFD_RELOC_RISCV_ADD32
5091 BFD_RELOC_RISCV_ADD64
5093 BFD_RELOC_RISCV_SUB8
5095 BFD_RELOC_RISCV_SUB16
5097 BFD_RELOC_RISCV_SUB32
5099 BFD_RELOC_RISCV_SUB64
5101 BFD_RELOC_RISCV_GOT_HI20
5103 BFD_RELOC_RISCV_TLS_GOT_HI20
5105 BFD_RELOC_RISCV_TLS_GD_HI20
5109 BFD_RELOC_RISCV_TLS_DTPMOD32
5111 BFD_RELOC_RISCV_TLS_DTPREL32
5113 BFD_RELOC_RISCV_TLS_DTPMOD64
5115 BFD_RELOC_RISCV_TLS_DTPREL64
5117 BFD_RELOC_RISCV_TLS_TPREL32
5119 BFD_RELOC_RISCV_TLS_TPREL64
5121 BFD_RELOC_RISCV_ALIGN
5123 BFD_RELOC_RISCV_RVC_BRANCH
5125 BFD_RELOC_RISCV_RVC_JUMP
5127 BFD_RELOC_RISCV_RVC_LUI
5129 BFD_RELOC_RISCV_GPREL_I
5131 BFD_RELOC_RISCV_GPREL_S
5133 BFD_RELOC_RISCV_TPREL_I
5135 BFD_RELOC_RISCV_TPREL_S
5137 BFD_RELOC_RISCV_RELAX
5141 BFD_RELOC_RISCV_SUB6
5143 BFD_RELOC_RISCV_SET6
5145 BFD_RELOC_RISCV_SET8
5147 BFD_RELOC_RISCV_SET16
5149 BFD_RELOC_RISCV_SET32
5156 BFD_RELOC_RL78_NEG16
5158 BFD_RELOC_RL78_NEG24
5160 BFD_RELOC_RL78_NEG32
5162 BFD_RELOC_RL78_16_OP
5164 BFD_RELOC_RL78_24_OP
5166 BFD_RELOC_RL78_32_OP
5174 BFD_RELOC_RL78_DIR3U_PCREL
5178 BFD_RELOC_RL78_GPRELB
5180 BFD_RELOC_RL78_GPRELW
5182 BFD_RELOC_RL78_GPRELL
5186 BFD_RELOC_RL78_OP_SUBTRACT
5188 BFD_RELOC_RL78_OP_NEG
5190 BFD_RELOC_RL78_OP_AND
5192 BFD_RELOC_RL78_OP_SHRA
5196 BFD_RELOC_RL78_ABS16
5198 BFD_RELOC_RL78_ABS16_REV
5200 BFD_RELOC_RL78_ABS32
5202 BFD_RELOC_RL78_ABS32_REV
5204 BFD_RELOC_RL78_ABS16U
5206 BFD_RELOC_RL78_ABS16UW
5208 BFD_RELOC_RL78_ABS16UL
5210 BFD_RELOC_RL78_RELAX
5220 BFD_RELOC_RL78_SADDR
5222 Renesas RL78 Relocations.
5245 BFD_RELOC_RX_DIR3U_PCREL
5257 BFD_RELOC_RX_OP_SUBTRACT
5265 BFD_RELOC_RX_ABS16_REV
5269 BFD_RELOC_RX_ABS32_REV
5273 BFD_RELOC_RX_ABS16UW
5275 BFD_RELOC_RX_ABS16UL
5279 Renesas RX Relocations.
5292 32 bit PC relative PLT address.
5296 Copy symbol at runtime.
5298 BFD_RELOC_390_GLOB_DAT
5302 BFD_RELOC_390_JMP_SLOT
5306 BFD_RELOC_390_RELATIVE
5308 Adjust by program base.
5312 32 bit PC relative offset to GOT.
5318 BFD_RELOC_390_PC12DBL
5320 PC relative 12 bit shifted by 1.
5322 BFD_RELOC_390_PLT12DBL
5324 12 bit PC rel. PLT shifted by 1.
5326 BFD_RELOC_390_PC16DBL
5328 PC relative 16 bit shifted by 1.
5330 BFD_RELOC_390_PLT16DBL
5332 16 bit PC rel. PLT shifted by 1.
5334 BFD_RELOC_390_PC24DBL
5336 PC relative 24 bit shifted by 1.
5338 BFD_RELOC_390_PLT24DBL
5340 24 bit PC rel. PLT shifted by 1.
5342 BFD_RELOC_390_PC32DBL
5344 PC relative 32 bit shifted by 1.
5346 BFD_RELOC_390_PLT32DBL
5348 32 bit PC rel. PLT shifted by 1.
5350 BFD_RELOC_390_GOTPCDBL
5352 32 bit PC rel. GOT shifted by 1.
5360 64 bit PC relative PLT address.
5362 BFD_RELOC_390_GOTENT
5364 32 bit rel. offset to GOT entry.
5366 BFD_RELOC_390_GOTOFF64
5368 64 bit offset to GOT.
5370 BFD_RELOC_390_GOTPLT12
5372 12-bit offset to symbol-entry within GOT, with PLT handling.
5374 BFD_RELOC_390_GOTPLT16
5376 16-bit offset to symbol-entry within GOT, with PLT handling.
5378 BFD_RELOC_390_GOTPLT32
5380 32-bit offset to symbol-entry within GOT, with PLT handling.
5382 BFD_RELOC_390_GOTPLT64
5384 64-bit offset to symbol-entry within GOT, with PLT handling.
5386 BFD_RELOC_390_GOTPLTENT
5388 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5390 BFD_RELOC_390_PLTOFF16
5392 16-bit rel. offset from the GOT to a PLT entry.
5394 BFD_RELOC_390_PLTOFF32
5396 32-bit rel. offset from the GOT to a PLT entry.
5398 BFD_RELOC_390_PLTOFF64
5400 64-bit rel. offset from the GOT to a PLT entry.
5403 BFD_RELOC_390_TLS_LOAD
5405 BFD_RELOC_390_TLS_GDCALL
5407 BFD_RELOC_390_TLS_LDCALL
5409 BFD_RELOC_390_TLS_GD32
5411 BFD_RELOC_390_TLS_GD64
5413 BFD_RELOC_390_TLS_GOTIE12
5415 BFD_RELOC_390_TLS_GOTIE32
5417 BFD_RELOC_390_TLS_GOTIE64
5419 BFD_RELOC_390_TLS_LDM32
5421 BFD_RELOC_390_TLS_LDM64
5423 BFD_RELOC_390_TLS_IE32
5425 BFD_RELOC_390_TLS_IE64
5427 BFD_RELOC_390_TLS_IEENT
5429 BFD_RELOC_390_TLS_LE32
5431 BFD_RELOC_390_TLS_LE64
5433 BFD_RELOC_390_TLS_LDO32
5435 BFD_RELOC_390_TLS_LDO64
5437 BFD_RELOC_390_TLS_DTPMOD
5439 BFD_RELOC_390_TLS_DTPOFF
5441 BFD_RELOC_390_TLS_TPOFF
5443 s390 tls relocations.
5450 BFD_RELOC_390_GOTPLT20
5452 BFD_RELOC_390_TLS_GOTIE20
5454 Long displacement extension.
5457 BFD_RELOC_390_IRELATIVE
5459 STT_GNU_IFUNC relocation.
5462 BFD_RELOC_SCORE_GPREL15
5465 Low 16 bit for load/store
5467 BFD_RELOC_SCORE_DUMMY2
5471 This is a 24-bit reloc with the right 1 bit assumed to be 0
5473 BFD_RELOC_SCORE_BRANCH
5475 This is a 19-bit reloc with the right 1 bit assumed to be 0
5477 BFD_RELOC_SCORE_IMM30
5479 This is a 32-bit reloc for 48-bit instructions.
5481 BFD_RELOC_SCORE_IMM32
5483 This is a 32-bit reloc for 48-bit instructions.
5485 BFD_RELOC_SCORE16_JMP
5487 This is a 11-bit reloc with the right 1 bit assumed to be 0
5489 BFD_RELOC_SCORE16_BRANCH
5491 This is a 8-bit reloc with the right 1 bit assumed to be 0
5493 BFD_RELOC_SCORE_BCMP
5495 This is a 9-bit reloc with the right 1 bit assumed to be 0
5497 BFD_RELOC_SCORE_GOT15
5499 BFD_RELOC_SCORE_GOT_LO16
5501 BFD_RELOC_SCORE_CALL15
5503 BFD_RELOC_SCORE_DUMMY_HI16
5505 Undocumented Score relocs
5510 Scenix IP2K - 9-bit register number / data address
5514 Scenix IP2K - 4-bit register/data bank number
5516 BFD_RELOC_IP2K_ADDR16CJP
5518 Scenix IP2K - low 13 bits of instruction word address
5520 BFD_RELOC_IP2K_PAGE3
5522 Scenix IP2K - high 3 bits of instruction word address
5524 BFD_RELOC_IP2K_LO8DATA
5526 BFD_RELOC_IP2K_HI8DATA
5528 BFD_RELOC_IP2K_EX8DATA
5530 Scenix IP2K - ext/low/high 8 bits of data address
5532 BFD_RELOC_IP2K_LO8INSN
5534 BFD_RELOC_IP2K_HI8INSN
5536 Scenix IP2K - low/high 8 bits of instruction word address
5538 BFD_RELOC_IP2K_PC_SKIP
5540 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5544 Scenix IP2K - 16 bit word address in text section.
5546 BFD_RELOC_IP2K_FR_OFFSET
5548 Scenix IP2K - 7-bit sp or dp offset
5550 BFD_RELOC_VPE4KMATH_DATA
5552 BFD_RELOC_VPE4KMATH_INSN
5554 Scenix VPE4K coprocessor - data/insn-space addressing
5557 BFD_RELOC_VTABLE_INHERIT
5559 BFD_RELOC_VTABLE_ENTRY
5561 These two relocations are used by the linker to determine which of
5562 the entries in a C++ virtual function table are actually used. When
5563 the --gc-sections option is given, the linker will zero out the entries
5564 that are not used, so that the code for those functions need not be
5565 included in the output.
5567 VTABLE_INHERIT is a zero-space relocation used to describe to the
5568 linker the inheritance tree of a C++ virtual function table. The
5569 relocation's symbol should be the parent class' vtable, and the
5570 relocation should be located at the child vtable.
5572 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5573 virtual function table entry. The reloc's symbol should refer to the
5574 table of the class mentioned in the code. Off of that base, an offset
5575 describes the entry that is being used. For Rela hosts, this offset
5576 is stored in the reloc's addend. For Rel hosts, we are forced to put
5577 this offset in the reloc's section offset.
5580 BFD_RELOC_IA64_IMM14
5582 BFD_RELOC_IA64_IMM22
5584 BFD_RELOC_IA64_IMM64
5586 BFD_RELOC_IA64_DIR32MSB
5588 BFD_RELOC_IA64_DIR32LSB
5590 BFD_RELOC_IA64_DIR64MSB
5592 BFD_RELOC_IA64_DIR64LSB
5594 BFD_RELOC_IA64_GPREL22
5596 BFD_RELOC_IA64_GPREL64I
5598 BFD_RELOC_IA64_GPREL32MSB
5600 BFD_RELOC_IA64_GPREL32LSB
5602 BFD_RELOC_IA64_GPREL64MSB
5604 BFD_RELOC_IA64_GPREL64LSB
5606 BFD_RELOC_IA64_LTOFF22
5608 BFD_RELOC_IA64_LTOFF64I
5610 BFD_RELOC_IA64_PLTOFF22
5612 BFD_RELOC_IA64_PLTOFF64I
5614 BFD_RELOC_IA64_PLTOFF64MSB
5616 BFD_RELOC_IA64_PLTOFF64LSB
5618 BFD_RELOC_IA64_FPTR64I
5620 BFD_RELOC_IA64_FPTR32MSB
5622 BFD_RELOC_IA64_FPTR32LSB
5624 BFD_RELOC_IA64_FPTR64MSB
5626 BFD_RELOC_IA64_FPTR64LSB
5628 BFD_RELOC_IA64_PCREL21B
5630 BFD_RELOC_IA64_PCREL21BI
5632 BFD_RELOC_IA64_PCREL21M
5634 BFD_RELOC_IA64_PCREL21F
5636 BFD_RELOC_IA64_PCREL22
5638 BFD_RELOC_IA64_PCREL60B
5640 BFD_RELOC_IA64_PCREL64I
5642 BFD_RELOC_IA64_PCREL32MSB
5644 BFD_RELOC_IA64_PCREL32LSB
5646 BFD_RELOC_IA64_PCREL64MSB
5648 BFD_RELOC_IA64_PCREL64LSB
5650 BFD_RELOC_IA64_LTOFF_FPTR22
5652 BFD_RELOC_IA64_LTOFF_FPTR64I
5654 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5656 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5658 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5660 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5662 BFD_RELOC_IA64_SEGREL32MSB
5664 BFD_RELOC_IA64_SEGREL32LSB
5666 BFD_RELOC_IA64_SEGREL64MSB
5668 BFD_RELOC_IA64_SEGREL64LSB
5670 BFD_RELOC_IA64_SECREL32MSB
5672 BFD_RELOC_IA64_SECREL32LSB
5674 BFD_RELOC_IA64_SECREL64MSB
5676 BFD_RELOC_IA64_SECREL64LSB
5678 BFD_RELOC_IA64_REL32MSB
5680 BFD_RELOC_IA64_REL32LSB
5682 BFD_RELOC_IA64_REL64MSB
5684 BFD_RELOC_IA64_REL64LSB
5686 BFD_RELOC_IA64_LTV32MSB
5688 BFD_RELOC_IA64_LTV32LSB
5690 BFD_RELOC_IA64_LTV64MSB
5692 BFD_RELOC_IA64_LTV64LSB
5694 BFD_RELOC_IA64_IPLTMSB
5696 BFD_RELOC_IA64_IPLTLSB
5700 BFD_RELOC_IA64_LTOFF22X
5702 BFD_RELOC_IA64_LDXMOV
5704 BFD_RELOC_IA64_TPREL14
5706 BFD_RELOC_IA64_TPREL22
5708 BFD_RELOC_IA64_TPREL64I
5710 BFD_RELOC_IA64_TPREL64MSB
5712 BFD_RELOC_IA64_TPREL64LSB
5714 BFD_RELOC_IA64_LTOFF_TPREL22
5716 BFD_RELOC_IA64_DTPMOD64MSB
5718 BFD_RELOC_IA64_DTPMOD64LSB
5720 BFD_RELOC_IA64_LTOFF_DTPMOD22
5722 BFD_RELOC_IA64_DTPREL14
5724 BFD_RELOC_IA64_DTPREL22
5726 BFD_RELOC_IA64_DTPREL64I
5728 BFD_RELOC_IA64_DTPREL32MSB
5730 BFD_RELOC_IA64_DTPREL32LSB
5732 BFD_RELOC_IA64_DTPREL64MSB
5734 BFD_RELOC_IA64_DTPREL64LSB
5736 BFD_RELOC_IA64_LTOFF_DTPREL22
5738 Intel IA64 Relocations.
5741 BFD_RELOC_M68HC11_HI8
5743 Motorola 68HC11 reloc.
5744 This is the 8 bit high part of an absolute address.
5746 BFD_RELOC_M68HC11_LO8
5748 Motorola 68HC11 reloc.
5749 This is the 8 bit low part of an absolute address.
5751 BFD_RELOC_M68HC11_3B
5753 Motorola 68HC11 reloc.
5754 This is the 3 bit of a value.
5756 BFD_RELOC_M68HC11_RL_JUMP
5758 Motorola 68HC11 reloc.
5759 This reloc marks the beginning of a jump/call instruction.
5760 It is used for linker relaxation to correctly identify beginning
5761 of instruction and change some branches to use PC-relative
5764 BFD_RELOC_M68HC11_RL_GROUP
5766 Motorola 68HC11 reloc.
5767 This reloc marks a group of several instructions that gcc generates
5768 and for which the linker relaxation pass can modify and/or remove
5771 BFD_RELOC_M68HC11_LO16
5773 Motorola 68HC11 reloc.
5774 This is the 16-bit lower part of an address. It is used for 'call'
5775 instruction to specify the symbol address without any special
5776 transformation (due to memory bank window).
5778 BFD_RELOC_M68HC11_PAGE
5780 Motorola 68HC11 reloc.
5781 This is a 8-bit reloc that specifies the page number of an address.
5782 It is used by 'call' instruction to specify the page number of
5785 BFD_RELOC_M68HC11_24
5787 Motorola 68HC11 reloc.
5788 This is a 24-bit reloc that represents the address with a 16-bit
5789 value and a 8-bit page number. The symbol address is transformed
5790 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5792 BFD_RELOC_M68HC12_5B
5794 Motorola 68HC12 reloc.
5795 This is the 5 bits of a value.
5797 BFD_RELOC_XGATE_RL_JUMP
5799 Freescale XGATE reloc.
5800 This reloc marks the beginning of a bra/jal instruction.
5802 BFD_RELOC_XGATE_RL_GROUP
5804 Freescale XGATE reloc.
5805 This reloc marks a group of several instructions that gcc generates
5806 and for which the linker relaxation pass can modify and/or remove
5809 BFD_RELOC_XGATE_LO16
5811 Freescale XGATE reloc.
5812 This is the 16-bit lower part of an address. It is used for the '16-bit'
5815 BFD_RELOC_XGATE_GPAGE
5817 Freescale XGATE reloc.
5821 Freescale XGATE reloc.
5823 BFD_RELOC_XGATE_PCREL_9
5825 Freescale XGATE reloc.
5826 This is a 9-bit pc-relative reloc.
5828 BFD_RELOC_XGATE_PCREL_10
5830 Freescale XGATE reloc.
5831 This is a 10-bit pc-relative reloc.
5833 BFD_RELOC_XGATE_IMM8_LO
5835 Freescale XGATE reloc.
5836 This is the 16-bit lower part of an address. It is used for the '16-bit'
5839 BFD_RELOC_XGATE_IMM8_HI
5841 Freescale XGATE reloc.
5842 This is the 16-bit higher part of an address. It is used for the '16-bit'
5845 BFD_RELOC_XGATE_IMM3
5847 Freescale XGATE reloc.
5848 This is a 3-bit pc-relative reloc.
5850 BFD_RELOC_XGATE_IMM4
5852 Freescale XGATE reloc.
5853 This is a 4-bit pc-relative reloc.
5855 BFD_RELOC_XGATE_IMM5
5857 Freescale XGATE reloc.
5858 This is a 5-bit pc-relative reloc.
5860 BFD_RELOC_M68HC12_9B
5862 Motorola 68HC12 reloc.
5863 This is the 9 bits of a value.
5865 BFD_RELOC_M68HC12_16B
5867 Motorola 68HC12 reloc.
5868 This is the 16 bits of a value.
5870 BFD_RELOC_M68HC12_9_PCREL
5872 Motorola 68HC12/XGATE reloc.
5873 This is a PCREL9 branch.
5875 BFD_RELOC_M68HC12_10_PCREL
5877 Motorola 68HC12/XGATE reloc.
5878 This is a PCREL10 branch.
5880 BFD_RELOC_M68HC12_LO8XG
5882 Motorola 68HC12/XGATE reloc.
5883 This is the 8 bit low part of an absolute address and immediately precedes
5884 a matching HI8XG part.
5886 BFD_RELOC_M68HC12_HI8XG
5888 Motorola 68HC12/XGATE reloc.
5889 This is the 8 bit high part of an absolute address and immediately follows
5890 a matching LO8XG part.
5894 BFD_RELOC_16C_NUM08_C
5898 BFD_RELOC_16C_NUM16_C
5902 BFD_RELOC_16C_NUM32_C
5904 BFD_RELOC_16C_DISP04
5906 BFD_RELOC_16C_DISP04_C
5908 BFD_RELOC_16C_DISP08
5910 BFD_RELOC_16C_DISP08_C
5912 BFD_RELOC_16C_DISP16
5914 BFD_RELOC_16C_DISP16_C
5916 BFD_RELOC_16C_DISP24
5918 BFD_RELOC_16C_DISP24_C
5920 BFD_RELOC_16C_DISP24a
5922 BFD_RELOC_16C_DISP24a_C
5926 BFD_RELOC_16C_REG04_C
5928 BFD_RELOC_16C_REG04a
5930 BFD_RELOC_16C_REG04a_C
5934 BFD_RELOC_16C_REG14_C
5938 BFD_RELOC_16C_REG16_C
5942 BFD_RELOC_16C_REG20_C
5946 BFD_RELOC_16C_ABS20_C
5950 BFD_RELOC_16C_ABS24_C
5954 BFD_RELOC_16C_IMM04_C
5958 BFD_RELOC_16C_IMM16_C
5962 BFD_RELOC_16C_IMM20_C
5966 BFD_RELOC_16C_IMM24_C
5970 BFD_RELOC_16C_IMM32_C
5972 NS CR16C Relocations.
5977 BFD_RELOC_CR16_NUM16
5979 BFD_RELOC_CR16_NUM32
5981 BFD_RELOC_CR16_NUM32a
5983 BFD_RELOC_CR16_REGREL0
5985 BFD_RELOC_CR16_REGREL4
5987 BFD_RELOC_CR16_REGREL4a
5989 BFD_RELOC_CR16_REGREL14
5991 BFD_RELOC_CR16_REGREL14a
5993 BFD_RELOC_CR16_REGREL16
5995 BFD_RELOC_CR16_REGREL20
5997 BFD_RELOC_CR16_REGREL20a
5999 BFD_RELOC_CR16_ABS20
6001 BFD_RELOC_CR16_ABS24
6007 BFD_RELOC_CR16_IMM16
6009 BFD_RELOC_CR16_IMM20
6011 BFD_RELOC_CR16_IMM24
6013 BFD_RELOC_CR16_IMM32
6015 BFD_RELOC_CR16_IMM32a
6017 BFD_RELOC_CR16_DISP4
6019 BFD_RELOC_CR16_DISP8
6021 BFD_RELOC_CR16_DISP16
6023 BFD_RELOC_CR16_DISP20
6025 BFD_RELOC_CR16_DISP24
6027 BFD_RELOC_CR16_DISP24a
6029 BFD_RELOC_CR16_SWITCH8
6031 BFD_RELOC_CR16_SWITCH16
6033 BFD_RELOC_CR16_SWITCH32
6035 BFD_RELOC_CR16_GOT_REGREL20
6037 BFD_RELOC_CR16_GOTC_REGREL20
6039 BFD_RELOC_CR16_GLOB_DAT
6041 NS CR16 Relocations.
6048 BFD_RELOC_CRX_REL8_CMP
6056 BFD_RELOC_CRX_REGREL12
6058 BFD_RELOC_CRX_REGREL22
6060 BFD_RELOC_CRX_REGREL28
6062 BFD_RELOC_CRX_REGREL32
6078 BFD_RELOC_CRX_SWITCH8
6080 BFD_RELOC_CRX_SWITCH16
6082 BFD_RELOC_CRX_SWITCH32
6087 BFD_RELOC_CRIS_BDISP8
6089 BFD_RELOC_CRIS_UNSIGNED_5
6091 BFD_RELOC_CRIS_SIGNED_6
6093 BFD_RELOC_CRIS_UNSIGNED_6
6095 BFD_RELOC_CRIS_SIGNED_8
6097 BFD_RELOC_CRIS_UNSIGNED_8
6099 BFD_RELOC_CRIS_SIGNED_16
6101 BFD_RELOC_CRIS_UNSIGNED_16
6103 BFD_RELOC_CRIS_LAPCQ_OFFSET
6105 BFD_RELOC_CRIS_UNSIGNED_4
6107 These relocs are only used within the CRIS assembler. They are not
6108 (at present) written to any object files.
6112 BFD_RELOC_CRIS_GLOB_DAT
6114 BFD_RELOC_CRIS_JUMP_SLOT
6116 BFD_RELOC_CRIS_RELATIVE
6118 Relocs used in ELF shared libraries for CRIS.
6120 BFD_RELOC_CRIS_32_GOT
6122 32-bit offset to symbol-entry within GOT.
6124 BFD_RELOC_CRIS_16_GOT
6126 16-bit offset to symbol-entry within GOT.
6128 BFD_RELOC_CRIS_32_GOTPLT
6130 32-bit offset to symbol-entry within GOT, with PLT handling.
6132 BFD_RELOC_CRIS_16_GOTPLT
6134 16-bit offset to symbol-entry within GOT, with PLT handling.
6136 BFD_RELOC_CRIS_32_GOTREL
6138 32-bit offset to symbol, relative to GOT.
6140 BFD_RELOC_CRIS_32_PLT_GOTREL
6142 32-bit offset to symbol with PLT entry, relative to GOT.
6144 BFD_RELOC_CRIS_32_PLT_PCREL
6146 32-bit offset to symbol with PLT entry, relative to this relocation.
6149 BFD_RELOC_CRIS_32_GOT_GD
6151 BFD_RELOC_CRIS_16_GOT_GD
6153 BFD_RELOC_CRIS_32_GD
6157 BFD_RELOC_CRIS_32_DTPREL
6159 BFD_RELOC_CRIS_16_DTPREL
6161 BFD_RELOC_CRIS_32_GOT_TPREL
6163 BFD_RELOC_CRIS_16_GOT_TPREL
6165 BFD_RELOC_CRIS_32_TPREL
6167 BFD_RELOC_CRIS_16_TPREL
6169 BFD_RELOC_CRIS_DTPMOD
6171 BFD_RELOC_CRIS_32_IE
6173 Relocs used in TLS code for CRIS.
6178 BFD_RELOC_860_GLOB_DAT
6180 BFD_RELOC_860_JUMP_SLOT
6182 BFD_RELOC_860_RELATIVE
6192 BFD_RELOC_860_SPLIT0
6196 BFD_RELOC_860_SPLIT1
6200 BFD_RELOC_860_SPLIT2
6204 BFD_RELOC_860_LOGOT0
6206 BFD_RELOC_860_SPGOT0
6208 BFD_RELOC_860_LOGOT1
6210 BFD_RELOC_860_SPGOT1
6212 BFD_RELOC_860_LOGOTOFF0
6214 BFD_RELOC_860_SPGOTOFF0
6216 BFD_RELOC_860_LOGOTOFF1
6218 BFD_RELOC_860_SPGOTOFF1
6220 BFD_RELOC_860_LOGOTOFF2
6222 BFD_RELOC_860_LOGOTOFF3
6226 BFD_RELOC_860_HIGHADJ
6230 BFD_RELOC_860_HAGOTOFF
6238 BFD_RELOC_860_HIGOTOFF
6240 Intel i860 Relocations.
6243 BFD_RELOC_OR1K_REL_26
6245 BFD_RELOC_OR1K_GOTPC_HI16
6247 BFD_RELOC_OR1K_GOTPC_LO16
6249 BFD_RELOC_OR1K_GOT16
6251 BFD_RELOC_OR1K_PLT26
6253 BFD_RELOC_OR1K_GOTOFF_HI16
6255 BFD_RELOC_OR1K_GOTOFF_LO16
6259 BFD_RELOC_OR1K_GLOB_DAT
6261 BFD_RELOC_OR1K_JMP_SLOT
6263 BFD_RELOC_OR1K_RELATIVE
6265 BFD_RELOC_OR1K_TLS_GD_HI16
6267 BFD_RELOC_OR1K_TLS_GD_LO16
6269 BFD_RELOC_OR1K_TLS_LDM_HI16
6271 BFD_RELOC_OR1K_TLS_LDM_LO16
6273 BFD_RELOC_OR1K_TLS_LDO_HI16
6275 BFD_RELOC_OR1K_TLS_LDO_LO16
6277 BFD_RELOC_OR1K_TLS_IE_HI16
6279 BFD_RELOC_OR1K_TLS_IE_LO16
6281 BFD_RELOC_OR1K_TLS_LE_HI16
6283 BFD_RELOC_OR1K_TLS_LE_LO16
6285 BFD_RELOC_OR1K_TLS_TPOFF
6287 BFD_RELOC_OR1K_TLS_DTPOFF
6289 BFD_RELOC_OR1K_TLS_DTPMOD
6291 OpenRISC 1000 Relocations.
6294 BFD_RELOC_H8_DIR16A8
6296 BFD_RELOC_H8_DIR16R8
6298 BFD_RELOC_H8_DIR24A8
6300 BFD_RELOC_H8_DIR24R8
6302 BFD_RELOC_H8_DIR32A16
6304 BFD_RELOC_H8_DISP32A16
6309 BFD_RELOC_XSTORMY16_REL_12
6311 BFD_RELOC_XSTORMY16_12
6313 BFD_RELOC_XSTORMY16_24
6315 BFD_RELOC_XSTORMY16_FPTR16
6317 Sony Xstormy16 Relocations.
6322 Self-describing complex relocations.
6334 Infineon Relocations.
6337 BFD_RELOC_VAX_GLOB_DAT
6339 BFD_RELOC_VAX_JMP_SLOT
6341 BFD_RELOC_VAX_RELATIVE
6343 Relocations used by VAX ELF.
6348 Morpho MT - 16 bit immediate relocation.
6352 Morpho MT - Hi 16 bits of an address.
6356 Morpho MT - Low 16 bits of an address.
6358 BFD_RELOC_MT_GNU_VTINHERIT
6360 Morpho MT - Used to tell the linker which vtable entries are used.
6362 BFD_RELOC_MT_GNU_VTENTRY
6364 Morpho MT - Used to tell the linker which vtable entries are used.
6366 BFD_RELOC_MT_PCINSN8
6368 Morpho MT - 8 bit immediate relocation.
6371 BFD_RELOC_MSP430_10_PCREL
6373 BFD_RELOC_MSP430_16_PCREL
6377 BFD_RELOC_MSP430_16_PCREL_BYTE
6379 BFD_RELOC_MSP430_16_BYTE
6381 BFD_RELOC_MSP430_2X_PCREL
6383 BFD_RELOC_MSP430_RL_PCREL
6385 BFD_RELOC_MSP430_ABS8
6387 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6389 BFD_RELOC_MSP430X_PCR20_EXT_DST
6391 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6393 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6395 BFD_RELOC_MSP430X_ABS20_EXT_DST
6397 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6399 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6401 BFD_RELOC_MSP430X_ABS20_ADR_DST
6403 BFD_RELOC_MSP430X_PCR16
6405 BFD_RELOC_MSP430X_PCR20_CALL
6407 BFD_RELOC_MSP430X_ABS16
6409 BFD_RELOC_MSP430_ABS_HI16
6411 BFD_RELOC_MSP430_PREL31
6413 BFD_RELOC_MSP430_SYM_DIFF
6415 msp430 specific relocation codes
6422 BFD_RELOC_NIOS2_CALL26
6424 BFD_RELOC_NIOS2_IMM5
6426 BFD_RELOC_NIOS2_CACHE_OPX
6428 BFD_RELOC_NIOS2_IMM6
6430 BFD_RELOC_NIOS2_IMM8
6432 BFD_RELOC_NIOS2_HI16
6434 BFD_RELOC_NIOS2_LO16
6436 BFD_RELOC_NIOS2_HIADJ16
6438 BFD_RELOC_NIOS2_GPREL
6440 BFD_RELOC_NIOS2_UJMP
6442 BFD_RELOC_NIOS2_CJMP
6444 BFD_RELOC_NIOS2_CALLR
6446 BFD_RELOC_NIOS2_ALIGN
6448 BFD_RELOC_NIOS2_GOT16
6450 BFD_RELOC_NIOS2_CALL16
6452 BFD_RELOC_NIOS2_GOTOFF_LO
6454 BFD_RELOC_NIOS2_GOTOFF_HA
6456 BFD_RELOC_NIOS2_PCREL_LO
6458 BFD_RELOC_NIOS2_PCREL_HA
6460 BFD_RELOC_NIOS2_TLS_GD16
6462 BFD_RELOC_NIOS2_TLS_LDM16
6464 BFD_RELOC_NIOS2_TLS_LDO16
6466 BFD_RELOC_NIOS2_TLS_IE16
6468 BFD_RELOC_NIOS2_TLS_LE16
6470 BFD_RELOC_NIOS2_TLS_DTPMOD
6472 BFD_RELOC_NIOS2_TLS_DTPREL
6474 BFD_RELOC_NIOS2_TLS_TPREL
6476 BFD_RELOC_NIOS2_COPY
6478 BFD_RELOC_NIOS2_GLOB_DAT
6480 BFD_RELOC_NIOS2_JUMP_SLOT
6482 BFD_RELOC_NIOS2_RELATIVE
6484 BFD_RELOC_NIOS2_GOTOFF
6486 BFD_RELOC_NIOS2_CALL26_NOAT
6488 BFD_RELOC_NIOS2_GOT_LO
6490 BFD_RELOC_NIOS2_GOT_HA
6492 BFD_RELOC_NIOS2_CALL_LO
6494 BFD_RELOC_NIOS2_CALL_HA
6496 BFD_RELOC_NIOS2_R2_S12
6498 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6500 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6502 BFD_RELOC_NIOS2_R2_T1I7_2
6504 BFD_RELOC_NIOS2_R2_T2I4
6506 BFD_RELOC_NIOS2_R2_T2I4_1
6508 BFD_RELOC_NIOS2_R2_T2I4_2
6510 BFD_RELOC_NIOS2_R2_X1I7_2
6512 BFD_RELOC_NIOS2_R2_X2L5
6514 BFD_RELOC_NIOS2_R2_F1I5_2
6516 BFD_RELOC_NIOS2_R2_L5I4X1
6518 BFD_RELOC_NIOS2_R2_T1X1I6
6520 BFD_RELOC_NIOS2_R2_T1X1I6_2
6522 Relocations used by the Altera Nios II core.
6527 PRU LDI 16-bit unsigned data-memory relocation.
6529 BFD_RELOC_PRU_U16_PMEMIMM
6531 PRU LDI 16-bit unsigned instruction-memory relocation.
6535 PRU relocation for two consecutive LDI load instructions that load a
6536 32 bit value into a register. If the higher bits are all zero, then
6537 the second instruction may be relaxed.
6539 BFD_RELOC_PRU_S10_PCREL
6541 PRU QBBx 10-bit signed PC-relative relocation.
6543 BFD_RELOC_PRU_U8_PCREL
6545 PRU 8-bit unsigned relocation used for the LOOP instruction.
6547 BFD_RELOC_PRU_32_PMEM
6549 BFD_RELOC_PRU_16_PMEM
6551 PRU Program Memory relocations. Used to convert from byte addressing to
6552 32-bit word addressing.
6554 BFD_RELOC_PRU_GNU_DIFF8
6556 BFD_RELOC_PRU_GNU_DIFF16
6558 BFD_RELOC_PRU_GNU_DIFF32
6560 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6562 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6564 PRU relocations to mark the difference of two local symbols.
6565 These are only needed to support linker relaxation and can be ignored
6566 when not relaxing. The field is set to the value of the difference
6567 assuming no relaxation. The relocation encodes the position of the
6568 second symbol so the linker can determine whether to adjust the field
6569 value. The PMEM variants encode the word difference, instead of byte
6570 difference between symbols.
6573 BFD_RELOC_IQ2000_OFFSET_16
6575 BFD_RELOC_IQ2000_OFFSET_21
6577 BFD_RELOC_IQ2000_UHI16
6582 BFD_RELOC_XTENSA_RTLD
6584 Special Xtensa relocation used only by PLT entries in ELF shared
6585 objects to indicate that the runtime linker should set the value
6586 to one of its own internal functions or data structures.
6588 BFD_RELOC_XTENSA_GLOB_DAT
6590 BFD_RELOC_XTENSA_JMP_SLOT
6592 BFD_RELOC_XTENSA_RELATIVE
6594 Xtensa relocations for ELF shared objects.
6596 BFD_RELOC_XTENSA_PLT
6598 Xtensa relocation used in ELF object files for symbols that may require
6599 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6601 BFD_RELOC_XTENSA_DIFF8
6603 BFD_RELOC_XTENSA_DIFF16
6605 BFD_RELOC_XTENSA_DIFF32
6607 Xtensa relocations to mark the difference of two local symbols.
6608 These are only needed to support linker relaxation and can be ignored
6609 when not relaxing. The field is set to the value of the difference
6610 assuming no relaxation. The relocation encodes the position of the
6611 first symbol so the linker can determine whether to adjust the field
6614 BFD_RELOC_XTENSA_SLOT0_OP
6616 BFD_RELOC_XTENSA_SLOT1_OP
6618 BFD_RELOC_XTENSA_SLOT2_OP
6620 BFD_RELOC_XTENSA_SLOT3_OP
6622 BFD_RELOC_XTENSA_SLOT4_OP
6624 BFD_RELOC_XTENSA_SLOT5_OP
6626 BFD_RELOC_XTENSA_SLOT6_OP
6628 BFD_RELOC_XTENSA_SLOT7_OP
6630 BFD_RELOC_XTENSA_SLOT8_OP
6632 BFD_RELOC_XTENSA_SLOT9_OP
6634 BFD_RELOC_XTENSA_SLOT10_OP
6636 BFD_RELOC_XTENSA_SLOT11_OP
6638 BFD_RELOC_XTENSA_SLOT12_OP
6640 BFD_RELOC_XTENSA_SLOT13_OP
6642 BFD_RELOC_XTENSA_SLOT14_OP
6644 Generic Xtensa relocations for instruction operands. Only the slot
6645 number is encoded in the relocation. The relocation applies to the
6646 last PC-relative immediate operand, or if there are no PC-relative
6647 immediates, to the last immediate operand.
6649 BFD_RELOC_XTENSA_SLOT0_ALT
6651 BFD_RELOC_XTENSA_SLOT1_ALT
6653 BFD_RELOC_XTENSA_SLOT2_ALT
6655 BFD_RELOC_XTENSA_SLOT3_ALT
6657 BFD_RELOC_XTENSA_SLOT4_ALT
6659 BFD_RELOC_XTENSA_SLOT5_ALT
6661 BFD_RELOC_XTENSA_SLOT6_ALT
6663 BFD_RELOC_XTENSA_SLOT7_ALT
6665 BFD_RELOC_XTENSA_SLOT8_ALT
6667 BFD_RELOC_XTENSA_SLOT9_ALT
6669 BFD_RELOC_XTENSA_SLOT10_ALT
6671 BFD_RELOC_XTENSA_SLOT11_ALT
6673 BFD_RELOC_XTENSA_SLOT12_ALT
6675 BFD_RELOC_XTENSA_SLOT13_ALT
6677 BFD_RELOC_XTENSA_SLOT14_ALT
6679 Alternate Xtensa relocations. Only the slot is encoded in the
6680 relocation. The meaning of these relocations is opcode-specific.
6682 BFD_RELOC_XTENSA_OP0
6684 BFD_RELOC_XTENSA_OP1
6686 BFD_RELOC_XTENSA_OP2
6688 Xtensa relocations for backward compatibility. These have all been
6689 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6691 BFD_RELOC_XTENSA_ASM_EXPAND
6693 Xtensa relocation to mark that the assembler expanded the
6694 instructions from an original target. The expansion size is
6695 encoded in the reloc size.
6697 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6699 Xtensa relocation to mark that the linker should simplify
6700 assembler-expanded instructions. This is commonly used
6701 internally by the linker after analysis of a
6702 BFD_RELOC_XTENSA_ASM_EXPAND.
6704 BFD_RELOC_XTENSA_TLSDESC_FN
6706 BFD_RELOC_XTENSA_TLSDESC_ARG
6708 BFD_RELOC_XTENSA_TLS_DTPOFF
6710 BFD_RELOC_XTENSA_TLS_TPOFF
6712 BFD_RELOC_XTENSA_TLS_FUNC
6714 BFD_RELOC_XTENSA_TLS_ARG
6716 BFD_RELOC_XTENSA_TLS_CALL
6718 Xtensa TLS relocations.
6723 8 bit signed offset in (ix+d) or (iy+d).
6741 BFD_RELOC_LM32_BRANCH
6743 BFD_RELOC_LM32_16_GOT
6745 BFD_RELOC_LM32_GOTOFF_HI16
6747 BFD_RELOC_LM32_GOTOFF_LO16
6751 BFD_RELOC_LM32_GLOB_DAT
6753 BFD_RELOC_LM32_JMP_SLOT
6755 BFD_RELOC_LM32_RELATIVE
6757 Lattice Mico32 relocations.
6760 BFD_RELOC_MACH_O_SECTDIFF
6762 Difference between two section addreses. Must be followed by a
6763 BFD_RELOC_MACH_O_PAIR.
6765 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6767 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6769 BFD_RELOC_MACH_O_PAIR
6771 Pair of relocation. Contains the first symbol.
6773 BFD_RELOC_MACH_O_SUBTRACTOR32
6775 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6777 BFD_RELOC_MACH_O_SUBTRACTOR64
6779 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6782 BFD_RELOC_MACH_O_X86_64_BRANCH32
6784 BFD_RELOC_MACH_O_X86_64_BRANCH8
6786 PCREL relocations. They are marked as branch to create PLT entry if
6789 BFD_RELOC_MACH_O_X86_64_GOT
6791 Used when referencing a GOT entry.
6793 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6795 Used when loading a GOT entry with movq. It is specially marked so that
6796 the linker could optimize the movq to a leaq if possible.
6798 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6800 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6802 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6804 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6806 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6808 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6812 BFD_RELOC_MACH_O_ARM64_ADDEND
6814 Addend for PAGE or PAGEOFF.
6816 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6818 Relative offset to page of GOT slot.
6820 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6822 Relative offset within page of GOT slot.
6824 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6826 Address of a GOT entry.
6829 BFD_RELOC_MICROBLAZE_32_LO
6831 This is a 32 bit reloc for the microblaze that stores the
6832 low 16 bits of a value
6834 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6836 This is a 32 bit pc-relative reloc for the microblaze that
6837 stores the low 16 bits of a value
6839 BFD_RELOC_MICROBLAZE_32_ROSDA
6841 This is a 32 bit reloc for the microblaze that stores a
6842 value relative to the read-only small data area anchor
6844 BFD_RELOC_MICROBLAZE_32_RWSDA
6846 This is a 32 bit reloc for the microblaze that stores a
6847 value relative to the read-write small data area anchor
6849 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6851 This is a 32 bit reloc for the microblaze to handle
6852 expressions of the form "Symbol Op Symbol"
6854 BFD_RELOC_MICROBLAZE_64_NONE
6856 This is a 64 bit reloc that stores the 32 bit pc relative
6857 value in two words (with an imm instruction). No relocation is
6858 done here - only used for relaxing
6860 BFD_RELOC_MICROBLAZE_64_GOTPC
6862 This is a 64 bit reloc that stores the 32 bit pc relative
6863 value in two words (with an imm instruction). The relocation is
6864 PC-relative GOT offset
6866 BFD_RELOC_MICROBLAZE_64_GOT
6868 This is a 64 bit reloc that stores the 32 bit pc relative
6869 value in two words (with an imm instruction). The relocation is
6872 BFD_RELOC_MICROBLAZE_64_PLT
6874 This is a 64 bit reloc that stores the 32 bit pc relative
6875 value in two words (with an imm instruction). The relocation is
6876 PC-relative offset into PLT
6878 BFD_RELOC_MICROBLAZE_64_GOTOFF
6880 This is a 64 bit reloc that stores the 32 bit GOT relative
6881 value in two words (with an imm instruction). The relocation is
6882 relative offset from _GLOBAL_OFFSET_TABLE_
6884 BFD_RELOC_MICROBLAZE_32_GOTOFF
6886 This is a 32 bit reloc that stores the 32 bit GOT relative
6887 value in a word. The relocation is relative offset from
6888 _GLOBAL_OFFSET_TABLE_
6890 BFD_RELOC_MICROBLAZE_COPY
6892 This is used to tell the dynamic linker to copy the value out of
6893 the dynamic object into the runtime process image.
6895 BFD_RELOC_MICROBLAZE_64_TLS
6899 BFD_RELOC_MICROBLAZE_64_TLSGD
6901 This is a 64 bit reloc that stores the 32 bit GOT relative value
6902 of the GOT TLS GD info entry in two words (with an imm instruction). The
6903 relocation is GOT offset.
6905 BFD_RELOC_MICROBLAZE_64_TLSLD
6907 This is a 64 bit reloc that stores the 32 bit GOT relative value
6908 of the GOT TLS LD info entry in two words (with an imm instruction). The
6909 relocation is GOT offset.
6911 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6913 This is a 32 bit reloc that stores the Module ID to GOT(n).
6915 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6917 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6919 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6921 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6924 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6926 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6927 to two words (uses imm instruction).
6929 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6931 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6932 to two words (uses imm instruction).
6935 BFD_RELOC_AARCH64_RELOC_START
6937 AArch64 pseudo relocation code to mark the start of the AArch64
6938 relocation enumerators. N.B. the order of the enumerators is
6939 important as several tables in the AArch64 bfd backend are indexed
6940 by these enumerators; make sure they are all synced.
6942 BFD_RELOC_AARCH64_NULL
6944 Deprecated AArch64 null relocation code.
6946 BFD_RELOC_AARCH64_NONE
6948 AArch64 null relocation code.
6950 BFD_RELOC_AARCH64_64
6952 BFD_RELOC_AARCH64_32
6954 BFD_RELOC_AARCH64_16
6956 Basic absolute relocations of N bits. These are equivalent to
6957 BFD_RELOC_N and they were added to assist the indexing of the howto
6960 BFD_RELOC_AARCH64_64_PCREL
6962 BFD_RELOC_AARCH64_32_PCREL
6964 BFD_RELOC_AARCH64_16_PCREL
6966 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6967 and they were added to assist the indexing of the howto table.
6969 BFD_RELOC_AARCH64_MOVW_G0
6971 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6972 of an unsigned address/value.
6974 BFD_RELOC_AARCH64_MOVW_G0_NC
6976 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6977 an address/value. No overflow checking.
6979 BFD_RELOC_AARCH64_MOVW_G1
6981 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6982 of an unsigned address/value.
6984 BFD_RELOC_AARCH64_MOVW_G1_NC
6986 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6987 of an address/value. No overflow checking.
6989 BFD_RELOC_AARCH64_MOVW_G2
6991 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6992 of an unsigned address/value.
6994 BFD_RELOC_AARCH64_MOVW_G2_NC
6996 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6997 of an address/value. No overflow checking.
6999 BFD_RELOC_AARCH64_MOVW_G3
7001 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7002 of a signed or unsigned address/value.
7004 BFD_RELOC_AARCH64_MOVW_G0_S
7006 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7007 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7010 BFD_RELOC_AARCH64_MOVW_G1_S
7012 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7013 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7016 BFD_RELOC_AARCH64_MOVW_G2_S
7018 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7019 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7022 BFD_RELOC_AARCH64_LD_LO19_PCREL
7024 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7025 offset. The lowest two bits must be zero and are not stored in the
7026 instruction, giving a 21 bit signed byte offset.
7028 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7030 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7032 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7034 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7035 offset, giving a 4KB aligned page base address.
7037 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7039 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7040 offset, giving a 4KB aligned page base address, but with no overflow
7043 BFD_RELOC_AARCH64_ADD_LO12
7045 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7046 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7048 BFD_RELOC_AARCH64_LDST8_LO12
7050 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7051 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7053 BFD_RELOC_AARCH64_TSTBR14
7055 AArch64 14 bit pc-relative test bit and branch.
7056 The lowest two bits must be zero and are not stored in the instruction,
7057 giving a 16 bit signed byte offset.
7059 BFD_RELOC_AARCH64_BRANCH19
7061 AArch64 19 bit pc-relative conditional branch and compare & branch.
7062 The lowest two bits must be zero and are not stored in the instruction,
7063 giving a 21 bit signed byte offset.
7065 BFD_RELOC_AARCH64_JUMP26
7067 AArch64 26 bit pc-relative unconditional branch.
7068 The lowest two bits must be zero and are not stored in the instruction,
7069 giving a 28 bit signed byte offset.
7071 BFD_RELOC_AARCH64_CALL26
7073 AArch64 26 bit pc-relative unconditional branch and link.
7074 The lowest two bits must be zero and are not stored in the instruction,
7075 giving a 28 bit signed byte offset.
7077 BFD_RELOC_AARCH64_LDST16_LO12
7079 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7080 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7082 BFD_RELOC_AARCH64_LDST32_LO12
7084 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7085 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7087 BFD_RELOC_AARCH64_LDST64_LO12
7089 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7090 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7092 BFD_RELOC_AARCH64_LDST128_LO12
7094 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7095 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7097 BFD_RELOC_AARCH64_GOT_LD_PREL19
7099 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7100 offset of the global offset table entry for a symbol. The lowest two
7101 bits must be zero and are not stored in the instruction, giving a 21
7102 bit signed byte offset. This relocation type requires signed overflow
7105 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7107 Get to the page base of the global offset table entry for a symbol as
7108 part of an ADRP instruction using a 21 bit PC relative value.Used in
7109 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7111 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7113 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7114 the GOT entry for this symbol. Used in conjunction with
7115 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
7117 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7119 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7120 the GOT entry for this symbol. Used in conjunction with
7121 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
7123 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7125 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7126 for this symbol. Valid in LP64 ABI only.
7128 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7130 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7131 for this symbol. Valid in LP64 ABI only.
7133 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7135 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7136 the GOT entry for this symbol. Valid in LP64 ABI only.
7138 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7140 Scaled 14 bit byte offset to the page base of the global offset table.
7142 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7144 Scaled 15 bit byte offset to the page base of the global offset table.
7146 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7148 Get to the page base of the global offset table entry for a symbols
7149 tls_index structure as part of an adrp instruction using a 21 bit PC
7150 relative value. Used in conjunction with
7151 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7153 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7155 AArch64 TLS General Dynamic
7157 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7159 Unsigned 12 bit byte offset to global offset table entry for a symbols
7160 tls_index structure. Used in conjunction with
7161 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7163 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7165 AArch64 TLS General Dynamic relocation.
7167 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7169 AArch64 TLS General Dynamic relocation.
7171 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7173 AArch64 TLS INITIAL EXEC relocation.
7175 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7177 AArch64 TLS INITIAL EXEC relocation.
7179 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7181 AArch64 TLS INITIAL EXEC relocation.
7183 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7185 AArch64 TLS INITIAL EXEC relocation.
7187 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7189 AArch64 TLS INITIAL EXEC relocation.
7191 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7193 AArch64 TLS INITIAL EXEC relocation.
7195 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7197 bit[23:12] of byte offset to module TLS base address.
7199 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7201 Unsigned 12 bit byte offset to module TLS base address.
7203 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7205 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7207 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7209 Unsigned 12 bit byte offset to global offset table entry for a symbols
7210 tls_index structure. Used in conjunction with
7211 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7213 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7215 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7218 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7220 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7222 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7224 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7227 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7229 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7231 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7233 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7236 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7238 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7240 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7242 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7245 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7247 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7249 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7251 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7254 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7256 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7258 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7260 bit[15:0] of byte offset to module TLS base address.
7262 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7264 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7266 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7268 bit[31:16] of byte offset to module TLS base address.
7270 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7272 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7274 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7276 bit[47:32] of byte offset to module TLS base address.
7278 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7280 AArch64 TLS LOCAL EXEC relocation.
7282 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7284 AArch64 TLS LOCAL EXEC relocation.
7286 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7288 AArch64 TLS LOCAL EXEC relocation.
7290 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7292 AArch64 TLS LOCAL EXEC relocation.
7294 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7296 AArch64 TLS LOCAL EXEC relocation.
7298 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7300 AArch64 TLS LOCAL EXEC relocation.
7302 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7304 AArch64 TLS LOCAL EXEC relocation.
7306 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7308 AArch64 TLS LOCAL EXEC relocation.
7310 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7312 AArch64 TLS DESC relocation.
7314 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7316 AArch64 TLS DESC relocation.
7318 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7320 AArch64 TLS DESC relocation.
7322 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7324 AArch64 TLS DESC relocation.
7326 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7328 AArch64 TLS DESC relocation.
7330 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7332 AArch64 TLS DESC relocation.
7334 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7336 AArch64 TLS DESC relocation.
7338 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7340 AArch64 TLS DESC relocation.
7342 BFD_RELOC_AARCH64_TLSDESC_LDR
7344 AArch64 TLS DESC relocation.
7346 BFD_RELOC_AARCH64_TLSDESC_ADD
7348 AArch64 TLS DESC relocation.
7350 BFD_RELOC_AARCH64_TLSDESC_CALL
7352 AArch64 TLS DESC relocation.
7354 BFD_RELOC_AARCH64_COPY
7356 AArch64 TLS relocation.
7358 BFD_RELOC_AARCH64_GLOB_DAT
7360 AArch64 TLS relocation.
7362 BFD_RELOC_AARCH64_JUMP_SLOT
7364 AArch64 TLS relocation.
7366 BFD_RELOC_AARCH64_RELATIVE
7368 AArch64 TLS relocation.
7370 BFD_RELOC_AARCH64_TLS_DTPMOD
7372 AArch64 TLS relocation.
7374 BFD_RELOC_AARCH64_TLS_DTPREL
7376 AArch64 TLS relocation.
7378 BFD_RELOC_AARCH64_TLS_TPREL
7380 AArch64 TLS relocation.
7382 BFD_RELOC_AARCH64_TLSDESC
7384 AArch64 TLS relocation.
7386 BFD_RELOC_AARCH64_IRELATIVE
7388 AArch64 support for STT_GNU_IFUNC.
7390 BFD_RELOC_AARCH64_RELOC_END
7392 AArch64 pseudo relocation code to mark the end of the AArch64
7393 relocation enumerators that have direct mapping to ELF reloc codes.
7394 There are a few more enumerators after this one; those are mainly
7395 used by the AArch64 assembler for the internal fixup or to select
7396 one of the above enumerators.
7398 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7400 AArch64 pseudo relocation code to be used internally by the AArch64
7401 assembler and not (currently) written to any object files.
7403 BFD_RELOC_AARCH64_LDST_LO12
7405 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7406 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7408 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7410 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7411 used internally by the AArch64 assembler and not (currently) written to
7414 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7416 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7418 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7420 AArch64 pseudo relocation code to be used internally by the AArch64
7421 assembler and not (currently) written to any object files.
7423 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7425 AArch64 pseudo relocation code to be used internally by the AArch64
7426 assembler and not (currently) written to any object files.
7428 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7430 AArch64 pseudo relocation code to be used internally by the AArch64
7431 assembler and not (currently) written to any object files.
7433 BFD_RELOC_TILEPRO_COPY
7435 BFD_RELOC_TILEPRO_GLOB_DAT
7437 BFD_RELOC_TILEPRO_JMP_SLOT
7439 BFD_RELOC_TILEPRO_RELATIVE
7441 BFD_RELOC_TILEPRO_BROFF_X1
7443 BFD_RELOC_TILEPRO_JOFFLONG_X1
7445 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7447 BFD_RELOC_TILEPRO_IMM8_X0
7449 BFD_RELOC_TILEPRO_IMM8_Y0
7451 BFD_RELOC_TILEPRO_IMM8_X1
7453 BFD_RELOC_TILEPRO_IMM8_Y1
7455 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7457 BFD_RELOC_TILEPRO_MT_IMM15_X1
7459 BFD_RELOC_TILEPRO_MF_IMM15_X1
7461 BFD_RELOC_TILEPRO_IMM16_X0
7463 BFD_RELOC_TILEPRO_IMM16_X1
7465 BFD_RELOC_TILEPRO_IMM16_X0_LO
7467 BFD_RELOC_TILEPRO_IMM16_X1_LO
7469 BFD_RELOC_TILEPRO_IMM16_X0_HI
7471 BFD_RELOC_TILEPRO_IMM16_X1_HI
7473 BFD_RELOC_TILEPRO_IMM16_X0_HA
7475 BFD_RELOC_TILEPRO_IMM16_X1_HA
7477 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7479 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7481 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7483 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7485 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7487 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7489 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7491 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7493 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7495 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7497 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7499 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7501 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7503 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7505 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7507 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7509 BFD_RELOC_TILEPRO_MMSTART_X0
7511 BFD_RELOC_TILEPRO_MMEND_X0
7513 BFD_RELOC_TILEPRO_MMSTART_X1
7515 BFD_RELOC_TILEPRO_MMEND_X1
7517 BFD_RELOC_TILEPRO_SHAMT_X0
7519 BFD_RELOC_TILEPRO_SHAMT_X1
7521 BFD_RELOC_TILEPRO_SHAMT_Y0
7523 BFD_RELOC_TILEPRO_SHAMT_Y1
7525 BFD_RELOC_TILEPRO_TLS_GD_CALL
7527 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7529 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7531 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7533 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7535 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7537 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7539 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7541 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7543 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7545 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7547 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7549 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7551 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7553 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7555 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7557 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7559 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7561 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7563 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7565 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7567 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7569 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7571 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7573 BFD_RELOC_TILEPRO_TLS_TPOFF32
7575 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7577 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7579 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7581 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7583 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7585 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7587 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7589 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7591 Tilera TILEPro Relocations.
7593 BFD_RELOC_TILEGX_HW0
7595 BFD_RELOC_TILEGX_HW1
7597 BFD_RELOC_TILEGX_HW2
7599 BFD_RELOC_TILEGX_HW3
7601 BFD_RELOC_TILEGX_HW0_LAST
7603 BFD_RELOC_TILEGX_HW1_LAST
7605 BFD_RELOC_TILEGX_HW2_LAST
7607 BFD_RELOC_TILEGX_COPY
7609 BFD_RELOC_TILEGX_GLOB_DAT
7611 BFD_RELOC_TILEGX_JMP_SLOT
7613 BFD_RELOC_TILEGX_RELATIVE
7615 BFD_RELOC_TILEGX_BROFF_X1
7617 BFD_RELOC_TILEGX_JUMPOFF_X1
7619 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7621 BFD_RELOC_TILEGX_IMM8_X0
7623 BFD_RELOC_TILEGX_IMM8_Y0
7625 BFD_RELOC_TILEGX_IMM8_X1
7627 BFD_RELOC_TILEGX_IMM8_Y1
7629 BFD_RELOC_TILEGX_DEST_IMM8_X1
7631 BFD_RELOC_TILEGX_MT_IMM14_X1
7633 BFD_RELOC_TILEGX_MF_IMM14_X1
7635 BFD_RELOC_TILEGX_MMSTART_X0
7637 BFD_RELOC_TILEGX_MMEND_X0
7639 BFD_RELOC_TILEGX_SHAMT_X0
7641 BFD_RELOC_TILEGX_SHAMT_X1
7643 BFD_RELOC_TILEGX_SHAMT_Y0
7645 BFD_RELOC_TILEGX_SHAMT_Y1
7647 BFD_RELOC_TILEGX_IMM16_X0_HW0
7649 BFD_RELOC_TILEGX_IMM16_X1_HW0
7651 BFD_RELOC_TILEGX_IMM16_X0_HW1
7653 BFD_RELOC_TILEGX_IMM16_X1_HW1
7655 BFD_RELOC_TILEGX_IMM16_X0_HW2
7657 BFD_RELOC_TILEGX_IMM16_X1_HW2
7659 BFD_RELOC_TILEGX_IMM16_X0_HW3
7661 BFD_RELOC_TILEGX_IMM16_X1_HW3
7663 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7665 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7667 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7669 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7671 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7673 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7675 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7677 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7679 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7681 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7683 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7685 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7687 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7689 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7691 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7693 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7695 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7697 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7699 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7701 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7703 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7705 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7707 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7709 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7711 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7713 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7715 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7717 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7719 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7721 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7723 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7725 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7727 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7729 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7731 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7733 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7735 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7737 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7739 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7741 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7743 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7745 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7747 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7749 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7751 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7753 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7755 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7757 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7759 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7761 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7763 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7765 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7767 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7769 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7771 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7773 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7775 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7777 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7779 BFD_RELOC_TILEGX_TLS_DTPMOD64
7781 BFD_RELOC_TILEGX_TLS_DTPOFF64
7783 BFD_RELOC_TILEGX_TLS_TPOFF64
7785 BFD_RELOC_TILEGX_TLS_DTPMOD32
7787 BFD_RELOC_TILEGX_TLS_DTPOFF32
7789 BFD_RELOC_TILEGX_TLS_TPOFF32
7791 BFD_RELOC_TILEGX_TLS_GD_CALL
7793 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7795 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7797 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7799 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7801 BFD_RELOC_TILEGX_TLS_IE_LOAD
7803 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7805 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7807 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7809 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7811 Tilera TILE-Gx Relocations.
7814 BFD_RELOC_EPIPHANY_SIMM8
7816 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7818 BFD_RELOC_EPIPHANY_SIMM24
7820 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7822 BFD_RELOC_EPIPHANY_HIGH
7824 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7826 BFD_RELOC_EPIPHANY_LOW
7828 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7830 BFD_RELOC_EPIPHANY_SIMM11
7832 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7834 BFD_RELOC_EPIPHANY_IMM11
7836 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7838 BFD_RELOC_EPIPHANY_IMM8
7840 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7843 BFD_RELOC_VISIUM_HI16
7845 BFD_RELOC_VISIUM_LO16
7847 BFD_RELOC_VISIUM_IM16
7849 BFD_RELOC_VISIUM_REL16
7851 BFD_RELOC_VISIUM_HI16_PCREL
7853 BFD_RELOC_VISIUM_LO16_PCREL
7855 BFD_RELOC_VISIUM_IM16_PCREL
7860 BFD_RELOC_WASM32_LEB128
7862 BFD_RELOC_WASM32_LEB128_GOT
7864 BFD_RELOC_WASM32_LEB128_GOT_CODE
7866 BFD_RELOC_WASM32_LEB128_PLT
7868 BFD_RELOC_WASM32_PLT_INDEX
7870 BFD_RELOC_WASM32_ABS32_CODE
7872 BFD_RELOC_WASM32_COPY
7874 BFD_RELOC_WASM32_CODE_POINTER
7876 BFD_RELOC_WASM32_INDEX
7878 BFD_RELOC_WASM32_PLT_SIG
7880 WebAssembly relocations.
7886 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7891 bfd_reloc_type_lookup
7892 bfd_reloc_name_lookup
7895 reloc_howto_type *bfd_reloc_type_lookup
7896 (bfd *abfd, bfd_reloc_code_real_type code);
7897 reloc_howto_type *bfd_reloc_name_lookup
7898 (bfd *abfd, const char *reloc_name);
7901 Return a pointer to a howto structure which, when
7902 invoked, will perform the relocation @var{code} on data from the
7908 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7910 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7914 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7916 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7919 static reloc_howto_type bfd_howto_32
=
7920 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7924 bfd_default_reloc_type_lookup
7927 reloc_howto_type *bfd_default_reloc_type_lookup
7928 (bfd *abfd, bfd_reloc_code_real_type code);
7931 Provides a default relocation lookup routine for any architecture.
7936 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7940 case BFD_RELOC_CTOR
:
7941 /* The type of reloc used in a ctor, which will be as wide as the
7942 address - so either a 64, 32, or 16 bitter. */
7943 switch (bfd_arch_bits_per_address (abfd
))
7949 return &bfd_howto_32
;
7965 bfd_get_reloc_code_name
7968 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7971 Provides a printable name for the supplied relocation code.
7972 Useful mainly for printing error messages.
7976 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7978 if (code
> BFD_RELOC_UNUSED
)
7980 return bfd_reloc_code_real_names
[code
];
7985 bfd_generic_relax_section
7988 bfd_boolean bfd_generic_relax_section
7991 struct bfd_link_info *,
7995 Provides default handling for relaxing for back ends which
8000 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8001 asection
*section ATTRIBUTE_UNUSED
,
8002 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8005 if (bfd_link_relocatable (link_info
))
8006 (*link_info
->callbacks
->einfo
)
8007 (_("%P%F: --relax and -r may not be used together\n"));
8015 bfd_generic_gc_sections
8018 bfd_boolean bfd_generic_gc_sections
8019 (bfd *, struct bfd_link_info *);
8022 Provides default handling for relaxing for back ends which
8023 don't do section gc -- i.e., does nothing.
8027 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8028 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8035 bfd_generic_lookup_section_flags
8038 bfd_boolean bfd_generic_lookup_section_flags
8039 (struct bfd_link_info *, struct flag_info *, asection *);
8042 Provides default handling for section flags lookup
8043 -- i.e., does nothing.
8044 Returns FALSE if the section should be omitted, otherwise TRUE.
8048 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8049 struct flag_info
*flaginfo
,
8050 asection
*section ATTRIBUTE_UNUSED
)
8052 if (flaginfo
!= NULL
)
8054 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported.\n"));
8062 bfd_generic_merge_sections
8065 bfd_boolean bfd_generic_merge_sections
8066 (bfd *, struct bfd_link_info *);
8069 Provides default handling for SEC_MERGE section merging for back ends
8070 which don't have SEC_MERGE support -- i.e., does nothing.
8074 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8075 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8082 bfd_generic_get_relocated_section_contents
8085 bfd_byte *bfd_generic_get_relocated_section_contents
8087 struct bfd_link_info *link_info,
8088 struct bfd_link_order *link_order,
8090 bfd_boolean relocatable,
8094 Provides default handling of relocation effort for back ends
8095 which can't be bothered to do it efficiently.
8100 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8101 struct bfd_link_info
*link_info
,
8102 struct bfd_link_order
*link_order
,
8104 bfd_boolean relocatable
,
8107 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8108 asection
*input_section
= link_order
->u
.indirect
.section
;
8110 arelent
**reloc_vector
;
8113 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8117 /* Read in the section. */
8118 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8121 if (reloc_size
== 0)
8124 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8125 if (reloc_vector
== NULL
)
8128 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8132 if (reloc_count
< 0)
8135 if (reloc_count
> 0)
8139 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8141 char *error_message
= NULL
;
8143 bfd_reloc_status_type r
;
8145 symbol
= *(*parent
)->sym_ptr_ptr
;
8146 /* PR ld/19628: A specially crafted input file
8147 can result in a NULL symbol pointer here. */
8150 link_info
->callbacks
->einfo
8151 /* xgettext:c-format */
8152 (_("%X%P: %B(%A): error: relocation for offset %V has no value\n"),
8153 abfd
, input_section
, (* parent
)->address
);
8157 if (symbol
->section
&& discarded_section (symbol
->section
))
8160 static reloc_howto_type none_howto
8161 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8162 "unused", FALSE
, 0, 0, FALSE
);
8164 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
8165 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
8167 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8168 (*parent
)->addend
= 0;
8169 (*parent
)->howto
= &none_howto
;
8173 r
= bfd_perform_relocation (input_bfd
,
8177 relocatable
? abfd
: NULL
,
8182 asection
*os
= input_section
->output_section
;
8184 /* A partial link, so keep the relocs. */
8185 os
->orelocation
[os
->reloc_count
] = *parent
;
8189 if (r
!= bfd_reloc_ok
)
8193 case bfd_reloc_undefined
:
8194 (*link_info
->callbacks
->undefined_symbol
)
8195 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8196 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8198 case bfd_reloc_dangerous
:
8199 BFD_ASSERT (error_message
!= NULL
);
8200 (*link_info
->callbacks
->reloc_dangerous
)
8201 (link_info
, error_message
,
8202 input_bfd
, input_section
, (*parent
)->address
);
8204 case bfd_reloc_overflow
:
8205 (*link_info
->callbacks
->reloc_overflow
)
8207 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8208 (*parent
)->howto
->name
, (*parent
)->addend
,
8209 input_bfd
, input_section
, (*parent
)->address
);
8211 case bfd_reloc_outofrange
:
8213 This error can result when processing some partially
8214 complete binaries. Do not abort, but issue an error
8216 link_info
->callbacks
->einfo
8217 /* xgettext:c-format */
8218 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
8219 abfd
, input_section
, * parent
);
8222 case bfd_reloc_notsupported
:
8224 This error can result when processing a corrupt binary.
8225 Do not abort. Issue an error message instead. */
8226 link_info
->callbacks
->einfo
8227 /* xgettext:c-format */
8228 (_("%X%P: %B(%A): relocation \"%R\" is not supported\n"),
8229 abfd
, input_section
, * parent
);
8233 /* PR 17512; file: 90c2a92e.
8234 Report unexpected results, without aborting. */
8235 link_info
->callbacks
->einfo
8236 /* xgettext:c-format */
8237 (_("%X%P: %B(%A): relocation \"%R\" returns an unrecognized value %x\n"),
8238 abfd
, input_section
, * parent
, r
);
8246 free (reloc_vector
);
8250 free (reloc_vector
);