1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2018 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
98 .typedef struct reloc_cache_entry
100 . {* A pointer into the canonical table of pointers. *}
101 . struct bfd_symbol **sym_ptr_ptr;
103 . {* offset in section. *}
104 . bfd_size_type address;
106 . {* addend for relocation value. *}
109 . {* Pointer to how to perform the required relocation. *}
110 . reloc_howto_type *howto;
120 Here is a description of each of the fields within an <<arelent>>:
124 The symbol table pointer points to a pointer to the symbol
125 associated with the relocation request. It is the pointer
126 into the table returned by the back end's
127 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
128 referenced through a pointer to a pointer so that tools like
129 the linker can fix up all the symbols of the same name by
130 modifying only one pointer. The relocation routine looks in
131 the symbol and uses the base of the section the symbol is
132 attached to and the value of the symbol as the initial
133 relocation offset. If the symbol pointer is zero, then the
134 section provided is looked up.
138 The <<address>> field gives the offset in bytes from the base of
139 the section data which owns the relocation record to the first
140 byte of relocatable information. The actual data relocated
141 will be relative to this point; for example, a relocation
142 type which modifies the bottom two bytes of a four byte word
143 would not touch the first byte pointed to in a big endian
148 The <<addend>> is a value provided by the back end to be added (!)
149 to the relocation offset. Its interpretation is dependent upon
150 the howto. For example, on the 68k the code:
155 | return foo[0x12345678];
158 Could be compiled into:
161 | moveb @@#12345678,d0
166 This could create a reloc pointing to <<foo>>, but leave the
167 offset in the data, something like:
169 |RELOCATION RECORDS FOR [.text]:
173 |00000000 4e56 fffc ; linkw fp,#-4
174 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
175 |0000000a 49c0 ; extbl d0
176 |0000000c 4e5e ; unlk fp
179 Using coff and an 88k, some instructions don't have enough
180 space in them to represent the full address range, and
181 pointers have to be loaded in two parts. So you'd get something like:
183 | or.u r13,r0,hi16(_foo+0x12345678)
184 | ld.b r2,r13,lo16(_foo+0x12345678)
187 This should create two relocs, both pointing to <<_foo>>, and with
188 0x12340000 in their addend field. The data would consist of:
190 |RELOCATION RECORDS FOR [.text]:
192 |00000002 HVRT16 _foo+0x12340000
193 |00000006 LVRT16 _foo+0x12340000
195 |00000000 5da05678 ; or.u r13,r0,0x5678
196 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
197 |00000008 f400c001 ; jmp r1
199 The relocation routine digs out the value from the data, adds
200 it to the addend to get the original offset, and then adds the
201 value of <<_foo>>. Note that all 32 bits have to be kept around
202 somewhere, to cope with carry from bit 15 to bit 16.
204 One further example is the sparc and the a.out format. The
205 sparc has a similar problem to the 88k, in that some
206 instructions don't have room for an entire offset, but on the
207 sparc the parts are created in odd sized lumps. The designers of
208 the a.out format chose to not use the data within the section
209 for storing part of the offset; all the offset is kept within
210 the reloc. Anything in the data should be ignored.
213 | sethi %hi(_foo+0x12345678),%g2
214 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
218 Both relocs contain a pointer to <<foo>>, and the offsets
221 |RELOCATION RECORDS FOR [.text]:
223 |00000004 HI22 _foo+0x12345678
224 |00000008 LO10 _foo+0x12345678
226 |00000000 9de3bf90 ; save %sp,-112,%sp
227 |00000004 05000000 ; sethi %hi(_foo+0),%g2
228 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
229 |0000000c 81c7e008 ; ret
230 |00000010 81e80000 ; restore
234 The <<howto>> field can be imagined as a
235 relocation instruction. It is a pointer to a structure which
236 contains information on what to do with all of the other
237 information in the reloc record and data section. A back end
238 would normally have a relocation instruction set and turn
239 relocations into pointers to the correct structure on input -
240 but it would be possible to create each howto field on demand.
246 <<enum complain_overflow>>
248 Indicates what sort of overflow checking should be done when
249 performing a relocation.
253 .enum complain_overflow
255 . {* Do not complain on overflow. *}
256 . complain_overflow_dont,
258 . {* Complain if the value overflows when considered as a signed
259 . number one bit larger than the field. ie. A bitfield of N bits
260 . is allowed to represent -2**n to 2**n-1. *}
261 . complain_overflow_bitfield,
263 . {* Complain if the value overflows when considered as a signed
265 . complain_overflow_signed,
267 . {* Complain if the value overflows when considered as an
268 . unsigned number. *}
269 . complain_overflow_unsigned
278 The <<reloc_howto_type>> is a structure which contains all the
279 information that libbfd needs to know to tie up a back end's data.
282 .struct bfd_symbol; {* Forward declaration. *}
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's
288 . external idea of what a reloc number is stored
289 . in this field. For example, a PC relative word relocation
290 . in a coff environment has the type 023 - because that's
291 . what the outside world calls a R_PCRWORD reloc. *}
294 . {* The value the final relocation is shifted right by. This drops
295 . unwanted data from the relocation. *}
296 . unsigned int rightshift;
298 . {* The size of the item to be relocated. This is *not* a
299 . power-of-two measure. To get the number of bytes operated
300 . on by a type of relocation, use bfd_get_reloc_size. *}
303 . {* The number of bits in the item to be relocated. This is used
304 . when doing overflow checking. *}
305 . unsigned int bitsize;
307 . {* The relocation is relative to the field being relocated. *}
308 . bfd_boolean pc_relative;
310 . {* The bit position of the reloc value in the destination.
311 . The relocated value is left shifted by this amount. *}
312 . unsigned int bitpos;
314 . {* What type of overflow error should be checked for when
316 . enum complain_overflow complain_on_overflow;
318 . {* If this field is non null, then the supplied function is
319 . called rather than the normal function. This allows really
320 . strange relocation methods to be accommodated. *}
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., ELF); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO macro fills in a reloc_howto_type (a typedef for
376 const struct reloc_howto_struct).
378 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
379 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
382 This is used to fill in an empty howto entry in an array.
384 .#define EMPTY_HOWTO(C) \
385 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
386 . NULL, FALSE, 0, 0, FALSE)
395 unsigned int bfd_get_reloc_size (reloc_howto_type *);
398 For a reloc_howto_type that operates on a fixed number of bytes,
399 this returns the number of bytes operated on.
403 bfd_get_reloc_size (reloc_howto_type
*howto
)
426 How relocs are tied together in an <<asection>>:
428 .typedef struct relent_chain
431 . struct relent_chain *next;
437 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
438 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
445 bfd_reloc_status_type bfd_check_overflow
446 (enum complain_overflow how,
447 unsigned int bitsize,
448 unsigned int rightshift,
449 unsigned int addrsize,
453 Perform overflow checking on @var{relocation} which has
454 @var{bitsize} significant bits and will be shifted right by
455 @var{rightshift} bits, on a machine with addresses containing
456 @var{addrsize} significant bits. The result is either of
457 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
461 bfd_reloc_status_type
462 bfd_check_overflow (enum complain_overflow how
,
463 unsigned int bitsize
,
464 unsigned int rightshift
,
465 unsigned int addrsize
,
468 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
469 bfd_reloc_status_type flag
= bfd_reloc_ok
;
471 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
472 we'll be permissive: extra bits in the field mask will
473 automatically extend the address mask for purposes of the
475 fieldmask
= N_ONES (bitsize
);
476 signmask
= ~fieldmask
;
477 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
478 a
= (relocation
& addrmask
) >> rightshift
;
482 case complain_overflow_dont
:
485 case complain_overflow_signed
:
486 /* If any sign bits are set, all sign bits must be set. That
487 is, A must be a valid negative address after shifting. */
488 signmask
= ~ (fieldmask
>> 1);
491 case complain_overflow_bitfield
:
492 /* Bitfields are sometimes signed, sometimes unsigned. We
493 explicitly allow an address wrap too, which means a bitfield
494 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
495 if the value has some, but not all, bits set outside the
498 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
499 flag
= bfd_reloc_overflow
;
502 case complain_overflow_unsigned
:
503 /* We have an overflow if the address does not fit in the field. */
504 if ((a
& signmask
) != 0)
505 flag
= bfd_reloc_overflow
;
517 bfd_reloc_offset_in_range
520 bfd_boolean bfd_reloc_offset_in_range
521 (reloc_howto_type *howto,
524 bfd_size_type offset);
527 Returns TRUE if the reloc described by @var{HOWTO} can be
528 applied at @var{OFFSET} octets in @var{SECTION}.
532 /* HOWTO describes a relocation, at offset OCTET. Return whether the
533 relocation field is within SECTION of ABFD. */
536 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
541 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
542 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
544 /* The reloc field must be contained entirely within the section.
545 Allow zero length fields (marker relocs or NONE relocs where no
546 relocation will be performed) at the end of the section. */
547 return octet
<= octet_end
&& octet
+ reloc_size
<= octet_end
;
550 /* Read and return the section contents at DATA converted to a host
551 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
554 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
559 return bfd_get_8 (abfd
, data
);
563 return bfd_get_16 (abfd
, data
);
567 return bfd_get_32 (abfd
, data
);
574 return bfd_get_64 (abfd
, data
);
578 return bfd_get_24 (abfd
, data
);
586 /* Convert VAL to target format and write to DATA. The number of
587 bytes written is given by the HOWTO. */
590 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
595 bfd_put_8 (abfd
, val
, data
);
600 bfd_put_16 (abfd
, val
, data
);
605 bfd_put_32 (abfd
, val
, data
);
613 bfd_put_64 (abfd
, val
, data
);
618 bfd_put_24 (abfd
, val
, data
);
626 /* Apply RELOCATION value to target bytes at DATA, according to
630 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
633 bfd_vma val
= read_reloc (abfd
, data
, howto
);
636 relocation
= -relocation
;
638 val
= ((val
& ~howto
->dst_mask
)
639 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
641 write_reloc (abfd
, val
, data
, howto
);
646 bfd_perform_relocation
649 bfd_reloc_status_type bfd_perform_relocation
651 arelent *reloc_entry,
653 asection *input_section,
655 char **error_message);
658 If @var{output_bfd} is supplied to this function, the
659 generated image will be relocatable; the relocations are
660 copied to the output file after they have been changed to
661 reflect the new state of the world. There are two ways of
662 reflecting the results of partial linkage in an output file:
663 by modifying the output data in place, and by modifying the
664 relocation record. Some native formats (e.g., basic a.out and
665 basic coff) have no way of specifying an addend in the
666 relocation type, so the addend has to go in the output data.
667 This is no big deal since in these formats the output data
668 slot will always be big enough for the addend. Complex reloc
669 types with addends were invented to solve just this problem.
670 The @var{error_message} argument is set to an error message if
671 this return @code{bfd_reloc_dangerous}.
675 bfd_reloc_status_type
676 bfd_perform_relocation (bfd
*abfd
,
677 arelent
*reloc_entry
,
679 asection
*input_section
,
681 char **error_message
)
684 bfd_reloc_status_type flag
= bfd_reloc_ok
;
685 bfd_size_type octets
;
686 bfd_vma output_base
= 0;
687 reloc_howto_type
*howto
= reloc_entry
->howto
;
688 asection
*reloc_target_output_section
;
691 symbol
= *(reloc_entry
->sym_ptr_ptr
);
693 /* If we are not producing relocatable output, return an error if
694 the symbol is not defined. An undefined weak symbol is
695 considered to have a value of zero (SVR4 ABI, p. 4-27). */
696 if (bfd_is_und_section (symbol
->section
)
697 && (symbol
->flags
& BSF_WEAK
) == 0
698 && output_bfd
== NULL
)
699 flag
= bfd_reloc_undefined
;
701 /* If there is a function supplied to handle this relocation type,
702 call it. It'll return `bfd_reloc_continue' if further processing
704 if (howto
&& howto
->special_function
)
706 bfd_reloc_status_type cont
;
708 /* Note - we do not call bfd_reloc_offset_in_range here as the
709 reloc_entry->address field might actually be valid for the
710 backend concerned. It is up to the special_function itself
711 to call bfd_reloc_offset_in_range if needed. */
712 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
713 input_section
, output_bfd
,
715 if (cont
!= bfd_reloc_continue
)
719 if (bfd_is_abs_section (symbol
->section
)
720 && output_bfd
!= NULL
)
722 reloc_entry
->address
+= input_section
->output_offset
;
726 /* PR 17512: file: 0f67f69d. */
728 return bfd_reloc_undefined
;
730 /* Is the address of the relocation really within the section? */
731 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
732 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
733 return bfd_reloc_outofrange
;
735 /* Work out which section the relocation is targeted at and the
736 initial relocation command value. */
738 /* Get symbol value. (Common symbols are special.) */
739 if (bfd_is_com_section (symbol
->section
))
742 relocation
= symbol
->value
;
744 reloc_target_output_section
= symbol
->section
->output_section
;
746 /* Convert input-section-relative symbol value to absolute. */
747 if ((output_bfd
&& ! howto
->partial_inplace
)
748 || reloc_target_output_section
== NULL
)
751 output_base
= reloc_target_output_section
->vma
;
753 relocation
+= output_base
+ symbol
->section
->output_offset
;
755 /* Add in supplied addend. */
756 relocation
+= reloc_entry
->addend
;
758 /* Here the variable relocation holds the final address of the
759 symbol we are relocating against, plus any addend. */
761 if (howto
->pc_relative
)
763 /* This is a PC relative relocation. We want to set RELOCATION
764 to the distance between the address of the symbol and the
765 location. RELOCATION is already the address of the symbol.
767 We start by subtracting the address of the section containing
770 If pcrel_offset is set, we must further subtract the position
771 of the location within the section. Some targets arrange for
772 the addend to be the negative of the position of the location
773 within the section; for example, i386-aout does this. For
774 i386-aout, pcrel_offset is FALSE. Some other targets do not
775 include the position of the location; for example, ELF.
776 For those targets, pcrel_offset is TRUE.
778 If we are producing relocatable output, then we must ensure
779 that this reloc will be correctly computed when the final
780 relocation is done. If pcrel_offset is FALSE we want to wind
781 up with the negative of the location within the section,
782 which means we must adjust the existing addend by the change
783 in the location within the section. If pcrel_offset is TRUE
784 we do not want to adjust the existing addend at all.
786 FIXME: This seems logical to me, but for the case of
787 producing relocatable output it is not what the code
788 actually does. I don't want to change it, because it seems
789 far too likely that something will break. */
792 input_section
->output_section
->vma
+ input_section
->output_offset
;
794 if (howto
->pcrel_offset
)
795 relocation
-= reloc_entry
->address
;
798 if (output_bfd
!= NULL
)
800 if (! howto
->partial_inplace
)
802 /* This is a partial relocation, and we want to apply the relocation
803 to the reloc entry rather than the raw data. Modify the reloc
804 inplace to reflect what we now know. */
805 reloc_entry
->addend
= relocation
;
806 reloc_entry
->address
+= input_section
->output_offset
;
811 /* This is a partial relocation, but inplace, so modify the
814 If we've relocated with a symbol with a section, change
815 into a ref to the section belonging to the symbol. */
817 reloc_entry
->address
+= input_section
->output_offset
;
820 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
821 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
822 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
824 /* For m68k-coff, the addend was being subtracted twice during
825 relocation with -r. Removing the line below this comment
826 fixes that problem; see PR 2953.
828 However, Ian wrote the following, regarding removing the line below,
829 which explains why it is still enabled: --djm
831 If you put a patch like that into BFD you need to check all the COFF
832 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
833 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
834 problem in a different way. There may very well be a reason that the
835 code works as it does.
837 Hmmm. The first obvious point is that bfd_perform_relocation should
838 not have any tests that depend upon the flavour. It's seem like
839 entirely the wrong place for such a thing. The second obvious point
840 is that the current code ignores the reloc addend when producing
841 relocatable output for COFF. That's peculiar. In fact, I really
842 have no idea what the point of the line you want to remove is.
844 A typical COFF reloc subtracts the old value of the symbol and adds in
845 the new value to the location in the object file (if it's a pc
846 relative reloc it adds the difference between the symbol value and the
847 location). When relocating we need to preserve that property.
849 BFD handles this by setting the addend to the negative of the old
850 value of the symbol. Unfortunately it handles common symbols in a
851 non-standard way (it doesn't subtract the old value) but that's a
852 different story (we can't change it without losing backward
853 compatibility with old object files) (coff-i386 does subtract the old
854 value, to be compatible with existing coff-i386 targets, like SCO).
856 So everything works fine when not producing relocatable output. When
857 we are producing relocatable output, logically we should do exactly
858 what we do when not producing relocatable output. Therefore, your
859 patch is correct. In fact, it should probably always just set
860 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
861 add the value into the object file. This won't hurt the COFF code,
862 which doesn't use the addend; I'm not sure what it will do to other
863 formats (the thing to check for would be whether any formats both use
864 the addend and set partial_inplace).
866 When I wanted to make coff-i386 produce relocatable output, I ran
867 into the problem that you are running into: I wanted to remove that
868 line. Rather than risk it, I made the coff-i386 relocs use a special
869 function; it's coff_i386_reloc in coff-i386.c. The function
870 specifically adds the addend field into the object file, knowing that
871 bfd_perform_relocation is not going to. If you remove that line, then
872 coff-i386.c will wind up adding the addend field in twice. It's
873 trivial to fix; it just needs to be done.
875 The problem with removing the line is just that it may break some
876 working code. With BFD it's hard to be sure of anything. The right
877 way to deal with this is simply to build and test at least all the
878 supported COFF targets. It should be straightforward if time and disk
879 space consuming. For each target:
881 2) generate some executable, and link it using -r (I would
882 probably use paranoia.o and link against newlib/libc.a, which
883 for all the supported targets would be available in
884 /usr/cygnus/progressive/H-host/target/lib/libc.a).
885 3) make the change to reloc.c
886 4) rebuild the linker
888 6) if the resulting object files are the same, you have at least
890 7) if they are different you have to figure out which version is
893 relocation
-= reloc_entry
->addend
;
894 reloc_entry
->addend
= 0;
898 reloc_entry
->addend
= relocation
;
903 /* FIXME: This overflow checking is incomplete, because the value
904 might have overflowed before we get here. For a correct check we
905 need to compute the value in a size larger than bitsize, but we
906 can't reasonably do that for a reloc the same size as a host
908 FIXME: We should also do overflow checking on the result after
909 adding in the value contained in the object file. */
910 if (howto
->complain_on_overflow
!= complain_overflow_dont
911 && flag
== bfd_reloc_ok
)
912 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
915 bfd_arch_bits_per_address (abfd
),
918 /* Either we are relocating all the way, or we don't want to apply
919 the relocation to the reloc entry (probably because there isn't
920 any room in the output format to describe addends to relocs). */
922 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
923 (OSF version 1.3, compiler version 3.11). It miscompiles the
937 x <<= (unsigned long) s.i0;
941 printf ("succeeded (%lx)\n", x);
945 relocation
>>= (bfd_vma
) howto
->rightshift
;
947 /* Shift everything up to where it's going to be used. */
948 relocation
<<= (bfd_vma
) howto
->bitpos
;
950 /* Wait for the day when all have the mask in them. */
953 i instruction to be left alone
954 o offset within instruction
955 r relocation offset to apply
964 (( i i i i i o o o o o from bfd_get<size>
965 and S S S S S) to get the size offset we want
966 + r r r r r r r r r r) to get the final value to place
967 and D D D D D to chop to right size
968 -----------------------
971 ( i i i i i o o o o o from bfd_get<size>
972 and N N N N N ) get instruction
973 -----------------------
979 -----------------------
980 = R R R R R R R R R R put into bfd_put<size>
983 data
= (bfd_byte
*) data
+ octets
;
984 apply_reloc (abfd
, data
, howto
, relocation
);
990 bfd_install_relocation
993 bfd_reloc_status_type bfd_install_relocation
995 arelent *reloc_entry,
996 void *data, bfd_vma data_start,
997 asection *input_section,
998 char **error_message);
1001 This looks remarkably like <<bfd_perform_relocation>>, except it
1002 does not expect that the section contents have been filled in.
1003 I.e., it's suitable for use when creating, rather than applying
1006 For now, this function should be considered reserved for the
1010 bfd_reloc_status_type
1011 bfd_install_relocation (bfd
*abfd
,
1012 arelent
*reloc_entry
,
1014 bfd_vma data_start_offset
,
1015 asection
*input_section
,
1016 char **error_message
)
1019 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1020 bfd_size_type octets
;
1021 bfd_vma output_base
= 0;
1022 reloc_howto_type
*howto
= reloc_entry
->howto
;
1023 asection
*reloc_target_output_section
;
1027 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1029 /* If there is a function supplied to handle this relocation type,
1030 call it. It'll return `bfd_reloc_continue' if further processing
1032 if (howto
&& howto
->special_function
)
1034 bfd_reloc_status_type cont
;
1036 /* Note - we do not call bfd_reloc_offset_in_range here as the
1037 reloc_entry->address field might actually be valid for the
1038 backend concerned. It is up to the special_function itself
1039 to call bfd_reloc_offset_in_range if needed. */
1040 /* XXX - The special_function calls haven't been fixed up to deal
1041 with creating new relocations and section contents. */
1042 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1043 /* XXX - Non-portable! */
1044 ((bfd_byte
*) data_start
1045 - data_start_offset
),
1046 input_section
, abfd
, error_message
);
1047 if (cont
!= bfd_reloc_continue
)
1051 if (bfd_is_abs_section (symbol
->section
))
1053 reloc_entry
->address
+= input_section
->output_offset
;
1054 return bfd_reloc_ok
;
1057 /* No need to check for howto != NULL if !bfd_is_abs_section as
1058 it will have been checked in `bfd_perform_relocation already'. */
1060 /* Is the address of the relocation really within the section? */
1061 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
1062 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1063 return bfd_reloc_outofrange
;
1065 /* Work out which section the relocation is targeted at and the
1066 initial relocation command value. */
1068 /* Get symbol value. (Common symbols are special.) */
1069 if (bfd_is_com_section (symbol
->section
))
1072 relocation
= symbol
->value
;
1074 reloc_target_output_section
= symbol
->section
->output_section
;
1076 /* Convert input-section-relative symbol value to absolute. */
1077 if (! howto
->partial_inplace
)
1080 output_base
= reloc_target_output_section
->vma
;
1082 relocation
+= output_base
+ symbol
->section
->output_offset
;
1084 /* Add in supplied addend. */
1085 relocation
+= reloc_entry
->addend
;
1087 /* Here the variable relocation holds the final address of the
1088 symbol we are relocating against, plus any addend. */
1090 if (howto
->pc_relative
)
1092 /* This is a PC relative relocation. We want to set RELOCATION
1093 to the distance between the address of the symbol and the
1094 location. RELOCATION is already the address of the symbol.
1096 We start by subtracting the address of the section containing
1099 If pcrel_offset is set, we must further subtract the position
1100 of the location within the section. Some targets arrange for
1101 the addend to be the negative of the position of the location
1102 within the section; for example, i386-aout does this. For
1103 i386-aout, pcrel_offset is FALSE. Some other targets do not
1104 include the position of the location; for example, ELF.
1105 For those targets, pcrel_offset is TRUE.
1107 If we are producing relocatable output, then we must ensure
1108 that this reloc will be correctly computed when the final
1109 relocation is done. If pcrel_offset is FALSE we want to wind
1110 up with the negative of the location within the section,
1111 which means we must adjust the existing addend by the change
1112 in the location within the section. If pcrel_offset is TRUE
1113 we do not want to adjust the existing addend at all.
1115 FIXME: This seems logical to me, but for the case of
1116 producing relocatable output it is not what the code
1117 actually does. I don't want to change it, because it seems
1118 far too likely that something will break. */
1121 input_section
->output_section
->vma
+ input_section
->output_offset
;
1123 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1124 relocation
-= reloc_entry
->address
;
1127 if (! howto
->partial_inplace
)
1129 /* This is a partial relocation, and we want to apply the relocation
1130 to the reloc entry rather than the raw data. Modify the reloc
1131 inplace to reflect what we now know. */
1132 reloc_entry
->addend
= relocation
;
1133 reloc_entry
->address
+= input_section
->output_offset
;
1138 /* This is a partial relocation, but inplace, so modify the
1141 If we've relocated with a symbol with a section, change
1142 into a ref to the section belonging to the symbol. */
1143 reloc_entry
->address
+= input_section
->output_offset
;
1146 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1147 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1148 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1151 /* For m68k-coff, the addend was being subtracted twice during
1152 relocation with -r. Removing the line below this comment
1153 fixes that problem; see PR 2953.
1155 However, Ian wrote the following, regarding removing the line below,
1156 which explains why it is still enabled: --djm
1158 If you put a patch like that into BFD you need to check all the COFF
1159 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1160 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1161 problem in a different way. There may very well be a reason that the
1162 code works as it does.
1164 Hmmm. The first obvious point is that bfd_install_relocation should
1165 not have any tests that depend upon the flavour. It's seem like
1166 entirely the wrong place for such a thing. The second obvious point
1167 is that the current code ignores the reloc addend when producing
1168 relocatable output for COFF. That's peculiar. In fact, I really
1169 have no idea what the point of the line you want to remove is.
1171 A typical COFF reloc subtracts the old value of the symbol and adds in
1172 the new value to the location in the object file (if it's a pc
1173 relative reloc it adds the difference between the symbol value and the
1174 location). When relocating we need to preserve that property.
1176 BFD handles this by setting the addend to the negative of the old
1177 value of the symbol. Unfortunately it handles common symbols in a
1178 non-standard way (it doesn't subtract the old value) but that's a
1179 different story (we can't change it without losing backward
1180 compatibility with old object files) (coff-i386 does subtract the old
1181 value, to be compatible with existing coff-i386 targets, like SCO).
1183 So everything works fine when not producing relocatable output. When
1184 we are producing relocatable output, logically we should do exactly
1185 what we do when not producing relocatable output. Therefore, your
1186 patch is correct. In fact, it should probably always just set
1187 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1188 add the value into the object file. This won't hurt the COFF code,
1189 which doesn't use the addend; I'm not sure what it will do to other
1190 formats (the thing to check for would be whether any formats both use
1191 the addend and set partial_inplace).
1193 When I wanted to make coff-i386 produce relocatable output, I ran
1194 into the problem that you are running into: I wanted to remove that
1195 line. Rather than risk it, I made the coff-i386 relocs use a special
1196 function; it's coff_i386_reloc in coff-i386.c. The function
1197 specifically adds the addend field into the object file, knowing that
1198 bfd_install_relocation is not going to. If you remove that line, then
1199 coff-i386.c will wind up adding the addend field in twice. It's
1200 trivial to fix; it just needs to be done.
1202 The problem with removing the line is just that it may break some
1203 working code. With BFD it's hard to be sure of anything. The right
1204 way to deal with this is simply to build and test at least all the
1205 supported COFF targets. It should be straightforward if time and disk
1206 space consuming. For each target:
1208 2) generate some executable, and link it using -r (I would
1209 probably use paranoia.o and link against newlib/libc.a, which
1210 for all the supported targets would be available in
1211 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1212 3) make the change to reloc.c
1213 4) rebuild the linker
1215 6) if the resulting object files are the same, you have at least
1217 7) if they are different you have to figure out which version is
1219 relocation
-= reloc_entry
->addend
;
1220 /* FIXME: There should be no target specific code here... */
1221 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1222 reloc_entry
->addend
= 0;
1226 reloc_entry
->addend
= relocation
;
1230 /* FIXME: This overflow checking is incomplete, because the value
1231 might have overflowed before we get here. For a correct check we
1232 need to compute the value in a size larger than bitsize, but we
1233 can't reasonably do that for a reloc the same size as a host
1235 FIXME: We should also do overflow checking on the result after
1236 adding in the value contained in the object file. */
1237 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1238 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1241 bfd_arch_bits_per_address (abfd
),
1244 /* Either we are relocating all the way, or we don't want to apply
1245 the relocation to the reloc entry (probably because there isn't
1246 any room in the output format to describe addends to relocs). */
1248 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1249 (OSF version 1.3, compiler version 3.11). It miscompiles the
1263 x <<= (unsigned long) s.i0;
1265 printf ("failed\n");
1267 printf ("succeeded (%lx)\n", x);
1271 relocation
>>= (bfd_vma
) howto
->rightshift
;
1273 /* Shift everything up to where it's going to be used. */
1274 relocation
<<= (bfd_vma
) howto
->bitpos
;
1276 /* Wait for the day when all have the mask in them. */
1279 i instruction to be left alone
1280 o offset within instruction
1281 r relocation offset to apply
1290 (( i i i i i o o o o o from bfd_get<size>
1291 and S S S S S) to get the size offset we want
1292 + r r r r r r r r r r) to get the final value to place
1293 and D D D D D to chop to right size
1294 -----------------------
1297 ( i i i i i o o o o o from bfd_get<size>
1298 and N N N N N ) get instruction
1299 -----------------------
1305 -----------------------
1306 = R R R R R R R R R R put into bfd_put<size>
1309 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1310 apply_reloc (abfd
, data
, howto
, relocation
);
1314 /* This relocation routine is used by some of the backend linkers.
1315 They do not construct asymbol or arelent structures, so there is no
1316 reason for them to use bfd_perform_relocation. Also,
1317 bfd_perform_relocation is so hacked up it is easier to write a new
1318 function than to try to deal with it.
1320 This routine does a final relocation. Whether it is useful for a
1321 relocatable link depends upon how the object format defines
1324 FIXME: This routine ignores any special_function in the HOWTO,
1325 since the existing special_function values have been written for
1326 bfd_perform_relocation.
1328 HOWTO is the reloc howto information.
1329 INPUT_BFD is the BFD which the reloc applies to.
1330 INPUT_SECTION is the section which the reloc applies to.
1331 CONTENTS is the contents of the section.
1332 ADDRESS is the address of the reloc within INPUT_SECTION.
1333 VALUE is the value of the symbol the reloc refers to.
1334 ADDEND is the addend of the reloc. */
1336 bfd_reloc_status_type
1337 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1339 asection
*input_section
,
1346 bfd_size_type octets
= address
* bfd_octets_per_byte (input_bfd
);
1348 /* Sanity check the address. */
1349 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1350 return bfd_reloc_outofrange
;
1352 /* This function assumes that we are dealing with a basic relocation
1353 against a symbol. We want to compute the value of the symbol to
1354 relocate to. This is just VALUE, the value of the symbol, plus
1355 ADDEND, any addend associated with the reloc. */
1356 relocation
= value
+ addend
;
1358 /* If the relocation is PC relative, we want to set RELOCATION to
1359 the distance between the symbol (currently in RELOCATION) and the
1360 location we are relocating. Some targets (e.g., i386-aout)
1361 arrange for the contents of the section to be the negative of the
1362 offset of the location within the section; for such targets
1363 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1364 the contents of the section as zero; for such targets
1365 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1366 subtract out the offset of the location within the section (which
1367 is just ADDRESS). */
1368 if (howto
->pc_relative
)
1370 relocation
-= (input_section
->output_section
->vma
1371 + input_section
->output_offset
);
1372 if (howto
->pcrel_offset
)
1373 relocation
-= address
;
1376 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1378 + address
* bfd_octets_per_byte (input_bfd
));
1381 /* Relocate a given location using a given value and howto. */
1383 bfd_reloc_status_type
1384 _bfd_relocate_contents (reloc_howto_type
*howto
,
1390 bfd_reloc_status_type flag
;
1391 unsigned int rightshift
= howto
->rightshift
;
1392 unsigned int bitpos
= howto
->bitpos
;
1394 /* If the size is negative, negate RELOCATION. This isn't very
1396 if (howto
->size
< 0)
1397 relocation
= -relocation
;
1399 /* Get the value we are going to relocate. */
1400 x
= read_reloc (input_bfd
, location
, howto
);
1402 /* Check for overflow. FIXME: We may drop bits during the addition
1403 which we don't check for. We must either check at every single
1404 operation, which would be tedious, or we must do the computations
1405 in a type larger than bfd_vma, which would be inefficient. */
1406 flag
= bfd_reloc_ok
;
1407 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1409 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1412 /* Get the values to be added together. For signed and unsigned
1413 relocations, we assume that all values should be truncated to
1414 the size of an address. For bitfields, all the bits matter.
1415 See also bfd_check_overflow. */
1416 fieldmask
= N_ONES (howto
->bitsize
);
1417 signmask
= ~fieldmask
;
1418 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1419 | (fieldmask
<< rightshift
));
1420 a
= (relocation
& addrmask
) >> rightshift
;
1421 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1422 addrmask
>>= rightshift
;
1424 switch (howto
->complain_on_overflow
)
1426 case complain_overflow_signed
:
1427 /* If any sign bits are set, all sign bits must be set.
1428 That is, A must be a valid negative address after
1430 signmask
= ~(fieldmask
>> 1);
1433 case complain_overflow_bitfield
:
1434 /* Much like the signed check, but for a field one bit
1435 wider. We allow a bitfield to represent numbers in the
1436 range -2**n to 2**n-1, where n is the number of bits in the
1437 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1438 can't overflow, which is exactly what we want. */
1440 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1441 flag
= bfd_reloc_overflow
;
1443 /* We only need this next bit of code if the sign bit of B
1444 is below the sign bit of A. This would only happen if
1445 SRC_MASK had fewer bits than BITSIZE. Note that if
1446 SRC_MASK has more bits than BITSIZE, we can get into
1447 trouble; we would need to verify that B is in range, as
1448 we do for A above. */
1449 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1452 /* Set all the bits above the sign bit. */
1455 /* Now we can do the addition. */
1458 /* See if the result has the correct sign. Bits above the
1459 sign bit are junk now; ignore them. If the sum is
1460 positive, make sure we did not have all negative inputs;
1461 if the sum is negative, make sure we did not have all
1462 positive inputs. The test below looks only at the sign
1463 bits, and it really just
1464 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1466 We mask with addrmask here to explicitly allow an address
1467 wrap-around. The Linux kernel relies on it, and it is
1468 the only way to write assembler code which can run when
1469 loaded at a location 0x80000000 away from the location at
1470 which it is linked. */
1471 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1472 flag
= bfd_reloc_overflow
;
1475 case complain_overflow_unsigned
:
1476 /* Checking for an unsigned overflow is relatively easy:
1477 trim the addresses and add, and trim the result as well.
1478 Overflow is normally indicated when the result does not
1479 fit in the field. However, we also need to consider the
1480 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1481 input is 0x80000000, and bfd_vma is only 32 bits; then we
1482 will get sum == 0, but there is an overflow, since the
1483 inputs did not fit in the field. Instead of doing a
1484 separate test, we can check for this by or-ing in the
1485 operands when testing for the sum overflowing its final
1487 sum
= (a
+ b
) & addrmask
;
1488 if ((a
| b
| sum
) & signmask
)
1489 flag
= bfd_reloc_overflow
;
1497 /* Put RELOCATION in the right bits. */
1498 relocation
>>= (bfd_vma
) rightshift
;
1499 relocation
<<= (bfd_vma
) bitpos
;
1501 /* Add RELOCATION to the right bits of X. */
1502 x
= ((x
& ~howto
->dst_mask
)
1503 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1505 /* Put the relocated value back in the object file. */
1506 write_reloc (input_bfd
, x
, location
, howto
);
1510 /* Clear a given location using a given howto, by applying a fixed relocation
1511 value and discarding any in-place addend. This is used for fixed-up
1512 relocations against discarded symbols, to make ignorable debug or unwind
1513 information more obvious. */
1516 _bfd_clear_contents (reloc_howto_type
*howto
,
1518 asection
*input_section
,
1523 /* Get the value we are going to relocate. */
1524 x
= read_reloc (input_bfd
, location
, howto
);
1526 /* Zero out the unwanted bits of X. */
1527 x
&= ~howto
->dst_mask
;
1529 /* For a range list, use 1 instead of 0 as placeholder. 0
1530 would terminate the list, hiding any later entries. */
1531 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1532 ".debug_ranges") == 0
1533 && (howto
->dst_mask
& 1) != 0)
1536 /* Put the relocated value back in the object file. */
1537 write_reloc (input_bfd
, x
, location
, howto
);
1543 howto manager, , typedef arelent, Relocations
1548 When an application wants to create a relocation, but doesn't
1549 know what the target machine might call it, it can find out by
1550 using this bit of code.
1559 The insides of a reloc code. The idea is that, eventually, there
1560 will be one enumerator for every type of relocation we ever do.
1561 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1562 return a howto pointer.
1564 This does mean that the application must determine the correct
1565 enumerator value; you can't get a howto pointer from a random set
1586 Basic absolute relocations of N bits.
1601 PC-relative relocations. Sometimes these are relative to the address
1602 of the relocation itself; sometimes they are relative to the start of
1603 the section containing the relocation. It depends on the specific target.
1608 Section relative relocations. Some targets need this for DWARF2.
1611 BFD_RELOC_32_GOT_PCREL
1613 BFD_RELOC_16_GOT_PCREL
1615 BFD_RELOC_8_GOT_PCREL
1621 BFD_RELOC_LO16_GOTOFF
1623 BFD_RELOC_HI16_GOTOFF
1625 BFD_RELOC_HI16_S_GOTOFF
1629 BFD_RELOC_64_PLT_PCREL
1631 BFD_RELOC_32_PLT_PCREL
1633 BFD_RELOC_24_PLT_PCREL
1635 BFD_RELOC_16_PLT_PCREL
1637 BFD_RELOC_8_PLT_PCREL
1645 BFD_RELOC_LO16_PLTOFF
1647 BFD_RELOC_HI16_PLTOFF
1649 BFD_RELOC_HI16_S_PLTOFF
1663 BFD_RELOC_68K_GLOB_DAT
1665 BFD_RELOC_68K_JMP_SLOT
1667 BFD_RELOC_68K_RELATIVE
1669 BFD_RELOC_68K_TLS_GD32
1671 BFD_RELOC_68K_TLS_GD16
1673 BFD_RELOC_68K_TLS_GD8
1675 BFD_RELOC_68K_TLS_LDM32
1677 BFD_RELOC_68K_TLS_LDM16
1679 BFD_RELOC_68K_TLS_LDM8
1681 BFD_RELOC_68K_TLS_LDO32
1683 BFD_RELOC_68K_TLS_LDO16
1685 BFD_RELOC_68K_TLS_LDO8
1687 BFD_RELOC_68K_TLS_IE32
1689 BFD_RELOC_68K_TLS_IE16
1691 BFD_RELOC_68K_TLS_IE8
1693 BFD_RELOC_68K_TLS_LE32
1695 BFD_RELOC_68K_TLS_LE16
1697 BFD_RELOC_68K_TLS_LE8
1699 Relocations used by 68K ELF.
1702 BFD_RELOC_32_BASEREL
1704 BFD_RELOC_16_BASEREL
1706 BFD_RELOC_LO16_BASEREL
1708 BFD_RELOC_HI16_BASEREL
1710 BFD_RELOC_HI16_S_BASEREL
1716 Linkage-table relative.
1721 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1724 BFD_RELOC_32_PCREL_S2
1726 BFD_RELOC_16_PCREL_S2
1728 BFD_RELOC_23_PCREL_S2
1730 These PC-relative relocations are stored as word displacements --
1731 i.e., byte displacements shifted right two bits. The 30-bit word
1732 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1733 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1734 signed 16-bit displacement is used on the MIPS, and the 23-bit
1735 displacement is used on the Alpha.
1742 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1743 the target word. These are used on the SPARC.
1750 For systems that allocate a Global Pointer register, these are
1751 displacements off that register. These relocation types are
1752 handled specially, because the value the register will have is
1753 decided relatively late.
1758 BFD_RELOC_SPARC_WDISP22
1764 BFD_RELOC_SPARC_GOT10
1766 BFD_RELOC_SPARC_GOT13
1768 BFD_RELOC_SPARC_GOT22
1770 BFD_RELOC_SPARC_PC10
1772 BFD_RELOC_SPARC_PC22
1774 BFD_RELOC_SPARC_WPLT30
1776 BFD_RELOC_SPARC_COPY
1778 BFD_RELOC_SPARC_GLOB_DAT
1780 BFD_RELOC_SPARC_JMP_SLOT
1782 BFD_RELOC_SPARC_RELATIVE
1784 BFD_RELOC_SPARC_UA16
1786 BFD_RELOC_SPARC_UA32
1788 BFD_RELOC_SPARC_UA64
1790 BFD_RELOC_SPARC_GOTDATA_HIX22
1792 BFD_RELOC_SPARC_GOTDATA_LOX10
1794 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1796 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1798 BFD_RELOC_SPARC_GOTDATA_OP
1800 BFD_RELOC_SPARC_JMP_IREL
1802 BFD_RELOC_SPARC_IRELATIVE
1804 SPARC ELF relocations. There is probably some overlap with other
1805 relocation types already defined.
1808 BFD_RELOC_SPARC_BASE13
1810 BFD_RELOC_SPARC_BASE22
1812 I think these are specific to SPARC a.out (e.g., Sun 4).
1822 BFD_RELOC_SPARC_OLO10
1824 BFD_RELOC_SPARC_HH22
1826 BFD_RELOC_SPARC_HM10
1828 BFD_RELOC_SPARC_LM22
1830 BFD_RELOC_SPARC_PC_HH22
1832 BFD_RELOC_SPARC_PC_HM10
1834 BFD_RELOC_SPARC_PC_LM22
1836 BFD_RELOC_SPARC_WDISP16
1838 BFD_RELOC_SPARC_WDISP19
1846 BFD_RELOC_SPARC_DISP64
1849 BFD_RELOC_SPARC_PLT32
1851 BFD_RELOC_SPARC_PLT64
1853 BFD_RELOC_SPARC_HIX22
1855 BFD_RELOC_SPARC_LOX10
1863 BFD_RELOC_SPARC_REGISTER
1867 BFD_RELOC_SPARC_SIZE32
1869 BFD_RELOC_SPARC_SIZE64
1871 BFD_RELOC_SPARC_WDISP10
1876 BFD_RELOC_SPARC_REV32
1878 SPARC little endian relocation
1880 BFD_RELOC_SPARC_TLS_GD_HI22
1882 BFD_RELOC_SPARC_TLS_GD_LO10
1884 BFD_RELOC_SPARC_TLS_GD_ADD
1886 BFD_RELOC_SPARC_TLS_GD_CALL
1888 BFD_RELOC_SPARC_TLS_LDM_HI22
1890 BFD_RELOC_SPARC_TLS_LDM_LO10
1892 BFD_RELOC_SPARC_TLS_LDM_ADD
1894 BFD_RELOC_SPARC_TLS_LDM_CALL
1896 BFD_RELOC_SPARC_TLS_LDO_HIX22
1898 BFD_RELOC_SPARC_TLS_LDO_LOX10
1900 BFD_RELOC_SPARC_TLS_LDO_ADD
1902 BFD_RELOC_SPARC_TLS_IE_HI22
1904 BFD_RELOC_SPARC_TLS_IE_LO10
1906 BFD_RELOC_SPARC_TLS_IE_LD
1908 BFD_RELOC_SPARC_TLS_IE_LDX
1910 BFD_RELOC_SPARC_TLS_IE_ADD
1912 BFD_RELOC_SPARC_TLS_LE_HIX22
1914 BFD_RELOC_SPARC_TLS_LE_LOX10
1916 BFD_RELOC_SPARC_TLS_DTPMOD32
1918 BFD_RELOC_SPARC_TLS_DTPMOD64
1920 BFD_RELOC_SPARC_TLS_DTPOFF32
1922 BFD_RELOC_SPARC_TLS_DTPOFF64
1924 BFD_RELOC_SPARC_TLS_TPOFF32
1926 BFD_RELOC_SPARC_TLS_TPOFF64
1928 SPARC TLS relocations
1937 BFD_RELOC_SPU_IMM10W
1941 BFD_RELOC_SPU_IMM16W
1945 BFD_RELOC_SPU_PCREL9a
1947 BFD_RELOC_SPU_PCREL9b
1949 BFD_RELOC_SPU_PCREL16
1959 BFD_RELOC_SPU_ADD_PIC
1964 BFD_RELOC_ALPHA_GPDISP_HI16
1966 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1967 "addend" in some special way.
1968 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1969 writing; when reading, it will be the absolute section symbol. The
1970 addend is the displacement in bytes of the "lda" instruction from
1971 the "ldah" instruction (which is at the address of this reloc).
1973 BFD_RELOC_ALPHA_GPDISP_LO16
1975 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1976 with GPDISP_HI16 relocs. The addend is ignored when writing the
1977 relocations out, and is filled in with the file's GP value on
1978 reading, for convenience.
1981 BFD_RELOC_ALPHA_GPDISP
1983 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1984 relocation except that there is no accompanying GPDISP_LO16
1988 BFD_RELOC_ALPHA_LITERAL
1990 BFD_RELOC_ALPHA_ELF_LITERAL
1992 BFD_RELOC_ALPHA_LITUSE
1994 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1995 the assembler turns it into a LDQ instruction to load the address of
1996 the symbol, and then fills in a register in the real instruction.
1998 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1999 section symbol. The addend is ignored when writing, but is filled
2000 in with the file's GP value on reading, for convenience, as with the
2003 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2004 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2005 but it generates output not based on the position within the .got
2006 section, but relative to the GP value chosen for the file during the
2009 The LITUSE reloc, on the instruction using the loaded address, gives
2010 information to the linker that it might be able to use to optimize
2011 away some literal section references. The symbol is ignored (read
2012 as the absolute section symbol), and the "addend" indicates the type
2013 of instruction using the register:
2014 1 - "memory" fmt insn
2015 2 - byte-manipulation (byte offset reg)
2016 3 - jsr (target of branch)
2019 BFD_RELOC_ALPHA_HINT
2021 The HINT relocation indicates a value that should be filled into the
2022 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2023 prediction logic which may be provided on some processors.
2026 BFD_RELOC_ALPHA_LINKAGE
2028 The LINKAGE relocation outputs a linkage pair in the object file,
2029 which is filled by the linker.
2032 BFD_RELOC_ALPHA_CODEADDR
2034 The CODEADDR relocation outputs a STO_CA in the object file,
2035 which is filled by the linker.
2038 BFD_RELOC_ALPHA_GPREL_HI16
2040 BFD_RELOC_ALPHA_GPREL_LO16
2042 The GPREL_HI/LO relocations together form a 32-bit offset from the
2046 BFD_RELOC_ALPHA_BRSGP
2048 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2049 share a common GP, and the target address is adjusted for
2050 STO_ALPHA_STD_GPLOAD.
2055 The NOP relocation outputs a NOP if the longword displacement
2056 between two procedure entry points is < 2^21.
2061 The BSR relocation outputs a BSR if the longword displacement
2062 between two procedure entry points is < 2^21.
2067 The LDA relocation outputs a LDA if the longword displacement
2068 between two procedure entry points is < 2^16.
2073 The BOH relocation outputs a BSR if the longword displacement
2074 between two procedure entry points is < 2^21, or else a hint.
2077 BFD_RELOC_ALPHA_TLSGD
2079 BFD_RELOC_ALPHA_TLSLDM
2081 BFD_RELOC_ALPHA_DTPMOD64
2083 BFD_RELOC_ALPHA_GOTDTPREL16
2085 BFD_RELOC_ALPHA_DTPREL64
2087 BFD_RELOC_ALPHA_DTPREL_HI16
2089 BFD_RELOC_ALPHA_DTPREL_LO16
2091 BFD_RELOC_ALPHA_DTPREL16
2093 BFD_RELOC_ALPHA_GOTTPREL16
2095 BFD_RELOC_ALPHA_TPREL64
2097 BFD_RELOC_ALPHA_TPREL_HI16
2099 BFD_RELOC_ALPHA_TPREL_LO16
2101 BFD_RELOC_ALPHA_TPREL16
2103 Alpha thread-local storage relocations.
2108 BFD_RELOC_MICROMIPS_JMP
2110 The MIPS jump instruction.
2113 BFD_RELOC_MIPS16_JMP
2115 The MIPS16 jump instruction.
2118 BFD_RELOC_MIPS16_GPREL
2120 MIPS16 GP relative reloc.
2125 High 16 bits of 32-bit value; simple reloc.
2130 High 16 bits of 32-bit value but the low 16 bits will be sign
2131 extended and added to form the final result. If the low 16
2132 bits form a negative number, we need to add one to the high value
2133 to compensate for the borrow when the low bits are added.
2141 BFD_RELOC_HI16_PCREL
2143 High 16 bits of 32-bit pc-relative value
2145 BFD_RELOC_HI16_S_PCREL
2147 High 16 bits of 32-bit pc-relative value, adjusted
2149 BFD_RELOC_LO16_PCREL
2151 Low 16 bits of pc-relative value
2154 BFD_RELOC_MIPS16_GOT16
2156 BFD_RELOC_MIPS16_CALL16
2158 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2159 16-bit immediate fields
2161 BFD_RELOC_MIPS16_HI16
2163 MIPS16 high 16 bits of 32-bit value.
2165 BFD_RELOC_MIPS16_HI16_S
2167 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2168 extended and added to form the final result. If the low 16
2169 bits form a negative number, we need to add one to the high value
2170 to compensate for the borrow when the low bits are added.
2172 BFD_RELOC_MIPS16_LO16
2177 BFD_RELOC_MIPS16_TLS_GD
2179 BFD_RELOC_MIPS16_TLS_LDM
2181 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2183 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2185 BFD_RELOC_MIPS16_TLS_GOTTPREL
2187 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2189 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2191 MIPS16 TLS relocations
2194 BFD_RELOC_MIPS_LITERAL
2196 BFD_RELOC_MICROMIPS_LITERAL
2198 Relocation against a MIPS literal section.
2201 BFD_RELOC_MICROMIPS_7_PCREL_S1
2203 BFD_RELOC_MICROMIPS_10_PCREL_S1
2205 BFD_RELOC_MICROMIPS_16_PCREL_S1
2207 microMIPS PC-relative relocations.
2210 BFD_RELOC_MIPS16_16_PCREL_S1
2212 MIPS16 PC-relative relocation.
2215 BFD_RELOC_MIPS_21_PCREL_S2
2217 BFD_RELOC_MIPS_26_PCREL_S2
2219 BFD_RELOC_MIPS_18_PCREL_S3
2221 BFD_RELOC_MIPS_19_PCREL_S2
2223 MIPS PC-relative relocations.
2226 BFD_RELOC_MICROMIPS_GPREL16
2228 BFD_RELOC_MICROMIPS_HI16
2230 BFD_RELOC_MICROMIPS_HI16_S
2232 BFD_RELOC_MICROMIPS_LO16
2234 microMIPS versions of generic BFD relocs.
2237 BFD_RELOC_MIPS_GOT16
2239 BFD_RELOC_MICROMIPS_GOT16
2241 BFD_RELOC_MIPS_CALL16
2243 BFD_RELOC_MICROMIPS_CALL16
2245 BFD_RELOC_MIPS_GOT_HI16
2247 BFD_RELOC_MICROMIPS_GOT_HI16
2249 BFD_RELOC_MIPS_GOT_LO16
2251 BFD_RELOC_MICROMIPS_GOT_LO16
2253 BFD_RELOC_MIPS_CALL_HI16
2255 BFD_RELOC_MICROMIPS_CALL_HI16
2257 BFD_RELOC_MIPS_CALL_LO16
2259 BFD_RELOC_MICROMIPS_CALL_LO16
2263 BFD_RELOC_MICROMIPS_SUB
2265 BFD_RELOC_MIPS_GOT_PAGE
2267 BFD_RELOC_MICROMIPS_GOT_PAGE
2269 BFD_RELOC_MIPS_GOT_OFST
2271 BFD_RELOC_MICROMIPS_GOT_OFST
2273 BFD_RELOC_MIPS_GOT_DISP
2275 BFD_RELOC_MICROMIPS_GOT_DISP
2277 BFD_RELOC_MIPS_SHIFT5
2279 BFD_RELOC_MIPS_SHIFT6
2281 BFD_RELOC_MIPS_INSERT_A
2283 BFD_RELOC_MIPS_INSERT_B
2285 BFD_RELOC_MIPS_DELETE
2287 BFD_RELOC_MIPS_HIGHEST
2289 BFD_RELOC_MICROMIPS_HIGHEST
2291 BFD_RELOC_MIPS_HIGHER
2293 BFD_RELOC_MICROMIPS_HIGHER
2295 BFD_RELOC_MIPS_SCN_DISP
2297 BFD_RELOC_MICROMIPS_SCN_DISP
2299 BFD_RELOC_MIPS_REL16
2301 BFD_RELOC_MIPS_RELGOT
2305 BFD_RELOC_MICROMIPS_JALR
2307 BFD_RELOC_MIPS_TLS_DTPMOD32
2309 BFD_RELOC_MIPS_TLS_DTPREL32
2311 BFD_RELOC_MIPS_TLS_DTPMOD64
2313 BFD_RELOC_MIPS_TLS_DTPREL64
2315 BFD_RELOC_MIPS_TLS_GD
2317 BFD_RELOC_MICROMIPS_TLS_GD
2319 BFD_RELOC_MIPS_TLS_LDM
2321 BFD_RELOC_MICROMIPS_TLS_LDM
2323 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2325 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2327 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2329 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2331 BFD_RELOC_MIPS_TLS_GOTTPREL
2333 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2335 BFD_RELOC_MIPS_TLS_TPREL32
2337 BFD_RELOC_MIPS_TLS_TPREL64
2339 BFD_RELOC_MIPS_TLS_TPREL_HI16
2341 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2343 BFD_RELOC_MIPS_TLS_TPREL_LO16
2345 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2349 MIPS ELF relocations.
2355 BFD_RELOC_MIPS_JUMP_SLOT
2357 MIPS ELF relocations (VxWorks and PLT extensions).
2361 BFD_RELOC_MOXIE_10_PCREL
2363 Moxie ELF relocations.
2375 BFD_RELOC_FT32_RELAX
2383 BFD_RELOC_FT32_DIFF32
2385 FT32 ELF relocations.
2389 BFD_RELOC_FRV_LABEL16
2391 BFD_RELOC_FRV_LABEL24
2397 BFD_RELOC_FRV_GPREL12
2399 BFD_RELOC_FRV_GPRELU12
2401 BFD_RELOC_FRV_GPREL32
2403 BFD_RELOC_FRV_GPRELHI
2405 BFD_RELOC_FRV_GPRELLO
2413 BFD_RELOC_FRV_FUNCDESC
2415 BFD_RELOC_FRV_FUNCDESC_GOT12
2417 BFD_RELOC_FRV_FUNCDESC_GOTHI
2419 BFD_RELOC_FRV_FUNCDESC_GOTLO
2421 BFD_RELOC_FRV_FUNCDESC_VALUE
2423 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2425 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2427 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2429 BFD_RELOC_FRV_GOTOFF12
2431 BFD_RELOC_FRV_GOTOFFHI
2433 BFD_RELOC_FRV_GOTOFFLO
2435 BFD_RELOC_FRV_GETTLSOFF
2437 BFD_RELOC_FRV_TLSDESC_VALUE
2439 BFD_RELOC_FRV_GOTTLSDESC12
2441 BFD_RELOC_FRV_GOTTLSDESCHI
2443 BFD_RELOC_FRV_GOTTLSDESCLO
2445 BFD_RELOC_FRV_TLSMOFF12
2447 BFD_RELOC_FRV_TLSMOFFHI
2449 BFD_RELOC_FRV_TLSMOFFLO
2451 BFD_RELOC_FRV_GOTTLSOFF12
2453 BFD_RELOC_FRV_GOTTLSOFFHI
2455 BFD_RELOC_FRV_GOTTLSOFFLO
2457 BFD_RELOC_FRV_TLSOFF
2459 BFD_RELOC_FRV_TLSDESC_RELAX
2461 BFD_RELOC_FRV_GETTLSOFF_RELAX
2463 BFD_RELOC_FRV_TLSOFF_RELAX
2465 BFD_RELOC_FRV_TLSMOFF
2467 Fujitsu Frv Relocations.
2471 BFD_RELOC_MN10300_GOTOFF24
2473 This is a 24bit GOT-relative reloc for the mn10300.
2475 BFD_RELOC_MN10300_GOT32
2477 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2480 BFD_RELOC_MN10300_GOT24
2482 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2485 BFD_RELOC_MN10300_GOT16
2487 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2490 BFD_RELOC_MN10300_COPY
2492 Copy symbol at runtime.
2494 BFD_RELOC_MN10300_GLOB_DAT
2498 BFD_RELOC_MN10300_JMP_SLOT
2502 BFD_RELOC_MN10300_RELATIVE
2504 Adjust by program base.
2506 BFD_RELOC_MN10300_SYM_DIFF
2508 Together with another reloc targeted at the same location,
2509 allows for a value that is the difference of two symbols
2510 in the same section.
2512 BFD_RELOC_MN10300_ALIGN
2514 The addend of this reloc is an alignment power that must
2515 be honoured at the offset's location, regardless of linker
2518 BFD_RELOC_MN10300_TLS_GD
2520 BFD_RELOC_MN10300_TLS_LD
2522 BFD_RELOC_MN10300_TLS_LDO
2524 BFD_RELOC_MN10300_TLS_GOTIE
2526 BFD_RELOC_MN10300_TLS_IE
2528 BFD_RELOC_MN10300_TLS_LE
2530 BFD_RELOC_MN10300_TLS_DTPMOD
2532 BFD_RELOC_MN10300_TLS_DTPOFF
2534 BFD_RELOC_MN10300_TLS_TPOFF
2536 Various TLS-related relocations.
2538 BFD_RELOC_MN10300_32_PCREL
2540 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2543 BFD_RELOC_MN10300_16_PCREL
2545 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2556 BFD_RELOC_386_GLOB_DAT
2558 BFD_RELOC_386_JUMP_SLOT
2560 BFD_RELOC_386_RELATIVE
2562 BFD_RELOC_386_GOTOFF
2566 BFD_RELOC_386_TLS_TPOFF
2568 BFD_RELOC_386_TLS_IE
2570 BFD_RELOC_386_TLS_GOTIE
2572 BFD_RELOC_386_TLS_LE
2574 BFD_RELOC_386_TLS_GD
2576 BFD_RELOC_386_TLS_LDM
2578 BFD_RELOC_386_TLS_LDO_32
2580 BFD_RELOC_386_TLS_IE_32
2582 BFD_RELOC_386_TLS_LE_32
2584 BFD_RELOC_386_TLS_DTPMOD32
2586 BFD_RELOC_386_TLS_DTPOFF32
2588 BFD_RELOC_386_TLS_TPOFF32
2590 BFD_RELOC_386_TLS_GOTDESC
2592 BFD_RELOC_386_TLS_DESC_CALL
2594 BFD_RELOC_386_TLS_DESC
2596 BFD_RELOC_386_IRELATIVE
2598 BFD_RELOC_386_GOT32X
2600 i386/elf relocations
2603 BFD_RELOC_X86_64_GOT32
2605 BFD_RELOC_X86_64_PLT32
2607 BFD_RELOC_X86_64_COPY
2609 BFD_RELOC_X86_64_GLOB_DAT
2611 BFD_RELOC_X86_64_JUMP_SLOT
2613 BFD_RELOC_X86_64_RELATIVE
2615 BFD_RELOC_X86_64_GOTPCREL
2617 BFD_RELOC_X86_64_32S
2619 BFD_RELOC_X86_64_DTPMOD64
2621 BFD_RELOC_X86_64_DTPOFF64
2623 BFD_RELOC_X86_64_TPOFF64
2625 BFD_RELOC_X86_64_TLSGD
2627 BFD_RELOC_X86_64_TLSLD
2629 BFD_RELOC_X86_64_DTPOFF32
2631 BFD_RELOC_X86_64_GOTTPOFF
2633 BFD_RELOC_X86_64_TPOFF32
2635 BFD_RELOC_X86_64_GOTOFF64
2637 BFD_RELOC_X86_64_GOTPC32
2639 BFD_RELOC_X86_64_GOT64
2641 BFD_RELOC_X86_64_GOTPCREL64
2643 BFD_RELOC_X86_64_GOTPC64
2645 BFD_RELOC_X86_64_GOTPLT64
2647 BFD_RELOC_X86_64_PLTOFF64
2649 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2651 BFD_RELOC_X86_64_TLSDESC_CALL
2653 BFD_RELOC_X86_64_TLSDESC
2655 BFD_RELOC_X86_64_IRELATIVE
2657 BFD_RELOC_X86_64_PC32_BND
2659 BFD_RELOC_X86_64_PLT32_BND
2661 BFD_RELOC_X86_64_GOTPCRELX
2663 BFD_RELOC_X86_64_REX_GOTPCRELX
2665 x86-64/elf relocations
2668 BFD_RELOC_NS32K_IMM_8
2670 BFD_RELOC_NS32K_IMM_16
2672 BFD_RELOC_NS32K_IMM_32
2674 BFD_RELOC_NS32K_IMM_8_PCREL
2676 BFD_RELOC_NS32K_IMM_16_PCREL
2678 BFD_RELOC_NS32K_IMM_32_PCREL
2680 BFD_RELOC_NS32K_DISP_8
2682 BFD_RELOC_NS32K_DISP_16
2684 BFD_RELOC_NS32K_DISP_32
2686 BFD_RELOC_NS32K_DISP_8_PCREL
2688 BFD_RELOC_NS32K_DISP_16_PCREL
2690 BFD_RELOC_NS32K_DISP_32_PCREL
2695 BFD_RELOC_PDP11_DISP_8_PCREL
2697 BFD_RELOC_PDP11_DISP_6_PCREL
2702 BFD_RELOC_PJ_CODE_HI16
2704 BFD_RELOC_PJ_CODE_LO16
2706 BFD_RELOC_PJ_CODE_DIR16
2708 BFD_RELOC_PJ_CODE_DIR32
2710 BFD_RELOC_PJ_CODE_REL16
2712 BFD_RELOC_PJ_CODE_REL32
2714 Picojava relocs. Not all of these appear in object files.
2725 BFD_RELOC_PPC_B16_BRTAKEN
2727 BFD_RELOC_PPC_B16_BRNTAKEN
2731 BFD_RELOC_PPC_BA16_BRTAKEN
2733 BFD_RELOC_PPC_BA16_BRNTAKEN
2737 BFD_RELOC_PPC_GLOB_DAT
2739 BFD_RELOC_PPC_JMP_SLOT
2741 BFD_RELOC_PPC_RELATIVE
2743 BFD_RELOC_PPC_LOCAL24PC
2745 BFD_RELOC_PPC_EMB_NADDR32
2747 BFD_RELOC_PPC_EMB_NADDR16
2749 BFD_RELOC_PPC_EMB_NADDR16_LO
2751 BFD_RELOC_PPC_EMB_NADDR16_HI
2753 BFD_RELOC_PPC_EMB_NADDR16_HA
2755 BFD_RELOC_PPC_EMB_SDAI16
2757 BFD_RELOC_PPC_EMB_SDA2I16
2759 BFD_RELOC_PPC_EMB_SDA2REL
2761 BFD_RELOC_PPC_EMB_SDA21
2763 BFD_RELOC_PPC_EMB_MRKREF
2765 BFD_RELOC_PPC_EMB_RELSEC16
2767 BFD_RELOC_PPC_EMB_RELST_LO
2769 BFD_RELOC_PPC_EMB_RELST_HI
2771 BFD_RELOC_PPC_EMB_RELST_HA
2773 BFD_RELOC_PPC_EMB_BIT_FLD
2775 BFD_RELOC_PPC_EMB_RELSDA
2777 BFD_RELOC_PPC_VLE_REL8
2779 BFD_RELOC_PPC_VLE_REL15
2781 BFD_RELOC_PPC_VLE_REL24
2783 BFD_RELOC_PPC_VLE_LO16A
2785 BFD_RELOC_PPC_VLE_LO16D
2787 BFD_RELOC_PPC_VLE_HI16A
2789 BFD_RELOC_PPC_VLE_HI16D
2791 BFD_RELOC_PPC_VLE_HA16A
2793 BFD_RELOC_PPC_VLE_HA16D
2795 BFD_RELOC_PPC_VLE_SDA21
2797 BFD_RELOC_PPC_VLE_SDA21_LO
2799 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2801 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2803 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2805 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2807 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2809 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2811 BFD_RELOC_PPC_16DX_HA
2813 BFD_RELOC_PPC_REL16DX_HA
2815 BFD_RELOC_PPC64_HIGHER
2817 BFD_RELOC_PPC64_HIGHER_S
2819 BFD_RELOC_PPC64_HIGHEST
2821 BFD_RELOC_PPC64_HIGHEST_S
2823 BFD_RELOC_PPC64_TOC16_LO
2825 BFD_RELOC_PPC64_TOC16_HI
2827 BFD_RELOC_PPC64_TOC16_HA
2831 BFD_RELOC_PPC64_PLTGOT16
2833 BFD_RELOC_PPC64_PLTGOT16_LO
2835 BFD_RELOC_PPC64_PLTGOT16_HI
2837 BFD_RELOC_PPC64_PLTGOT16_HA
2839 BFD_RELOC_PPC64_ADDR16_DS
2841 BFD_RELOC_PPC64_ADDR16_LO_DS
2843 BFD_RELOC_PPC64_GOT16_DS
2845 BFD_RELOC_PPC64_GOT16_LO_DS
2847 BFD_RELOC_PPC64_PLT16_LO_DS
2849 BFD_RELOC_PPC64_SECTOFF_DS
2851 BFD_RELOC_PPC64_SECTOFF_LO_DS
2853 BFD_RELOC_PPC64_TOC16_DS
2855 BFD_RELOC_PPC64_TOC16_LO_DS
2857 BFD_RELOC_PPC64_PLTGOT16_DS
2859 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2861 BFD_RELOC_PPC64_ADDR16_HIGH
2863 BFD_RELOC_PPC64_ADDR16_HIGHA
2865 BFD_RELOC_PPC64_ADDR64_LOCAL
2867 BFD_RELOC_PPC64_ENTRY
2869 BFD_RELOC_PPC64_REL24_NOTOC
2871 Power(rs6000) and PowerPC relocations.
2880 BFD_RELOC_PPC_DTPMOD
2882 BFD_RELOC_PPC_TPREL16
2884 BFD_RELOC_PPC_TPREL16_LO
2886 BFD_RELOC_PPC_TPREL16_HI
2888 BFD_RELOC_PPC_TPREL16_HA
2892 BFD_RELOC_PPC_DTPREL16
2894 BFD_RELOC_PPC_DTPREL16_LO
2896 BFD_RELOC_PPC_DTPREL16_HI
2898 BFD_RELOC_PPC_DTPREL16_HA
2900 BFD_RELOC_PPC_DTPREL
2902 BFD_RELOC_PPC_GOT_TLSGD16
2904 BFD_RELOC_PPC_GOT_TLSGD16_LO
2906 BFD_RELOC_PPC_GOT_TLSGD16_HI
2908 BFD_RELOC_PPC_GOT_TLSGD16_HA
2910 BFD_RELOC_PPC_GOT_TLSLD16
2912 BFD_RELOC_PPC_GOT_TLSLD16_LO
2914 BFD_RELOC_PPC_GOT_TLSLD16_HI
2916 BFD_RELOC_PPC_GOT_TLSLD16_HA
2918 BFD_RELOC_PPC_GOT_TPREL16
2920 BFD_RELOC_PPC_GOT_TPREL16_LO
2922 BFD_RELOC_PPC_GOT_TPREL16_HI
2924 BFD_RELOC_PPC_GOT_TPREL16_HA
2926 BFD_RELOC_PPC_GOT_DTPREL16
2928 BFD_RELOC_PPC_GOT_DTPREL16_LO
2930 BFD_RELOC_PPC_GOT_DTPREL16_HI
2932 BFD_RELOC_PPC_GOT_DTPREL16_HA
2934 BFD_RELOC_PPC64_TPREL16_DS
2936 BFD_RELOC_PPC64_TPREL16_LO_DS
2938 BFD_RELOC_PPC64_TPREL16_HIGHER
2940 BFD_RELOC_PPC64_TPREL16_HIGHERA
2942 BFD_RELOC_PPC64_TPREL16_HIGHEST
2944 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2946 BFD_RELOC_PPC64_DTPREL16_DS
2948 BFD_RELOC_PPC64_DTPREL16_LO_DS
2950 BFD_RELOC_PPC64_DTPREL16_HIGHER
2952 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2954 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2956 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2958 BFD_RELOC_PPC64_TPREL16_HIGH
2960 BFD_RELOC_PPC64_TPREL16_HIGHA
2962 BFD_RELOC_PPC64_DTPREL16_HIGH
2964 BFD_RELOC_PPC64_DTPREL16_HIGHA
2966 PowerPC and PowerPC64 thread-local storage relocations.
2971 IBM 370/390 relocations
2976 The type of reloc used to build a constructor table - at the moment
2977 probably a 32 bit wide absolute relocation, but the target can choose.
2978 It generally does map to one of the other relocation types.
2981 BFD_RELOC_ARM_PCREL_BRANCH
2983 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
2984 not stored in the instruction.
2986 BFD_RELOC_ARM_PCREL_BLX
2988 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
2989 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2990 field in the instruction.
2992 BFD_RELOC_THUMB_PCREL_BLX
2994 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
2995 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2996 field in the instruction.
2998 BFD_RELOC_ARM_PCREL_CALL
3000 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3002 BFD_RELOC_ARM_PCREL_JUMP
3004 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3007 BFD_RELOC_THUMB_PCREL_BRANCH7
3009 BFD_RELOC_THUMB_PCREL_BRANCH9
3011 BFD_RELOC_THUMB_PCREL_BRANCH12
3013 BFD_RELOC_THUMB_PCREL_BRANCH20
3015 BFD_RELOC_THUMB_PCREL_BRANCH23
3017 BFD_RELOC_THUMB_PCREL_BRANCH25
3019 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3020 The lowest bit must be zero and is not stored in the instruction.
3021 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3022 "nn" one smaller in all cases. Note further that BRANCH23
3023 corresponds to R_ARM_THM_CALL.
3026 BFD_RELOC_ARM_OFFSET_IMM
3028 12-bit immediate offset, used in ARM-format ldr and str instructions.
3031 BFD_RELOC_ARM_THUMB_OFFSET
3033 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3036 BFD_RELOC_ARM_TARGET1
3038 Pc-relative or absolute relocation depending on target. Used for
3039 entries in .init_array sections.
3041 BFD_RELOC_ARM_ROSEGREL32
3043 Read-only segment base relative address.
3045 BFD_RELOC_ARM_SBREL32
3047 Data segment base relative address.
3049 BFD_RELOC_ARM_TARGET2
3051 This reloc is used for references to RTTI data from exception handling
3052 tables. The actual definition depends on the target. It may be a
3053 pc-relative or some form of GOT-indirect relocation.
3055 BFD_RELOC_ARM_PREL31
3057 31-bit PC relative address.
3063 BFD_RELOC_ARM_MOVW_PCREL
3065 BFD_RELOC_ARM_MOVT_PCREL
3067 BFD_RELOC_ARM_THUMB_MOVW
3069 BFD_RELOC_ARM_THUMB_MOVT
3071 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3073 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3075 Low and High halfword relocations for MOVW and MOVT instructions.
3078 BFD_RELOC_ARM_GOTFUNCDESC
3080 BFD_RELOC_ARM_GOTOFFFUNCDESC
3082 BFD_RELOC_ARM_FUNCDESC
3084 BFD_RELOC_ARM_FUNCDESC_VALUE
3086 BFD_RELOC_ARM_TLS_GD32_FDPIC
3088 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3090 BFD_RELOC_ARM_TLS_IE32_FDPIC
3092 ARM FDPIC specific relocations.
3095 BFD_RELOC_ARM_JUMP_SLOT
3097 BFD_RELOC_ARM_GLOB_DAT
3103 BFD_RELOC_ARM_RELATIVE
3105 BFD_RELOC_ARM_GOTOFF
3109 BFD_RELOC_ARM_GOT_PREL
3111 Relocations for setting up GOTs and PLTs for shared libraries.
3114 BFD_RELOC_ARM_TLS_GD32
3116 BFD_RELOC_ARM_TLS_LDO32
3118 BFD_RELOC_ARM_TLS_LDM32
3120 BFD_RELOC_ARM_TLS_DTPOFF32
3122 BFD_RELOC_ARM_TLS_DTPMOD32
3124 BFD_RELOC_ARM_TLS_TPOFF32
3126 BFD_RELOC_ARM_TLS_IE32
3128 BFD_RELOC_ARM_TLS_LE32
3130 BFD_RELOC_ARM_TLS_GOTDESC
3132 BFD_RELOC_ARM_TLS_CALL
3134 BFD_RELOC_ARM_THM_TLS_CALL
3136 BFD_RELOC_ARM_TLS_DESCSEQ
3138 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3140 BFD_RELOC_ARM_TLS_DESC
3142 ARM thread-local storage relocations.
3145 BFD_RELOC_ARM_ALU_PC_G0_NC
3147 BFD_RELOC_ARM_ALU_PC_G0
3149 BFD_RELOC_ARM_ALU_PC_G1_NC
3151 BFD_RELOC_ARM_ALU_PC_G1
3153 BFD_RELOC_ARM_ALU_PC_G2
3155 BFD_RELOC_ARM_LDR_PC_G0
3157 BFD_RELOC_ARM_LDR_PC_G1
3159 BFD_RELOC_ARM_LDR_PC_G2
3161 BFD_RELOC_ARM_LDRS_PC_G0
3163 BFD_RELOC_ARM_LDRS_PC_G1
3165 BFD_RELOC_ARM_LDRS_PC_G2
3167 BFD_RELOC_ARM_LDC_PC_G0
3169 BFD_RELOC_ARM_LDC_PC_G1
3171 BFD_RELOC_ARM_LDC_PC_G2
3173 BFD_RELOC_ARM_ALU_SB_G0_NC
3175 BFD_RELOC_ARM_ALU_SB_G0
3177 BFD_RELOC_ARM_ALU_SB_G1_NC
3179 BFD_RELOC_ARM_ALU_SB_G1
3181 BFD_RELOC_ARM_ALU_SB_G2
3183 BFD_RELOC_ARM_LDR_SB_G0
3185 BFD_RELOC_ARM_LDR_SB_G1
3187 BFD_RELOC_ARM_LDR_SB_G2
3189 BFD_RELOC_ARM_LDRS_SB_G0
3191 BFD_RELOC_ARM_LDRS_SB_G1
3193 BFD_RELOC_ARM_LDRS_SB_G2
3195 BFD_RELOC_ARM_LDC_SB_G0
3197 BFD_RELOC_ARM_LDC_SB_G1
3199 BFD_RELOC_ARM_LDC_SB_G2
3201 ARM group relocations.
3206 Annotation of BX instructions.
3209 BFD_RELOC_ARM_IRELATIVE
3211 ARM support for STT_GNU_IFUNC.
3214 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3216 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3218 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3220 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3222 Thumb1 relocations to support execute-only code.
3225 BFD_RELOC_ARM_IMMEDIATE
3227 BFD_RELOC_ARM_ADRL_IMMEDIATE
3229 BFD_RELOC_ARM_T32_IMMEDIATE
3231 BFD_RELOC_ARM_T32_ADD_IMM
3233 BFD_RELOC_ARM_T32_IMM12
3235 BFD_RELOC_ARM_T32_ADD_PC12
3237 BFD_RELOC_ARM_SHIFT_IMM
3247 BFD_RELOC_ARM_CP_OFF_IMM
3249 BFD_RELOC_ARM_CP_OFF_IMM_S2
3251 BFD_RELOC_ARM_T32_CP_OFF_IMM
3253 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3255 BFD_RELOC_ARM_ADR_IMM
3257 BFD_RELOC_ARM_LDR_IMM
3259 BFD_RELOC_ARM_LITERAL
3261 BFD_RELOC_ARM_IN_POOL
3263 BFD_RELOC_ARM_OFFSET_IMM8
3265 BFD_RELOC_ARM_T32_OFFSET_U8
3267 BFD_RELOC_ARM_T32_OFFSET_IMM
3269 BFD_RELOC_ARM_HWLITERAL
3271 BFD_RELOC_ARM_THUMB_ADD
3273 BFD_RELOC_ARM_THUMB_IMM
3275 BFD_RELOC_ARM_THUMB_SHIFT
3277 These relocs are only used within the ARM assembler. They are not
3278 (at present) written to any object files.
3281 BFD_RELOC_SH_PCDISP8BY2
3283 BFD_RELOC_SH_PCDISP12BY2
3291 BFD_RELOC_SH_DISP12BY2
3293 BFD_RELOC_SH_DISP12BY4
3295 BFD_RELOC_SH_DISP12BY8
3299 BFD_RELOC_SH_DISP20BY8
3303 BFD_RELOC_SH_IMM4BY2
3305 BFD_RELOC_SH_IMM4BY4
3309 BFD_RELOC_SH_IMM8BY2
3311 BFD_RELOC_SH_IMM8BY4
3313 BFD_RELOC_SH_PCRELIMM8BY2
3315 BFD_RELOC_SH_PCRELIMM8BY4
3317 BFD_RELOC_SH_SWITCH16
3319 BFD_RELOC_SH_SWITCH32
3333 BFD_RELOC_SH_LOOP_START
3335 BFD_RELOC_SH_LOOP_END
3339 BFD_RELOC_SH_GLOB_DAT
3341 BFD_RELOC_SH_JMP_SLOT
3343 BFD_RELOC_SH_RELATIVE
3347 BFD_RELOC_SH_GOT_LOW16
3349 BFD_RELOC_SH_GOT_MEDLOW16
3351 BFD_RELOC_SH_GOT_MEDHI16
3353 BFD_RELOC_SH_GOT_HI16
3355 BFD_RELOC_SH_GOTPLT_LOW16
3357 BFD_RELOC_SH_GOTPLT_MEDLOW16
3359 BFD_RELOC_SH_GOTPLT_MEDHI16
3361 BFD_RELOC_SH_GOTPLT_HI16
3363 BFD_RELOC_SH_PLT_LOW16
3365 BFD_RELOC_SH_PLT_MEDLOW16
3367 BFD_RELOC_SH_PLT_MEDHI16
3369 BFD_RELOC_SH_PLT_HI16
3371 BFD_RELOC_SH_GOTOFF_LOW16
3373 BFD_RELOC_SH_GOTOFF_MEDLOW16
3375 BFD_RELOC_SH_GOTOFF_MEDHI16
3377 BFD_RELOC_SH_GOTOFF_HI16
3379 BFD_RELOC_SH_GOTPC_LOW16
3381 BFD_RELOC_SH_GOTPC_MEDLOW16
3383 BFD_RELOC_SH_GOTPC_MEDHI16
3385 BFD_RELOC_SH_GOTPC_HI16
3389 BFD_RELOC_SH_GLOB_DAT64
3391 BFD_RELOC_SH_JMP_SLOT64
3393 BFD_RELOC_SH_RELATIVE64
3395 BFD_RELOC_SH_GOT10BY4
3397 BFD_RELOC_SH_GOT10BY8
3399 BFD_RELOC_SH_GOTPLT10BY4
3401 BFD_RELOC_SH_GOTPLT10BY8
3403 BFD_RELOC_SH_GOTPLT32
3405 BFD_RELOC_SH_SHMEDIA_CODE
3411 BFD_RELOC_SH_IMMS6BY32
3417 BFD_RELOC_SH_IMMS10BY2
3419 BFD_RELOC_SH_IMMS10BY4
3421 BFD_RELOC_SH_IMMS10BY8
3427 BFD_RELOC_SH_IMM_LOW16
3429 BFD_RELOC_SH_IMM_LOW16_PCREL
3431 BFD_RELOC_SH_IMM_MEDLOW16
3433 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3435 BFD_RELOC_SH_IMM_MEDHI16
3437 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3439 BFD_RELOC_SH_IMM_HI16
3441 BFD_RELOC_SH_IMM_HI16_PCREL
3445 BFD_RELOC_SH_TLS_GD_32
3447 BFD_RELOC_SH_TLS_LD_32
3449 BFD_RELOC_SH_TLS_LDO_32
3451 BFD_RELOC_SH_TLS_IE_32
3453 BFD_RELOC_SH_TLS_LE_32
3455 BFD_RELOC_SH_TLS_DTPMOD32
3457 BFD_RELOC_SH_TLS_DTPOFF32
3459 BFD_RELOC_SH_TLS_TPOFF32
3463 BFD_RELOC_SH_GOTOFF20
3465 BFD_RELOC_SH_GOTFUNCDESC
3467 BFD_RELOC_SH_GOTFUNCDESC20
3469 BFD_RELOC_SH_GOTOFFFUNCDESC
3471 BFD_RELOC_SH_GOTOFFFUNCDESC20
3473 BFD_RELOC_SH_FUNCDESC
3475 Renesas / SuperH SH relocs. Not all of these appear in object files.
3498 BFD_RELOC_ARC_SECTOFF
3500 BFD_RELOC_ARC_S21H_PCREL
3502 BFD_RELOC_ARC_S21W_PCREL
3504 BFD_RELOC_ARC_S25H_PCREL
3506 BFD_RELOC_ARC_S25W_PCREL
3510 BFD_RELOC_ARC_SDA_LDST
3512 BFD_RELOC_ARC_SDA_LDST1
3514 BFD_RELOC_ARC_SDA_LDST2
3516 BFD_RELOC_ARC_SDA16_LD
3518 BFD_RELOC_ARC_SDA16_LD1
3520 BFD_RELOC_ARC_SDA16_LD2
3522 BFD_RELOC_ARC_S13_PCREL
3528 BFD_RELOC_ARC_32_ME_S
3530 BFD_RELOC_ARC_N32_ME
3532 BFD_RELOC_ARC_SECTOFF_ME
3534 BFD_RELOC_ARC_SDA32_ME
3538 BFD_RELOC_AC_SECTOFF_U8
3540 BFD_RELOC_AC_SECTOFF_U8_1
3542 BFD_RELOC_AC_SECTOFF_U8_2
3544 BFD_RELOC_AC_SECTOFF_S9
3546 BFD_RELOC_AC_SECTOFF_S9_1
3548 BFD_RELOC_AC_SECTOFF_S9_2
3550 BFD_RELOC_ARC_SECTOFF_ME_1
3552 BFD_RELOC_ARC_SECTOFF_ME_2
3554 BFD_RELOC_ARC_SECTOFF_1
3556 BFD_RELOC_ARC_SECTOFF_2
3558 BFD_RELOC_ARC_SDA_12
3560 BFD_RELOC_ARC_SDA16_ST2
3562 BFD_RELOC_ARC_32_PCREL
3568 BFD_RELOC_ARC_GOTPC32
3574 BFD_RELOC_ARC_GLOB_DAT
3576 BFD_RELOC_ARC_JMP_SLOT
3578 BFD_RELOC_ARC_RELATIVE
3580 BFD_RELOC_ARC_GOTOFF
3584 BFD_RELOC_ARC_S21W_PCREL_PLT
3586 BFD_RELOC_ARC_S25H_PCREL_PLT
3588 BFD_RELOC_ARC_TLS_DTPMOD
3590 BFD_RELOC_ARC_TLS_TPOFF
3592 BFD_RELOC_ARC_TLS_GD_GOT
3594 BFD_RELOC_ARC_TLS_GD_LD
3596 BFD_RELOC_ARC_TLS_GD_CALL
3598 BFD_RELOC_ARC_TLS_IE_GOT
3600 BFD_RELOC_ARC_TLS_DTPOFF
3602 BFD_RELOC_ARC_TLS_DTPOFF_S9
3604 BFD_RELOC_ARC_TLS_LE_S9
3606 BFD_RELOC_ARC_TLS_LE_32
3608 BFD_RELOC_ARC_S25W_PCREL_PLT
3610 BFD_RELOC_ARC_S21H_PCREL_PLT
3612 BFD_RELOC_ARC_NPS_CMEM16
3614 BFD_RELOC_ARC_JLI_SECTOFF
3619 BFD_RELOC_BFIN_16_IMM
3621 ADI Blackfin 16 bit immediate absolute reloc.
3623 BFD_RELOC_BFIN_16_HIGH
3625 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3627 BFD_RELOC_BFIN_4_PCREL
3629 ADI Blackfin 'a' part of LSETUP.
3631 BFD_RELOC_BFIN_5_PCREL
3635 BFD_RELOC_BFIN_16_LOW
3637 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3639 BFD_RELOC_BFIN_10_PCREL
3643 BFD_RELOC_BFIN_11_PCREL
3645 ADI Blackfin 'b' part of LSETUP.
3647 BFD_RELOC_BFIN_12_PCREL_JUMP
3651 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3653 ADI Blackfin Short jump, pcrel.
3655 BFD_RELOC_BFIN_24_PCREL_CALL_X
3657 ADI Blackfin Call.x not implemented.
3659 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3661 ADI Blackfin Long Jump pcrel.
3663 BFD_RELOC_BFIN_GOT17M4
3665 BFD_RELOC_BFIN_GOTHI
3667 BFD_RELOC_BFIN_GOTLO
3669 BFD_RELOC_BFIN_FUNCDESC
3671 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3673 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3675 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3677 BFD_RELOC_BFIN_FUNCDESC_VALUE
3679 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3681 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3683 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3685 BFD_RELOC_BFIN_GOTOFF17M4
3687 BFD_RELOC_BFIN_GOTOFFHI
3689 BFD_RELOC_BFIN_GOTOFFLO
3691 ADI Blackfin FD-PIC relocations.
3695 ADI Blackfin GOT relocation.
3697 BFD_RELOC_BFIN_PLTPC
3699 ADI Blackfin PLTPC relocation.
3701 BFD_ARELOC_BFIN_PUSH
3703 ADI Blackfin arithmetic relocation.
3705 BFD_ARELOC_BFIN_CONST
3707 ADI Blackfin arithmetic relocation.
3711 ADI Blackfin arithmetic relocation.
3715 ADI Blackfin arithmetic relocation.
3717 BFD_ARELOC_BFIN_MULT
3719 ADI Blackfin arithmetic relocation.
3723 ADI Blackfin arithmetic relocation.
3727 ADI Blackfin arithmetic relocation.
3729 BFD_ARELOC_BFIN_LSHIFT
3731 ADI Blackfin arithmetic relocation.
3733 BFD_ARELOC_BFIN_RSHIFT
3735 ADI Blackfin arithmetic relocation.
3739 ADI Blackfin arithmetic relocation.
3743 ADI Blackfin arithmetic relocation.
3747 ADI Blackfin arithmetic relocation.
3749 BFD_ARELOC_BFIN_LAND
3751 ADI Blackfin arithmetic relocation.
3755 ADI Blackfin arithmetic relocation.
3759 ADI Blackfin arithmetic relocation.
3763 ADI Blackfin arithmetic relocation.
3765 BFD_ARELOC_BFIN_COMP
3767 ADI Blackfin arithmetic relocation.
3769 BFD_ARELOC_BFIN_PAGE
3771 ADI Blackfin arithmetic relocation.
3773 BFD_ARELOC_BFIN_HWPAGE
3775 ADI Blackfin arithmetic relocation.
3777 BFD_ARELOC_BFIN_ADDR
3779 ADI Blackfin arithmetic relocation.
3782 BFD_RELOC_D10V_10_PCREL_R
3784 Mitsubishi D10V relocs.
3785 This is a 10-bit reloc with the right 2 bits
3788 BFD_RELOC_D10V_10_PCREL_L
3790 Mitsubishi D10V relocs.
3791 This is a 10-bit reloc with the right 2 bits
3792 assumed to be 0. This is the same as the previous reloc
3793 except it is in the left container, i.e.,
3794 shifted left 15 bits.
3798 This is an 18-bit reloc with the right 2 bits
3801 BFD_RELOC_D10V_18_PCREL
3803 This is an 18-bit reloc with the right 2 bits
3809 Mitsubishi D30V relocs.
3810 This is a 6-bit absolute reloc.
3812 BFD_RELOC_D30V_9_PCREL
3814 This is a 6-bit pc-relative reloc with
3815 the right 3 bits assumed to be 0.
3817 BFD_RELOC_D30V_9_PCREL_R
3819 This is a 6-bit pc-relative reloc with
3820 the right 3 bits assumed to be 0. Same
3821 as the previous reloc but on the right side
3826 This is a 12-bit absolute reloc with the
3827 right 3 bitsassumed to be 0.
3829 BFD_RELOC_D30V_15_PCREL
3831 This is a 12-bit pc-relative reloc with
3832 the right 3 bits assumed to be 0.
3834 BFD_RELOC_D30V_15_PCREL_R
3836 This is a 12-bit pc-relative reloc with
3837 the right 3 bits assumed to be 0. Same
3838 as the previous reloc but on the right side
3843 This is an 18-bit absolute reloc with
3844 the right 3 bits assumed to be 0.
3846 BFD_RELOC_D30V_21_PCREL
3848 This is an 18-bit pc-relative reloc with
3849 the right 3 bits assumed to be 0.
3851 BFD_RELOC_D30V_21_PCREL_R
3853 This is an 18-bit pc-relative reloc with
3854 the right 3 bits assumed to be 0. Same
3855 as the previous reloc but on the right side
3860 This is a 32-bit absolute reloc.
3862 BFD_RELOC_D30V_32_PCREL
3864 This is a 32-bit pc-relative reloc.
3867 BFD_RELOC_DLX_HI16_S
3882 BFD_RELOC_M32C_RL_JUMP
3884 BFD_RELOC_M32C_RL_1ADDR
3886 BFD_RELOC_M32C_RL_2ADDR
3888 Renesas M16C/M32C Relocations.
3893 Renesas M32R (formerly Mitsubishi M32R) relocs.
3894 This is a 24 bit absolute address.
3896 BFD_RELOC_M32R_10_PCREL
3898 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3900 BFD_RELOC_M32R_18_PCREL
3902 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3904 BFD_RELOC_M32R_26_PCREL
3906 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3908 BFD_RELOC_M32R_HI16_ULO
3910 This is a 16-bit reloc containing the high 16 bits of an address
3911 used when the lower 16 bits are treated as unsigned.
3913 BFD_RELOC_M32R_HI16_SLO
3915 This is a 16-bit reloc containing the high 16 bits of an address
3916 used when the lower 16 bits are treated as signed.
3920 This is a 16-bit reloc containing the lower 16 bits of an address.
3922 BFD_RELOC_M32R_SDA16
3924 This is a 16-bit reloc containing the small data area offset for use in
3925 add3, load, and store instructions.
3927 BFD_RELOC_M32R_GOT24
3929 BFD_RELOC_M32R_26_PLTREL
3933 BFD_RELOC_M32R_GLOB_DAT
3935 BFD_RELOC_M32R_JMP_SLOT
3937 BFD_RELOC_M32R_RELATIVE
3939 BFD_RELOC_M32R_GOTOFF
3941 BFD_RELOC_M32R_GOTOFF_HI_ULO
3943 BFD_RELOC_M32R_GOTOFF_HI_SLO
3945 BFD_RELOC_M32R_GOTOFF_LO
3947 BFD_RELOC_M32R_GOTPC24
3949 BFD_RELOC_M32R_GOT16_HI_ULO
3951 BFD_RELOC_M32R_GOT16_HI_SLO
3953 BFD_RELOC_M32R_GOT16_LO
3955 BFD_RELOC_M32R_GOTPC_HI_ULO
3957 BFD_RELOC_M32R_GOTPC_HI_SLO
3959 BFD_RELOC_M32R_GOTPC_LO
3968 This is a 20 bit absolute address.
3970 BFD_RELOC_NDS32_9_PCREL
3972 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3974 BFD_RELOC_NDS32_WORD_9_PCREL
3976 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3978 BFD_RELOC_NDS32_15_PCREL
3980 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3982 BFD_RELOC_NDS32_17_PCREL
3984 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3986 BFD_RELOC_NDS32_25_PCREL
3988 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3990 BFD_RELOC_NDS32_HI20
3992 This is a 20-bit reloc containing the high 20 bits of an address
3993 used with the lower 12 bits
3995 BFD_RELOC_NDS32_LO12S3
3997 This is a 12-bit reloc containing the lower 12 bits of an address
3998 then shift right by 3. This is used with ldi,sdi...
4000 BFD_RELOC_NDS32_LO12S2
4002 This is a 12-bit reloc containing the lower 12 bits of an address
4003 then shift left by 2. This is used with lwi,swi...
4005 BFD_RELOC_NDS32_LO12S1
4007 This is a 12-bit reloc containing the lower 12 bits of an address
4008 then shift left by 1. This is used with lhi,shi...
4010 BFD_RELOC_NDS32_LO12S0
4012 This is a 12-bit reloc containing the lower 12 bits of an address
4013 then shift left by 0. This is used with lbisbi...
4015 BFD_RELOC_NDS32_LO12S0_ORI
4017 This is a 12-bit reloc containing the lower 12 bits of an address
4018 then shift left by 0. This is only used with branch relaxations
4020 BFD_RELOC_NDS32_SDA15S3
4022 This is a 15-bit reloc containing the small data area 18-bit signed offset
4023 and shift left by 3 for use in ldi, sdi...
4025 BFD_RELOC_NDS32_SDA15S2
4027 This is a 15-bit reloc containing the small data area 17-bit signed offset
4028 and shift left by 2 for use in lwi, swi...
4030 BFD_RELOC_NDS32_SDA15S1
4032 This is a 15-bit reloc containing the small data area 16-bit signed offset
4033 and shift left by 1 for use in lhi, shi...
4035 BFD_RELOC_NDS32_SDA15S0
4037 This is a 15-bit reloc containing the small data area 15-bit signed offset
4038 and shift left by 0 for use in lbi, sbi...
4040 BFD_RELOC_NDS32_SDA16S3
4042 This is a 16-bit reloc containing the small data area 16-bit signed offset
4045 BFD_RELOC_NDS32_SDA17S2
4047 This is a 17-bit reloc containing the small data area 17-bit signed offset
4048 and shift left by 2 for use in lwi.gp, swi.gp...
4050 BFD_RELOC_NDS32_SDA18S1
4052 This is a 18-bit reloc containing the small data area 18-bit signed offset
4053 and shift left by 1 for use in lhi.gp, shi.gp...
4055 BFD_RELOC_NDS32_SDA19S0
4057 This is a 19-bit reloc containing the small data area 19-bit signed offset
4058 and shift left by 0 for use in lbi.gp, sbi.gp...
4060 BFD_RELOC_NDS32_GOT20
4062 BFD_RELOC_NDS32_9_PLTREL
4064 BFD_RELOC_NDS32_25_PLTREL
4066 BFD_RELOC_NDS32_COPY
4068 BFD_RELOC_NDS32_GLOB_DAT
4070 BFD_RELOC_NDS32_JMP_SLOT
4072 BFD_RELOC_NDS32_RELATIVE
4074 BFD_RELOC_NDS32_GOTOFF
4076 BFD_RELOC_NDS32_GOTOFF_HI20
4078 BFD_RELOC_NDS32_GOTOFF_LO12
4080 BFD_RELOC_NDS32_GOTPC20
4082 BFD_RELOC_NDS32_GOT_HI20
4084 BFD_RELOC_NDS32_GOT_LO12
4086 BFD_RELOC_NDS32_GOTPC_HI20
4088 BFD_RELOC_NDS32_GOTPC_LO12
4092 BFD_RELOC_NDS32_INSN16
4094 BFD_RELOC_NDS32_LABEL
4096 BFD_RELOC_NDS32_LONGCALL1
4098 BFD_RELOC_NDS32_LONGCALL2
4100 BFD_RELOC_NDS32_LONGCALL3
4102 BFD_RELOC_NDS32_LONGJUMP1
4104 BFD_RELOC_NDS32_LONGJUMP2
4106 BFD_RELOC_NDS32_LONGJUMP3
4108 BFD_RELOC_NDS32_LOADSTORE
4110 BFD_RELOC_NDS32_9_FIXED
4112 BFD_RELOC_NDS32_15_FIXED
4114 BFD_RELOC_NDS32_17_FIXED
4116 BFD_RELOC_NDS32_25_FIXED
4118 BFD_RELOC_NDS32_LONGCALL4
4120 BFD_RELOC_NDS32_LONGCALL5
4122 BFD_RELOC_NDS32_LONGCALL6
4124 BFD_RELOC_NDS32_LONGJUMP4
4126 BFD_RELOC_NDS32_LONGJUMP5
4128 BFD_RELOC_NDS32_LONGJUMP6
4130 BFD_RELOC_NDS32_LONGJUMP7
4134 BFD_RELOC_NDS32_PLTREL_HI20
4136 BFD_RELOC_NDS32_PLTREL_LO12
4138 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4140 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4144 BFD_RELOC_NDS32_SDA12S2_DP
4146 BFD_RELOC_NDS32_SDA12S2_SP
4148 BFD_RELOC_NDS32_LO12S2_DP
4150 BFD_RELOC_NDS32_LO12S2_SP
4154 BFD_RELOC_NDS32_DWARF2_OP1
4156 BFD_RELOC_NDS32_DWARF2_OP2
4158 BFD_RELOC_NDS32_DWARF2_LEB
4160 for dwarf2 debug_line.
4162 BFD_RELOC_NDS32_UPDATE_TA
4164 for eliminate 16-bit instructions
4166 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4168 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4170 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4172 BFD_RELOC_NDS32_GOT_LO15
4174 BFD_RELOC_NDS32_GOT_LO19
4176 BFD_RELOC_NDS32_GOTOFF_LO15
4178 BFD_RELOC_NDS32_GOTOFF_LO19
4180 BFD_RELOC_NDS32_GOT15S2
4182 BFD_RELOC_NDS32_GOT17S2
4184 for PIC object relaxation
4189 This is a 5 bit absolute address.
4191 BFD_RELOC_NDS32_10_UPCREL
4193 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4195 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4197 If fp were omitted, fp can used as another gp.
4199 BFD_RELOC_NDS32_RELAX_ENTRY
4201 BFD_RELOC_NDS32_GOT_SUFF
4203 BFD_RELOC_NDS32_GOTOFF_SUFF
4205 BFD_RELOC_NDS32_PLT_GOT_SUFF
4207 BFD_RELOC_NDS32_MULCALL_SUFF
4211 BFD_RELOC_NDS32_PTR_COUNT
4213 BFD_RELOC_NDS32_PTR_RESOLVED
4215 BFD_RELOC_NDS32_PLTBLOCK
4217 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4219 BFD_RELOC_NDS32_RELAX_REGION_END
4221 BFD_RELOC_NDS32_MINUEND
4223 BFD_RELOC_NDS32_SUBTRAHEND
4225 BFD_RELOC_NDS32_DIFF8
4227 BFD_RELOC_NDS32_DIFF16
4229 BFD_RELOC_NDS32_DIFF32
4231 BFD_RELOC_NDS32_DIFF_ULEB128
4233 BFD_RELOC_NDS32_EMPTY
4235 relaxation relative relocation types
4237 BFD_RELOC_NDS32_25_ABS
4239 This is a 25 bit absolute address.
4241 BFD_RELOC_NDS32_DATA
4243 BFD_RELOC_NDS32_TRAN
4245 BFD_RELOC_NDS32_17IFC_PCREL
4247 BFD_RELOC_NDS32_10IFCU_PCREL
4249 For ex9 and ifc using.
4251 BFD_RELOC_NDS32_TPOFF
4253 BFD_RELOC_NDS32_TLS_LE_HI20
4255 BFD_RELOC_NDS32_TLS_LE_LO12
4257 BFD_RELOC_NDS32_TLS_LE_ADD
4259 BFD_RELOC_NDS32_TLS_LE_LS
4261 BFD_RELOC_NDS32_GOTTPOFF
4263 BFD_RELOC_NDS32_TLS_IE_HI20
4265 BFD_RELOC_NDS32_TLS_IE_LO12S2
4267 BFD_RELOC_NDS32_TLS_TPOFF
4269 BFD_RELOC_NDS32_TLS_LE_20
4271 BFD_RELOC_NDS32_TLS_LE_15S0
4273 BFD_RELOC_NDS32_TLS_LE_15S1
4275 BFD_RELOC_NDS32_TLS_LE_15S2
4281 BFD_RELOC_V850_9_PCREL
4283 This is a 9-bit reloc
4285 BFD_RELOC_V850_22_PCREL
4287 This is a 22-bit reloc
4290 BFD_RELOC_V850_SDA_16_16_OFFSET
4292 This is a 16 bit offset from the short data area pointer.
4294 BFD_RELOC_V850_SDA_15_16_OFFSET
4296 This is a 16 bit offset (of which only 15 bits are used) from the
4297 short data area pointer.
4299 BFD_RELOC_V850_ZDA_16_16_OFFSET
4301 This is a 16 bit offset from the zero data area pointer.
4303 BFD_RELOC_V850_ZDA_15_16_OFFSET
4305 This is a 16 bit offset (of which only 15 bits are used) from the
4306 zero data area pointer.
4308 BFD_RELOC_V850_TDA_6_8_OFFSET
4310 This is an 8 bit offset (of which only 6 bits are used) from the
4311 tiny data area pointer.
4313 BFD_RELOC_V850_TDA_7_8_OFFSET
4315 This is an 8bit offset (of which only 7 bits are used) from the tiny
4318 BFD_RELOC_V850_TDA_7_7_OFFSET
4320 This is a 7 bit offset from the tiny data area pointer.
4322 BFD_RELOC_V850_TDA_16_16_OFFSET
4324 This is a 16 bit offset from the tiny data area pointer.
4327 BFD_RELOC_V850_TDA_4_5_OFFSET
4329 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4332 BFD_RELOC_V850_TDA_4_4_OFFSET
4334 This is a 4 bit offset from the tiny data area pointer.
4336 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4338 This is a 16 bit offset from the short data area pointer, with the
4339 bits placed non-contiguously in the instruction.
4341 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4343 This is a 16 bit offset from the zero data area pointer, with the
4344 bits placed non-contiguously in the instruction.
4346 BFD_RELOC_V850_CALLT_6_7_OFFSET
4348 This is a 6 bit offset from the call table base pointer.
4350 BFD_RELOC_V850_CALLT_16_16_OFFSET
4352 This is a 16 bit offset from the call table base pointer.
4354 BFD_RELOC_V850_LONGCALL
4356 Used for relaxing indirect function calls.
4358 BFD_RELOC_V850_LONGJUMP
4360 Used for relaxing indirect jumps.
4362 BFD_RELOC_V850_ALIGN
4364 Used to maintain alignment whilst relaxing.
4366 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4368 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4371 BFD_RELOC_V850_16_PCREL
4373 This is a 16-bit reloc.
4375 BFD_RELOC_V850_17_PCREL
4377 This is a 17-bit reloc.
4381 This is a 23-bit reloc.
4383 BFD_RELOC_V850_32_PCREL
4385 This is a 32-bit reloc.
4387 BFD_RELOC_V850_32_ABS
4389 This is a 32-bit reloc.
4391 BFD_RELOC_V850_16_SPLIT_OFFSET
4393 This is a 16-bit reloc.
4395 BFD_RELOC_V850_16_S1
4397 This is a 16-bit reloc.
4399 BFD_RELOC_V850_LO16_S1
4401 Low 16 bits. 16 bit shifted by 1.
4403 BFD_RELOC_V850_CALLT_15_16_OFFSET
4405 This is a 16 bit offset from the call table base pointer.
4407 BFD_RELOC_V850_32_GOTPCREL
4411 BFD_RELOC_V850_16_GOT
4415 BFD_RELOC_V850_32_GOT
4419 BFD_RELOC_V850_22_PLT_PCREL
4423 BFD_RELOC_V850_32_PLT_PCREL
4431 BFD_RELOC_V850_GLOB_DAT
4435 BFD_RELOC_V850_JMP_SLOT
4439 BFD_RELOC_V850_RELATIVE
4443 BFD_RELOC_V850_16_GOTOFF
4447 BFD_RELOC_V850_32_GOTOFF
4462 This is a 8bit DP reloc for the tms320c30, where the most
4463 significant 8 bits of a 24 bit word are placed into the least
4464 significant 8 bits of the opcode.
4467 BFD_RELOC_TIC54X_PARTLS7
4469 This is a 7bit reloc for the tms320c54x, where the least
4470 significant 7 bits of a 16 bit word are placed into the least
4471 significant 7 bits of the opcode.
4474 BFD_RELOC_TIC54X_PARTMS9
4476 This is a 9bit DP reloc for the tms320c54x, where the most
4477 significant 9 bits of a 16 bit word are placed into the least
4478 significant 9 bits of the opcode.
4483 This is an extended address 23-bit reloc for the tms320c54x.
4486 BFD_RELOC_TIC54X_16_OF_23
4488 This is a 16-bit reloc for the tms320c54x, where the least
4489 significant 16 bits of a 23-bit extended address are placed into
4493 BFD_RELOC_TIC54X_MS7_OF_23
4495 This is a reloc for the tms320c54x, where the most
4496 significant 7 bits of a 23-bit extended address are placed into
4500 BFD_RELOC_C6000_PCR_S21
4502 BFD_RELOC_C6000_PCR_S12
4504 BFD_RELOC_C6000_PCR_S10
4506 BFD_RELOC_C6000_PCR_S7
4508 BFD_RELOC_C6000_ABS_S16
4510 BFD_RELOC_C6000_ABS_L16
4512 BFD_RELOC_C6000_ABS_H16
4514 BFD_RELOC_C6000_SBR_U15_B
4516 BFD_RELOC_C6000_SBR_U15_H
4518 BFD_RELOC_C6000_SBR_U15_W
4520 BFD_RELOC_C6000_SBR_S16
4522 BFD_RELOC_C6000_SBR_L16_B
4524 BFD_RELOC_C6000_SBR_L16_H
4526 BFD_RELOC_C6000_SBR_L16_W
4528 BFD_RELOC_C6000_SBR_H16_B
4530 BFD_RELOC_C6000_SBR_H16_H
4532 BFD_RELOC_C6000_SBR_H16_W
4534 BFD_RELOC_C6000_SBR_GOT_U15_W
4536 BFD_RELOC_C6000_SBR_GOT_L16_W
4538 BFD_RELOC_C6000_SBR_GOT_H16_W
4540 BFD_RELOC_C6000_DSBT_INDEX
4542 BFD_RELOC_C6000_PREL31
4544 BFD_RELOC_C6000_COPY
4546 BFD_RELOC_C6000_JUMP_SLOT
4548 BFD_RELOC_C6000_EHTYPE
4550 BFD_RELOC_C6000_PCR_H16
4552 BFD_RELOC_C6000_PCR_L16
4554 BFD_RELOC_C6000_ALIGN
4556 BFD_RELOC_C6000_FPHEAD
4558 BFD_RELOC_C6000_NOCMP
4560 TMS320C6000 relocations.
4565 This is a 48 bit reloc for the FR30 that stores 32 bits.
4569 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4572 BFD_RELOC_FR30_6_IN_4
4574 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4577 BFD_RELOC_FR30_8_IN_8
4579 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4582 BFD_RELOC_FR30_9_IN_8
4584 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4587 BFD_RELOC_FR30_10_IN_8
4589 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4592 BFD_RELOC_FR30_9_PCREL
4594 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4595 short offset into 8 bits.
4597 BFD_RELOC_FR30_12_PCREL
4599 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4600 short offset into 11 bits.
4603 BFD_RELOC_MCORE_PCREL_IMM8BY4
4605 BFD_RELOC_MCORE_PCREL_IMM11BY2
4607 BFD_RELOC_MCORE_PCREL_IMM4BY2
4609 BFD_RELOC_MCORE_PCREL_32
4611 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4615 Motorola Mcore relocations.
4624 BFD_RELOC_MEP_PCREL8A2
4626 BFD_RELOC_MEP_PCREL12A2
4628 BFD_RELOC_MEP_PCREL17A2
4630 BFD_RELOC_MEP_PCREL24A2
4632 BFD_RELOC_MEP_PCABS24A2
4644 BFD_RELOC_MEP_TPREL7
4646 BFD_RELOC_MEP_TPREL7A2
4648 BFD_RELOC_MEP_TPREL7A4
4650 BFD_RELOC_MEP_UIMM24
4652 BFD_RELOC_MEP_ADDR24A4
4654 BFD_RELOC_MEP_GNU_VTINHERIT
4656 BFD_RELOC_MEP_GNU_VTENTRY
4658 Toshiba Media Processor Relocations.
4662 BFD_RELOC_METAG_HIADDR16
4664 BFD_RELOC_METAG_LOADDR16
4666 BFD_RELOC_METAG_RELBRANCH
4668 BFD_RELOC_METAG_GETSETOFF
4670 BFD_RELOC_METAG_HIOG
4672 BFD_RELOC_METAG_LOOG
4674 BFD_RELOC_METAG_REL8
4676 BFD_RELOC_METAG_REL16
4678 BFD_RELOC_METAG_HI16_GOTOFF
4680 BFD_RELOC_METAG_LO16_GOTOFF
4682 BFD_RELOC_METAG_GETSET_GOTOFF
4684 BFD_RELOC_METAG_GETSET_GOT
4686 BFD_RELOC_METAG_HI16_GOTPC
4688 BFD_RELOC_METAG_LO16_GOTPC
4690 BFD_RELOC_METAG_HI16_PLT
4692 BFD_RELOC_METAG_LO16_PLT
4694 BFD_RELOC_METAG_RELBRANCH_PLT
4696 BFD_RELOC_METAG_GOTOFF
4700 BFD_RELOC_METAG_COPY
4702 BFD_RELOC_METAG_JMP_SLOT
4704 BFD_RELOC_METAG_RELATIVE
4706 BFD_RELOC_METAG_GLOB_DAT
4708 BFD_RELOC_METAG_TLS_GD
4710 BFD_RELOC_METAG_TLS_LDM
4712 BFD_RELOC_METAG_TLS_LDO_HI16
4714 BFD_RELOC_METAG_TLS_LDO_LO16
4716 BFD_RELOC_METAG_TLS_LDO
4718 BFD_RELOC_METAG_TLS_IE
4720 BFD_RELOC_METAG_TLS_IENONPIC
4722 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4724 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4726 BFD_RELOC_METAG_TLS_TPOFF
4728 BFD_RELOC_METAG_TLS_DTPMOD
4730 BFD_RELOC_METAG_TLS_DTPOFF
4732 BFD_RELOC_METAG_TLS_LE
4734 BFD_RELOC_METAG_TLS_LE_HI16
4736 BFD_RELOC_METAG_TLS_LE_LO16
4738 Imagination Technologies Meta relocations.
4743 BFD_RELOC_MMIX_GETA_1
4745 BFD_RELOC_MMIX_GETA_2
4747 BFD_RELOC_MMIX_GETA_3
4749 These are relocations for the GETA instruction.
4751 BFD_RELOC_MMIX_CBRANCH
4753 BFD_RELOC_MMIX_CBRANCH_J
4755 BFD_RELOC_MMIX_CBRANCH_1
4757 BFD_RELOC_MMIX_CBRANCH_2
4759 BFD_RELOC_MMIX_CBRANCH_3
4761 These are relocations for a conditional branch instruction.
4763 BFD_RELOC_MMIX_PUSHJ
4765 BFD_RELOC_MMIX_PUSHJ_1
4767 BFD_RELOC_MMIX_PUSHJ_2
4769 BFD_RELOC_MMIX_PUSHJ_3
4771 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4773 These are relocations for the PUSHJ instruction.
4777 BFD_RELOC_MMIX_JMP_1
4779 BFD_RELOC_MMIX_JMP_2
4781 BFD_RELOC_MMIX_JMP_3
4783 These are relocations for the JMP instruction.
4785 BFD_RELOC_MMIX_ADDR19
4787 This is a relocation for a relative address as in a GETA instruction or
4790 BFD_RELOC_MMIX_ADDR27
4792 This is a relocation for a relative address as in a JMP instruction.
4794 BFD_RELOC_MMIX_REG_OR_BYTE
4796 This is a relocation for an instruction field that may be a general
4797 register or a value 0..255.
4801 This is a relocation for an instruction field that may be a general
4804 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4806 This is a relocation for two instruction fields holding a register and
4807 an offset, the equivalent of the relocation.
4809 BFD_RELOC_MMIX_LOCAL
4811 This relocation is an assertion that the expression is not allocated as
4812 a global register. It does not modify contents.
4815 BFD_RELOC_AVR_7_PCREL
4817 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4818 short offset into 7 bits.
4820 BFD_RELOC_AVR_13_PCREL
4822 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4823 short offset into 12 bits.
4827 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4828 program memory address) into 16 bits.
4830 BFD_RELOC_AVR_LO8_LDI
4832 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4833 data memory address) into 8 bit immediate value of LDI insn.
4835 BFD_RELOC_AVR_HI8_LDI
4837 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4838 of data memory address) into 8 bit immediate value of LDI insn.
4840 BFD_RELOC_AVR_HH8_LDI
4842 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4843 of program memory address) into 8 bit immediate value of LDI insn.
4845 BFD_RELOC_AVR_MS8_LDI
4847 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4848 of 32 bit value) into 8 bit immediate value of LDI insn.
4850 BFD_RELOC_AVR_LO8_LDI_NEG
4852 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4853 (usually data memory address) into 8 bit immediate value of SUBI insn.
4855 BFD_RELOC_AVR_HI8_LDI_NEG
4857 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4858 (high 8 bit of data memory address) into 8 bit immediate value of
4861 BFD_RELOC_AVR_HH8_LDI_NEG
4863 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4864 (most high 8 bit of program memory address) into 8 bit immediate value
4865 of LDI or SUBI insn.
4867 BFD_RELOC_AVR_MS8_LDI_NEG
4869 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4870 of 32 bit value) into 8 bit immediate value of LDI insn.
4872 BFD_RELOC_AVR_LO8_LDI_PM
4874 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4875 command address) into 8 bit immediate value of LDI insn.
4877 BFD_RELOC_AVR_LO8_LDI_GS
4879 This is a 16 bit reloc for the AVR that stores 8 bit value
4880 (command address) into 8 bit immediate value of LDI insn. If the address
4881 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4884 BFD_RELOC_AVR_HI8_LDI_PM
4886 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4887 of command address) into 8 bit immediate value of LDI insn.
4889 BFD_RELOC_AVR_HI8_LDI_GS
4891 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4892 of command address) into 8 bit immediate value of LDI insn. If the address
4893 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4896 BFD_RELOC_AVR_HH8_LDI_PM
4898 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4899 of command address) into 8 bit immediate value of LDI insn.
4901 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4903 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4904 (usually command address) into 8 bit immediate value of SUBI insn.
4906 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4908 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4909 (high 8 bit of 16 bit command address) into 8 bit immediate value
4912 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4914 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4915 (high 6 bit of 22 bit command address) into 8 bit immediate
4920 This is a 32 bit reloc for the AVR that stores 23 bit value
4925 This is a 16 bit reloc for the AVR that stores all needed bits
4926 for absolute addressing with ldi with overflow check to linktime
4930 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4933 BFD_RELOC_AVR_6_ADIW
4935 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4940 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4941 in .byte lo8(symbol)
4945 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4946 in .byte hi8(symbol)
4950 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4951 in .byte hlo8(symbol)
4955 BFD_RELOC_AVR_DIFF16
4957 BFD_RELOC_AVR_DIFF32
4959 AVR relocations to mark the difference of two local symbols.
4960 These are only needed to support linker relaxation and can be ignored
4961 when not relaxing. The field is set to the value of the difference
4962 assuming no relaxation. The relocation encodes the position of the
4963 second symbol so the linker can determine whether to adjust the field
4966 BFD_RELOC_AVR_LDS_STS_16
4968 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4969 lds and sts instructions supported only tiny core.
4973 This is a 6 bit reloc for the AVR that stores an I/O register
4974 number for the IN and OUT instructions
4978 This is a 5 bit reloc for the AVR that stores an I/O register
4979 number for the SBIC, SBIS, SBI and CBI instructions
4982 BFD_RELOC_RISCV_HI20
4984 BFD_RELOC_RISCV_PCREL_HI20
4986 BFD_RELOC_RISCV_PCREL_LO12_I
4988 BFD_RELOC_RISCV_PCREL_LO12_S
4990 BFD_RELOC_RISCV_LO12_I
4992 BFD_RELOC_RISCV_LO12_S
4994 BFD_RELOC_RISCV_GPREL12_I
4996 BFD_RELOC_RISCV_GPREL12_S
4998 BFD_RELOC_RISCV_TPREL_HI20
5000 BFD_RELOC_RISCV_TPREL_LO12_I
5002 BFD_RELOC_RISCV_TPREL_LO12_S
5004 BFD_RELOC_RISCV_TPREL_ADD
5006 BFD_RELOC_RISCV_CALL
5008 BFD_RELOC_RISCV_CALL_PLT
5010 BFD_RELOC_RISCV_ADD8
5012 BFD_RELOC_RISCV_ADD16
5014 BFD_RELOC_RISCV_ADD32
5016 BFD_RELOC_RISCV_ADD64
5018 BFD_RELOC_RISCV_SUB8
5020 BFD_RELOC_RISCV_SUB16
5022 BFD_RELOC_RISCV_SUB32
5024 BFD_RELOC_RISCV_SUB64
5026 BFD_RELOC_RISCV_GOT_HI20
5028 BFD_RELOC_RISCV_TLS_GOT_HI20
5030 BFD_RELOC_RISCV_TLS_GD_HI20
5034 BFD_RELOC_RISCV_TLS_DTPMOD32
5036 BFD_RELOC_RISCV_TLS_DTPREL32
5038 BFD_RELOC_RISCV_TLS_DTPMOD64
5040 BFD_RELOC_RISCV_TLS_DTPREL64
5042 BFD_RELOC_RISCV_TLS_TPREL32
5044 BFD_RELOC_RISCV_TLS_TPREL64
5046 BFD_RELOC_RISCV_ALIGN
5048 BFD_RELOC_RISCV_RVC_BRANCH
5050 BFD_RELOC_RISCV_RVC_JUMP
5052 BFD_RELOC_RISCV_RVC_LUI
5054 BFD_RELOC_RISCV_GPREL_I
5056 BFD_RELOC_RISCV_GPREL_S
5058 BFD_RELOC_RISCV_TPREL_I
5060 BFD_RELOC_RISCV_TPREL_S
5062 BFD_RELOC_RISCV_RELAX
5066 BFD_RELOC_RISCV_SUB6
5068 BFD_RELOC_RISCV_SET6
5070 BFD_RELOC_RISCV_SET8
5072 BFD_RELOC_RISCV_SET16
5074 BFD_RELOC_RISCV_SET32
5076 BFD_RELOC_RISCV_32_PCREL
5083 BFD_RELOC_RL78_NEG16
5085 BFD_RELOC_RL78_NEG24
5087 BFD_RELOC_RL78_NEG32
5089 BFD_RELOC_RL78_16_OP
5091 BFD_RELOC_RL78_24_OP
5093 BFD_RELOC_RL78_32_OP
5101 BFD_RELOC_RL78_DIR3U_PCREL
5105 BFD_RELOC_RL78_GPRELB
5107 BFD_RELOC_RL78_GPRELW
5109 BFD_RELOC_RL78_GPRELL
5113 BFD_RELOC_RL78_OP_SUBTRACT
5115 BFD_RELOC_RL78_OP_NEG
5117 BFD_RELOC_RL78_OP_AND
5119 BFD_RELOC_RL78_OP_SHRA
5123 BFD_RELOC_RL78_ABS16
5125 BFD_RELOC_RL78_ABS16_REV
5127 BFD_RELOC_RL78_ABS32
5129 BFD_RELOC_RL78_ABS32_REV
5131 BFD_RELOC_RL78_ABS16U
5133 BFD_RELOC_RL78_ABS16UW
5135 BFD_RELOC_RL78_ABS16UL
5137 BFD_RELOC_RL78_RELAX
5147 BFD_RELOC_RL78_SADDR
5149 Renesas RL78 Relocations.
5172 BFD_RELOC_RX_DIR3U_PCREL
5184 BFD_RELOC_RX_OP_SUBTRACT
5192 BFD_RELOC_RX_ABS16_REV
5196 BFD_RELOC_RX_ABS32_REV
5200 BFD_RELOC_RX_ABS16UW
5202 BFD_RELOC_RX_ABS16UL
5206 Renesas RX Relocations.
5219 32 bit PC relative PLT address.
5223 Copy symbol at runtime.
5225 BFD_RELOC_390_GLOB_DAT
5229 BFD_RELOC_390_JMP_SLOT
5233 BFD_RELOC_390_RELATIVE
5235 Adjust by program base.
5239 32 bit PC relative offset to GOT.
5245 BFD_RELOC_390_PC12DBL
5247 PC relative 12 bit shifted by 1.
5249 BFD_RELOC_390_PLT12DBL
5251 12 bit PC rel. PLT shifted by 1.
5253 BFD_RELOC_390_PC16DBL
5255 PC relative 16 bit shifted by 1.
5257 BFD_RELOC_390_PLT16DBL
5259 16 bit PC rel. PLT shifted by 1.
5261 BFD_RELOC_390_PC24DBL
5263 PC relative 24 bit shifted by 1.
5265 BFD_RELOC_390_PLT24DBL
5267 24 bit PC rel. PLT shifted by 1.
5269 BFD_RELOC_390_PC32DBL
5271 PC relative 32 bit shifted by 1.
5273 BFD_RELOC_390_PLT32DBL
5275 32 bit PC rel. PLT shifted by 1.
5277 BFD_RELOC_390_GOTPCDBL
5279 32 bit PC rel. GOT shifted by 1.
5287 64 bit PC relative PLT address.
5289 BFD_RELOC_390_GOTENT
5291 32 bit rel. offset to GOT entry.
5293 BFD_RELOC_390_GOTOFF64
5295 64 bit offset to GOT.
5297 BFD_RELOC_390_GOTPLT12
5299 12-bit offset to symbol-entry within GOT, with PLT handling.
5301 BFD_RELOC_390_GOTPLT16
5303 16-bit offset to symbol-entry within GOT, with PLT handling.
5305 BFD_RELOC_390_GOTPLT32
5307 32-bit offset to symbol-entry within GOT, with PLT handling.
5309 BFD_RELOC_390_GOTPLT64
5311 64-bit offset to symbol-entry within GOT, with PLT handling.
5313 BFD_RELOC_390_GOTPLTENT
5315 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5317 BFD_RELOC_390_PLTOFF16
5319 16-bit rel. offset from the GOT to a PLT entry.
5321 BFD_RELOC_390_PLTOFF32
5323 32-bit rel. offset from the GOT to a PLT entry.
5325 BFD_RELOC_390_PLTOFF64
5327 64-bit rel. offset from the GOT to a PLT entry.
5330 BFD_RELOC_390_TLS_LOAD
5332 BFD_RELOC_390_TLS_GDCALL
5334 BFD_RELOC_390_TLS_LDCALL
5336 BFD_RELOC_390_TLS_GD32
5338 BFD_RELOC_390_TLS_GD64
5340 BFD_RELOC_390_TLS_GOTIE12
5342 BFD_RELOC_390_TLS_GOTIE32
5344 BFD_RELOC_390_TLS_GOTIE64
5346 BFD_RELOC_390_TLS_LDM32
5348 BFD_RELOC_390_TLS_LDM64
5350 BFD_RELOC_390_TLS_IE32
5352 BFD_RELOC_390_TLS_IE64
5354 BFD_RELOC_390_TLS_IEENT
5356 BFD_RELOC_390_TLS_LE32
5358 BFD_RELOC_390_TLS_LE64
5360 BFD_RELOC_390_TLS_LDO32
5362 BFD_RELOC_390_TLS_LDO64
5364 BFD_RELOC_390_TLS_DTPMOD
5366 BFD_RELOC_390_TLS_DTPOFF
5368 BFD_RELOC_390_TLS_TPOFF
5370 s390 tls relocations.
5377 BFD_RELOC_390_GOTPLT20
5379 BFD_RELOC_390_TLS_GOTIE20
5381 Long displacement extension.
5384 BFD_RELOC_390_IRELATIVE
5386 STT_GNU_IFUNC relocation.
5389 BFD_RELOC_SCORE_GPREL15
5392 Low 16 bit for load/store
5394 BFD_RELOC_SCORE_DUMMY2
5398 This is a 24-bit reloc with the right 1 bit assumed to be 0
5400 BFD_RELOC_SCORE_BRANCH
5402 This is a 19-bit reloc with the right 1 bit assumed to be 0
5404 BFD_RELOC_SCORE_IMM30
5406 This is a 32-bit reloc for 48-bit instructions.
5408 BFD_RELOC_SCORE_IMM32
5410 This is a 32-bit reloc for 48-bit instructions.
5412 BFD_RELOC_SCORE16_JMP
5414 This is a 11-bit reloc with the right 1 bit assumed to be 0
5416 BFD_RELOC_SCORE16_BRANCH
5418 This is a 8-bit reloc with the right 1 bit assumed to be 0
5420 BFD_RELOC_SCORE_BCMP
5422 This is a 9-bit reloc with the right 1 bit assumed to be 0
5424 BFD_RELOC_SCORE_GOT15
5426 BFD_RELOC_SCORE_GOT_LO16
5428 BFD_RELOC_SCORE_CALL15
5430 BFD_RELOC_SCORE_DUMMY_HI16
5432 Undocumented Score relocs
5437 Scenix IP2K - 9-bit register number / data address
5441 Scenix IP2K - 4-bit register/data bank number
5443 BFD_RELOC_IP2K_ADDR16CJP
5445 Scenix IP2K - low 13 bits of instruction word address
5447 BFD_RELOC_IP2K_PAGE3
5449 Scenix IP2K - high 3 bits of instruction word address
5451 BFD_RELOC_IP2K_LO8DATA
5453 BFD_RELOC_IP2K_HI8DATA
5455 BFD_RELOC_IP2K_EX8DATA
5457 Scenix IP2K - ext/low/high 8 bits of data address
5459 BFD_RELOC_IP2K_LO8INSN
5461 BFD_RELOC_IP2K_HI8INSN
5463 Scenix IP2K - low/high 8 bits of instruction word address
5465 BFD_RELOC_IP2K_PC_SKIP
5467 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5471 Scenix IP2K - 16 bit word address in text section.
5473 BFD_RELOC_IP2K_FR_OFFSET
5475 Scenix IP2K - 7-bit sp or dp offset
5477 BFD_RELOC_VPE4KMATH_DATA
5479 BFD_RELOC_VPE4KMATH_INSN
5481 Scenix VPE4K coprocessor - data/insn-space addressing
5484 BFD_RELOC_VTABLE_INHERIT
5486 BFD_RELOC_VTABLE_ENTRY
5488 These two relocations are used by the linker to determine which of
5489 the entries in a C++ virtual function table are actually used. When
5490 the --gc-sections option is given, the linker will zero out the entries
5491 that are not used, so that the code for those functions need not be
5492 included in the output.
5494 VTABLE_INHERIT is a zero-space relocation used to describe to the
5495 linker the inheritance tree of a C++ virtual function table. The
5496 relocation's symbol should be the parent class' vtable, and the
5497 relocation should be located at the child vtable.
5499 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5500 virtual function table entry. The reloc's symbol should refer to the
5501 table of the class mentioned in the code. Off of that base, an offset
5502 describes the entry that is being used. For Rela hosts, this offset
5503 is stored in the reloc's addend. For Rel hosts, we are forced to put
5504 this offset in the reloc's section offset.
5507 BFD_RELOC_IA64_IMM14
5509 BFD_RELOC_IA64_IMM22
5511 BFD_RELOC_IA64_IMM64
5513 BFD_RELOC_IA64_DIR32MSB
5515 BFD_RELOC_IA64_DIR32LSB
5517 BFD_RELOC_IA64_DIR64MSB
5519 BFD_RELOC_IA64_DIR64LSB
5521 BFD_RELOC_IA64_GPREL22
5523 BFD_RELOC_IA64_GPREL64I
5525 BFD_RELOC_IA64_GPREL32MSB
5527 BFD_RELOC_IA64_GPREL32LSB
5529 BFD_RELOC_IA64_GPREL64MSB
5531 BFD_RELOC_IA64_GPREL64LSB
5533 BFD_RELOC_IA64_LTOFF22
5535 BFD_RELOC_IA64_LTOFF64I
5537 BFD_RELOC_IA64_PLTOFF22
5539 BFD_RELOC_IA64_PLTOFF64I
5541 BFD_RELOC_IA64_PLTOFF64MSB
5543 BFD_RELOC_IA64_PLTOFF64LSB
5545 BFD_RELOC_IA64_FPTR64I
5547 BFD_RELOC_IA64_FPTR32MSB
5549 BFD_RELOC_IA64_FPTR32LSB
5551 BFD_RELOC_IA64_FPTR64MSB
5553 BFD_RELOC_IA64_FPTR64LSB
5555 BFD_RELOC_IA64_PCREL21B
5557 BFD_RELOC_IA64_PCREL21BI
5559 BFD_RELOC_IA64_PCREL21M
5561 BFD_RELOC_IA64_PCREL21F
5563 BFD_RELOC_IA64_PCREL22
5565 BFD_RELOC_IA64_PCREL60B
5567 BFD_RELOC_IA64_PCREL64I
5569 BFD_RELOC_IA64_PCREL32MSB
5571 BFD_RELOC_IA64_PCREL32LSB
5573 BFD_RELOC_IA64_PCREL64MSB
5575 BFD_RELOC_IA64_PCREL64LSB
5577 BFD_RELOC_IA64_LTOFF_FPTR22
5579 BFD_RELOC_IA64_LTOFF_FPTR64I
5581 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5583 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5585 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5587 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5589 BFD_RELOC_IA64_SEGREL32MSB
5591 BFD_RELOC_IA64_SEGREL32LSB
5593 BFD_RELOC_IA64_SEGREL64MSB
5595 BFD_RELOC_IA64_SEGREL64LSB
5597 BFD_RELOC_IA64_SECREL32MSB
5599 BFD_RELOC_IA64_SECREL32LSB
5601 BFD_RELOC_IA64_SECREL64MSB
5603 BFD_RELOC_IA64_SECREL64LSB
5605 BFD_RELOC_IA64_REL32MSB
5607 BFD_RELOC_IA64_REL32LSB
5609 BFD_RELOC_IA64_REL64MSB
5611 BFD_RELOC_IA64_REL64LSB
5613 BFD_RELOC_IA64_LTV32MSB
5615 BFD_RELOC_IA64_LTV32LSB
5617 BFD_RELOC_IA64_LTV64MSB
5619 BFD_RELOC_IA64_LTV64LSB
5621 BFD_RELOC_IA64_IPLTMSB
5623 BFD_RELOC_IA64_IPLTLSB
5627 BFD_RELOC_IA64_LTOFF22X
5629 BFD_RELOC_IA64_LDXMOV
5631 BFD_RELOC_IA64_TPREL14
5633 BFD_RELOC_IA64_TPREL22
5635 BFD_RELOC_IA64_TPREL64I
5637 BFD_RELOC_IA64_TPREL64MSB
5639 BFD_RELOC_IA64_TPREL64LSB
5641 BFD_RELOC_IA64_LTOFF_TPREL22
5643 BFD_RELOC_IA64_DTPMOD64MSB
5645 BFD_RELOC_IA64_DTPMOD64LSB
5647 BFD_RELOC_IA64_LTOFF_DTPMOD22
5649 BFD_RELOC_IA64_DTPREL14
5651 BFD_RELOC_IA64_DTPREL22
5653 BFD_RELOC_IA64_DTPREL64I
5655 BFD_RELOC_IA64_DTPREL32MSB
5657 BFD_RELOC_IA64_DTPREL32LSB
5659 BFD_RELOC_IA64_DTPREL64MSB
5661 BFD_RELOC_IA64_DTPREL64LSB
5663 BFD_RELOC_IA64_LTOFF_DTPREL22
5665 Intel IA64 Relocations.
5668 BFD_RELOC_M68HC11_HI8
5670 Motorola 68HC11 reloc.
5671 This is the 8 bit high part of an absolute address.
5673 BFD_RELOC_M68HC11_LO8
5675 Motorola 68HC11 reloc.
5676 This is the 8 bit low part of an absolute address.
5678 BFD_RELOC_M68HC11_3B
5680 Motorola 68HC11 reloc.
5681 This is the 3 bit of a value.
5683 BFD_RELOC_M68HC11_RL_JUMP
5685 Motorola 68HC11 reloc.
5686 This reloc marks the beginning of a jump/call instruction.
5687 It is used for linker relaxation to correctly identify beginning
5688 of instruction and change some branches to use PC-relative
5691 BFD_RELOC_M68HC11_RL_GROUP
5693 Motorola 68HC11 reloc.
5694 This reloc marks a group of several instructions that gcc generates
5695 and for which the linker relaxation pass can modify and/or remove
5698 BFD_RELOC_M68HC11_LO16
5700 Motorola 68HC11 reloc.
5701 This is the 16-bit lower part of an address. It is used for 'call'
5702 instruction to specify the symbol address without any special
5703 transformation (due to memory bank window).
5705 BFD_RELOC_M68HC11_PAGE
5707 Motorola 68HC11 reloc.
5708 This is a 8-bit reloc that specifies the page number of an address.
5709 It is used by 'call' instruction to specify the page number of
5712 BFD_RELOC_M68HC11_24
5714 Motorola 68HC11 reloc.
5715 This is a 24-bit reloc that represents the address with a 16-bit
5716 value and a 8-bit page number. The symbol address is transformed
5717 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5719 BFD_RELOC_M68HC12_5B
5721 Motorola 68HC12 reloc.
5722 This is the 5 bits of a value.
5724 BFD_RELOC_XGATE_RL_JUMP
5726 Freescale XGATE reloc.
5727 This reloc marks the beginning of a bra/jal instruction.
5729 BFD_RELOC_XGATE_RL_GROUP
5731 Freescale XGATE reloc.
5732 This reloc marks a group of several instructions that gcc generates
5733 and for which the linker relaxation pass can modify and/or remove
5736 BFD_RELOC_XGATE_LO16
5738 Freescale XGATE reloc.
5739 This is the 16-bit lower part of an address. It is used for the '16-bit'
5742 BFD_RELOC_XGATE_GPAGE
5744 Freescale XGATE reloc.
5748 Freescale XGATE reloc.
5750 BFD_RELOC_XGATE_PCREL_9
5752 Freescale XGATE reloc.
5753 This is a 9-bit pc-relative reloc.
5755 BFD_RELOC_XGATE_PCREL_10
5757 Freescale XGATE reloc.
5758 This is a 10-bit pc-relative reloc.
5760 BFD_RELOC_XGATE_IMM8_LO
5762 Freescale XGATE reloc.
5763 This is the 16-bit lower part of an address. It is used for the '16-bit'
5766 BFD_RELOC_XGATE_IMM8_HI
5768 Freescale XGATE reloc.
5769 This is the 16-bit higher part of an address. It is used for the '16-bit'
5772 BFD_RELOC_XGATE_IMM3
5774 Freescale XGATE reloc.
5775 This is a 3-bit pc-relative reloc.
5777 BFD_RELOC_XGATE_IMM4
5779 Freescale XGATE reloc.
5780 This is a 4-bit pc-relative reloc.
5782 BFD_RELOC_XGATE_IMM5
5784 Freescale XGATE reloc.
5785 This is a 5-bit pc-relative reloc.
5787 BFD_RELOC_M68HC12_9B
5789 Motorola 68HC12 reloc.
5790 This is the 9 bits of a value.
5792 BFD_RELOC_M68HC12_16B
5794 Motorola 68HC12 reloc.
5795 This is the 16 bits of a value.
5797 BFD_RELOC_M68HC12_9_PCREL
5799 Motorola 68HC12/XGATE reloc.
5800 This is a PCREL9 branch.
5802 BFD_RELOC_M68HC12_10_PCREL
5804 Motorola 68HC12/XGATE reloc.
5805 This is a PCREL10 branch.
5807 BFD_RELOC_M68HC12_LO8XG
5809 Motorola 68HC12/XGATE reloc.
5810 This is the 8 bit low part of an absolute address and immediately precedes
5811 a matching HI8XG part.
5813 BFD_RELOC_M68HC12_HI8XG
5815 Motorola 68HC12/XGATE reloc.
5816 This is the 8 bit high part of an absolute address and immediately follows
5817 a matching LO8XG part.
5819 BFD_RELOC_S12Z_15_PCREL
5821 Freescale S12Z reloc.
5822 This is a 15 bit relative address. If the most significant bits are all zero
5823 then it may be truncated to 8 bits.
5827 BFD_RELOC_16C_NUM08_C
5831 BFD_RELOC_16C_NUM16_C
5835 BFD_RELOC_16C_NUM32_C
5837 BFD_RELOC_16C_DISP04
5839 BFD_RELOC_16C_DISP04_C
5841 BFD_RELOC_16C_DISP08
5843 BFD_RELOC_16C_DISP08_C
5845 BFD_RELOC_16C_DISP16
5847 BFD_RELOC_16C_DISP16_C
5849 BFD_RELOC_16C_DISP24
5851 BFD_RELOC_16C_DISP24_C
5853 BFD_RELOC_16C_DISP24a
5855 BFD_RELOC_16C_DISP24a_C
5859 BFD_RELOC_16C_REG04_C
5861 BFD_RELOC_16C_REG04a
5863 BFD_RELOC_16C_REG04a_C
5867 BFD_RELOC_16C_REG14_C
5871 BFD_RELOC_16C_REG16_C
5875 BFD_RELOC_16C_REG20_C
5879 BFD_RELOC_16C_ABS20_C
5883 BFD_RELOC_16C_ABS24_C
5887 BFD_RELOC_16C_IMM04_C
5891 BFD_RELOC_16C_IMM16_C
5895 BFD_RELOC_16C_IMM20_C
5899 BFD_RELOC_16C_IMM24_C
5903 BFD_RELOC_16C_IMM32_C
5905 NS CR16C Relocations.
5910 BFD_RELOC_CR16_NUM16
5912 BFD_RELOC_CR16_NUM32
5914 BFD_RELOC_CR16_NUM32a
5916 BFD_RELOC_CR16_REGREL0
5918 BFD_RELOC_CR16_REGREL4
5920 BFD_RELOC_CR16_REGREL4a
5922 BFD_RELOC_CR16_REGREL14
5924 BFD_RELOC_CR16_REGREL14a
5926 BFD_RELOC_CR16_REGREL16
5928 BFD_RELOC_CR16_REGREL20
5930 BFD_RELOC_CR16_REGREL20a
5932 BFD_RELOC_CR16_ABS20
5934 BFD_RELOC_CR16_ABS24
5940 BFD_RELOC_CR16_IMM16
5942 BFD_RELOC_CR16_IMM20
5944 BFD_RELOC_CR16_IMM24
5946 BFD_RELOC_CR16_IMM32
5948 BFD_RELOC_CR16_IMM32a
5950 BFD_RELOC_CR16_DISP4
5952 BFD_RELOC_CR16_DISP8
5954 BFD_RELOC_CR16_DISP16
5956 BFD_RELOC_CR16_DISP20
5958 BFD_RELOC_CR16_DISP24
5960 BFD_RELOC_CR16_DISP24a
5962 BFD_RELOC_CR16_SWITCH8
5964 BFD_RELOC_CR16_SWITCH16
5966 BFD_RELOC_CR16_SWITCH32
5968 BFD_RELOC_CR16_GOT_REGREL20
5970 BFD_RELOC_CR16_GOTC_REGREL20
5972 BFD_RELOC_CR16_GLOB_DAT
5974 NS CR16 Relocations.
5981 BFD_RELOC_CRX_REL8_CMP
5989 BFD_RELOC_CRX_REGREL12
5991 BFD_RELOC_CRX_REGREL22
5993 BFD_RELOC_CRX_REGREL28
5995 BFD_RELOC_CRX_REGREL32
6011 BFD_RELOC_CRX_SWITCH8
6013 BFD_RELOC_CRX_SWITCH16
6015 BFD_RELOC_CRX_SWITCH32
6020 BFD_RELOC_CRIS_BDISP8
6022 BFD_RELOC_CRIS_UNSIGNED_5
6024 BFD_RELOC_CRIS_SIGNED_6
6026 BFD_RELOC_CRIS_UNSIGNED_6
6028 BFD_RELOC_CRIS_SIGNED_8
6030 BFD_RELOC_CRIS_UNSIGNED_8
6032 BFD_RELOC_CRIS_SIGNED_16
6034 BFD_RELOC_CRIS_UNSIGNED_16
6036 BFD_RELOC_CRIS_LAPCQ_OFFSET
6038 BFD_RELOC_CRIS_UNSIGNED_4
6040 These relocs are only used within the CRIS assembler. They are not
6041 (at present) written to any object files.
6045 BFD_RELOC_CRIS_GLOB_DAT
6047 BFD_RELOC_CRIS_JUMP_SLOT
6049 BFD_RELOC_CRIS_RELATIVE
6051 Relocs used in ELF shared libraries for CRIS.
6053 BFD_RELOC_CRIS_32_GOT
6055 32-bit offset to symbol-entry within GOT.
6057 BFD_RELOC_CRIS_16_GOT
6059 16-bit offset to symbol-entry within GOT.
6061 BFD_RELOC_CRIS_32_GOTPLT
6063 32-bit offset to symbol-entry within GOT, with PLT handling.
6065 BFD_RELOC_CRIS_16_GOTPLT
6067 16-bit offset to symbol-entry within GOT, with PLT handling.
6069 BFD_RELOC_CRIS_32_GOTREL
6071 32-bit offset to symbol, relative to GOT.
6073 BFD_RELOC_CRIS_32_PLT_GOTREL
6075 32-bit offset to symbol with PLT entry, relative to GOT.
6077 BFD_RELOC_CRIS_32_PLT_PCREL
6079 32-bit offset to symbol with PLT entry, relative to this relocation.
6082 BFD_RELOC_CRIS_32_GOT_GD
6084 BFD_RELOC_CRIS_16_GOT_GD
6086 BFD_RELOC_CRIS_32_GD
6090 BFD_RELOC_CRIS_32_DTPREL
6092 BFD_RELOC_CRIS_16_DTPREL
6094 BFD_RELOC_CRIS_32_GOT_TPREL
6096 BFD_RELOC_CRIS_16_GOT_TPREL
6098 BFD_RELOC_CRIS_32_TPREL
6100 BFD_RELOC_CRIS_16_TPREL
6102 BFD_RELOC_CRIS_DTPMOD
6104 BFD_RELOC_CRIS_32_IE
6106 Relocs used in TLS code for CRIS.
6109 BFD_RELOC_OR1K_REL_26
6111 BFD_RELOC_OR1K_GOTPC_HI16
6113 BFD_RELOC_OR1K_GOTPC_LO16
6115 BFD_RELOC_OR1K_GOT16
6117 BFD_RELOC_OR1K_PLT26
6119 BFD_RELOC_OR1K_GOTOFF_HI16
6121 BFD_RELOC_OR1K_GOTOFF_LO16
6125 BFD_RELOC_OR1K_GLOB_DAT
6127 BFD_RELOC_OR1K_JMP_SLOT
6129 BFD_RELOC_OR1K_RELATIVE
6131 BFD_RELOC_OR1K_TLS_GD_HI16
6133 BFD_RELOC_OR1K_TLS_GD_LO16
6135 BFD_RELOC_OR1K_TLS_LDM_HI16
6137 BFD_RELOC_OR1K_TLS_LDM_LO16
6139 BFD_RELOC_OR1K_TLS_LDO_HI16
6141 BFD_RELOC_OR1K_TLS_LDO_LO16
6143 BFD_RELOC_OR1K_TLS_IE_HI16
6145 BFD_RELOC_OR1K_TLS_IE_LO16
6147 BFD_RELOC_OR1K_TLS_LE_HI16
6149 BFD_RELOC_OR1K_TLS_LE_LO16
6151 BFD_RELOC_OR1K_TLS_TPOFF
6153 BFD_RELOC_OR1K_TLS_DTPOFF
6155 BFD_RELOC_OR1K_TLS_DTPMOD
6157 OpenRISC 1000 Relocations.
6160 BFD_RELOC_H8_DIR16A8
6162 BFD_RELOC_H8_DIR16R8
6164 BFD_RELOC_H8_DIR24A8
6166 BFD_RELOC_H8_DIR24R8
6168 BFD_RELOC_H8_DIR32A16
6170 BFD_RELOC_H8_DISP32A16
6175 BFD_RELOC_XSTORMY16_REL_12
6177 BFD_RELOC_XSTORMY16_12
6179 BFD_RELOC_XSTORMY16_24
6181 BFD_RELOC_XSTORMY16_FPTR16
6183 Sony Xstormy16 Relocations.
6188 Self-describing complex relocations.
6200 Infineon Relocations.
6203 BFD_RELOC_VAX_GLOB_DAT
6205 BFD_RELOC_VAX_JMP_SLOT
6207 BFD_RELOC_VAX_RELATIVE
6209 Relocations used by VAX ELF.
6214 Morpho MT - 16 bit immediate relocation.
6218 Morpho MT - Hi 16 bits of an address.
6222 Morpho MT - Low 16 bits of an address.
6224 BFD_RELOC_MT_GNU_VTINHERIT
6226 Morpho MT - Used to tell the linker which vtable entries are used.
6228 BFD_RELOC_MT_GNU_VTENTRY
6230 Morpho MT - Used to tell the linker which vtable entries are used.
6232 BFD_RELOC_MT_PCINSN8
6234 Morpho MT - 8 bit immediate relocation.
6237 BFD_RELOC_MSP430_10_PCREL
6239 BFD_RELOC_MSP430_16_PCREL
6243 BFD_RELOC_MSP430_16_PCREL_BYTE
6245 BFD_RELOC_MSP430_16_BYTE
6247 BFD_RELOC_MSP430_2X_PCREL
6249 BFD_RELOC_MSP430_RL_PCREL
6251 BFD_RELOC_MSP430_ABS8
6253 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6255 BFD_RELOC_MSP430X_PCR20_EXT_DST
6257 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6259 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6261 BFD_RELOC_MSP430X_ABS20_EXT_DST
6263 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6265 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6267 BFD_RELOC_MSP430X_ABS20_ADR_DST
6269 BFD_RELOC_MSP430X_PCR16
6271 BFD_RELOC_MSP430X_PCR20_CALL
6273 BFD_RELOC_MSP430X_ABS16
6275 BFD_RELOC_MSP430_ABS_HI16
6277 BFD_RELOC_MSP430_PREL31
6279 BFD_RELOC_MSP430_SYM_DIFF
6281 msp430 specific relocation codes
6288 BFD_RELOC_NIOS2_CALL26
6290 BFD_RELOC_NIOS2_IMM5
6292 BFD_RELOC_NIOS2_CACHE_OPX
6294 BFD_RELOC_NIOS2_IMM6
6296 BFD_RELOC_NIOS2_IMM8
6298 BFD_RELOC_NIOS2_HI16
6300 BFD_RELOC_NIOS2_LO16
6302 BFD_RELOC_NIOS2_HIADJ16
6304 BFD_RELOC_NIOS2_GPREL
6306 BFD_RELOC_NIOS2_UJMP
6308 BFD_RELOC_NIOS2_CJMP
6310 BFD_RELOC_NIOS2_CALLR
6312 BFD_RELOC_NIOS2_ALIGN
6314 BFD_RELOC_NIOS2_GOT16
6316 BFD_RELOC_NIOS2_CALL16
6318 BFD_RELOC_NIOS2_GOTOFF_LO
6320 BFD_RELOC_NIOS2_GOTOFF_HA
6322 BFD_RELOC_NIOS2_PCREL_LO
6324 BFD_RELOC_NIOS2_PCREL_HA
6326 BFD_RELOC_NIOS2_TLS_GD16
6328 BFD_RELOC_NIOS2_TLS_LDM16
6330 BFD_RELOC_NIOS2_TLS_LDO16
6332 BFD_RELOC_NIOS2_TLS_IE16
6334 BFD_RELOC_NIOS2_TLS_LE16
6336 BFD_RELOC_NIOS2_TLS_DTPMOD
6338 BFD_RELOC_NIOS2_TLS_DTPREL
6340 BFD_RELOC_NIOS2_TLS_TPREL
6342 BFD_RELOC_NIOS2_COPY
6344 BFD_RELOC_NIOS2_GLOB_DAT
6346 BFD_RELOC_NIOS2_JUMP_SLOT
6348 BFD_RELOC_NIOS2_RELATIVE
6350 BFD_RELOC_NIOS2_GOTOFF
6352 BFD_RELOC_NIOS2_CALL26_NOAT
6354 BFD_RELOC_NIOS2_GOT_LO
6356 BFD_RELOC_NIOS2_GOT_HA
6358 BFD_RELOC_NIOS2_CALL_LO
6360 BFD_RELOC_NIOS2_CALL_HA
6362 BFD_RELOC_NIOS2_R2_S12
6364 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6366 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6368 BFD_RELOC_NIOS2_R2_T1I7_2
6370 BFD_RELOC_NIOS2_R2_T2I4
6372 BFD_RELOC_NIOS2_R2_T2I4_1
6374 BFD_RELOC_NIOS2_R2_T2I4_2
6376 BFD_RELOC_NIOS2_R2_X1I7_2
6378 BFD_RELOC_NIOS2_R2_X2L5
6380 BFD_RELOC_NIOS2_R2_F1I5_2
6382 BFD_RELOC_NIOS2_R2_L5I4X1
6384 BFD_RELOC_NIOS2_R2_T1X1I6
6386 BFD_RELOC_NIOS2_R2_T1X1I6_2
6388 Relocations used by the Altera Nios II core.
6393 PRU LDI 16-bit unsigned data-memory relocation.
6395 BFD_RELOC_PRU_U16_PMEMIMM
6397 PRU LDI 16-bit unsigned instruction-memory relocation.
6401 PRU relocation for two consecutive LDI load instructions that load a
6402 32 bit value into a register. If the higher bits are all zero, then
6403 the second instruction may be relaxed.
6405 BFD_RELOC_PRU_S10_PCREL
6407 PRU QBBx 10-bit signed PC-relative relocation.
6409 BFD_RELOC_PRU_U8_PCREL
6411 PRU 8-bit unsigned relocation used for the LOOP instruction.
6413 BFD_RELOC_PRU_32_PMEM
6415 BFD_RELOC_PRU_16_PMEM
6417 PRU Program Memory relocations. Used to convert from byte addressing to
6418 32-bit word addressing.
6420 BFD_RELOC_PRU_GNU_DIFF8
6422 BFD_RELOC_PRU_GNU_DIFF16
6424 BFD_RELOC_PRU_GNU_DIFF32
6426 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6428 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6430 PRU relocations to mark the difference of two local symbols.
6431 These are only needed to support linker relaxation and can be ignored
6432 when not relaxing. The field is set to the value of the difference
6433 assuming no relaxation. The relocation encodes the position of the
6434 second symbol so the linker can determine whether to adjust the field
6435 value. The PMEM variants encode the word difference, instead of byte
6436 difference between symbols.
6439 BFD_RELOC_IQ2000_OFFSET_16
6441 BFD_RELOC_IQ2000_OFFSET_21
6443 BFD_RELOC_IQ2000_UHI16
6448 BFD_RELOC_XTENSA_RTLD
6450 Special Xtensa relocation used only by PLT entries in ELF shared
6451 objects to indicate that the runtime linker should set the value
6452 to one of its own internal functions or data structures.
6454 BFD_RELOC_XTENSA_GLOB_DAT
6456 BFD_RELOC_XTENSA_JMP_SLOT
6458 BFD_RELOC_XTENSA_RELATIVE
6460 Xtensa relocations for ELF shared objects.
6462 BFD_RELOC_XTENSA_PLT
6464 Xtensa relocation used in ELF object files for symbols that may require
6465 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6467 BFD_RELOC_XTENSA_DIFF8
6469 BFD_RELOC_XTENSA_DIFF16
6471 BFD_RELOC_XTENSA_DIFF32
6473 Xtensa relocations to mark the difference of two local symbols.
6474 These are only needed to support linker relaxation and can be ignored
6475 when not relaxing. The field is set to the value of the difference
6476 assuming no relaxation. The relocation encodes the position of the
6477 first symbol so the linker can determine whether to adjust the field
6480 BFD_RELOC_XTENSA_SLOT0_OP
6482 BFD_RELOC_XTENSA_SLOT1_OP
6484 BFD_RELOC_XTENSA_SLOT2_OP
6486 BFD_RELOC_XTENSA_SLOT3_OP
6488 BFD_RELOC_XTENSA_SLOT4_OP
6490 BFD_RELOC_XTENSA_SLOT5_OP
6492 BFD_RELOC_XTENSA_SLOT6_OP
6494 BFD_RELOC_XTENSA_SLOT7_OP
6496 BFD_RELOC_XTENSA_SLOT8_OP
6498 BFD_RELOC_XTENSA_SLOT9_OP
6500 BFD_RELOC_XTENSA_SLOT10_OP
6502 BFD_RELOC_XTENSA_SLOT11_OP
6504 BFD_RELOC_XTENSA_SLOT12_OP
6506 BFD_RELOC_XTENSA_SLOT13_OP
6508 BFD_RELOC_XTENSA_SLOT14_OP
6510 Generic Xtensa relocations for instruction operands. Only the slot
6511 number is encoded in the relocation. The relocation applies to the
6512 last PC-relative immediate operand, or if there are no PC-relative
6513 immediates, to the last immediate operand.
6515 BFD_RELOC_XTENSA_SLOT0_ALT
6517 BFD_RELOC_XTENSA_SLOT1_ALT
6519 BFD_RELOC_XTENSA_SLOT2_ALT
6521 BFD_RELOC_XTENSA_SLOT3_ALT
6523 BFD_RELOC_XTENSA_SLOT4_ALT
6525 BFD_RELOC_XTENSA_SLOT5_ALT
6527 BFD_RELOC_XTENSA_SLOT6_ALT
6529 BFD_RELOC_XTENSA_SLOT7_ALT
6531 BFD_RELOC_XTENSA_SLOT8_ALT
6533 BFD_RELOC_XTENSA_SLOT9_ALT
6535 BFD_RELOC_XTENSA_SLOT10_ALT
6537 BFD_RELOC_XTENSA_SLOT11_ALT
6539 BFD_RELOC_XTENSA_SLOT12_ALT
6541 BFD_RELOC_XTENSA_SLOT13_ALT
6543 BFD_RELOC_XTENSA_SLOT14_ALT
6545 Alternate Xtensa relocations. Only the slot is encoded in the
6546 relocation. The meaning of these relocations is opcode-specific.
6548 BFD_RELOC_XTENSA_OP0
6550 BFD_RELOC_XTENSA_OP1
6552 BFD_RELOC_XTENSA_OP2
6554 Xtensa relocations for backward compatibility. These have all been
6555 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6557 BFD_RELOC_XTENSA_ASM_EXPAND
6559 Xtensa relocation to mark that the assembler expanded the
6560 instructions from an original target. The expansion size is
6561 encoded in the reloc size.
6563 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6565 Xtensa relocation to mark that the linker should simplify
6566 assembler-expanded instructions. This is commonly used
6567 internally by the linker after analysis of a
6568 BFD_RELOC_XTENSA_ASM_EXPAND.
6570 BFD_RELOC_XTENSA_TLSDESC_FN
6572 BFD_RELOC_XTENSA_TLSDESC_ARG
6574 BFD_RELOC_XTENSA_TLS_DTPOFF
6576 BFD_RELOC_XTENSA_TLS_TPOFF
6578 BFD_RELOC_XTENSA_TLS_FUNC
6580 BFD_RELOC_XTENSA_TLS_ARG
6582 BFD_RELOC_XTENSA_TLS_CALL
6584 Xtensa TLS relocations.
6589 8 bit signed offset in (ix+d) or (iy+d).
6607 BFD_RELOC_LM32_BRANCH
6609 BFD_RELOC_LM32_16_GOT
6611 BFD_RELOC_LM32_GOTOFF_HI16
6613 BFD_RELOC_LM32_GOTOFF_LO16
6617 BFD_RELOC_LM32_GLOB_DAT
6619 BFD_RELOC_LM32_JMP_SLOT
6621 BFD_RELOC_LM32_RELATIVE
6623 Lattice Mico32 relocations.
6626 BFD_RELOC_MACH_O_SECTDIFF
6628 Difference between two section addreses. Must be followed by a
6629 BFD_RELOC_MACH_O_PAIR.
6631 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6633 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6635 BFD_RELOC_MACH_O_PAIR
6637 Pair of relocation. Contains the first symbol.
6639 BFD_RELOC_MACH_O_SUBTRACTOR32
6641 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6643 BFD_RELOC_MACH_O_SUBTRACTOR64
6645 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6648 BFD_RELOC_MACH_O_X86_64_BRANCH32
6650 BFD_RELOC_MACH_O_X86_64_BRANCH8
6652 PCREL relocations. They are marked as branch to create PLT entry if
6655 BFD_RELOC_MACH_O_X86_64_GOT
6657 Used when referencing a GOT entry.
6659 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6661 Used when loading a GOT entry with movq. It is specially marked so that
6662 the linker could optimize the movq to a leaq if possible.
6664 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6666 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6668 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6670 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6672 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6674 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6676 BFD_RELOC_MACH_O_X86_64_TLV
6678 Used when referencing a TLV entry.
6682 BFD_RELOC_MACH_O_ARM64_ADDEND
6684 Addend for PAGE or PAGEOFF.
6686 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6688 Relative offset to page of GOT slot.
6690 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6692 Relative offset within page of GOT slot.
6694 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6696 Address of a GOT entry.
6699 BFD_RELOC_MICROBLAZE_32_LO
6701 This is a 32 bit reloc for the microblaze that stores the
6702 low 16 bits of a value
6704 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6706 This is a 32 bit pc-relative reloc for the microblaze that
6707 stores the low 16 bits of a value
6709 BFD_RELOC_MICROBLAZE_32_ROSDA
6711 This is a 32 bit reloc for the microblaze that stores a
6712 value relative to the read-only small data area anchor
6714 BFD_RELOC_MICROBLAZE_32_RWSDA
6716 This is a 32 bit reloc for the microblaze that stores a
6717 value relative to the read-write small data area anchor
6719 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6721 This is a 32 bit reloc for the microblaze to handle
6722 expressions of the form "Symbol Op Symbol"
6724 BFD_RELOC_MICROBLAZE_64_NONE
6726 This is a 64 bit reloc that stores the 32 bit pc relative
6727 value in two words (with an imm instruction). No relocation is
6728 done here - only used for relaxing
6730 BFD_RELOC_MICROBLAZE_64_GOTPC
6732 This is a 64 bit reloc that stores the 32 bit pc relative
6733 value in two words (with an imm instruction). The relocation is
6734 PC-relative GOT offset
6736 BFD_RELOC_MICROBLAZE_64_GOT
6738 This is a 64 bit reloc that stores the 32 bit pc relative
6739 value in two words (with an imm instruction). The relocation is
6742 BFD_RELOC_MICROBLAZE_64_PLT
6744 This is a 64 bit reloc that stores the 32 bit pc relative
6745 value in two words (with an imm instruction). The relocation is
6746 PC-relative offset into PLT
6748 BFD_RELOC_MICROBLAZE_64_GOTOFF
6750 This is a 64 bit reloc that stores the 32 bit GOT relative
6751 value in two words (with an imm instruction). The relocation is
6752 relative offset from _GLOBAL_OFFSET_TABLE_
6754 BFD_RELOC_MICROBLAZE_32_GOTOFF
6756 This is a 32 bit reloc that stores the 32 bit GOT relative
6757 value in a word. The relocation is relative offset from
6758 _GLOBAL_OFFSET_TABLE_
6760 BFD_RELOC_MICROBLAZE_COPY
6762 This is used to tell the dynamic linker to copy the value out of
6763 the dynamic object into the runtime process image.
6765 BFD_RELOC_MICROBLAZE_64_TLS
6769 BFD_RELOC_MICROBLAZE_64_TLSGD
6771 This is a 64 bit reloc that stores the 32 bit GOT relative value
6772 of the GOT TLS GD info entry in two words (with an imm instruction). The
6773 relocation is GOT offset.
6775 BFD_RELOC_MICROBLAZE_64_TLSLD
6777 This is a 64 bit reloc that stores the 32 bit GOT relative value
6778 of the GOT TLS LD info entry in two words (with an imm instruction). The
6779 relocation is GOT offset.
6781 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6783 This is a 32 bit reloc that stores the Module ID to GOT(n).
6785 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6787 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6789 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6791 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6794 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6796 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6797 to two words (uses imm instruction).
6799 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6801 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6802 to two words (uses imm instruction).
6804 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6806 This is a 64 bit reloc that stores the 32 bit pc relative
6807 value in two words (with an imm instruction). The relocation is
6808 PC-relative offset from start of TEXT.
6810 BFD_RELOC_MICROBLAZE_64_TEXTREL
6812 This is a 64 bit reloc that stores the 32 bit offset
6813 value in two words (with an imm instruction). The relocation is
6814 relative offset from start of TEXT.
6817 BFD_RELOC_AARCH64_RELOC_START
6819 AArch64 pseudo relocation code to mark the start of the AArch64
6820 relocation enumerators. N.B. the order of the enumerators is
6821 important as several tables in the AArch64 bfd backend are indexed
6822 by these enumerators; make sure they are all synced.
6824 BFD_RELOC_AARCH64_NULL
6826 Deprecated AArch64 null relocation code.
6828 BFD_RELOC_AARCH64_NONE
6830 AArch64 null relocation code.
6832 BFD_RELOC_AARCH64_64
6834 BFD_RELOC_AARCH64_32
6836 BFD_RELOC_AARCH64_16
6838 Basic absolute relocations of N bits. These are equivalent to
6839 BFD_RELOC_N and they were added to assist the indexing of the howto
6842 BFD_RELOC_AARCH64_64_PCREL
6844 BFD_RELOC_AARCH64_32_PCREL
6846 BFD_RELOC_AARCH64_16_PCREL
6848 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6849 and they were added to assist the indexing of the howto table.
6851 BFD_RELOC_AARCH64_MOVW_G0
6853 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6854 of an unsigned address/value.
6856 BFD_RELOC_AARCH64_MOVW_G0_NC
6858 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6859 an address/value. No overflow checking.
6861 BFD_RELOC_AARCH64_MOVW_G1
6863 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6864 of an unsigned address/value.
6866 BFD_RELOC_AARCH64_MOVW_G1_NC
6868 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6869 of an address/value. No overflow checking.
6871 BFD_RELOC_AARCH64_MOVW_G2
6873 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6874 of an unsigned address/value.
6876 BFD_RELOC_AARCH64_MOVW_G2_NC
6878 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6879 of an address/value. No overflow checking.
6881 BFD_RELOC_AARCH64_MOVW_G3
6883 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6884 of a signed or unsigned address/value.
6886 BFD_RELOC_AARCH64_MOVW_G0_S
6888 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6889 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6892 BFD_RELOC_AARCH64_MOVW_G1_S
6894 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6895 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6898 BFD_RELOC_AARCH64_MOVW_G2_S
6900 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6901 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6904 BFD_RELOC_AARCH64_MOVW_PREL_G0
6906 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6907 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6910 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
6912 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6913 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6916 BFD_RELOC_AARCH64_MOVW_PREL_G1
6918 AArch64 MOVK instruction with most significant bits 16 to 31
6921 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
6923 AArch64 MOVK instruction with most significant bits 16 to 31
6926 BFD_RELOC_AARCH64_MOVW_PREL_G2
6928 AArch64 MOVK instruction with most significant bits 32 to 47
6931 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
6933 AArch64 MOVK instruction with most significant bits 32 to 47
6936 BFD_RELOC_AARCH64_MOVW_PREL_G3
6938 AArch64 MOVK instruction with most significant bits 47 to 63
6941 BFD_RELOC_AARCH64_LD_LO19_PCREL
6943 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6944 offset. The lowest two bits must be zero and are not stored in the
6945 instruction, giving a 21 bit signed byte offset.
6947 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6949 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6951 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6953 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6954 offset, giving a 4KB aligned page base address.
6956 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6958 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6959 offset, giving a 4KB aligned page base address, but with no overflow
6962 BFD_RELOC_AARCH64_ADD_LO12
6964 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6965 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6967 BFD_RELOC_AARCH64_LDST8_LO12
6969 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6970 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6972 BFD_RELOC_AARCH64_TSTBR14
6974 AArch64 14 bit pc-relative test bit and branch.
6975 The lowest two bits must be zero and are not stored in the instruction,
6976 giving a 16 bit signed byte offset.
6978 BFD_RELOC_AARCH64_BRANCH19
6980 AArch64 19 bit pc-relative conditional branch and compare & branch.
6981 The lowest two bits must be zero and are not stored in the instruction,
6982 giving a 21 bit signed byte offset.
6984 BFD_RELOC_AARCH64_JUMP26
6986 AArch64 26 bit pc-relative unconditional branch.
6987 The lowest two bits must be zero and are not stored in the instruction,
6988 giving a 28 bit signed byte offset.
6990 BFD_RELOC_AARCH64_CALL26
6992 AArch64 26 bit pc-relative unconditional branch and link.
6993 The lowest two bits must be zero and are not stored in the instruction,
6994 giving a 28 bit signed byte offset.
6996 BFD_RELOC_AARCH64_LDST16_LO12
6998 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6999 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7001 BFD_RELOC_AARCH64_LDST32_LO12
7003 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7004 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7006 BFD_RELOC_AARCH64_LDST64_LO12
7008 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7009 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7011 BFD_RELOC_AARCH64_LDST128_LO12
7013 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7014 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7016 BFD_RELOC_AARCH64_GOT_LD_PREL19
7018 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7019 offset of the global offset table entry for a symbol. The lowest two
7020 bits must be zero and are not stored in the instruction, giving a 21
7021 bit signed byte offset. This relocation type requires signed overflow
7024 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7026 Get to the page base of the global offset table entry for a symbol as
7027 part of an ADRP instruction using a 21 bit PC relative value.Used in
7028 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7030 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7032 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7033 the GOT entry for this symbol. Used in conjunction with
7034 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7036 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7038 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7039 the GOT entry for this symbol. Used in conjunction with
7040 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7042 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7044 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7045 for this symbol. Valid in LP64 ABI only.
7047 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7049 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7050 for this symbol. Valid in LP64 ABI only.
7052 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7054 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7055 the GOT entry for this symbol. Valid in LP64 ABI only.
7057 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7059 Scaled 14 bit byte offset to the page base of the global offset table.
7061 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7063 Scaled 15 bit byte offset to the page base of the global offset table.
7065 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7067 Get to the page base of the global offset table entry for a symbols
7068 tls_index structure as part of an adrp instruction using a 21 bit PC
7069 relative value. Used in conjunction with
7070 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7072 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7074 AArch64 TLS General Dynamic
7076 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7078 Unsigned 12 bit byte offset to global offset table entry for a symbols
7079 tls_index structure. Used in conjunction with
7080 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7082 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7084 AArch64 TLS General Dynamic relocation.
7086 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7088 AArch64 TLS General Dynamic relocation.
7090 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7092 AArch64 TLS INITIAL EXEC relocation.
7094 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7096 AArch64 TLS INITIAL EXEC relocation.
7098 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7100 AArch64 TLS INITIAL EXEC relocation.
7102 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7104 AArch64 TLS INITIAL EXEC relocation.
7106 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7108 AArch64 TLS INITIAL EXEC relocation.
7110 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7112 AArch64 TLS INITIAL EXEC relocation.
7114 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7116 bit[23:12] of byte offset to module TLS base address.
7118 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7120 Unsigned 12 bit byte offset to module TLS base address.
7122 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7124 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7126 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7128 Unsigned 12 bit byte offset to global offset table entry for a symbols
7129 tls_index structure. Used in conjunction with
7130 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7132 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7134 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7137 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7139 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7141 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7143 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7146 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7148 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7150 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7152 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7155 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7157 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7159 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7161 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7164 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7166 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7168 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7170 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7173 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7175 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7177 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7179 bit[15:0] of byte offset to module TLS base address.
7181 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7183 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7185 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7187 bit[31:16] of byte offset to module TLS base address.
7189 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7191 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7193 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7195 bit[47:32] of byte offset to module TLS base address.
7197 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7199 AArch64 TLS LOCAL EXEC relocation.
7201 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7203 AArch64 TLS LOCAL EXEC relocation.
7205 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7207 AArch64 TLS LOCAL EXEC relocation.
7209 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7211 AArch64 TLS LOCAL EXEC relocation.
7213 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7215 AArch64 TLS LOCAL EXEC relocation.
7217 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7219 AArch64 TLS LOCAL EXEC relocation.
7221 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7223 AArch64 TLS LOCAL EXEC relocation.
7225 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7227 AArch64 TLS LOCAL EXEC relocation.
7229 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7231 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7234 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7236 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7238 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7240 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7243 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7245 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7247 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7249 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7252 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7254 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7256 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7258 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7261 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7263 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7265 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7267 AArch64 TLS DESC relocation.
7269 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7271 AArch64 TLS DESC relocation.
7273 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7275 AArch64 TLS DESC relocation.
7277 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7279 AArch64 TLS DESC relocation.
7281 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7283 AArch64 TLS DESC relocation.
7285 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7287 AArch64 TLS DESC relocation.
7289 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7291 AArch64 TLS DESC relocation.
7293 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7295 AArch64 TLS DESC relocation.
7297 BFD_RELOC_AARCH64_TLSDESC_LDR
7299 AArch64 TLS DESC relocation.
7301 BFD_RELOC_AARCH64_TLSDESC_ADD
7303 AArch64 TLS DESC relocation.
7305 BFD_RELOC_AARCH64_TLSDESC_CALL
7307 AArch64 TLS DESC relocation.
7309 BFD_RELOC_AARCH64_COPY
7311 AArch64 TLS relocation.
7313 BFD_RELOC_AARCH64_GLOB_DAT
7315 AArch64 TLS relocation.
7317 BFD_RELOC_AARCH64_JUMP_SLOT
7319 AArch64 TLS relocation.
7321 BFD_RELOC_AARCH64_RELATIVE
7323 AArch64 TLS relocation.
7325 BFD_RELOC_AARCH64_TLS_DTPMOD
7327 AArch64 TLS relocation.
7329 BFD_RELOC_AARCH64_TLS_DTPREL
7331 AArch64 TLS relocation.
7333 BFD_RELOC_AARCH64_TLS_TPREL
7335 AArch64 TLS relocation.
7337 BFD_RELOC_AARCH64_TLSDESC
7339 AArch64 TLS relocation.
7341 BFD_RELOC_AARCH64_IRELATIVE
7343 AArch64 support for STT_GNU_IFUNC.
7345 BFD_RELOC_AARCH64_RELOC_END
7347 AArch64 pseudo relocation code to mark the end of the AArch64
7348 relocation enumerators that have direct mapping to ELF reloc codes.
7349 There are a few more enumerators after this one; those are mainly
7350 used by the AArch64 assembler for the internal fixup or to select
7351 one of the above enumerators.
7353 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7355 AArch64 pseudo relocation code to be used internally by the AArch64
7356 assembler and not (currently) written to any object files.
7358 BFD_RELOC_AARCH64_LDST_LO12
7360 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7361 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7363 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7365 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7366 used internally by the AArch64 assembler and not (currently) written to
7369 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7371 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7373 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7375 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7376 used internally by the AArch64 assembler and not (currently) written to
7379 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7381 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7383 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7385 AArch64 pseudo relocation code to be used internally by the AArch64
7386 assembler and not (currently) written to any object files.
7388 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7390 AArch64 pseudo relocation code to be used internally by the AArch64
7391 assembler and not (currently) written to any object files.
7393 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7395 AArch64 pseudo relocation code to be used internally by the AArch64
7396 assembler and not (currently) written to any object files.
7398 BFD_RELOC_TILEPRO_COPY
7400 BFD_RELOC_TILEPRO_GLOB_DAT
7402 BFD_RELOC_TILEPRO_JMP_SLOT
7404 BFD_RELOC_TILEPRO_RELATIVE
7406 BFD_RELOC_TILEPRO_BROFF_X1
7408 BFD_RELOC_TILEPRO_JOFFLONG_X1
7410 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7412 BFD_RELOC_TILEPRO_IMM8_X0
7414 BFD_RELOC_TILEPRO_IMM8_Y0
7416 BFD_RELOC_TILEPRO_IMM8_X1
7418 BFD_RELOC_TILEPRO_IMM8_Y1
7420 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7422 BFD_RELOC_TILEPRO_MT_IMM15_X1
7424 BFD_RELOC_TILEPRO_MF_IMM15_X1
7426 BFD_RELOC_TILEPRO_IMM16_X0
7428 BFD_RELOC_TILEPRO_IMM16_X1
7430 BFD_RELOC_TILEPRO_IMM16_X0_LO
7432 BFD_RELOC_TILEPRO_IMM16_X1_LO
7434 BFD_RELOC_TILEPRO_IMM16_X0_HI
7436 BFD_RELOC_TILEPRO_IMM16_X1_HI
7438 BFD_RELOC_TILEPRO_IMM16_X0_HA
7440 BFD_RELOC_TILEPRO_IMM16_X1_HA
7442 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7444 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7446 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7448 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7450 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7452 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7454 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7456 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7458 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7460 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7462 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7464 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7466 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7468 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7470 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7472 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7474 BFD_RELOC_TILEPRO_MMSTART_X0
7476 BFD_RELOC_TILEPRO_MMEND_X0
7478 BFD_RELOC_TILEPRO_MMSTART_X1
7480 BFD_RELOC_TILEPRO_MMEND_X1
7482 BFD_RELOC_TILEPRO_SHAMT_X0
7484 BFD_RELOC_TILEPRO_SHAMT_X1
7486 BFD_RELOC_TILEPRO_SHAMT_Y0
7488 BFD_RELOC_TILEPRO_SHAMT_Y1
7490 BFD_RELOC_TILEPRO_TLS_GD_CALL
7492 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7494 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7496 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7498 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7500 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7502 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7504 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7506 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7508 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7510 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7512 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7514 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7516 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7518 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7520 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7522 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7524 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7526 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7528 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7530 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7532 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7534 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7536 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7538 BFD_RELOC_TILEPRO_TLS_TPOFF32
7540 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7542 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7544 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7546 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7548 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7550 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7552 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7554 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7556 Tilera TILEPro Relocations.
7558 BFD_RELOC_TILEGX_HW0
7560 BFD_RELOC_TILEGX_HW1
7562 BFD_RELOC_TILEGX_HW2
7564 BFD_RELOC_TILEGX_HW3
7566 BFD_RELOC_TILEGX_HW0_LAST
7568 BFD_RELOC_TILEGX_HW1_LAST
7570 BFD_RELOC_TILEGX_HW2_LAST
7572 BFD_RELOC_TILEGX_COPY
7574 BFD_RELOC_TILEGX_GLOB_DAT
7576 BFD_RELOC_TILEGX_JMP_SLOT
7578 BFD_RELOC_TILEGX_RELATIVE
7580 BFD_RELOC_TILEGX_BROFF_X1
7582 BFD_RELOC_TILEGX_JUMPOFF_X1
7584 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7586 BFD_RELOC_TILEGX_IMM8_X0
7588 BFD_RELOC_TILEGX_IMM8_Y0
7590 BFD_RELOC_TILEGX_IMM8_X1
7592 BFD_RELOC_TILEGX_IMM8_Y1
7594 BFD_RELOC_TILEGX_DEST_IMM8_X1
7596 BFD_RELOC_TILEGX_MT_IMM14_X1
7598 BFD_RELOC_TILEGX_MF_IMM14_X1
7600 BFD_RELOC_TILEGX_MMSTART_X0
7602 BFD_RELOC_TILEGX_MMEND_X0
7604 BFD_RELOC_TILEGX_SHAMT_X0
7606 BFD_RELOC_TILEGX_SHAMT_X1
7608 BFD_RELOC_TILEGX_SHAMT_Y0
7610 BFD_RELOC_TILEGX_SHAMT_Y1
7612 BFD_RELOC_TILEGX_IMM16_X0_HW0
7614 BFD_RELOC_TILEGX_IMM16_X1_HW0
7616 BFD_RELOC_TILEGX_IMM16_X0_HW1
7618 BFD_RELOC_TILEGX_IMM16_X1_HW1
7620 BFD_RELOC_TILEGX_IMM16_X0_HW2
7622 BFD_RELOC_TILEGX_IMM16_X1_HW2
7624 BFD_RELOC_TILEGX_IMM16_X0_HW3
7626 BFD_RELOC_TILEGX_IMM16_X1_HW3
7628 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7630 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7632 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7634 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7636 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7638 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7640 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7642 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7644 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7646 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7648 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7650 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7652 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7654 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7656 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7658 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7660 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7662 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7664 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7666 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7668 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7670 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7672 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7674 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7676 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7678 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7680 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7682 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7684 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7686 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7688 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7690 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7692 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7694 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7696 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7698 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7700 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7702 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7704 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7706 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7708 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7710 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7712 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7714 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7716 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7718 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7720 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7722 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7724 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7726 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7728 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7730 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7732 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7734 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7736 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7738 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7740 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7742 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7744 BFD_RELOC_TILEGX_TLS_DTPMOD64
7746 BFD_RELOC_TILEGX_TLS_DTPOFF64
7748 BFD_RELOC_TILEGX_TLS_TPOFF64
7750 BFD_RELOC_TILEGX_TLS_DTPMOD32
7752 BFD_RELOC_TILEGX_TLS_DTPOFF32
7754 BFD_RELOC_TILEGX_TLS_TPOFF32
7756 BFD_RELOC_TILEGX_TLS_GD_CALL
7758 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7760 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7762 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7764 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7766 BFD_RELOC_TILEGX_TLS_IE_LOAD
7768 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7770 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7772 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7774 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7776 Tilera TILE-Gx Relocations.
7779 BFD_RELOC_EPIPHANY_SIMM8
7781 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7783 BFD_RELOC_EPIPHANY_SIMM24
7785 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7787 BFD_RELOC_EPIPHANY_HIGH
7789 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7791 BFD_RELOC_EPIPHANY_LOW
7793 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7795 BFD_RELOC_EPIPHANY_SIMM11
7797 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7799 BFD_RELOC_EPIPHANY_IMM11
7801 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7803 BFD_RELOC_EPIPHANY_IMM8
7805 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7808 BFD_RELOC_VISIUM_HI16
7810 BFD_RELOC_VISIUM_LO16
7812 BFD_RELOC_VISIUM_IM16
7814 BFD_RELOC_VISIUM_REL16
7816 BFD_RELOC_VISIUM_HI16_PCREL
7818 BFD_RELOC_VISIUM_LO16_PCREL
7820 BFD_RELOC_VISIUM_IM16_PCREL
7825 BFD_RELOC_WASM32_LEB128
7827 BFD_RELOC_WASM32_LEB128_GOT
7829 BFD_RELOC_WASM32_LEB128_GOT_CODE
7831 BFD_RELOC_WASM32_LEB128_PLT
7833 BFD_RELOC_WASM32_PLT_INDEX
7835 BFD_RELOC_WASM32_ABS32_CODE
7837 BFD_RELOC_WASM32_COPY
7839 BFD_RELOC_WASM32_CODE_POINTER
7841 BFD_RELOC_WASM32_INDEX
7843 BFD_RELOC_WASM32_PLT_SIG
7845 WebAssembly relocations.
7848 BFD_RELOC_CKCORE_NONE
7850 BFD_RELOC_CKCORE_ADDR32
7852 BFD_RELOC_CKCORE_PCREL_IMM8BY4
7854 BFD_RELOC_CKCORE_PCREL_IMM11BY2
7856 BFD_RELOC_CKCORE_PCREL_IMM4BY2
7858 BFD_RELOC_CKCORE_PCREL32
7860 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
7862 BFD_RELOC_CKCORE_GNU_VTINHERIT
7864 BFD_RELOC_CKCORE_GNU_VTENTRY
7866 BFD_RELOC_CKCORE_RELATIVE
7868 BFD_RELOC_CKCORE_COPY
7870 BFD_RELOC_CKCORE_GLOB_DAT
7872 BFD_RELOC_CKCORE_JUMP_SLOT
7874 BFD_RELOC_CKCORE_GOTOFF
7876 BFD_RELOC_CKCORE_GOTPC
7878 BFD_RELOC_CKCORE_GOT32
7880 BFD_RELOC_CKCORE_PLT32
7882 BFD_RELOC_CKCORE_ADDRGOT
7884 BFD_RELOC_CKCORE_ADDRPLT
7886 BFD_RELOC_CKCORE_PCREL_IMM26BY2
7888 BFD_RELOC_CKCORE_PCREL_IMM16BY2
7890 BFD_RELOC_CKCORE_PCREL_IMM16BY4
7892 BFD_RELOC_CKCORE_PCREL_IMM10BY2
7894 BFD_RELOC_CKCORE_PCREL_IMM10BY4
7896 BFD_RELOC_CKCORE_ADDR_HI16
7898 BFD_RELOC_CKCORE_ADDR_LO16
7900 BFD_RELOC_CKCORE_GOTPC_HI16
7902 BFD_RELOC_CKCORE_GOTPC_LO16
7904 BFD_RELOC_CKCORE_GOTOFF_HI16
7906 BFD_RELOC_CKCORE_GOTOFF_LO16
7908 BFD_RELOC_CKCORE_GOT12
7910 BFD_RELOC_CKCORE_GOT_HI16
7912 BFD_RELOC_CKCORE_GOT_LO16
7914 BFD_RELOC_CKCORE_PLT12
7916 BFD_RELOC_CKCORE_PLT_HI16
7918 BFD_RELOC_CKCORE_PLT_LO16
7920 BFD_RELOC_CKCORE_ADDRGOT_HI16
7922 BFD_RELOC_CKCORE_ADDRGOT_LO16
7924 BFD_RELOC_CKCORE_ADDRPLT_HI16
7926 BFD_RELOC_CKCORE_ADDRPLT_LO16
7928 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
7930 BFD_RELOC_CKCORE_TOFFSET_LO16
7932 BFD_RELOC_CKCORE_DOFFSET_LO16
7934 BFD_RELOC_CKCORE_PCREL_IMM18BY2
7936 BFD_RELOC_CKCORE_DOFFSET_IMM18
7938 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
7940 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
7942 BFD_RELOC_CKCORE_GOTOFF_IMM18
7944 BFD_RELOC_CKCORE_GOT_IMM18BY4
7946 BFD_RELOC_CKCORE_PLT_IMM18BY4
7948 BFD_RELOC_CKCORE_PCREL_IMM7BY4
7950 BFD_RELOC_CKCORE_TLS_LE32
7952 BFD_RELOC_CKCORE_TLS_IE32
7954 BFD_RELOC_CKCORE_TLS_GD32
7956 BFD_RELOC_CKCORE_TLS_LDM32
7958 BFD_RELOC_CKCORE_TLS_LDO32
7960 BFD_RELOC_CKCORE_TLS_DTPMOD32
7962 BFD_RELOC_CKCORE_TLS_DTPOFF32
7964 BFD_RELOC_CKCORE_TLS_TPOFF32
7966 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
7968 BFD_RELOC_CKCORE_NOJSRI
7970 BFD_RELOC_CKCORE_CALLGRAPH
7972 BFD_RELOC_CKCORE_IRELATIVE
7974 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
7976 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
7984 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7989 bfd_reloc_type_lookup
7990 bfd_reloc_name_lookup
7993 reloc_howto_type *bfd_reloc_type_lookup
7994 (bfd *abfd, bfd_reloc_code_real_type code);
7995 reloc_howto_type *bfd_reloc_name_lookup
7996 (bfd *abfd, const char *reloc_name);
7999 Return a pointer to a howto structure which, when
8000 invoked, will perform the relocation @var{code} on data from the
8006 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8008 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8012 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8014 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8017 static reloc_howto_type bfd_howto_32
=
8018 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
8022 bfd_default_reloc_type_lookup
8025 reloc_howto_type *bfd_default_reloc_type_lookup
8026 (bfd *abfd, bfd_reloc_code_real_type code);
8029 Provides a default relocation lookup routine for any architecture.
8034 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8038 case BFD_RELOC_CTOR
:
8039 /* The type of reloc used in a ctor, which will be as wide as the
8040 address - so either a 64, 32, or 16 bitter. */
8041 switch (bfd_arch_bits_per_address (abfd
))
8047 return &bfd_howto_32
;
8063 bfd_get_reloc_code_name
8066 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8069 Provides a printable name for the supplied relocation code.
8070 Useful mainly for printing error messages.
8074 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8076 if (code
> BFD_RELOC_UNUSED
)
8078 return bfd_reloc_code_real_names
[code
];
8083 bfd_generic_relax_section
8086 bfd_boolean bfd_generic_relax_section
8089 struct bfd_link_info *,
8093 Provides default handling for relaxing for back ends which
8098 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8099 asection
*section ATTRIBUTE_UNUSED
,
8100 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8103 if (bfd_link_relocatable (link_info
))
8104 (*link_info
->callbacks
->einfo
)
8105 (_("%P%F: --relax and -r may not be used together\n"));
8113 bfd_generic_gc_sections
8116 bfd_boolean bfd_generic_gc_sections
8117 (bfd *, struct bfd_link_info *);
8120 Provides default handling for relaxing for back ends which
8121 don't do section gc -- i.e., does nothing.
8125 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8126 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8133 bfd_generic_lookup_section_flags
8136 bfd_boolean bfd_generic_lookup_section_flags
8137 (struct bfd_link_info *, struct flag_info *, asection *);
8140 Provides default handling for section flags lookup
8141 -- i.e., does nothing.
8142 Returns FALSE if the section should be omitted, otherwise TRUE.
8146 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8147 struct flag_info
*flaginfo
,
8148 asection
*section ATTRIBUTE_UNUSED
)
8150 if (flaginfo
!= NULL
)
8152 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8160 bfd_generic_merge_sections
8163 bfd_boolean bfd_generic_merge_sections
8164 (bfd *, struct bfd_link_info *);
8167 Provides default handling for SEC_MERGE section merging for back ends
8168 which don't have SEC_MERGE support -- i.e., does nothing.
8172 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8173 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8180 bfd_generic_get_relocated_section_contents
8183 bfd_byte *bfd_generic_get_relocated_section_contents
8185 struct bfd_link_info *link_info,
8186 struct bfd_link_order *link_order,
8188 bfd_boolean relocatable,
8192 Provides default handling of relocation effort for back ends
8193 which can't be bothered to do it efficiently.
8198 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8199 struct bfd_link_info
*link_info
,
8200 struct bfd_link_order
*link_order
,
8202 bfd_boolean relocatable
,
8205 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8206 asection
*input_section
= link_order
->u
.indirect
.section
;
8208 arelent
**reloc_vector
;
8211 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8215 /* Read in the section. */
8216 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8222 if (reloc_size
== 0)
8225 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8226 if (reloc_vector
== NULL
)
8229 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8233 if (reloc_count
< 0)
8236 if (reloc_count
> 0)
8240 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8242 char *error_message
= NULL
;
8244 bfd_reloc_status_type r
;
8246 symbol
= *(*parent
)->sym_ptr_ptr
;
8247 /* PR ld/19628: A specially crafted input file
8248 can result in a NULL symbol pointer here. */
8251 link_info
->callbacks
->einfo
8252 /* xgettext:c-format */
8253 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8254 abfd
, input_section
, (* parent
)->address
);
8258 if (symbol
->section
&& discarded_section (symbol
->section
))
8261 static reloc_howto_type none_howto
8262 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
8263 "unused", FALSE
, 0, 0, FALSE
);
8265 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
8266 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
8268 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8269 (*parent
)->addend
= 0;
8270 (*parent
)->howto
= &none_howto
;
8274 r
= bfd_perform_relocation (input_bfd
,
8278 relocatable
? abfd
: NULL
,
8283 asection
*os
= input_section
->output_section
;
8285 /* A partial link, so keep the relocs. */
8286 os
->orelocation
[os
->reloc_count
] = *parent
;
8290 if (r
!= bfd_reloc_ok
)
8294 case bfd_reloc_undefined
:
8295 (*link_info
->callbacks
->undefined_symbol
)
8296 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8297 input_bfd
, input_section
, (*parent
)->address
, TRUE
);
8299 case bfd_reloc_dangerous
:
8300 BFD_ASSERT (error_message
!= NULL
);
8301 (*link_info
->callbacks
->reloc_dangerous
)
8302 (link_info
, error_message
,
8303 input_bfd
, input_section
, (*parent
)->address
);
8305 case bfd_reloc_overflow
:
8306 (*link_info
->callbacks
->reloc_overflow
)
8308 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8309 (*parent
)->howto
->name
, (*parent
)->addend
,
8310 input_bfd
, input_section
, (*parent
)->address
);
8312 case bfd_reloc_outofrange
:
8314 This error can result when processing some partially
8315 complete binaries. Do not abort, but issue an error
8317 link_info
->callbacks
->einfo
8318 /* xgettext:c-format */
8319 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8320 abfd
, input_section
, * parent
);
8323 case bfd_reloc_notsupported
:
8325 This error can result when processing a corrupt binary.
8326 Do not abort. Issue an error message instead. */
8327 link_info
->callbacks
->einfo
8328 /* xgettext:c-format */
8329 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8330 abfd
, input_section
, * parent
);
8334 /* PR 17512; file: 90c2a92e.
8335 Report unexpected results, without aborting. */
8336 link_info
->callbacks
->einfo
8337 /* xgettext:c-format */
8338 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8339 abfd
, input_section
, * parent
, r
);
8347 free (reloc_vector
);
8351 free (reloc_vector
);
8357 _bfd_generic_set_reloc
8360 void _bfd_generic_set_reloc
8364 unsigned int count);
8367 Installs a new set of internal relocations in SECTION.
8371 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8376 section
->orelocation
= relptr
;
8377 section
->reloc_count
= count
;
8382 _bfd_unrecognized_reloc
8385 bfd_boolean _bfd_unrecognized_reloc
8388 unsigned int r_type);
8391 Reports an unrecognized reloc.
8392 Written as a function in order to reduce code duplication.
8393 Returns FALSE so that it can be called from a return statement.
8397 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8399 /* xgettext:c-format */
8400 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8401 abfd
, r_type
, section
);
8403 /* PR 21803: Suggest the most likely cause of this error. */
8404 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8405 BFD_VERSION_STRING
);
8407 bfd_set_error (bfd_error_bad_value
);
8412 _bfd_norelocs_bfd_reloc_type_lookup
8414 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8416 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8420 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8421 const char *reloc_name ATTRIBUTE_UNUSED
)
8423 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8427 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8428 arelent
**relp ATTRIBUTE_UNUSED
,
8429 asymbol
**symp ATTRIBUTE_UNUSED
)
8431 return _bfd_long_bfd_n1_error (abfd
);