1 /* Disassemble i80960 instructions.
2 Copyright (C) 1990, 1991 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Diddler.
6 BFD is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 BFD is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with BFD; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 extern char *xmalloc();
28 static char *reg_names
[] = {
29 /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
30 /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
31 /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
32 /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
33 /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
37 static FILE *stream
; /* Output goes here */
38 static void print_addr();
46 static void invalid();
48 static void put_abs();
51 /* Print the i960 instruction at address 'memaddr' in debugged memory,
52 * on stream 's'. Returns length of the instruction, in bytes.
55 print_insn_i960( memaddr
, buffer
, s
)
60 unsigned int word1
, word2
;
63 word1
=buffer
[0] |( buffer
[1]<< 8) | (buffer
[2] << 16) | ( buffer
[3] <<24);
64 word2
=buffer
[4] |( buffer
[5]<< 8) | (buffer
[6] << 16) | ( buffer
[7] <<24);
65 return pinsn( memaddr
, word1
, word2
);
70 /*****************************************************************************
71 * All code below this point should be identical with that of
72 * the disassembler in gdmp960.
73 *****************************************************************************/
81 pinsn( memaddr
, word1
, word2
)
82 unsigned long memaddr
;
83 unsigned long word1
, word2
;
88 put_abs( word1
, word2
);
90 /* Divide instruction set into classes based on high 4 bits of opcode*/
91 switch ( (word1
>> 28) & 0xf ){
94 ctrl( memaddr
, word1
, word2
);
98 cobr( memaddr
, word1
, word2
);
110 instr_len
= mem( memaddr
, word1
, word2
, 0 );
113 /* invalid instruction, print as data word */
120 /****************************************/
122 /****************************************/
124 ctrl( memaddr
, word1
, word2
)
125 unsigned long memaddr
;
126 unsigned long word1
, word2
;
129 static struct tabent ctrl_tab
[] = {
139 "call", 1, /* 0x09 */
154 "faultno", 0, /* 0x18 */
155 "faultg", 0, /* 0x19 */
156 "faulte", 0, /* 0x1a */
157 "faultge", 0, /* 0x1b */
158 "faultl", 0, /* 0x1c */
159 "faultne", 0, /* 0x1d */
160 "faultle", 0, /* 0x1e */
161 "faulto", 0, /* 0x1f */
164 i
= (word1
>> 24) & 0xff;
165 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
170 fputs( ctrl_tab
[i
].name
, stream
);
171 if ( word1
& 2 ){ /* Predicts branch not taken */
172 fputs( ".f", stream
);
175 if ( ctrl_tab
[i
].numops
== 1 ){
176 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
178 if ( word1
& 0x00800000 ){ /* Sign bit is set */
179 word1
|= (-1 & ~0xffffff); /* Sign extend */
181 putc( '\t', stream
);
182 print_addr( word1
+ memaddr
);
186 /****************************************/
188 /****************************************/
190 cobr( memaddr
, word1
, word2
)
191 unsigned long memaddr
;
192 unsigned long word1
, word2
;
198 static struct tabent cobr_tab
[] = {
199 "testno", 1, /* 0x20 */
200 "testg", 1, /* 0x21 */
201 "teste", 1, /* 0x22 */
202 "testge", 1, /* 0x23 */
203 "testl", 1, /* 0x24 */
204 "testne", 1, /* 0x25 */
205 "testle", 1, /* 0x26 */
206 "testo", 1, /* 0x27 */
216 "cmpobg", 3, /* 0x31 */
217 "cmpobe", 3, /* 0x32 */
218 "cmpobge", 3, /* 0x33 */
219 "cmpobl", 3, /* 0x34 */
220 "cmpobne", 3, /* 0x35 */
221 "cmpoble", 3, /* 0x36 */
223 "cmpibno", 3, /* 0x38 */
224 "cmpibg", 3, /* 0x39 */
225 "cmpibe", 3, /* 0x3a */
226 "cmpibge", 3, /* 0x3b */
227 "cmpibl", 3, /* 0x3c */
228 "cmpibne", 3, /* 0x3d */
229 "cmpible", 3, /* 0x3e */
230 "cmpibo", 3, /* 0x3f */
233 i
= ((word1
>> 24) & 0xff) - 0x20;
234 if ( cobr_tab
[i
].name
== NULL
){
239 fputs( cobr_tab
[i
].name
, stream
);
240 if ( word1
& 2 ){ /* Predicts branch not taken */
241 fputs( ".f", stream
);
243 putc( '\t', stream
);
245 src1
= (word1
>> 19) & 0x1f;
246 src2
= (word1
>> 14) & 0x1f;
248 if ( word1
& 0x02000 ){ /* M1 is 1 */
249 fprintf( stream
, "%d", src1
);
250 } else { /* M1 is 0 */
251 fputs( reg_names
[src1
], stream
);
254 if ( cobr_tab
[i
].numops
> 1 ){
255 if ( word1
& 1 ){ /* S2 is 1 */
256 fprintf( stream
, ",sf%d,", src2
);
257 } else { /* S1 is 0 */
258 fprintf( stream
, ",%s,", reg_names
[src2
] );
261 /* Extract displacement and convert to address
264 if ( word1
& 0x00001000 ){ /* Negative displacement */
265 word1
|= (-1 & ~0x1fff); /* Sign extend */
267 print_addr( memaddr
+ word1
);
271 /****************************************/
273 /****************************************/
274 static int /* returns instruction length: 4 or 8 */
275 mem( memaddr
, word1
, word2
, noprint
)
276 unsigned long memaddr
;
277 unsigned long word1
, word2
;
278 int noprint
; /* If TRUE, return instruction length, but
279 * don't output any text.
286 char *reg1
, *reg2
, *reg3
;
288 /* This lookup table is too sparse to make it worth typing in, but not
289 * so large as to make a sparse array necessary. We allocate the
290 * table at runtime, initialize all entries to empty, and copy the
291 * real ones in from an initialization table.
293 * NOTE: In this table, the meaning of 'numops' is:
295 * 2: 2 operands, load instruction
296 * -2: 2 operands, store instruction
298 static struct tabent
*mem_tab
= NULL
;
299 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
322 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
326 if ( mem_tab
== NULL
){
327 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
328 bzero( (void *) mem_tab
, MEM_SIZ
);
329 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
330 j
= mem_init
[i
].opcode
- MEM_MIN
;
331 mem_tab
[j
].name
= mem_init
[i
].name
;
332 mem_tab
[j
].numops
= mem_init
[i
].numops
;
336 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
337 mode
= (word1
>> 10) & 0xf;
339 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
340 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
350 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
355 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
357 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
358 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
359 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
360 offset
= word1
& 0xfff; /* MEMA only */
362 switch ( mem_tab
[i
].numops
){
364 case 2: /* LOAD INSTRUCTION */
365 if ( mode
& 4 ){ /* MEMB FORMAT */
366 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
367 fprintf( stream
, ",%s", reg1
);
368 } else { /* MEMA FORMAT */
369 fprintf( stream
, "0x%x", (unsigned) offset
);
371 fprintf( stream
, "(%s)", reg2
);
373 fprintf( stream
, ",%s", reg1
);
377 case -2: /* STORE INSTRUCTION */
378 if ( mode
& 4 ){ /* MEMB FORMAT */
379 fprintf( stream
, "%s,", reg1
);
380 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
381 } else { /* MEMA FORMAT */
382 fprintf( stream
, "%s,0x%x", reg1
, (unsigned) offset
);
384 fprintf( stream
, "(%s)", reg2
);
389 case 1: /* BX/CALLX INSTRUCTION */
390 if ( mode
& 4 ){ /* MEMB FORMAT */
391 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
392 } else { /* MEMA FORMAT */
393 fprintf( stream
, "0x%x", (unsigned) offset
);
395 fprintf( stream
, "(%s)", reg2
);
404 /****************************************/
406 /****************************************/
419 /* This lookup table is too sparse to make it worth typing in, but not
420 * so large as to make a sparse array necessary. We allocate the
421 * table at runtime, initialize all entries to empty, and copy the
422 * real ones in from an initialization table.
424 * NOTE: In this table, the meaning of 'numops' is:
425 * 1: single operand, which is NOT a destination.
426 * -1: single operand, which IS a destination.
427 * 2: 2 operands, the 2nd of which is NOT a destination.
428 * -2: 2 operands, the 2nd of which IS a destination.
431 * If an opcode mnemonic begins with "F", it is a floating-point
432 * opcode (the "F" is not printed).
435 static struct tabent
*reg_tab
= NULL
;
436 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
437 #define REG_MIN 0x580
452 0x58f, "alterbit", 3,
471 0x5ac, "scanbyte", 2,
488 0x613, "inspacc", -2,
494 0x640, "spanbit", -2,
495 0x641, "scanbit", -2,
500 0x646, "condrec", -2,
505 0x656, "receive", -2,
509 0x663, "sendserv", 1,
510 0x664, "resumprcs", 1,
511 0x665, "schedprcs", 1,
512 0x666, "saveprcs", 0,
513 0x668, "condwait", 1,
518 0x66d, "flushreg", 0,
524 0x675, "Fcvtilr", -2,
525 0x676, "Fscalerl", 3,
535 0x68a, "Flogbnr", -2,
536 0x68b, "Froundr", -2,
542 0x691, "Flogeprl", 3,
547 0x698, "Fsqrtrl", -2,
549 0x69a, "Flogbnrl", -2,
550 0x69b, "Froundrl", -2,
554 0x69f, "Fclassrl", 1,
556 0x6c1, "Fcvtril", -2,
557 0x6c2, "Fcvtzri", -2,
558 0x6c3, "Fcvtzril", -2,
563 0x6e3, "Fcpyrsre", 3,
579 #define REG_MAX 0x79f
580 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
584 if ( reg_tab
== NULL
){
585 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
586 bzero( (void *) reg_tab
, REG_SIZ
);
587 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
588 j
= reg_init
[i
].opcode
- REG_MIN
;
589 reg_tab
[j
].name
= reg_init
[i
].name
;
590 reg_tab
[j
].numops
= reg_init
[i
].numops
;
594 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
595 i
= opcode
- REG_MIN
;
597 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
602 mnemp
= reg_tab
[i
].name
;
603 if ( *mnemp
== 'F' ){
610 fputs( mnemp
, stream
);
612 s1
= (word1
>> 5) & 1;
613 s2
= (word1
>> 6) & 1;
614 m1
= (word1
>> 11) & 1;
615 m2
= (word1
>> 12) & 1;
616 m3
= (word1
>> 13) & 1;
618 src2
= (word1
>> 14) & 0x1f;
619 dst
= (word1
>> 19) & 0x1f;
621 if ( reg_tab
[i
].numops
!= 0 ){
622 putc( '\t', stream
);
624 switch ( reg_tab
[i
].numops
){
626 regop( m1
, s1
, src
, fp
);
629 dstop( m3
, dst
, fp
);
632 regop( m1
, s1
, src
, fp
);
634 regop( m2
, s2
, src2
, fp
);
637 regop( m1
, s1
, src
, fp
);
639 dstop( m3
, dst
, fp
);
642 regop( m1
, s1
, src
, fp
);
644 regop( m2
, s2
, src2
, fp
);
646 dstop( m3
, dst
, fp
);
654 * Print out effective address for memb instructions.
657 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
658 unsigned long memaddr
;
665 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
667 scale
= (word1
>> 7) & 0x07;
668 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
672 scale
= scale_tab
[scale
];
676 fprintf( stream
, "(%s)", reg2
);
678 case 5: /* displ+8(ip) */
679 print_addr( word2
+8+memaddr
);
681 case 7: /* (reg)[index*scale] */
683 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
685 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
688 case 12: /* displacement */
691 case 13: /* displ(reg) */
693 fprintf( stream
, "(%s)", reg2
);
695 case 14: /* displ[index*scale] */
698 fprintf( stream
, "[%s]", reg3
);
700 fprintf( stream
, "[%s*%d]", reg3
, scale
);
703 case 15: /* displ(reg)[index*scale] */
706 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
708 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
718 /************************************************/
719 /* Register Instruction Operand */
720 /************************************************/
722 regop( mode
, spec
, reg
, fp
)
723 int mode
, spec
, reg
, fp
;
725 if ( fp
){ /* FLOATING POINT INSTRUCTION */
726 if ( mode
== 1 ){ /* FP operand */
728 case 0: fputs( "fp0", stream
); break;
729 case 1: fputs( "fp1", stream
); break;
730 case 2: fputs( "fp2", stream
); break;
731 case 3: fputs( "fp3", stream
); break;
732 case 16: fputs( "0f0.0", stream
); break;
733 case 22: fputs( "0f1.0", stream
); break;
734 default: putc( '?', stream
); break;
736 } else { /* Non-FP register */
737 fputs( reg_names
[reg
], stream
);
739 } else { /* NOT FLOATING POINT */
740 if ( mode
== 1 ){ /* Literal */
741 fprintf( stream
, "%d", reg
);
742 } else { /* Register */
744 fputs( reg_names
[reg
], stream
);
746 fprintf( stream
, "sf%d", reg
);
752 /************************************************/
753 /* Register Instruction Destination Operand */
754 /************************************************/
756 dstop( mode
, reg
, fp
)
759 /* 'dst' operand can't be a literal. On non-FP instructions, register
760 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
761 * sf registers are not allowed so m3 acts normally.
764 regop( mode
, 0, reg
, fp
);
766 regop( 0, mode
, reg
, fp
);
775 fprintf( stream
, ".word\t0x%08x", (unsigned) word1
);
782 fprintf( stream
, "0x%x", (unsigned) a
);
786 put_abs( word1
, word2
)
787 unsigned long word1
, word2
;
794 switch ( (word1
>> 28) & 0xf ){
800 /* MEM format instruction */
801 len
= mem( 0, word1
, word2
, 1 );
809 fprintf( stream
, "%08x %08x\t", word1
, word2
);
811 fprintf( stream
, "%08x \t", word1
);
This page took 0.047915 seconds and 4 git commands to generate.