1 /* Disassemble i80960 instructions.
4 /* Copyright (C) 1990, 1991 Free Software Foundation, Inc.
6 This file is part of BFD, the Binary File Diddler.
8 BFD is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 1, or (at your option)
13 BFD is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with BFD; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
29 extern char *xmalloc();
32 static char *reg_names
[] = {
33 /* 0 */ "pfp", "sp", "rip", "r3", "r4", "r5", "r6", "r7",
34 /* 8 */ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
35 /* 16 */ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
36 /* 24 */ "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp",
37 /* 32 */ "pc", "ac", "ip", "tc", "fp0", "fp1", "fp2", "fp3"
41 static FILE *stream
; /* Output goes here */
42 static void print_addr();
50 static void invalid();
52 static void put_abs();
55 /* Print the i960 instruction at address 'memaddr' in debugged memory,
56 * on stream 's'. Returns length of the instruction, in bytes.
59 print_insn_i960( memaddr
, buffer
, s
)
64 unsigned int word1
, word2
;
67 word1
=buffer
[0] |( buffer
[1]<< 8) | (buffer
[2] << 16) | ( buffer
[3] <<24);
68 word2
=buffer
[4] |( buffer
[5]<< 8) | (buffer
[6] << 16) | ( buffer
[7] <<24);
69 return pinsn( memaddr
, word1
, word2
);
74 /*****************************************************************************
75 * All code below this point should be identical with that of
76 * the disassembler in gdmp960.
77 *****************************************************************************/
85 pinsn( memaddr
, word1
, word2
)
86 unsigned long memaddr
;
87 unsigned long word1
, word2
;
92 put_abs( word1
, word2
);
94 /* Divide instruction set into classes based on high 4 bits of opcode*/
95 switch ( (word1
>> 28) & 0xf ){
98 ctrl( memaddr
, word1
, word2
);
102 cobr( memaddr
, word1
, word2
);
114 instr_len
= mem( memaddr
, word1
, word2
, 0 );
117 /* invalid instruction, print as data word */
124 /****************************************/
126 /****************************************/
128 ctrl( memaddr
, word1
, word2
)
129 unsigned long memaddr
;
130 unsigned long word1
, word2
;
133 static struct tabent ctrl_tab
[] = {
143 "call", 1, /* 0x09 */
158 "faultno", 0, /* 0x18 */
159 "faultg", 0, /* 0x19 */
160 "faulte", 0, /* 0x1a */
161 "faultge", 0, /* 0x1b */
162 "faultl", 0, /* 0x1c */
163 "faultne", 0, /* 0x1d */
164 "faultle", 0, /* 0x1e */
165 "faulto", 0, /* 0x1f */
168 i
= (word1
>> 24) & 0xff;
169 if ( (ctrl_tab
[i
].name
== NULL
) || ((word1
& 1) != 0) ){
174 fputs( ctrl_tab
[i
].name
, stream
);
175 if ( word1
& 2 ){ /* Predicts branch not taken */
176 fputs( ".f", stream
);
179 if ( ctrl_tab
[i
].numops
== 1 ){
180 /* EXTRACT DISPLACEMENT AND CONVERT TO ADDRESS */
182 if ( word1
& 0x00800000 ){ /* Sign bit is set */
183 word1
|= (-1 & ~0xffffff); /* Sign extend */
185 putc( '\t', stream
);
186 print_addr( word1
+ memaddr
);
190 /****************************************/
192 /****************************************/
194 cobr( memaddr
, word1
, word2
)
195 unsigned long memaddr
;
196 unsigned long word1
, word2
;
202 static struct tabent cobr_tab
[] = {
203 "testno", 1, /* 0x20 */
204 "testg", 1, /* 0x21 */
205 "teste", 1, /* 0x22 */
206 "testge", 1, /* 0x23 */
207 "testl", 1, /* 0x24 */
208 "testne", 1, /* 0x25 */
209 "testle", 1, /* 0x26 */
210 "testo", 1, /* 0x27 */
220 "cmpobg", 3, /* 0x31 */
221 "cmpobe", 3, /* 0x32 */
222 "cmpobge", 3, /* 0x33 */
223 "cmpobl", 3, /* 0x34 */
224 "cmpobne", 3, /* 0x35 */
225 "cmpoble", 3, /* 0x36 */
227 "cmpibno", 3, /* 0x38 */
228 "cmpibg", 3, /* 0x39 */
229 "cmpibe", 3, /* 0x3a */
230 "cmpibge", 3, /* 0x3b */
231 "cmpibl", 3, /* 0x3c */
232 "cmpibne", 3, /* 0x3d */
233 "cmpible", 3, /* 0x3e */
234 "cmpibo", 3, /* 0x3f */
237 i
= ((word1
>> 24) & 0xff) - 0x20;
238 if ( cobr_tab
[i
].name
== NULL
){
243 fputs( cobr_tab
[i
].name
, stream
);
244 if ( word1
& 2 ){ /* Predicts branch not taken */
245 fputs( ".f", stream
);
247 putc( '\t', stream
);
249 src1
= (word1
>> 19) & 0x1f;
250 src2
= (word1
>> 14) & 0x1f;
252 if ( word1
& 0x02000 ){ /* M1 is 1 */
253 fprintf( stream
, "%d", src1
);
254 } else { /* M1 is 0 */
255 fputs( reg_names
[src1
], stream
);
258 if ( cobr_tab
[i
].numops
> 1 ){
259 if ( word1
& 1 ){ /* S2 is 1 */
260 fprintf( stream
, ",sf%d,", src2
);
261 } else { /* S1 is 0 */
262 fprintf( stream
, ",%s,", reg_names
[src2
] );
265 /* Extract displacement and convert to address
268 if ( word1
& 0x00001000 ){ /* Negative displacement */
269 word1
|= (-1 & ~0x1fff); /* Sign extend */
271 print_addr( memaddr
+ word1
);
275 /****************************************/
277 /****************************************/
278 static int /* returns instruction length: 4 or 8 */
279 mem( memaddr
, word1
, word2
, noprint
)
280 unsigned long memaddr
;
281 unsigned long word1
, word2
;
282 int noprint
; /* If TRUE, return instruction length, but
283 * don't output any text.
290 char *reg1
, *reg2
, *reg3
;
292 /* This lookup table is too sparse to make it worth typing in, but not
293 * so large as to make a sparse array necessary. We allocate the
294 * table at runtime, initialize all entries to empty, and copy the
295 * real ones in from an initialization table.
297 * NOTE: In this table, the meaning of 'numops' is:
299 * 2: 2 operands, load instruction
300 * -2: 2 operands, store instruction
302 static struct tabent
*mem_tab
= NULL
;
303 static struct { int opcode
; char *name
; char numops
; } mem_init
[] = {
326 #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent))
330 if ( mem_tab
== NULL
){
331 mem_tab
= (struct tabent
*) xmalloc( MEM_SIZ
);
332 bzero( (void *) mem_tab
, MEM_SIZ
);
333 for ( i
= 0; mem_init
[i
].opcode
!= 0; i
++ ){
334 j
= mem_init
[i
].opcode
- MEM_MIN
;
335 mem_tab
[j
].name
= mem_init
[i
].name
;
336 mem_tab
[j
].numops
= mem_init
[i
].numops
;
340 i
= ((word1
>> 24) & 0xff) - MEM_MIN
;
341 mode
= (word1
>> 10) & 0xf;
343 if ( (mem_tab
[i
].name
!= NULL
) /* Valid instruction */
344 && ((mode
== 5) || (mode
>=12)) ){ /* With 32-bit displacement */
354 if ( (mem_tab
[i
].name
== NULL
) || (mode
== 6) ){
359 fprintf( stream
, "%s\t", mem_tab
[i
].name
);
361 reg1
= reg_names
[ (word1
>> 19) & 0x1f ]; /* MEMB only */
362 reg2
= reg_names
[ (word1
>> 14) & 0x1f ];
363 reg3
= reg_names
[ word1
& 0x1f ]; /* MEMB only */
364 offset
= word1
& 0xfff; /* MEMA only */
366 switch ( mem_tab
[i
].numops
){
368 case 2: /* LOAD INSTRUCTION */
369 if ( mode
& 4 ){ /* MEMB FORMAT */
370 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
371 fprintf( stream
, ",%s", reg1
);
372 } else { /* MEMA FORMAT */
373 fprintf( stream
, "0x%x", (unsigned) offset
);
375 fprintf( stream
, "(%s)", reg2
);
377 fprintf( stream
, ",%s", reg1
);
381 case -2: /* STORE INSTRUCTION */
382 if ( mode
& 4 ){ /* MEMB FORMAT */
383 fprintf( stream
, "%s,", reg1
);
384 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
385 } else { /* MEMA FORMAT */
386 fprintf( stream
, "%s,0x%x", reg1
, (unsigned) offset
);
388 fprintf( stream
, "(%s)", reg2
);
393 case 1: /* BX/CALLX INSTRUCTION */
394 if ( mode
& 4 ){ /* MEMB FORMAT */
395 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
);
396 } else { /* MEMA FORMAT */
397 fprintf( stream
, "0x%x", (unsigned) offset
);
399 fprintf( stream
, "(%s)", reg2
);
408 /****************************************/
410 /****************************************/
423 /* This lookup table is too sparse to make it worth typing in, but not
424 * so large as to make a sparse array necessary. We allocate the
425 * table at runtime, initialize all entries to empty, and copy the
426 * real ones in from an initialization table.
428 * NOTE: In this table, the meaning of 'numops' is:
429 * 1: single operand, which is NOT a destination.
430 * -1: single operand, which IS a destination.
431 * 2: 2 operands, the 2nd of which is NOT a destination.
432 * -2: 2 operands, the 2nd of which IS a destination.
435 * If an opcode mnemonic begins with "F", it is a floating-point
436 * opcode (the "F" is not printed).
439 static struct tabent
*reg_tab
= NULL
;
440 static struct { int opcode
; char *name
; char numops
; } reg_init
[] = {
441 #define REG_MIN 0x580
456 0x58f, "alterbit", 3,
475 0x5ac, "scanbyte", 2,
492 0x613, "inspacc", -2,
498 0x640, "spanbit", -2,
499 0x641, "scanbit", -2,
504 0x646, "condrec", -2,
509 0x656, "receive", -2,
513 0x663, "sendserv", 1,
514 0x664, "resumprcs", 1,
515 0x665, "schedprcs", 1,
516 0x666, "saveprcs", 0,
517 0x668, "condwait", 1,
522 0x66d, "flushreg", 0,
528 0x675, "Fcvtilr", -2,
529 0x676, "Fscalerl", 3,
539 0x68a, "Flogbnr", -2,
540 0x68b, "Froundr", -2,
546 0x691, "Flogeprl", 3,
551 0x698, "Fsqrtrl", -2,
553 0x69a, "Flogbnrl", -2,
554 0x69b, "Froundrl", -2,
558 0x69f, "Fclassrl", 1,
560 0x6c1, "Fcvtril", -2,
561 0x6c2, "Fcvtzri", -2,
562 0x6c3, "Fcvtzril", -2,
567 0x6e3, "Fcpyrsre", 3,
583 #define REG_MAX 0x79f
584 #define REG_SIZ ((REG_MAX-REG_MIN+1) * sizeof(struct tabent))
588 if ( reg_tab
== NULL
){
589 reg_tab
= (struct tabent
*) xmalloc( REG_SIZ
);
590 bzero( (void *) reg_tab
, REG_SIZ
);
591 for ( i
= 0; reg_init
[i
].opcode
!= 0; i
++ ){
592 j
= reg_init
[i
].opcode
- REG_MIN
;
593 reg_tab
[j
].name
= reg_init
[i
].name
;
594 reg_tab
[j
].numops
= reg_init
[i
].numops
;
598 opcode
= ((word1
>> 20) & 0xff0) | ((word1
>> 7) & 0xf);
599 i
= opcode
- REG_MIN
;
601 if ( (opcode
<REG_MIN
) || (opcode
>REG_MAX
) || (reg_tab
[i
].name
==NULL
) ){
606 mnemp
= reg_tab
[i
].name
;
607 if ( *mnemp
== 'F' ){
614 fputs( mnemp
, stream
);
616 s1
= (word1
>> 5) & 1;
617 s2
= (word1
>> 6) & 1;
618 m1
= (word1
>> 11) & 1;
619 m2
= (word1
>> 12) & 1;
620 m3
= (word1
>> 13) & 1;
622 src2
= (word1
>> 14) & 0x1f;
623 dst
= (word1
>> 19) & 0x1f;
625 if ( reg_tab
[i
].numops
!= 0 ){
626 putc( '\t', stream
);
628 switch ( reg_tab
[i
].numops
){
630 regop( m1
, s1
, src
, fp
);
633 dstop( m3
, dst
, fp
);
636 regop( m1
, s1
, src
, fp
);
638 regop( m2
, s2
, src2
, fp
);
641 regop( m1
, s1
, src
, fp
);
643 dstop( m3
, dst
, fp
);
646 regop( m1
, s1
, src
, fp
);
648 regop( m2
, s2
, src2
, fp
);
650 dstop( m3
, dst
, fp
);
658 * Print out effective address for memb instructions.
661 ea( memaddr
, mode
, reg2
, reg3
, word1
, word2
)
662 unsigned long memaddr
;
669 static int scale_tab
[] = { 1, 2, 4, 8, 16 };
671 scale
= (word1
>> 7) & 0x07;
672 if ( (scale
> 4) || ((word1
>> 5) & 0x03 != 0) ){
676 scale
= scale_tab
[scale
];
680 fprintf( stream
, "(%s)", reg2
);
682 case 5: /* displ+8(ip) */
683 print_addr( word2
+8+memaddr
);
685 case 7: /* (reg)[index*scale] */
687 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
689 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
692 case 12: /* displacement */
695 case 13: /* displ(reg) */
697 fprintf( stream
, "(%s)", reg2
);
699 case 14: /* displ[index*scale] */
702 fprintf( stream
, "[%s]", reg3
);
704 fprintf( stream
, "[%s*%d]", reg3
, scale
);
707 case 15: /* displ(reg)[index*scale] */
710 fprintf( stream
, "(%s)[%s]", reg2
, reg3
);
712 fprintf( stream
, "(%s)[%s*%d]",reg2
,reg3
,scale
);
722 /************************************************/
723 /* Register Instruction Operand */
724 /************************************************/
726 regop( mode
, spec
, reg
, fp
)
727 int mode
, spec
, reg
, fp
;
729 if ( fp
){ /* FLOATING POINT INSTRUCTION */
730 if ( mode
== 1 ){ /* FP operand */
732 case 0: fputs( "fp0", stream
); break;
733 case 1: fputs( "fp1", stream
); break;
734 case 2: fputs( "fp2", stream
); break;
735 case 3: fputs( "fp3", stream
); break;
736 case 16: fputs( "0f0.0", stream
); break;
737 case 22: fputs( "0f1.0", stream
); break;
738 default: putc( '?', stream
); break;
740 } else { /* Non-FP register */
741 fputs( reg_names
[reg
], stream
);
743 } else { /* NOT FLOATING POINT */
744 if ( mode
== 1 ){ /* Literal */
745 fprintf( stream
, "%d", reg
);
746 } else { /* Register */
748 fputs( reg_names
[reg
], stream
);
750 fprintf( stream
, "sf%d", reg
);
756 /************************************************/
757 /* Register Instruction Destination Operand */
758 /************************************************/
760 dstop( mode
, reg
, fp
)
763 /* 'dst' operand can't be a literal. On non-FP instructions, register
764 * mode is assumed and "m3" acts as if were "s3"; on FP-instructions,
765 * sf registers are not allowed so m3 acts normally.
768 regop( mode
, 0, reg
, fp
);
770 regop( 0, mode
, reg
, fp
);
779 fprintf( stream
, ".word\t0x%08x", (unsigned) word1
);
786 fprintf( stream
, "0x%x", (unsigned) a
);
790 put_abs( word1
, word2
)
791 unsigned long word1
, word2
;
798 switch ( (word1
>> 28) & 0xf ){
804 /* MEM format instruction */
805 len
= mem( 0, word1
, word2
, 1 );
813 fprintf( stream
, "%08x %08x\t", word1
, word2
);
815 fprintf( stream
, "%08x \t", word1
);
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