cpu/m32r.cpu

   1 ; Renesas M32R CPU description.  -*- Scheme -*-
   2 ;
   3 ; Copyright 1998, 1999, 2000, 2001, 2003, 2007 Free Software Foundation, Inc.
   4 ;
   5 ; Contributed by Red Hat Inc; developed under contract from Mitsubishi
   6 ; Electric Corporation.
   7 ;
   8 ; This file is part of the GNU Binutils.
   9 ;
  10 ; This program is free software; you can redistribute it and/or modify
  11 ; it under the terms of the GNU General Public License as published by
  12 ; the Free Software Foundation; either version 3 of the License, or
  13 ; (at your option) any later version.
  14 ;
  15 ; This program is distributed in the hope that it will be useful,
  16 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 ; GNU General Public License for more details.
  19 ;
  20 ; You should have received a copy of the GNU General Public License
  21 ; along with this program; if not, write to the Free Software
  22 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  23 ; MA 02110-1301, USA.
  24
  25 (include "simplify.inc")
  26
  27 ; FIXME: Delete sign extension of accumulator results.
  28 ; Sign extension is done when accumulator is read.
  29
  30 ; define-arch must appear first
  31
  32 (define-arch
  33   (name m32r) ; name of cpu family
  34   (comment "Renesas M32R")
  35   (default-alignment aligned)
  36   (insn-lsb0? #f)
  37   (machs m32r m32rx m32r2)
  38   (isas m32r)
  39 )
  40
  41 ; Attributes.
  42
  43 ; An attribute to describe which pipeline an insn runs in.
  44 ; O_OS is a special attribute for sll, sra, sla, slli, srai, slai.
  45 ; These instructions have O attribute for m32rx and OS attribute for m32r2.
  46
  47 (define-attr
  48   (for insn)
  49   (type enum)
  50   (name PIPE)
  51   (comment "parallel execution pipeline selection")
  52   (values NONE O S OS O_OS)
  53 )
  54
  55 ; A derived attribute that says which insns can be executed in parallel
  56 ; with others.  This is a required attribute for architectures with
  57 ; parallel execution.
  58
  59 (define-attr
  60   (for insn)
  61   (type enum)
  62   (name PARALLEL)
  63   (attrs META) ; do not define in any generated file for now
  64   (values NO YES)
  65   (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
  66 )
  67
  68 ; Instruction set parameters.
  69
  70 (define-isa
  71   (name m32r)
  72
  73   ; This is 32 because 16 bit insns always appear as pairs.
  74   ; ??? See if this can go away.  It's only used by the disassembler (right?)
  75   ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
  76   ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
  77   (default-insn-bitsize 32)
  78
  79   ; Number of bytes of insn we can initially fetch.
  80   ; The M32R is tricky in that insns are either two 16-bit insns
  81   ; (executed sequentially or in parallel) or one 32-bit insn.
  82   ; So on one hand the base insn size is 16 bits, but on another it's 32.
  83   ; 32 is chosen because:
  84   ; - if the chip were ever bi-endian it is believed that the byte order would
  85   ;   be based on 32 bit quantities
  86   ; - 32 bit insns are always aligned on 32 bit boundaries
  87   ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
  88   ;   [well actually it can, but there are no branches to such places]
  89   (base-insn-bitsize 32)
  90
  91   ; Used in computing bit numbers.
  92   (default-insn-word-bitsize 32)
  93
  94   ; The m32r fetches 2 insns at a time.
  95   (liw-insns 2)
  96
  97   ; While the m32r can execute insns in parallel, the base mach can't
  98   ; (other than nop).  The base mach is greatly handicapped by this, but
  99   ; we still need to cleanly handle it.
 100   (parallel-insns 2)
 101
 102   ; Initial bitnumbers to decode insns by.
 103   (decode-assist (0 1 2 3 8 9 10 11))
 104
 105   ; Classification of instructions that fit in the various frames.
 106   ; wip, not currently used
 107   (insn-types (long ; name
 108                31 ; length
 109                (eq-attr (current-insn) LENGTH 31) ; matching insns
 110                (0 1 2 7 8 9 10) ; decode-assist
 111                )
 112               (short
 113                15
 114                (eq-attr (current-insn) LENGTH 15) ; matching insns
 115                (0 1 2 7 8 9 10)
 116                )
 117               )
 118
 119   ; Instruction framing.
 120   ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
 121   ; serially (left->right), or two 16 bit insns executed parallelly.
 122   ; wip, not currently used
 123   (frame long32 ; name
 124          ((long)) ; list of insns in frame, plus constraint
 125          "$0"   ; assembler
 126          (+ (1 1) (31 $0)) ; value
 127          (sequence () (execute $0)) ; action
 128          )
 129   (frame serial2x16
 130          ((short)
 131           (short))
 132          "$0 -> $1"
 133          (+ (1 0) (15 $0) (1 0) (15 $1))
 134          (sequence ()
 135                    (execute $0)
 136                    (execute $1))
 137          )
 138   (frame parallel2x16
 139          ((short (eq-attr (current-insn) PIPE "O,BOTH"))
 140           (short (eq-attr (current-insn) PIPE "S,BOTH")))
 141          "$0 || $1"
 142          (+ (1 0) (15 $0) (1 1) (15 $1))
 143          (parallel ()
 144                    (execute $0)
 145                    (execute $1))
 146          )
 147 )
 148 \f
 149 ; Cpu family definitions.
 150
 151 ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
 152 ; define-cpu.
 153 ; ??? Have define-arch provide defaults for architecture that define-cpu can
 154 ; then override [reduces duplication in define-cpu].
 155 ; ??? Another way to go is to delete cpu-families entirely and have one mach
 156 ; able to inherit things from another mach (would also need the ability to
 157 ; not only override specific inherited things but also disable some,
 158 ; e.g. if an insn wasn't supported).
 159
 160 (define-cpu
 161   ; cpu names must be distinct from the architecture name and machine names.
 162   ; The "b" suffix stands for "base" and is the convention.
 163   ; The "f" suffix stands for "family" and is the convention.
 164   (name m32rbf)
 165   (comment "Renesas M32R base family")
 166   (endian either)
 167   (word-bitsize 32)
 168   ; Override isa spec (??? keeps things simpler, though it was more true
 169   ; in the early days and not so much now).
 170   (parallel-insns 1)
 171 )
 172
 173 (define-cpu
 174   (name m32rxf)
 175   (comment "Renesas M32Rx family")
 176   (endian either)
 177   (word-bitsize 32)
 178   ; Generated files have an "x" suffix.
 179   (file-transform "x")
 180 )
 181
 182 (define-cpu
 183   (name m32r2f)
 184   (comment "Renesas M32R2 family")
 185   (endian either)
 186   (word-bitsize 32)
 187   ; Generated files have an "2" suffix.
 188   (file-transform "2")
 189 )
 190
 191 (define-mach
 192   (name m32r)
 193   (comment "Generic M32R cpu")
 194   (cpu m32rbf)
 195 )
 196
 197 (define-mach
 198   (name m32rx)
 199   (comment "M32RX cpu")
 200   (cpu m32rxf)
 201 )
 202
 203 (define-mach
 204   (name m32r2)
 205   (comment "M32R2 cpu")
 206   (cpu m32r2f)
 207 )
 208 \f
 209 ; Model descriptions.
 210
 211 ; The meaning of this value is wip but at the moment it's intended to describe
 212 ; the implementation (i.e. what -mtune=foo does in sparc gcc).
 213 ;
 214 ; Notes while wip:
 215 ; - format of pipeline entry:
 216 ;   (pipeline name (stage1-name ...) (stage2-name ...) ...)
 217 ;   The contents of a stage description is wip.
 218 ; - each mach must have at least one model
 219 ; - the default model must be the first one
 220 ;- maybe have `retire' support update total cycle count to handle current
 221 ;  parallel insn cycle counting problems
 222
 223 (define-model
 224   (name m32r/d) (comment "m32r/d") (attrs)
 225   (mach m32r)
 226
 227   ;(prefetch)
 228   ;(retire)
 229
 230   (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
 231   (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
 232
 233   ; `state' is a list of variables for recording model state
 234   (state
 235    ; bit mask of h-gr registers, =1 means value being loaded from memory
 236    (h-gr UINT)
 237    )
 238
 239   (unit u-exec "Execution Unit" ()
 240         1 1 ; issue done
 241         () ; state
 242         ((sr INT -1) (dr INT -1)) ; inputs
 243         ((dr INT -1)) ; outputs
 244         () ; profile action (default)
 245         )
 246   (unit u-cmp "Compare Unit" ()
 247         1 1 ; issue done
 248         () ; state
 249         ((src1 INT -1) (src2 INT -1)) ; inputs
 250         () ; outputs
 251         () ; profile action (default)
 252         )
 253   (unit u-mac "Multiply/Accumulate Unit" ()
 254         1 1 ; issue done
 255         () ; state
 256         ((src1 INT -1) (src2 INT -1)) ; inputs
 257         () ; outputs
 258         () ; profile action (default)
 259         )
 260   (unit u-cti "Branch Unit" ()
 261         1 1 ; issue done
 262         () ; state
 263         ((sr INT -1)) ; inputs
 264         ((pc)) ; outputs
 265         () ; profile action (default)
 266         )
 267   (unit u-load "Memory Load Unit" ()
 268         1 1 ; issue done
 269         () ; state
 270         ((sr INT)
 271          ;(ld-mem AI)
 272          ) ; inputs
 273         ((dr INT)) ; outputs
 274         () ; profile action (default)
 275         )
 276   (unit u-store "Memory Store Unit" ()
 277         1 1 ; issue done
 278         () ; state
 279         ((src1 INT) (src2 INT)) ; inputs
 280         () ; ((st-mem AI)) ; outputs
 281         () ; profile action (default)
 282         )
 283 )
 284
 285 (define-model
 286   (name test) (comment "test") (attrs)
 287   (mach m32r)
 288   (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
 289   (unit u-exec "Execution Unit" ()
 290         1 1 ; issue done
 291         () () () ())
 292 )
 293
 294 ; Each mach must have at least one model.
 295
 296 (define-model
 297   (name m32rx) (comment "m32rx") (attrs)
 298   (mach m32rx)
 299
 300   ; ??? It's 6 stages but I forget the details right now.
 301   (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
 302   (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
 303   (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
 304
 305   (unit u-exec "Execution Unit" ()
 306         1 1 ; issue done
 307         () ; state
 308         ((sr INT -1) (dr INT -1)) ; inputs
 309         ((dr INT -1)) ; outputs
 310         () ; profile action (default)
 311         )
 312   (unit u-cmp "Compare Unit" ()
 313         1 1 ; issue done
 314         () ; state
 315         ((src1 INT -1) (src2 INT -1)) ; inputs
 316         () ; outputs
 317         () ; profile action (default)
 318         )
 319   (unit u-mac "Multiply/Accumulate Unit" ()
 320         1 1 ; issue done
 321         () ; state
 322         ((src1 INT -1) (src2 INT -1)) ; inputs
 323         () ; outputs
 324         () ; profile action (default)
 325         )
 326   (unit u-cti "Branch Unit" ()
 327         1 1 ; issue done
 328         () ; state
 329         ((sr INT -1)) ; inputs
 330         ((pc)) ; outputs
 331         () ; profile action (default)
 332         )
 333   (unit u-load "Memory Load Unit" ()
 334         1 1 ; issue done
 335         () ; state
 336         ((sr INT)) ; inputs
 337         ((dr INT)) ; outputs
 338         () ; profile action (default)
 339         )
 340   (unit u-store "Memory Store Unit" ()
 341         1 1 ; issue done
 342         () ; state
 343         ((src1 INT) (src2 INT)) ; inputs
 344         () ; outputs
 345         () ; profile action (default)
 346         )
 347 )
 348
 349 (define-model
 350   (name m32r2) (comment "m32r2") (attrs)
 351   (mach m32r2)
 352
 353   ; ??? It's 6 stages but I forget the details right now.
 354   (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
 355   (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
 356   (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
 357
 358   (unit u-exec "Execution Unit" ()
 359         1 1 ; issue done
 360         () ; state
 361         ((sr INT -1) (dr INT -1)) ; inputs
 362         ((dr INT -1)) ; outputs
 363         () ; profile action (default)
 364         )
 365   (unit u-cmp "Compare Unit" ()
 366         1 1 ; issue done
 367         () ; state
 368         ((src1 INT -1) (src2 INT -1)) ; inputs
 369         () ; outputs
 370         () ; profile action (default)
 371         )
 372   (unit u-mac "Multiply/Accumulate Unit" ()
 373         1 1 ; issue done
 374         () ; state
 375         ((src1 INT -1) (src2 INT -1)) ; inputs
 376         () ; outputs
 377         () ; profile action (default)
 378         )
 379   (unit u-cti "Branch Unit" ()
 380         1 1 ; issue done
 381         () ; state
 382         ((sr INT -1)) ; inputs
 383         ((pc)) ; outputs
 384         () ; profile action (default)
 385         )
 386   (unit u-load "Memory Load Unit" ()
 387         1 1 ; issue done
 388         () ; state
 389         ((sr INT)) ; inputs
 390         ((dr INT)) ; outputs
 391         () ; profile action (default)
 392         )
 393   (unit u-store "Memory Store Unit" ()
 394         1 1 ; issue done
 395         () ; state
 396         ((src1 INT) (src2 INT)) ; inputs
 397         () ; outputs
 398         () ; profile action (default)
 399         )
 400 )
 401 \f
 402 ; The instruction fetch/execute cycle.
 403 ; This is split into two parts as sometimes more than one instruction is
 404 ; decoded at once.
 405 ; The `const SI' argument to decode/execute is used to distinguish
 406 ; multiple instructions processed at the same time (e.g. m32r).
 407 ;
 408 ; ??? This is wip, and not currently used.
 409 ; ??? Needs to be moved to define-isa.
 410
 411 ; This is how to fetch and decode an instruction.
 412
 413 ;(define-extract
 414 ;  (sequence VOID
 415 ;           (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
 416 ;               (sequence VOID
 417 ;                         (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
 418 ;                         (decode VOID pc (and UHI insn1 (const UHI #x7fff))
 419 ;                                 (const SI 0)))
 420 ;               (sequence VOID
 421 ;                         (set-quiet USI (scratch USI insn) (ifetch USI pc))
 422 ;                         (if VOID (ne USI (and USI insn (const USI #x80000000))
 423 ;                                    (const USI 0))
 424 ;                             (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
 425 ;                             (sequence VOID
 426 ;                                       ; ??? parallel support
 427 ;                                       (decode VOID pc (srl USI insn (const WI 16))
 428 ;                                               (const SI 0))
 429 ;                                       (decode VOID (add AI pc (const AI 2))
 430 ;                                               (and USI insn (const WI #x7fff))
 431 ;                                               (const SI 1))))))
 432 ;           )
 433 ;)
 434
 435 ; This is how to execute a decoded instruction.
 436
 437 ;(define-execute
 438 ;  (sequence VOID () ; () is empty option list
 439 ;            ((AI new_pc))
 440 ;            (set AI new_pc (execute: AI (const 0)) #:quiet)
 441 ;            (set AI pc new_pc #:direct)
 442 ;            )
 443 ;)
 444
 445 ; FIXME: It might simplify things to separate the execute process from the
 446 ; one that updates the PC.
 447 \f
 448 ; Instruction fields.
 449 ;
 450 ; Attributes:
 451 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
 452 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
 453 ; RESERVED: bits are not used to decode insn, must be all 0
 454 ; RELOC: there is a relocation associated with this field (experiment)
 455
 456 (define-attr
 457   (for ifield operand)
 458   (type boolean)
 459   (name RELOC)
 460   (comment "there is a reloc associated with this field (experiment)")
 461 )
 462
 463 (dnf f-op1       "op1"                 () 0 4)
 464 (dnf f-op2       "op2"                 () 8 4)
 465 (dnf f-cond      "cond"                () 4 4)
 466 (dnf f-r1        "r1"                  () 4 4)
 467 (dnf f-r2        "r2"                  () 12 4)
 468 (df f-simm8      "simm8"               () 8 8 INT #f #f)
 469 (df f-simm16     "simm16"              () 16 16 INT #f #f)
 470 (dnf f-shift-op2 "shift op2"           () 8 3)
 471 (dnf f-uimm3     "uimm3"               () 5 3)
 472 (dnf f-uimm4     "uimm4"               () 12 4)
 473 (dnf f-uimm5     "uimm5"               () 11 5)
 474 (dnf f-uimm8     "uimm8"               () 8 8)
 475 (dnf f-uimm16    "uimm16"              () 16 16)
 476 (dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)
 477 (dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
 478 (df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
 479     ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
 480     ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
 481 (df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
 482     ((value pc) (sra WI (sub WI value pc) (const 2)))
 483     ((value pc) (add WI (sll WI value (const 2)) pc)))
 484 (df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
 485     ((value pc) (sra WI (sub WI value pc) (const 2)))
 486     ((value pc) (add WI (sll WI value (const 2)) pc)))
 487
 488 (dnf f-op23      "op2.3"               ()  9 3)
 489 (dnf f-op3       "op3"                 () 14 2)
 490 (dnf f-acc       "acc"                 ()  8 1)
 491 (dnf f-accs      "accs"                () 12 2)
 492 (dnf f-accd      "accd"                ()  4 2)
 493 (dnf f-bits67    "bits67"              ()  6 2)
 494 (dnf f-bit4      "bit4"                ()  4 1)
 495 (dnf f-bit14     "bit14"               () 14 1)
 496
 497 (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
 498   (attrs)
 499   (start 15) (length 1)
 500   (encode (value pc) (sub WI value (const WI 1)))
 501   (decode (value pc) (add WI value (const WI 1)))
 502 )
 503 \f
 504 ; Enums.
 505
 506 ; insn-op1: bits 0-3
 507 ; FIXME: should use die macro or some such
 508 (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
 509   ("0" "1" "2" "3" "4" "5" "6" "7"
 510    "8" "9" "10" "11" "12" "13" "14" "15")
 511 )
 512
 513 ; insn-op2: bits 8-11
 514 ; FIXME: should use die macro or some such
 515 (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
 516   ("0" "1" "2" "3" "4" "5" "6" "7"
 517    "8" "9" "10" "11" "12" "13" "14" "15")
 518 )
 519 \f
 520 ; Hardware pieces.
 521 ; These entries list the elements of the raw hardware.
 522 ; They're also used to provide tables and other elements of the assembly
 523 ; language.
 524
 525 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
 526
 527 (dnh h-hi16 "high 16 bits" ()
 528      (immediate (UINT 16))
 529      () () ()
 530 )
 531
 532 ; These two aren't technically needed.
 533 ; They're here for illustration sake mostly.
 534 ; Plus they cause the value to be stored in the extraction buffers to only
 535 ; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.
 536 (dnh h-slo16 "signed low 16 bits" ()
 537      (immediate (INT 16))
 538      () () ()
 539 )
 540 (dnh h-ulo16 "unsigned low 16 bits" ()
 541      (immediate (UINT 16))
 542      () () ()
 543 )
 544
 545 (define-keyword
 546   (name gr-names)
 547   (print-name h-gr)
 548   (prefix "")
 549   (values (fp 13) (lr 14) (sp 15)
 550           (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
 551           (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
 552 )
 553
 554 (define-hardware
 555   (name h-gr)
 556   (comment "general registers")
 557   (attrs PROFILE CACHE-ADDR)
 558   (type register WI (16))
 559   (indices extern-keyword gr-names)
 560 )
 561
 562 (define-keyword
 563   (name cr-names)
 564   (print-name h-cr)
 565   (prefix "")
 566   (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)
 567           (bpc 6)   (bbpsw 8) (bbpc 14) (evb 5)
 568           (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)
 569           (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)
 570           (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)
 571           (cr12 12) (cr13 13) (cr14 14) (cr15 15))
 572 )
 573
 574 (define-hardware
 575   (name h-cr)
 576   (comment "control registers")
 577   (type register UWI (16))
 578   (indices extern-keyword cr-names)
 579   (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
 580   (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
 581 )
 582
 583 ; The actual accumulator is only 56 bits.
 584 ; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
 585 ; To simplify the accumulator instructions, no attempt is made to keep the
 586 ; top 8 bits properly sign extended (currently there's no point since they
 587 ; all ignore them).  When the value is read it is properly sign extended
 588 ; [in the `get' handler].
 589 (define-hardware
 590   (name h-accum)
 591   (comment "accumulator")
 592   (type register DI)
 593   (get () (c-call DI "@cpu@_h_accum_get_handler"))
 594   (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
 595 )
 596
 597 ; FIXME: Revisit after sanitization can be removed.  Remove h-accum.
 598 (define-hardware
 599   (name h-accums)
 600   (comment "accumulators")
 601   (attrs (MACH m32rx,m32r2))
 602   (type register DI (2))
 603   (indices keyword "" ((a0 0) (a1 1)))
 604   ; get/set so a0 accesses are redirected to h-accum.
 605   ; They're also so reads can properly sign extend the value.
 606   ; FIXME: Needn't be a function call.
 607   (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
 608   (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
 609 )
 610
 611 ; For condbit operand.  FIXME: Need to allow spec of get/set of operands.
 612 ; Having this separate from h-psw keeps the parts that use it simpler
 613 ; [since they greatly outnumber those that use h-psw].
 614 (dsh h-cond "condition bit" () (register BI))
 615
 616 ; The actual values of psw,bpsw,bbpsw are recorded here to allow access
 617 ; to them as a unit.
 618 (define-hardware
 619   (name h-psw)
 620   (comment "psw part of psw")
 621   (type register UQI)
 622   ; get/set to handle cond bit.
 623   ; FIXME: missing: use's and clobber's
 624   ; FIXME: remove c-call?
 625   (get () (c-call UQI "@cpu@_h_psw_get_handler"))
 626   (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
 627 )
 628 (dsh h-bpsw  "backup psw"      () (register UQI))
 629 (dsh h-bbpsw "backup bpsw"     () (register UQI))
 630
 631 ; FIXME: Later make add get/set specs and support SMP.
 632 (dsh h-lock  "lock"  () (register BI))
 633 \f
 634 ; Instruction Operands.
 635 ; These entries provide a layer between the assembler and the raw hardware
 636 ; description, and are used to refer to hardware elements in the semantic
 637 ; code.  Usually there's a bit of over-specification, but in more complicated
 638 ; instruction sets there isn't.
 639
 640 ; M32R specific operand attributes:
 641
 642 (define-attr
 643   (for operand)
 644   (type boolean)
 645   (name HASH-PREFIX)
 646   (comment "immediates have an optional '#' prefix")
 647 )
 648
 649 ; ??? Convention says this should be o-sr, but then the insn definitions
 650 ; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
 651 ; then it should be implicit for all the symbols here, but then there would
 652 ; be confusion between (f-)simm8 and (h-)simm8.
 653 ; So for now the rule is exactly as it appears here.
 654
 655 (dnop sr     "source register"              () h-gr   f-r2)
 656 (dnop dr     "destination register"         () h-gr   f-r1)
 657 ;; The assembler relies upon the fact that dr and src1 are the same field.
 658 ;; FIXME: Revisit.
 659 (dnop src1   "source register 1"            () h-gr   f-r1)
 660 (dnop src2   "source register 2"            () h-gr   f-r2)
 661 (dnop scr    "source control register"      () h-cr   f-r2)
 662 (dnop dcr    "destination control register" () h-cr   f-r1)
 663
 664 (dnop simm8  "8 bit signed immediate"       (HASH-PREFIX) h-sint f-simm8)
 665 (dnop simm16 "16 bit signed immediate"      (HASH-PREFIX) h-sint f-simm16)
 666 (dnop uimm3  "3 bit unsigned number"        (HASH-PREFIX) h-uint f-uimm3)
 667 (dnop uimm4  "4 bit trap number"            (HASH-PREFIX) h-uint f-uimm4)
 668 (dnop uimm5  "5 bit shift count"            (HASH-PREFIX) h-uint f-uimm5)
 669 (dnop uimm8  "8 bit unsigned immediate"     (HASH-PREFIX) h-uint f-uimm8)
 670 (dnop uimm16 "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
 671
 672 (dnop imm1   "1 bit immediate"              ((MACH m32rx,m32r2) HASH-PREFIX) h-uint f-imm1)
 673 (dnop accd   "accumulator destination register" ((MACH m32rx,m32r2))        h-accums f-accd)
 674 (dnop accs   "accumulator source register"  ((MACH m32rx,m32r2))            h-accums f-accs)
 675 (dnop acc    "accumulator reg (d)"          ((MACH m32rx,m32r2))            h-accums f-acc)
 676
 677 ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
 678 ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use HASH-PREFIX.
 679 ; Instead we create a fake operand `hash'.  The m32r is an illustration port,
 680 ; so we often try out various ways of doing things.
 681
 682 (define-operand (name hash) (comment "# prefix") (attrs)
 683   (type h-sint) ; doesn't really matter
 684   (index f-nil)
 685   (handlers (parse "hash") (print "hash"))
 686 )
 687
 688 ; For high(foo),shigh(foo).
 689 (define-operand
 690   (name hi16)
 691   (comment "high 16 bit immediate, sign optional")
 692   (attrs)
 693   (type h-hi16)
 694   (index f-hi16)
 695   (handlers (parse "hi16"))
 696 )
 697
 698 ; For low(foo),sda(foo).
 699 (define-operand
 700   (name slo16)
 701   (comment "16 bit signed immediate, for low()")
 702   (attrs)
 703   (type h-slo16)
 704   (index f-simm16)
 705   (handlers (parse "slo16"))
 706 )
 707
 708 ; For low(foo).
 709 (define-operand
 710   (name ulo16)
 711   (comment "16 bit unsigned immediate, for low()")
 712   (attrs)
 713   (type h-ulo16)
 714   (index f-uimm16)
 715   (handlers (parse "ulo16"))
 716 )
 717
 718 (dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
 719
 720 (define-operand
 721   (name disp8)
 722   (comment "8 bit displacement")
 723   (attrs RELAX)
 724   (type h-iaddr)
 725   (index f-disp8)
 726   ; ??? Early experiments had insert/extract fields here.
 727   ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
 728   ; fields here to handle more complicated cases.
 729 )
 730
 731 (dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
 732 (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
 733
 734 ; These hardware elements are refered to frequently.
 735
 736 (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
 737 (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
 738 \f
 739 ; Instruction definitions.
 740 ;
 741 ; Notes while wip:
 742 ; - dni is a cover macro to the real "this is an instruction" keyword.
 743 ;   The syntax of the real one is yet to be determined.
 744 ;   At the lowest level (i.e. the "real" one) it will probably take a variable
 745 ;   list of arguments where each argument [perhaps after the standard three of
 746 ;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple
 747 ;   and yet completely upward extensible.  And given the macro facility, one
 748 ;   needn't code at that low a level so even though it'll be more verbose than
 749 ;   necessary it won't matter.  This same reasoning can be applied to most
 750 ;   types of entries in this file.
 751
 752 ; M32R specific instruction attributes:
 753
 754 ; FILL-SLOT: Need next insn to begin on 32 bit boundary.
 755 ; (A "slot" as used here is a 32 bit quantity that can either be filled with
 756 ; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
 757 ; bin" where the left bin is the one with a lower address).
 758
 759 (define-attr
 760   (for insn)
 761   (type boolean)
 762   (name FILL-SLOT)
 763   (comment "fill right bin with `nop' if insn is in left bin")
 764 )
 765
 766 (define-attr
 767   (for insn)
 768   (type boolean)
 769   (name SPECIAL)
 770   (comment "non-public m32rx insn")
 771 )
 772
 773 (define-attr
 774   (for insn)
 775   (type boolean)
 776   (name SPECIAL_M32R)
 777   (comment "non-public m32r insn")
 778 )
 779
 780 (define-attr
 781   (for insn)
 782   (type boolean)
 783   (name SPECIAL_FLOAT)
 784   (comment "floating point insn")
 785 )
 786
 787 ; IDOC attribute for instruction documentation.
 788
 789 (define-attr
 790   (for insn)
 791   (type enum)
 792   (name IDOC)
 793   (comment "insn kind for documentation")
 794   (attrs META)
 795   (values
 796    (MEM - () "Memory")
 797    (ALU - () "ALU")
 798    (BR - () "Branch")
 799    (ACCUM - () "Accumulator")
 800    (MAC - () "Multiply/Accumulate")
 801    (MISC - () "Miscellaneous")
 802   )
 803 )
 804
 805 (define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
 806   (begin
 807      (dni mnemonic
 808           (.str mnemonic " reg/reg")
 809           ((PIPE OS) (IDOC ALU))
 810           (.str mnemonic " $dr,$sr")
 811           (+ OP1_0 op2-op dr sr)
 812           (set dr (sem-op dr sr))
 813           ()
 814      )
 815      (dni (.sym mnemonic "3")
 816           (.str mnemonic " reg/" imm)
 817           ((IDOC ALU))
 818           (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
 819           (+ OP1_8 op2-op dr sr imm)
 820           (set dr (sem-op sr imm))
 821           ()
 822      )
 823    )
 824 )
 825 (bin-op add OP2_10 add "$hash" slo16)
 826 ; sub isn't present because sub3 doesn't exist.
 827 (bin-op and OP2_12 and "" uimm16)
 828 (bin-op or OP2_14 or "$hash" ulo16)
 829 (bin-op xor OP2_13 xor "" uimm16)
 830
 831 (dni addi "addi"
 832      ((PIPE OS) (IDOC ALU))
 833      ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
 834      "addi $dr,$simm8"
 835      (+ OP1_4 dr simm8)
 836      (set dr (add dr simm8))
 837      ((m32r/d (unit u-exec))
 838       (m32rx (unit u-exec))
 839       (m32r2 (unit u-exec)))
 840 )
 841
 842 (dni addv "addv"
 843      ((PIPE OS) (IDOC ALU))
 844      "addv $dr,$sr"
 845      (+ OP1_0 OP2_8 dr sr)
 846      (parallel ()
 847                (set dr (add dr sr))
 848                (set condbit (add-oflag dr sr (const 0))))
 849      ()
 850 )
 851
 852 (dni addv3 "addv3"
 853      ((IDOC ALU))
 854      "addv3 $dr,$sr,$simm16"
 855      (+ OP1_8 OP2_8 dr sr simm16)
 856      (parallel ()
 857                (set dr (add sr simm16))
 858                (set condbit (add-oflag sr simm16 (const 0))))
 859      ()
 860 )
 861
 862 (dni addx "addx"
 863      ((PIPE OS) (IDOC ALU))
 864      "addx $dr,$sr"
 865      (+ OP1_0 OP2_9 dr sr)
 866      (parallel ()
 867                (set dr (addc dr sr condbit))
 868                (set condbit (add-cflag dr sr condbit)))
 869      ()
 870 )
 871
 872 (dni bc8 "bc with 8 bit displacement"
 873      (COND-CTI (PIPE O) (IDOC BR))
 874      "bc.s $disp8"
 875      (+ OP1_7 (f-r1 12) disp8)
 876      (if condbit (set pc disp8))
 877      ((m32r/d (unit u-cti))
 878       (m32rx (unit u-cti))
 879       (m32r2 (unit u-cti)))
 880 )
 881
 882 (dnmi bc8r "relaxable bc8"
 883      (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
 884      "bc $disp8"
 885      (emit bc8 disp8)
 886 )
 887
 888 (dni bc24 "bc with 24 bit displacement"
 889      (COND-CTI (IDOC BR))
 890      "bc.l $disp24"
 891      (+ OP1_15 (f-r1 12) disp24)
 892      (if condbit (set pc disp24))
 893      ((m32r/d (unit u-cti))
 894       (m32rx (unit u-cti))
 895       (m32r2 (unit u-cti)))
 896 )
 897
 898 (dnmi bc24r "relaxable bc24"
 899      (COND-CTI RELAXED (IDOC BR))
 900      "bc $disp24"
 901      (emit bc24 disp24)
 902 )
 903
 904 (dni beq "beq"
 905      (COND-CTI (IDOC BR))
 906      "beq $src1,$src2,$disp16"
 907      (+ OP1_11 OP2_0 src1 src2 disp16)
 908      (if (eq src1 src2) (set pc disp16))
 909      ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
 910       (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
 911       (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
 912 )
 913
 914 (define-pmacro (cbranch sym comment op2-op comp-op)
 915   (dni sym comment (COND-CTI (IDOC BR))
 916         (.str sym " $src2,$disp16")
 917         (+ OP1_11 op2-op (f-r1 0) src2 disp16)
 918         (if (comp-op src2 (const WI 0)) (set pc disp16))
 919         ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
 920          (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
 921          (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
 922         )
 923 )
 924 (cbranch beqz "beqz" OP2_8 eq)
 925 (cbranch bgez "bgez" OP2_11 ge)
 926 (cbranch bgtz "bgtz" OP2_13 gt)
 927 (cbranch blez "blez" OP2_12 le)
 928 (cbranch bltz "bltz" OP2_10 lt)
 929 (cbranch bnez "bnez" OP2_9 ne)
 930
 931 (dni bl8 "bl with 8 bit displacement"
 932      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
 933      "bl.s $disp8"
 934      (+ OP1_7 (f-r1 14) disp8)
 935      (sequence ()
 936                (set (reg h-gr 14)
 937                     (add (and pc (const -4)) (const 4)))
 938                (set pc disp8))
 939      ((m32r/d (unit u-cti))
 940       (m32rx (unit u-cti))
 941       (m32r2 (unit u-cti)))
 942 )
 943
 944 (dnmi bl8r "relaxable bl8"
 945      (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
 946      "bl $disp8"
 947      (emit bl8 disp8)
 948 )
 949
 950 (dni bl24 "bl with 24 bit displacement"
 951      (UNCOND-CTI (IDOC BR))
 952      "bl.l $disp24"
 953      (+ OP1_15 (f-r1 14) disp24)
 954      (sequence ()
 955                (set (reg h-gr 14) (add pc (const 4)))
 956                (set pc disp24))
 957      ((m32r/d (unit u-cti))
 958       (m32rx (unit u-cti))
 959       (m32r2 (unit u-cti)))
 960 )
 961
 962 (dnmi bl24r "relaxable bl24"
 963      (UNCOND-CTI RELAXED (IDOC BR))
 964      "bl $disp24"
 965      (emit bl24 disp24)
 966 )
 967
 968 (dni bcl8 "bcl with 8 bit displacement"
 969      (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
 970      "bcl.s $disp8"
 971      (+ OP1_7 (f-r1 8) disp8)
 972      (if condbit
 973          (sequence ()
 974                    (set (reg h-gr 14)
 975                         (add (and pc (const -4))
 976                              (const 4)))
 977                    (set pc disp8)))
 978      ((m32rx (unit u-cti))
 979       (m32r2 (unit u-cti)))
 980 )
 981
 982 (dnmi bcl8r "relaxable bcl8"
 983      (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
 984      "bcl $disp8"
 985      (emit bcl8 disp8)
 986 )
 987
 988 (dni bcl24 "bcl with 24 bit displacement"
 989      (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
 990      "bcl.l $disp24"
 991      (+ OP1_15 (f-r1 8) disp24)
 992      (if condbit
 993          (sequence ()
 994                    (set (reg h-gr 14) (add pc (const 4)))
 995                    (set pc disp24)))
 996      ((m32rx (unit u-cti))
 997       (m32r2 (unit u-cti)))
 998 )
 999
1000 (dnmi bcl24r "relaxable bcl24"
1001      (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
1002      "bcl $disp24"
1003      (emit bcl24 disp24)
1004 )
1005
1006 (dni bnc8 "bnc with 8 bit displacement"
1007      (COND-CTI (PIPE O) (IDOC BR))
1008      "bnc.s $disp8"
1009      (+ OP1_7 (f-r1 13) disp8)
1010      (if (not condbit) (set pc disp8))
1011      ((m32r/d (unit u-cti))
1012       (m32rx (unit u-cti))
1013       (m32r2 (unit u-cti)))
1014 )
1015
1016 (dnmi bnc8r "relaxable bnc8"
1017      (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
1018      "bnc $disp8"
1019      (emit bnc8 disp8)
1020 )
1021
1022 (dni bnc24 "bnc with 24 bit displacement"
1023      (COND-CTI (IDOC BR))
1024      "bnc.l $disp24"
1025      (+ OP1_15 (f-r1 13) disp24)
1026      (if (not condbit) (set pc disp24))
1027      ((m32r/d (unit u-cti))
1028       (m32rx (unit u-cti))
1029       (m32r2 (unit u-cti)))
1030 )
1031
1032 (dnmi bnc24r "relaxable bnc24"
1033      (COND-CTI RELAXED (IDOC BR))
1034      "bnc $disp24"
1035      (emit bnc24 disp24)
1036 )
1037
1038 (dni bne "bne"
1039      (COND-CTI (IDOC BR))
1040      "bne $src1,$src2,$disp16"
1041      (+ OP1_11 OP2_1 src1 src2 disp16)
1042      (if (ne src1 src2) (set pc disp16))
1043      ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
1044       (m32rx (unit u-cti) (unit u-cmp (cycles 0)))
1045       (m32r2 (unit u-cti) (unit u-cmp (cycles 0))))
1046 )
1047
1048 (dni bra8 "bra with 8 bit displacement"
1049      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
1050      "bra.s $disp8"
1051      (+ OP1_7 (f-r1 15) disp8)
1052      (set pc disp8)
1053      ((m32r/d (unit u-cti))
1054       (m32rx (unit u-cti))
1055       (m32r2 (unit u-cti)))
1056 )
1057
1058 (dnmi bra8r "relaxable bra8"
1059      (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
1060      "bra $disp8"
1061      (emit bra8 disp8)
1062 )
1063
1064 (dni bra24 "bra with 24 displacement"
1065      (UNCOND-CTI (IDOC BR))
1066      "bra.l $disp24"
1067      (+ OP1_15 (f-r1 15) disp24)
1068      (set pc disp24)
1069      ((m32r/d (unit u-cti))
1070       (m32rx (unit u-cti))
1071       (m32r2 (unit u-cti)))
1072 )
1073
1074 (dnmi bra24r "relaxable bra24"
1075      (UNCOND-CTI RELAXED (IDOC BR))
1076      "bra $disp24"
1077      (emit bra24 disp24)
1078 )
1079
1080 (dni bncl8 "bncl with 8 bit displacement"
1081      (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR))
1082      "bncl.s $disp8"
1083      (+ OP1_7 (f-r1 9) disp8)
1084      (if (not condbit)
1085          (sequence ()
1086                    (set (reg h-gr 14)
1087                         (add (and pc (const -4))
1088                              (const 4)))
1089                    (set pc disp8)))
1090      ((m32rx (unit u-cti))
1091       (m32r2 (unit u-cti)))
1092 )
1093
1094 (dnmi bncl8r "relaxable bncl8"
1095      (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR))
1096      "bncl $disp8"
1097      (emit bncl8 disp8)
1098 )
1099
1100 (dni bncl24 "bncl with 24 bit displacement"
1101      (COND-CTI (MACH m32rx,m32r2) (IDOC BR))
1102      "bncl.l $disp24"
1103      (+ OP1_15 (f-r1 9) disp24)
1104      (if (not condbit)
1105          (sequence ()
1106                    (set (reg h-gr 14) (add pc (const 4)))
1107                    (set pc disp24)))
1108      ((m32rx (unit u-cti))
1109       (m32r2 (unit u-cti)))
1110 )
1111
1112 (dnmi bncl24r "relaxable bncl24"
1113      (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR))
1114      "bncl $disp24"
1115      (emit bncl24 disp24)
1116 )
1117
1118 (dni cmp "cmp"
1119      ((PIPE OS) (IDOC ALU))
1120      "cmp $src1,$src2"
1121      (+ OP1_0 OP2_4 src1 src2)
1122      (set condbit (lt src1 src2))
1123      ((m32r/d (unit u-cmp))
1124       (m32rx (unit u-cmp))
1125       (m32r2 (unit u-cmp)))
1126 )
1127
1128 (dni cmpi "cmpi"
1129      ((IDOC ALU))
1130      "cmpi $src2,$simm16"
1131      (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
1132      (set condbit (lt src2 simm16))
1133      ((m32r/d (unit u-cmp))
1134       (m32rx (unit u-cmp))
1135       (m32r2 (unit u-cmp)))
1136 )
1137
1138 (dni cmpu "cmpu"
1139      ((PIPE OS) (IDOC ALU))
1140      "cmpu $src1,$src2"
1141      (+ OP1_0 OP2_5 src1 src2)
1142      (set condbit (ltu src1 src2))
1143      ((m32r/d (unit u-cmp))
1144       (m32rx (unit u-cmp))
1145       (m32r2 (unit u-cmp)))
1146 )
1147
1148 (dni cmpui "cmpui"
1149      ((IDOC ALU))
1150      "cmpui $src2,$simm16"
1151      (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
1152      (set condbit (ltu src2 simm16))
1153      ((m32r/d (unit u-cmp))
1154       (m32rx (unit u-cmp))
1155       (m32r2 (unit u-cmp)))
1156 )
1157
1158 (dni cmpeq "cmpeq"
1159      ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
1160      "cmpeq $src1,$src2"
1161      (+ OP1_0 OP2_6 src1 src2)
1162      (set condbit (eq src1 src2))
1163      ((m32rx (unit u-cmp))
1164       (m32r2 (unit u-cmp)))
1165 )
1166
1167 (dni cmpz "cmpz"
1168      ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU))
1169      "cmpz $src2"
1170      (+ OP1_0 OP2_7 (f-r1 0) src2)
1171      (set condbit (eq src2 (const 0)))
1172      ((m32rx (unit u-cmp))
1173       (m32r2 (unit u-cmp)))
1174 )
1175
1176 (dni div "div"
1177      ((IDOC ALU))
1178      "div $dr,$sr"
1179      (+ OP1_9 OP2_0 dr sr (f-simm16 0))
1180      (if (ne sr (const 0)) (set dr (div dr sr)))
1181      ((m32r/d (unit u-exec (cycles 37)))
1182       (m32rx (unit u-exec (cycles 37)))
1183       (m32r2 (unit u-exec (cycles 37))))
1184 )
1185
1186 (dni divu "divu"
1187      ((IDOC ALU))
1188      "divu $dr,$sr"
1189      (+ OP1_9 OP2_1 dr sr (f-simm16 0))
1190      (if (ne sr (const 0)) (set dr (udiv dr sr)))
1191      ((m32r/d (unit u-exec (cycles 37)))
1192       (m32rx (unit u-exec (cycles 37)))
1193       (m32r2 (unit u-exec (cycles 37))))
1194 )
1195
1196 (dni rem "rem"
1197      ((IDOC ALU))
1198      "rem $dr,$sr"
1199      (+ OP1_9 OP2_2 dr sr (f-simm16 0))
1200      ; FIXME: Check rounding direction.
1201      (if (ne sr (const 0)) (set dr (mod dr sr)))
1202      ((m32r/d (unit u-exec (cycles 37)))
1203       (m32rx (unit u-exec (cycles 37)))
1204       (m32r2 (unit u-exec (cycles 37))))
1205 )
1206
1207 (dni remu "remu"
1208      ((IDOC ALU))
1209      "remu $dr,$sr"
1210      (+ OP1_9 OP2_3 dr sr (f-simm16 0))
1211      ; FIXME: Check rounding direction.
1212      (if (ne sr (const 0)) (set dr (umod dr sr)))
1213      ((m32r/d (unit u-exec (cycles 37)))
1214       (m32rx (unit u-exec (cycles 37)))
1215       (m32r2 (unit u-exec (cycles 37))))
1216 )
1217
1218 (dni remh "remh"
1219      ((MACH m32r2))
1220      "remh $dr,$sr"
1221      (+ OP1_9 OP2_2 dr sr (f-simm16 #x10))
1222      ; FIXME: Check rounding direction.
1223      (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr)))
1224      ((m32r2 (unit u-exec (cycles 21))))
1225 )
1226
1227 (dni remuh "remuh"
1228      ((MACH m32r2))
1229      "remuh $dr,$sr"
1230      (+ OP1_9 OP2_3 dr sr (f-simm16 #x10))
1231      ; FIXME: Check rounding direction.
1232      (if (ne sr (const 0)) (set dr (umod dr sr)))
1233      ((m32r2 (unit u-exec (cycles 21))))
1234 )
1235
1236 (dni remb "remb"
1237      ((MACH m32r2))
1238      "remb $dr,$sr"
1239      (+ OP1_9 OP2_2 dr sr (f-simm16 #x18))
1240      ; FIXME: Check rounding direction.
1241      (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr)))
1242      ((m32r2 (unit u-exec (cycles 21))))
1243 )
1244
1245 (dni remub "remub"
1246      ((MACH m32r2))
1247      "remub $dr,$sr"
1248      (+ OP1_9 OP2_3 dr sr (f-simm16 #x18))
1249      ; FIXME: Check rounding direction.
1250      (if (ne sr (const 0)) (set dr (umod dr sr)))
1251      ((m32r2 (unit u-exec (cycles 21))))
1252 )
1253
1254 (dni divuh "divuh"
1255      ((MACH m32r2))
1256      "divuh $dr,$sr"
1257      (+ OP1_9 OP2_1 dr sr (f-simm16 #x10))
1258      (if (ne sr (const 0)) (set dr (udiv dr sr)))
1259      ((m32r2 (unit u-exec (cycles 21))))
1260 )
1261
1262 (dni divb "divb"
1263      ((MACH m32r2))
1264      "divb $dr,$sr"
1265      (+ OP1_9 OP2_0 dr sr (f-simm16 #x18))
1266      (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr)))
1267      ((m32r2 (unit u-exec (cycles 21))))
1268 )
1269
1270 (dni divub "divub"
1271      ((MACH m32r2))
1272      "divub $dr,$sr"
1273      (+ OP1_9 OP2_1 dr sr (f-simm16 #x18))
1274      (if (ne sr (const 0)) (set dr (udiv dr sr)))
1275      ((m32r2 (unit u-exec (cycles 21))))
1276 )
1277
1278 (dni divh "divh"
1279      ((MACH m32rx,m32r2) (IDOC ALU))
1280      "divh $dr,$sr"
1281      (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
1282      (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
1283      ((m32rx (unit u-exec (cycles 21)))
1284       (m32r2 (unit u-exec (cycles 21))))
1285 )
1286
1287 (dni jc "jc"
1288      (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
1289      "jc $sr"
1290      (+ OP1_1 (f-r1 12) OP2_12 sr)
1291      (if condbit (set pc (and sr (const -4))))
1292      ((m32rx (unit u-cti))
1293       (m32r2 (unit u-cti)))
1294 )
1295
1296 (dni jnc "jnc"
1297      (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
1298      "jnc $sr"
1299      (+ OP1_1 (f-r1 13) OP2_12 sr)
1300      (if (not condbit) (set pc (and sr (const -4))))
1301      ((m32rx (unit u-cti))
1302       (m32r2 (unit u-cti)))
1303 )
1304
1305 (dni jl "jl"
1306      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
1307      "jl $sr"
1308      (+ OP1_1 (f-r1 14) OP2_12 sr)
1309      (parallel ()
1310                (set (reg h-gr 14)
1311                     (add (and pc (const -4)) (const 4)))
1312                (set pc (and sr (const -4))))
1313      ((m32r/d (unit u-cti))
1314       (m32rx (unit u-cti))
1315       (m32r2 (unit u-cti)))
1316 )
1317
1318 (dni jmp "jmp"
1319      (UNCOND-CTI (PIPE O) (IDOC BR))
1320      "jmp $sr"
1321      (+ OP1_1 (f-r1 15) OP2_12 sr)
1322      (set pc (and sr (const -4)))
1323      ; The above works now so this kludge has been commented out.
1324      ; It's kept around because the f-r1 reference in the semantic part
1325      ; should work.
1326      ; FIXME: kludge, instruction decoding not finished.
1327      ; But this should work, so that's another FIXME.
1328      ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
1329      ; FIXME: abuf->insn should be a macro of some sort.
1330      ;(sequence VOID
1331      ;         (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
1332      ;                    (const SI 14))
1333      ;             (set WI (reg WI h-gr 14)
1334      ;                  (add WI (and WI pc (const WI -4)) (const WI 4))))
1335      ;         (set WI pc sr))
1336      ((m32r/d (unit u-cti))
1337       (m32rx (unit u-cti))
1338       (m32r2 (unit u-cti)))
1339 )
1340
1341 (define-pmacro (no-ext-expr mode expr) expr)
1342 (define-pmacro (ext-expr mode expr) (ext mode expr))
1343 (define-pmacro (zext-expr mode expr) (zext mode expr))
1344
1345 (define-pmacro (load-op suffix op2-op mode ext-op)
1346   (begin
1347     (dni (.sym ld suffix) (.str "ld" suffix)
1348          ((PIPE O) (IDOC MEM))
1349          (.str "ld" suffix " $dr,@$sr")
1350          (+ OP1_2 op2-op dr sr)
1351          (set dr (ext-op WI (mem mode sr)))
1352          ((m32r/d (unit u-load))
1353           (m32rx (unit u-load))
1354           (m32r2 (unit u-load)))
1355          )
1356     (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
1357           (NO-DIS (PIPE O) (IDOC MEM))
1358           (.str "ld" suffix " $dr,@($sr)")
1359           (emit (.sym ld suffix) dr sr))
1360     (dni (.sym ld suffix -d) (.str "ld" suffix "-d")
1361          ((IDOC MEM))
1362          (.str "ld" suffix " $dr,@($slo16,$sr)")
1363          (+ OP1_10 op2-op dr sr slo16)
1364          (set dr (ext-op WI (mem mode (add sr slo16))))
1365          ((m32r/d (unit u-load (cycles 2)))
1366           (m32rx (unit u-load (cycles 2)))
1367           (m32r2 (unit u-load (cycles 2))))
1368          )
1369     (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
1370           (NO-DIS (IDOC MEM))
1371           (.str "ld" suffix " $dr,@($sr,$slo16)")
1372           (emit (.sym ld suffix -d) dr sr slo16))
1373     )
1374 )
1375 (load-op "" OP2_12 WI no-ext-expr)
1376 (load-op b OP2_8 QI ext-expr)
1377 (load-op h OP2_10 HI ext-expr)
1378 (load-op ub OP2_9 QI zext-expr)
1379 (load-op uh OP2_11 HI zext-expr)
1380
1381 (dni ld-plus "ld+"
1382      ((PIPE O) (IDOC MEM))
1383      "ld $dr,@$sr+"
1384      (+ OP1_2 dr OP2_14 sr)
1385      (parallel ()
1386                ; wip: memory addresses in profiling support
1387                ;(set dr (name ld-mem (mem WI sr)))
1388                (set dr (mem WI sr))
1389                (set sr (add sr (const 4))))
1390      ; Note: `pred' is the constraint.  Also useful here is (ref name)
1391      ; and returns true if operand <name> was referenced
1392      ; (where "referenced" means _read_ if input operand and _written_ if
1393      ; output operand).
1394      ; args to unit are "unit-name (name1 value1) ..."
1395      ; - cycles(done),issue,pred are also specified this way
1396      ; - if unspecified, default is used
1397      ; - for ins/outs, extra arg is passed that says what was specified
1398      ;   - this is AND'd with `written' for outs
1399      ((m32r/d (unit u-load (pred (const 1)))
1400               (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1401       (m32rx (unit u-load)
1402              (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1403       (m32r2 (unit u-load)
1404              (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1405       )
1406 )
1407
1408 (dnmi pop "pop"
1409       ((PIPE O) (IDOC MEM))
1410       "pop $dr"
1411       (emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
1412 )
1413
1414 (dni ld24 "ld24"
1415      ((IDOC MEM))
1416      "ld24 $dr,$uimm24"
1417      (+ OP1_14 dr uimm24)
1418      (set dr uimm24)
1419      ()
1420 )
1421
1422 ; ldi8 appears before ldi16 so we try the shorter version first
1423
1424 (dni ldi8 "ldi8"
1425      ((PIPE OS) (IDOC ALU))
1426      "ldi8 $dr,$simm8"
1427      (+ OP1_6 dr simm8)
1428      (set dr simm8)
1429      ()
1430 )
1431
1432 (dnmi ldi8a "ldi8 alias"
1433      ((PIPE OS) (IDOC ALU))
1434      "ldi $dr,$simm8"
1435      (emit ldi8 dr simm8)
1436 )
1437
1438 (dni ldi16 "ldi16"
1439      ((IDOC ALU))
1440      "ldi16 $dr,$hash$slo16"
1441      (+ OP1_9 OP2_15 (f-r2 0) dr slo16)
1442      (set dr slo16)
1443      ()
1444 )
1445
1446 (dnmi ldi16a "ldi16 alias"
1447      ((IDOC ALU))
1448      "ldi $dr,$hash$slo16"
1449      (emit ldi16 dr slo16)
1450 )
1451
1452 (dni lock "lock"
1453      ((PIPE O) (IDOC MISC))
1454      "lock $dr,@$sr"
1455      (+ OP1_2 OP2_13 dr sr)
1456      (sequence ()
1457                (set (reg h-lock) (const BI 1))
1458                (set dr (mem WI sr)))
1459      ((m32r/d (unit u-load))
1460       (m32rx (unit u-load))
1461       (m32r2 (unit u-load)))
1462 )
1463
1464 (dni machi "machi"
1465      (
1466       ; (MACH m32r) is a temporary hack.  This insn collides with machi-a
1467       ; in the simulator so disable it for m32rx.
1468       (MACH m32r) (PIPE S) (IDOC MAC)
1469      )
1470      "machi $src1,$src2"
1471      (+ OP1_3 OP2_4 src1 src2)
1472      ; FIXME: TRACE_RESULT will print the wrong thing since we
1473      ; alter one of the arguments.
1474      (set accum
1475           (sra DI
1476                (sll DI
1477                     (add DI
1478                          accum
1479                          (mul DI
1480                               (ext DI (and WI src1 (const #xffff0000)))
1481                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1482                     (const 8))
1483                (const 8)))
1484      ((m32r/d (unit u-mac)))
1485 )
1486
1487 (dni machi-a "machi-a"
1488      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1489      "machi $src1,$src2,$acc"
1490      (+ OP1_3 src1 acc (f-op23 4) src2)
1491      (set acc
1492           (sra DI
1493                (sll DI
1494                     (add DI
1495                          acc
1496                          (mul DI
1497                               (ext DI (and WI src1 (const #xffff0000)))
1498                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1499                     (const 8))
1500                (const 8)))
1501      ((m32rx (unit u-mac))
1502       (m32r2 (unit u-mac)))
1503 )
1504
1505 (dni maclo "maclo"
1506      ((MACH m32r) (PIPE S) (IDOC MAC))
1507      "maclo $src1,$src2"
1508      (+ OP1_3 OP2_5 src1 src2)
1509      (set accum
1510           (sra DI
1511                (sll DI
1512                     (add DI
1513                          accum
1514                          (mul DI
1515                               (ext DI (sll WI src1 (const 16)))
1516                               (ext DI (trunc HI src2))))
1517                     (const 8))
1518                (const 8)))
1519      ((m32r/d (unit u-mac)))
1520 )
1521
1522 (dni maclo-a "maclo-a"
1523      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1524      "maclo $src1,$src2,$acc"
1525      (+ OP1_3 src1 acc (f-op23 5) src2)
1526      (set acc
1527           (sra DI
1528                (sll DI
1529                     (add DI
1530                          acc
1531                          (mul DI
1532                               (ext DI (sll WI src1 (const 16)))
1533                               (ext DI (trunc HI src2))))
1534                     (const 8))
1535                (const 8)))
1536      ((m32rx (unit u-mac))
1537       (m32r2 (unit u-mac)))
1538 )
1539
1540 (dni macwhi "macwhi"
1541      ((MACH m32r) (PIPE S) (IDOC MAC))
1542      "macwhi $src1,$src2"
1543      (+ OP1_3 OP2_6 src1 src2)
1544      (set accum
1545           (sra DI
1546                (sll DI
1547                     (add DI
1548                          accum
1549                          (mul DI
1550                               (ext DI src1)
1551                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1552                     (const 8))
1553                (const 8)))
1554      ((m32r/d (unit u-mac)))
1555 )
1556
1557 (dni macwhi-a "macwhi-a"
1558      ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
1559      "macwhi $src1,$src2,$acc"
1560      (+ OP1_3 src1 acc (f-op23 6) src2)
1561      ; Note that this doesn't do the sign extension, which is correct.
1562      (set acc
1563           (add acc
1564                (mul (ext DI src1)
1565                     (ext DI (trunc HI (sra src2 (const 16)))))))
1566      ((m32rx (unit u-mac))
1567       (m32r2 (unit u-mac)))
1568 )
1569
1570 (dni macwlo "macwlo"
1571      ((MACH m32r) (PIPE S) (IDOC MAC))
1572      "macwlo $src1,$src2"
1573      (+ OP1_3 OP2_7 src1 src2)
1574      (set accum
1575           (sra DI
1576                (sll DI
1577                     (add DI
1578                          accum
1579                          (mul DI
1580                               (ext DI src1)
1581                               (ext DI (trunc HI src2))))
1582                     (const 8))
1583                (const 8)))
1584      ((m32r/d (unit u-mac)))
1585 )
1586
1587 (dni macwlo-a "macwlo-a"
1588      ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC))
1589      "macwlo $src1,$src2,$acc"
1590      (+ OP1_3 src1 acc (f-op23 7) src2)
1591      ; Note that this doesn't do the sign extension, which is correct.
1592      (set acc
1593           (add acc
1594                (mul (ext DI src1)
1595                     (ext DI (trunc HI src2)))))
1596      ((m32rx (unit u-mac))
1597       (m32r2 (unit u-mac)))
1598 )
1599
1600 (dni mul "mul"
1601      ((PIPE S) (IDOC ALU))
1602      "mul $dr,$sr"
1603      (+ OP1_1 OP2_6 dr sr)
1604      (set dr (mul dr sr))
1605      ((m32r/d (unit u-exec (cycles 4)))
1606       (m32rx (unit u-exec (cycles 4)))
1607       (m32r2 (unit u-exec (cycles 4))))
1608 )
1609
1610 (dni mulhi "mulhi"
1611      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1612      "mulhi $src1,$src2"
1613      (+ OP1_3 OP2_0 src1 src2)
1614      (set accum
1615           (sra DI
1616                (sll DI
1617                     (mul DI
1618                          (ext DI (and WI src1 (const #xffff0000)))
1619                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1620                     (const 16))
1621                (const 16)))
1622      ((m32r/d (unit u-mac)))
1623 )
1624
1625 (dni mulhi-a "mulhi-a"
1626      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1627      "mulhi $src1,$src2,$acc"
1628      (+ OP1_3 (f-op23 0) src1 acc src2)
1629      (set acc
1630           (sra DI
1631                (sll DI
1632                     (mul DI
1633                          (ext DI (and WI src1 (const #xffff0000)))
1634                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1635                     (const 16))
1636                (const 16)))
1637      ((m32rx (unit u-mac))
1638       (m32r2 (unit u-mac)))
1639 )
1640
1641 (dni mullo "mullo"
1642      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1643      "mullo $src1,$src2"
1644      (+ OP1_3 OP2_1 src1 src2)
1645      (set accum
1646           (sra DI
1647                (sll DI
1648                     (mul DI
1649                          (ext DI (sll WI src1 (const 16)))
1650                          (ext DI (trunc HI src2)))
1651                     (const 16))
1652                (const 16)))
1653      ((m32r/d (unit u-mac)))
1654 )
1655
1656 (dni mullo-a "mullo-a"
1657      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1658      "mullo $src1,$src2,$acc"
1659      (+ OP1_3 src1 acc (f-op23 1) src2)
1660      (set acc
1661           (sra DI
1662                (sll DI
1663                     (mul DI
1664                          (ext DI (sll WI src1 (const 16)))
1665                          (ext DI (trunc HI src2)))
1666                     (const 16))
1667                (const 16)))
1668      ((m32rx (unit u-mac))
1669       (m32r2 (unit u-mac)))
1670 )
1671
1672 (dni mulwhi "mulwhi"
1673      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1674      "mulwhi $src1,$src2"
1675      (+ OP1_3 OP2_2 src1 src2)
1676      (set accum
1677           (sra DI
1678                (sll DI
1679                     (mul DI
1680                          (ext DI src1)
1681                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1682                     (const 8))
1683                (const 8)))
1684      ((m32r/d (unit u-mac)))
1685 )
1686
1687 (dni mulwhi-a "mulwhi-a"
1688      ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
1689      "mulwhi $src1,$src2,$acc"
1690      (+ OP1_3 src1 acc (f-op23 2) src2)
1691      ; Note that this doesn't do the sign extension, which is correct.
1692      (set acc
1693           (mul (ext DI src1)
1694                (ext DI (trunc HI (sra src2 (const 16))))))
1695      ((m32rx (unit u-mac))
1696       (m32r2 (unit u-mac)))
1697 )
1698
1699 (dni mulwlo "mulwlo"
1700      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1701      "mulwlo $src1,$src2"
1702      (+ OP1_3 OP2_3 src1 src2)
1703      (set accum
1704           (sra DI
1705                (sll DI
1706                     (mul DI
1707                          (ext DI src1)
1708                          (ext DI (trunc HI src2)))
1709                     (const 8))
1710                (const 8)))
1711      ((m32r/d (unit u-mac)))
1712 )
1713
1714 (dni mulwlo-a "mulwlo-a"
1715      ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM))
1716      "mulwlo $src1,$src2,$acc"
1717      (+ OP1_3 src1 acc (f-op23 3) src2)
1718      ; Note that this doesn't do the sign extension, which is correct.
1719      (set acc
1720           (mul (ext DI src1)
1721                (ext DI (trunc HI src2))))
1722      ((m32rx (unit u-mac))
1723       (m32r2 (unit u-mac)))
1724 )
1725
1726 (dni mv "mv"
1727      ((PIPE OS) (IDOC ALU))
1728      "mv $dr,$sr"
1729      (+ OP1_1 OP2_8 dr sr)
1730      (set dr sr)
1731      ()
1732 )
1733
1734 (dni mvfachi "mvfachi"
1735      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1736      "mvfachi $dr"
1737      (+ OP1_5 OP2_15 (f-r2 0) dr)
1738      (set dr (trunc WI (sra DI accum (const 32))))
1739      ((m32r/d (unit u-exec (cycles 2))))
1740 )
1741
1742 (dni mvfachi-a "mvfachi-a"
1743      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1744      "mvfachi $dr,$accs"
1745      (+ OP1_5 dr OP2_15 accs (f-op3 0))
1746      (set dr (trunc WI (sra DI accs (const 32))))
1747      ((m32rx (unit u-exec (cycles 2)))
1748       (m32r2 (unit u-exec (cycles 2))))
1749 )
1750
1751 (dni mvfaclo "mvfaclo"
1752      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1753      "mvfaclo $dr"
1754      (+ OP1_5 OP2_15 (f-r2 1) dr)
1755      (set dr (trunc WI accum))
1756      ((m32r/d (unit u-exec (cycles 2))))
1757 )
1758
1759 (dni mvfaclo-a "mvfaclo-a"
1760      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1761      "mvfaclo $dr,$accs"
1762      (+ OP1_5 dr OP2_15 accs (f-op3 1))
1763      (set dr (trunc WI accs))
1764      ((m32rx (unit u-exec (cycles 2)))
1765       (m32r2 (unit u-exec (cycles 2))))
1766 )
1767
1768 (dni mvfacmi "mvfacmi"
1769      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1770      "mvfacmi $dr"
1771      (+ OP1_5 OP2_15 (f-r2 2) dr)
1772      (set dr (trunc WI (sra DI accum (const 16))))
1773      ((m32r/d (unit u-exec (cycles 2))))
1774 )
1775
1776 (dni mvfacmi-a "mvfacmi-a"
1777      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1778      "mvfacmi $dr,$accs"
1779      (+ OP1_5 dr OP2_15 accs (f-op3 2))
1780      (set dr (trunc WI (sra DI accs (const 16))))
1781      ((m32rx (unit u-exec (cycles 2)))
1782       (m32r2 (unit u-exec (cycles 2))))
1783 )
1784
1785 (dni mvfc "mvfc"
1786      ((PIPE O) (IDOC MISC))
1787      "mvfc $dr,$scr"
1788      (+ OP1_1 OP2_9 dr scr)
1789      (set dr scr)
1790      ()
1791 )
1792
1793 (dni mvtachi "mvtachi"
1794      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1795      "mvtachi $src1"
1796      (+ OP1_5 OP2_7 (f-r2 0) src1)
1797      (set accum
1798           (or DI
1799               (and DI accum (const DI #xffffffff))
1800               (sll DI (ext DI src1) (const 32))))
1801      ((m32r/d (unit u-exec (in sr src1))))
1802 )
1803
1804 (dni mvtachi-a "mvtachi-a"
1805      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1806      "mvtachi $src1,$accs"
1807      (+ OP1_5 src1 OP2_7 accs (f-op3 0))
1808      (set accs
1809           (or DI
1810               (and DI accs (const DI #xffffffff))
1811               (sll DI (ext DI src1) (const 32))))
1812      ((m32rx (unit u-exec (in sr src1)))
1813       (m32r2 (unit u-exec (in sr src1))))
1814 )
1815
1816 (dni mvtaclo "mvtaclo"
1817      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1818      "mvtaclo $src1"
1819      (+ OP1_5 OP2_7 (f-r2 1) src1)
1820      (set accum
1821           (or DI
1822               (and DI accum (const DI #xffffffff00000000))
1823               (zext DI src1)))
1824      ((m32r/d (unit u-exec (in sr src1))))
1825 )
1826
1827 (dni mvtaclo-a "mvtaclo-a"
1828      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
1829      "mvtaclo $src1,$accs"
1830      (+ OP1_5 src1 OP2_7 accs (f-op3 1))
1831      (set accs
1832           (or DI
1833               (and DI accs (const DI #xffffffff00000000))
1834               (zext DI src1)))
1835      ((m32rx (unit u-exec (in sr src1)))
1836       (m32r2 (unit u-exec (in sr src1))))
1837 )
1838
1839 (dni mvtc "mvtc"
1840      ((PIPE O) (IDOC MISC))
1841      "mvtc $sr,$dcr"
1842      (+ OP1_1 OP2_10 dcr sr)
1843      (set dcr sr)
1844      ()
1845 )
1846
1847 (dni neg "neg"
1848      ((PIPE OS) (IDOC ALU))
1849      "neg $dr,$sr"
1850      (+ OP1_0 OP2_3 dr sr)
1851      (set dr (neg sr))
1852      ()
1853 )
1854
1855 (dni nop "nop"
1856      ((PIPE OS) (IDOC MISC))
1857      "nop"
1858      (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
1859      (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
1860      ; FIXME: quick hack: parallel nops don't contribute to cycle count.
1861      ; Other kinds of nops do however (which we currently ignore).
1862      ((m32r/d (unit u-exec (cycles 0)))
1863       (m32rx (unit u-exec (cycles 0)))
1864       (m32r2 (unit u-exec (cycles 0))))
1865 )
1866
1867 (dni not "not"
1868      ((PIPE OS) (IDOC ALU))
1869      "not $dr,$sr"
1870      (+ OP1_0 OP2_11 dr sr)
1871      (set dr (inv sr))
1872      ()
1873 )
1874
1875 (dni rac "rac"
1876      ((MACH m32r) (PIPE S) (IDOC MAC))
1877      "rac"
1878      (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
1879      (sequence ((DI tmp1))
1880                (set tmp1 (sll DI accum (const 1)))
1881                (set tmp1 (add DI tmp1 (const DI #x8000)))
1882                (set accum
1883                     (cond DI
1884                           ((gt tmp1 (const DI #x00007fffffff0000))
1885                            (const DI #x00007fffffff0000))
1886                           ((lt tmp1 (const DI #xffff800000000000))
1887                            (const DI #xffff800000000000))
1888                           (else (and tmp1 (const DI #xffffffffffff0000)))))
1889                )
1890      ((m32r/d (unit u-mac)))
1891 )
1892
1893 (dni rac-dsi "rac-dsi"
1894      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1895      "rac $accd,$accs,$imm1"
1896      (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
1897      (sequence ((DI tmp1))
1898                (set tmp1 (sll accs imm1))
1899                (set tmp1 (add tmp1 (const DI #x8000)))
1900                (set accd
1901                     (cond DI
1902                           ((gt tmp1 (const DI #x00007fffffff0000))
1903                            (const DI #x00007fffffff0000))
1904                           ((lt tmp1 (const DI #xffff800000000000))
1905                            (const DI #xffff800000000000))
1906                           (else (and tmp1 (const DI #xffffffffffff0000)))))
1907                )
1908      ((m32rx (unit u-mac))
1909       (m32r2 (unit u-mac)))
1910 )
1911
1912 (dnmi rac-d "rac-d"
1913      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1914      "rac $accd"
1915      (emit rac-dsi accd (f-accs 0) (f-imm1 0))
1916 )
1917
1918 (dnmi rac-ds "rac-ds"
1919      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1920      "rac $accd,$accs"
1921      (emit rac-dsi accd accs (f-imm1 0))
1922 )
1923
1924
1925 (dni rach "rach"
1926      ((MACH m32r) (PIPE S) (IDOC MAC))
1927      "rach"
1928      (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
1929      (sequence ((DI tmp1))
1930                ; Lop off top 8 bits.
1931                ; The sign bit we want to use is bit 55 so the 64 bit value
1932                ; isn't properly signed which we deal with in the if's below.
1933                (set tmp1 (and accum (const DI #xffffffffffffff)))
1934                (if (andif (ge tmp1 (const DI #x003fff80000000))
1935                           (le tmp1 (const DI #x7fffffffffffff)))
1936                    (set tmp1 (const DI #x003fff80000000))
1937                    ; else part
1938                    (if (andif (ge tmp1 (const DI #x80000000000000))
1939                               (le tmp1 (const DI #xffc00000000000)))
1940                        (set tmp1 (const DI #xffc00000000000))
1941                        (set tmp1 (and (add accum (const DI #x40000000))
1942                                       (const DI #xffffffff80000000)))))
1943                (set tmp1 (sll tmp1 (const 1)))
1944                ; Sign extend top 8 bits.
1945                (set accum
1946                     ; FIXME: 7?
1947                     (sra DI (sll DI tmp1 (const 7)) (const 7)))
1948                )
1949      ((m32r/d (unit u-mac)))
1950 )
1951
1952 (dni rach-dsi "rach-dsi"
1953      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1954      "rach $accd,$accs,$imm1"
1955      (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
1956      (sequence ((DI tmp1))
1957                (set tmp1 (sll accs imm1))
1958                (set tmp1 (add tmp1 (const DI #x80000000)))
1959                (set accd
1960                     (cond DI
1961                           ((gt tmp1 (const DI #x00007fff00000000))
1962                            (const DI #x00007fff00000000))
1963                           ((lt tmp1 (const DI #xffff800000000000))
1964                            (const DI #xffff800000000000))
1965                           (else (and tmp1 (const DI #xffffffff00000000)))))
1966                )
1967      ((m32rx (unit u-mac))
1968       (m32r2 (unit u-mac)))
1969 )
1970
1971 (dnmi rach-d "rach-d"
1972      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1973      "rach $accd"
1974      (emit rach-dsi accd (f-accs 0) (f-imm1 0))
1975 )
1976
1977 (dnmi rach-ds "rach-ds"
1978      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
1979      "rach $accd,$accs"
1980      (emit rach-dsi accd accs (f-imm1 0))
1981 )
1982
1983 (dni rte "rte"
1984      (UNCOND-CTI (PIPE O) (IDOC BR))
1985      "rte"
1986      (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
1987      (sequence ()
1988                ; pc = bpc & -4
1989                (set pc (and (reg h-cr 6) (const -4)))
1990                ; bpc = bbpc
1991                (set (reg h-cr 6) (reg h-cr 14))
1992                ; psw = bpsw
1993                (set (reg h-psw) (reg h-bpsw))
1994                ; bpsw = bbpsw
1995                (set (reg h-bpsw) (reg h-bbpsw))
1996      )
1997      ()
1998 )
1999
2000 (dni seth "seth"
2001      ((IDOC ALU))
2002      "seth $dr,$hash$hi16"
2003      (+ OP1_13 OP2_12 dr (f-r2 0) hi16)
2004      (set dr (sll WI hi16 (const 16)))
2005      ()
2006 )
2007
2008 (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
2009   (begin
2010      (dni sym sym ((PIPE O_OS) (IDOC ALU))
2011           (.str sym " $dr,$sr")
2012           (+ OP1_1 op2-r-op dr sr)
2013           (set dr (sem-op dr (and sr (const 31))))
2014           ()
2015      )
2016      (dni (.sym sym "3") sym ((IDOC ALU))
2017           (.str sym "3 $dr,$sr,$simm16")
2018           (+ OP1_9 op2-3-op dr sr simm16)
2019           (set dr (sem-op sr (and WI simm16 (const 31))))
2020           ()
2021      )
2022      (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU))
2023           (.str sym "i $dr,$uimm5")
2024           (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
2025           (set dr (sem-op dr uimm5))
2026           ()
2027      )
2028    )
2029 )
2030 (shift-op sll OP2_4 OP2_12 2 sll)
2031 (shift-op sra OP2_2 OP2_10 1 sra)
2032 (shift-op srl OP2_0 OP2_8 0 srl)
2033
2034 (define-pmacro (store-op suffix op2-op mode)
2035   (begin
2036     (dni (.sym st suffix) (.str "st" suffix)
2037          ((PIPE O) (IDOC MEM))
2038          (.str "st" suffix " $src1,@$src2")
2039          (+ OP1_2 op2-op src1 src2)
2040          (set mode (mem mode src2) src1)
2041          ((m32r/d (unit u-store (cycles 1)))
2042           (m32rx (unit u-store (cycles 1)))
2043           (m32r2 (unit u-store (cycles 1))))
2044          )
2045     (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
2046           (NO-DIS (PIPE O) (IDOC MEM))
2047           (.str "st" suffix " $src1,@($src2)")
2048           (emit (.sym st suffix) src1 src2))
2049     (dni (.sym st suffix -d) (.str "st" suffix "-d")
2050          ((IDOC MEM))
2051          (.str "st" suffix " $src1,@($slo16,$src2)")
2052          (+ OP1_10 op2-op src1 src2 slo16)
2053          (set mode (mem mode (add src2 slo16)) src1)
2054          ((m32r/d (unit u-store (cycles 2)))
2055           (m32rx (unit u-store (cycles 2)))
2056           (m32r2 (unit u-store (cycles 2))))
2057          )
2058     (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
2059           (NO-DIS (IDOC MEM))
2060           (.str "st" suffix " $src1,@($src2,$slo16)")
2061           (emit (.sym st suffix -d) src1 src2 slo16))
2062     )
2063 )
2064 (store-op "" OP2_4 WI)
2065 (store-op b OP2_0 QI)
2066 (store-op h OP2_2 HI)
2067
2068 (dni st-plus "st+"
2069      ((PIPE O) (IDOC MEM))
2070      "st $src1,@+$src2"
2071      (+ OP1_2 OP2_6 src1 src2)
2072      ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2073      (sequence ((WI new-src2))
2074                (set new-src2 (add WI src2 (const WI 4)))
2075                (set (mem WI new-src2) src1)
2076                (set src2 new-src2))
2077      ((m32r/d (unit u-store)
2078               (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2079       (m32rx (unit u-store)
2080              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2081       (m32r2 (unit u-store)
2082              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2083       )
2084 )
2085
2086 (dni sth-plus "sth+"
2087      ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
2088      "sth $src1,@$src2+"
2089      (+ OP1_2 OP2_3 src1 src2)
2090      ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2091      (sequence ((HI new-src2))
2092              (set (mem HI new-src2) src1)
2093              (set new-src2 (add src2 (const 2)))
2094              (set src2 new-src2))
2095      ((m32rx (unit u-store)
2096            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2097       (m32r2 (unit u-store)
2098            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2099       )
2100 )
2101
2102 (dni stb-plus "stb+"
2103      ((MACH m32rx,m32r2) (PIPE O) SPECIAL)
2104      "stb $src1,@$src2+"
2105      (+ OP1_2 OP2_1 src1 src2)
2106      ; This has to be coded carefully to avoid an "earlyclobber" of src2.
2107      (sequence ((QI new-src2))
2108              (set (mem QI new-src2) src1)
2109              (set new-src2 (add src2 (const 1)))
2110              (set src2 new-src2))
2111      ((m32rx (unit u-store)
2112            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2113       (m32r2 (unit u-store)
2114            (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2115       )
2116 )
2117
2118 (dni st-minus "st-"
2119      ((PIPE O) (IDOC MEM))
2120      "st $src1,@-$src2"
2121      (+ OP1_2 OP2_7 src1 src2)
2122      ; This is the original way.  It doesn't work for parallel execution
2123      ; because of the earlyclobber of src2.
2124      ;(sequence ()
2125      ;         (set src2 (sub src2 (const 4)))
2126      ;         (set (mem WI src2) src1))
2127      (sequence ((WI new-src2))
2128                (set new-src2 (sub src2 (const 4)))
2129                (set (mem WI new-src2) src1)
2130                (set src2 new-src2))
2131      ((m32r/d (unit u-store)
2132               (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2133       (m32rx (unit u-store)
2134              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2135       (m32r2 (unit u-store)
2136              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
2137       )
2138 )
2139
2140 (dnmi push "push" ((PIPE O) (IDOC MEM))
2141   "push $src1"
2142   (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
2143 )
2144
2145 (dni sub "sub"
2146      ((PIPE OS) (IDOC ALU))
2147      "sub $dr,$sr"
2148      (+ OP1_0 OP2_2 dr sr)
2149      (set dr (sub dr sr))
2150      ()
2151 )
2152
2153 (dni subv "sub:rv"
2154      ((PIPE OS) (IDOC ALU))
2155      "subv $dr,$sr"
2156      (+ OP1_0 OP2_0 dr sr)
2157      (parallel ()
2158                (set dr (sub dr sr))
2159                (set condbit (sub-oflag dr sr (const 0))))
2160      ()
2161 )
2162
2163 (dni subx "sub:rx"
2164      ((PIPE OS) (IDOC ALU))
2165      "subx $dr,$sr"
2166      (+ OP1_0 OP2_1 dr sr)
2167      (parallel ()
2168                (set dr (subc dr sr condbit))
2169                (set condbit (sub-cflag dr sr condbit)))
2170      ()
2171 )
2172
2173 (dni trap "trap"
2174      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
2175      "trap $uimm4"
2176      (+ OP1_1 OP2_15 (f-r1 0) uimm4)
2177      (sequence ()
2178                ; bbpc = bpc
2179                (set (reg h-cr 14) (reg h-cr 6))
2180                ; Set bpc to the return address.  Actually it's not quite the
2181                ; return address as RTE rounds the address down to a word
2182                ; boundary.
2183                (set (reg h-cr 6) (add pc (const 4)))
2184                ; bbpsw = bpsw
2185                (set (reg h-bbpsw) (reg h-bpsw))
2186                ; bpsw = psw
2187                (set (reg h-bpsw) (reg h-psw))
2188                ; sm is unchanged, ie,c are set to zero.
2189                (set (reg h-psw) (and (reg h-psw) (const #x80)))
2190                ; m32r_trap handles operating vs user mode
2191                (set WI pc (c-call WI "m32r_trap" pc uimm4))
2192      )
2193      ()
2194 )
2195
2196 (dni unlock "unlock"
2197      ((PIPE O) (IDOC MISC))
2198      "unlock $src1,@$src2"
2199      (+ OP1_2 OP2_5 src1 src2)
2200      (sequence ()
2201                (if (reg h-lock)
2202                    (set (mem WI src2) src1))
2203                (set (reg h-lock) (const BI 0)))
2204      ((m32r/d (unit u-load))
2205       (m32rx (unit u-load))
2206       (m32r2 (unit u-load)))
2207 )
2208
2209 ; Saturate into byte.
2210 (dni satb "satb"
2211      ((MACH m32rx,m32r2) (IDOC ALU))
2212      "satb $dr,$sr"
2213      (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
2214      (set dr
2215           ; FIXME: min/max would simplify this nicely of course.
2216           (cond WI
2217                 ((ge sr (const 127)) (const 127))
2218                 ((le sr (const -128)) (const -128))
2219                 (else sr)))
2220      ()
2221 )
2222
2223 ; Saturate into half word.
2224 (dni sath "sath"
2225      ((MACH m32rx,m32r2) (IDOC ALU))
2226      "sath $dr,$sr"
2227      (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
2228      (set dr
2229           (cond WI
2230                 ((ge sr (const 32767)) (const 32767))
2231                 ((le sr (const -32768)) (const -32768))
2232                 (else sr)))
2233      ()
2234 )
2235
2236 ; Saturate word.
2237 (dni sat "sat"
2238      ((MACH m32rx,m32r2) SPECIAL (IDOC ALU))
2239      "sat $dr,$sr"
2240      (+ OP1_8 dr OP2_6 sr (f-uimm16 0))
2241      (set dr
2242           (if WI condbit
2243                (if WI (lt sr (const 0))
2244                     (const #x7fffffff)
2245                     (const #x80000000))
2246                sr))
2247      ()
2248 )
2249
2250 ; Parallel compare byte zeros.
2251 ; Set C bit in condition register if any byte in source register is zero.
2252 (dni pcmpbz "pcmpbz"
2253      ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU))
2254      "pcmpbz $src2"
2255      (+ OP1_0 (f-r1 3) OP2_7 src2)
2256      (set condbit
2257           (cond BI
2258                  ((eq (and src2 (const #xff)) (const 0)) (const BI 1))
2259                  ((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
2260                  ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
2261                  ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
2262                  (else (const BI 0))))
2263      ((m32rx (unit u-cmp))
2264       (m32r2 (unit u-cmp)))
2265 )
2266
2267 ; Add accumulators
2268 (dni sadd "sadd"
2269      ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM))
2270      "sadd"
2271      (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
2272      (set (reg h-accums 0)
2273           (add (sra (reg h-accums 1) (const 16))
2274                (reg h-accums 0)))
2275      ((m32rx (unit u-mac))
2276       (m32r2 (unit u-mac)))
2277 )
2278
2279 ; Multiply and add into accumulator 1
2280 (dni macwu1 "macwu1"
2281      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2282      "macwu1 $src1,$src2"
2283      (+ OP1_5 src1 OP2_11 src2)
2284      (set (reg h-accums 1)
2285           (sra DI
2286                 (sll DI
2287                       (add DI
2288                             (reg h-accums 1)
2289                             (mul DI
2290                                   (ext DI src1)
2291                                   (ext DI (and src2 (const #xffff)))))
2292                       (const 8))
2293                 (const 8)))
2294      ((m32rx (unit u-mac))
2295       (m32r2 (unit u-mac)))
2296 )
2297
2298 ; Multiply and subtract from accumulator 0
2299 (dni msblo "msblo"
2300      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2301      "msblo $src1,$src2"
2302      (+ OP1_5 src1 OP2_13 src2)
2303      (set accum
2304           (sra DI
2305                 (sll DI
2306                       (sub accum
2307                            (sra DI
2308                                  (sll DI
2309                                        (mul DI
2310                                              (ext DI (trunc HI src1))
2311                                              (ext DI (trunc HI src2)))
2312                                        (const 32))
2313                                  (const 16)))
2314                       (const 8))
2315                 (const 8)))
2316      ((m32rx (unit u-mac))
2317       (m32r2 (unit u-mac)))
2318 )
2319
2320 ; Multiply into accumulator 1
2321 (dni mulwu1 "mulwu1"
2322      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2323      "mulwu1 $src1,$src2"
2324      (+ OP1_5 src1 OP2_10 src2)
2325      (set (reg h-accums 1)
2326           (sra DI
2327                 (sll DI
2328                       (mul DI
2329                             (ext DI src1)
2330                             (ext DI (and src2 (const #xffff))))
2331                       (const 16))
2332                 (const 16)))
2333      ((m32rx (unit u-mac))
2334       (m32r2 (unit u-mac)))
2335 )
2336
2337 ; Multiply and add into accumulator 1
2338 (dni maclh1 "maclh1"
2339      ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC))
2340      "maclh1 $src1,$src2"
2341      (+ OP1_5 src1 OP2_12 src2)
2342      (set (reg h-accums 1)
2343           (sra DI
2344                 (sll DI
2345                     (add DI
2346                           (reg h-accums 1)
2347                           (sll DI
2348                                 (ext DI
2349                                       (mul SI
2350                                             (ext SI (trunc HI src1))
2351                                             (sra SI src2 (const SI 16))))
2352                               (const 16)))
2353                     (const 8))
2354                (const 8)))
2355      ((m32rx (unit u-mac))
2356       (m32r2 (unit u-mac)))
2357 )
2358
2359 ; skip instruction if C
2360 (dni sc "sc"
2361      ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
2362      "sc"
2363      (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
2364      (skip (zext INT condbit))
2365      ()
2366 )
2367
2368 ; skip instruction if not C
2369 (dni snc "snc"
2370      ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR))
2371      "snc"
2372      (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
2373      (skip (zext INT (not condbit)))
2374      ()
2375 )
2376
2377 ; PSW &= ~((unsigned char) uimm8 | 0x000ff00)
2378 (dni clrpsw "clrpsw"
2379      ((PIPE O) SPECIAL_M32R)
2380      "clrpsw $uimm8"
2381      (+ OP1_7 (f-r1 2) uimm8)
2382      (set USI (reg h-cr 0)
2383               (and USI (reg h-cr 0)
2384                      (or USI (inv BI uimm8) (const #xff00))))
2385      ()
2386 )
2387
2388 ; PSW |= (unsigned char) uimm8
2389 (dni setpsw "setpsw"
2390      ((PIPE O) SPECIAL_M32R)
2391      "setpsw $uimm8"
2392      (+ OP1_7 (f-r1 1) uimm8)
2393      (set USI (reg h-cr 0) uimm8)
2394      ()
2395 )
2396
2397 ; bset
2398 (dni bset "bset"
2399      (SPECIAL_M32R)
2400      "bset $uimm3,@($slo16,$sr)"
2401      (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16)
2402      (set QI (mem QI (add sr slo16))
2403              (or QI (mem QI (add sr slo16))
2404                   (sll USI (const 1) (sub (const 7) uimm3))))
2405      ()
2406 )
2407
2408 ; bclr
2409 (dni bclr "bclr"
2410      (SPECIAL_M32R)
2411      "bclr $uimm3,@($slo16,$sr)"
2412      (+ OP1_10 (f-bit4 0) uimm3  OP2_7 sr slo16)
2413      (set QI (mem QI (add sr slo16))
2414              (and QI (mem QI (add sr slo16))
2415                    (inv QI (sll USI (const 1) (sub (const 7) uimm3)))))
2416      ()
2417 )
2418
2419 ; btst
2420 (dni btst "btst"
2421      (SPECIAL_M32R (PIPE O))
2422      "btst $uimm3,$sr"
2423      (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr)
2424      (set condbit (and QI (srl USI sr (sub (const 7) uimm3)) (const 1)))
2425      ()
2426 )
2427