cpu/m32r.cpu

   1 ; Mitsubishi M32R CPU description.  -*- Scheme -*-
   2 ;
   3 ; Copyright 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
   4 ;
   5 ; Contributed by Red Hat Inc; developed under contract from Mitsubishi
   6 ; Electric Corporation.
   7 ;
   8 ; This file is part of the GNU Binutils.
   9 ;
  10 ; This program is free software; you can redistribute it and/or modify
  11 ; it under the terms of the GNU General Public License as published by
  12 ; the Free Software Foundation; either version 2 of the License, or
  13 ; (at your option) any later version.
  14 ;
  15 ; This program is distributed in the hope that it will be useful,
  16 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 ; GNU General Public License for more details.
  19 ;
  20 ; You should have received a copy of the GNU General Public License
  21 ; along with this program; if not, write to the Free Software
  22 ; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23
  24 (include "simplify.inc")
  25
  26 ; FIXME: Delete sign extension of accumulator results.
  27 ; Sign extension is done when accumulator is read.
  28
  29 ; define-arch must appear first
  30
  31 (define-arch
  32   (name m32r) ; name of cpu family
  33   (comment "Mitsubishi M32R")
  34   (default-alignment aligned)
  35   (insn-lsb0? #f)
  36   (machs m32r m32rx)
  37   (isas m32r)
  38 )
  39
  40 ; Attributes.
  41
  42 ; An attribute to describe which pipeline an insn runs in.
  43
  44 (define-attr
  45   (for insn)
  46   (type enum)
  47   (name PIPE)
  48   (comment "parallel execution pipeline selection")
  49   (values NONE O S OS)
  50 )
  51
  52 ; A derived attribute that says which insns can be executed in parallel
  53 ; with others.  This is a required attribute for architectures with
  54 ; parallel execution.
  55
  56 (define-attr
  57   (for insn)
  58   (type enum)
  59   (name PARALLEL)
  60   (attrs META) ; do not define in any generated file for now
  61   (values NO YES)
  62   (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES)))
  63 )
  64
  65 ; Instruction set parameters.
  66
  67 (define-isa
  68   (name m32r)
  69
  70   ; This is 32 because 16 bit insns always appear as pairs.
  71   ; ??? See if this can go away.  It's only used by the disassembler (right?)
  72   ; to decide how long an unknown insn is.  One value isn't sufficient (e.g. if
  73   ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.)
  74   (default-insn-bitsize 32)
  75
  76   ; Number of bytes of insn we can initially fetch.
  77   ; The M32R is tricky in that insns are either two 16-bit insns
  78   ; (executed sequentially or in parallel) or one 32-bit insn.
  79   ; So on one hand the base insn size is 16 bits, but on another it's 32.
  80   ; 32 is chosen because:
  81   ; - if the chip were ever bi-endian it is believed that the byte order would
  82   ;   be based on 32 bit quantities
  83   ; - 32 bit insns are always aligned on 32 bit boundaries
  84   ; - the pc will never stop on a 16 bit (and not 32 bit) boundary
  85   ;   [well actually it can, but there are no branches to such places]
  86   (base-insn-bitsize 32)
  87
  88   ; Used in computing bit numbers.
  89   (default-insn-word-bitsize 32)
  90
  91   ; The m32r fetches 2 insns at a time.
  92   (liw-insns 2)
  93
  94   ; While the m32r can execute insns in parallel, the base mach can't
  95   ; (other than nop).  The base mach is greatly handicapped by this, but
  96   ; we still need to cleanly handle it.
  97   (parallel-insns 2)
  98
  99   ; Initial bitnumbers to decode insns by.
 100   (decode-assist (0 1 2 3 8 9 10 11))
 101
 102   ; Classification of instructions that fit in the various frames.
 103   ; wip, not currently used
 104   (insn-types (long ; name
 105                31 ; length
 106                (eq-attr (current-insn) LENGTH 31) ; matching insns
 107                (0 1 2 7 8 9 10) ; decode-assist
 108                )
 109               (short
 110                15
 111                (eq-attr (current-insn) LENGTH 15) ; matching insns
 112                (0 1 2 7 8 9 10)
 113                )
 114               )
 115
 116   ; Instruction framing.
 117   ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed
 118   ; serially (left->right), or two 16 bit insns executed parallelly.
 119   ; wip, not currently used
 120   (frame long32 ; name
 121          ((long)) ; list of insns in frame, plus constraint
 122          "$0"   ; assembler
 123          (+ (1 1) (31 $0)) ; value
 124          (sequence () (execute $0)) ; action
 125          )
 126   (frame serial2x16
 127          ((short)
 128           (short))
 129          "$0 -> $1"
 130          (+ (1 0) (15 $0) (1 0) (15 $1))
 131          (sequence ()
 132                    (execute $0)
 133                    (execute $1))
 134          )
 135   (frame parallel2x16
 136          ((short (eq-attr (current-insn) PIPE "O,BOTH"))
 137           (short (eq-attr (current-insn) PIPE "S,BOTH")))
 138          "$0 || $1"
 139          (+ (1 0) (15 $0) (1 1) (15 $1))
 140          (parallel ()
 141                    (execute $0)
 142                    (execute $1))
 143          )
 144 )
 145 \f
 146 ; Cpu family definitions.
 147
 148 ; ??? define-cpu-family [and in general "cpu-family"] might be clearer than
 149 ; define-cpu.
 150 ; ??? Have define-arch provide defaults for architecture that define-cpu can
 151 ; then override [reduces duplication in define-cpu].
 152 ; ??? Another way to go is to delete cpu-families entirely and have one mach
 153 ; able to inherit things from another mach (would also need the ability to
 154 ; not only override specific inherited things but also disable some,
 155 ; e.g. if an insn wasn't supported).
 156
 157 (define-cpu
 158   ; cpu names must be distinct from the architecture name and machine names.
 159   ; The "b" suffix stands for "base" and is the convention.
 160   ; The "f" suffix stands for "family" and is the convention.
 161   (name m32rbf)
 162   (comment "Mitsubishi M32R base family")
 163   (endian big)
 164   (word-bitsize 32)
 165   ; Override isa spec (??? keeps things simpler, though it was more true
 166   ; in the early days and not so much now).
 167   (parallel-insns 1)
 168 )
 169
 170 (define-cpu
 171   (name m32rxf)
 172   (comment "Mitsubishi M32Rx family")
 173   (endian big)
 174   (word-bitsize 32)
 175   ; Generated files have an "x" suffix.
 176   (file-transform "x")
 177 )
 178
 179 (define-mach
 180   (name m32r)
 181   (comment "Generic M32R cpu")
 182   (cpu m32rbf)
 183 )
 184
 185 (define-mach
 186   (name m32rx)
 187   (comment "M32RX cpu")
 188   (cpu m32rxf)
 189 )
 190 \f
 191 ; Model descriptions.
 192
 193 ; The meaning of this value is wip but at the moment it's intended to describe
 194 ; the implementation (i.e. what -mtune=foo does in sparc gcc).
 195 ;
 196 ; Notes while wip:
 197 ; - format of pipeline entry:
 198 ;   (pipeline name (stage1-name ...) (stage2-name ...) ...)
 199 ;   The contents of a stage description is wip.
 200 ; - each mach must have at least one model
 201 ; - the default model must be the first one
 202 ;- maybe have `retire' support update total cycle count to handle current
 203 ;  parallel insn cycle counting problems
 204
 205 (define-model
 206   (name m32r/d) (comment "m32r/d") (attrs)
 207   (mach m32r)
 208
 209   ;(prefetch)
 210   ;(retire)
 211
 212   (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
 213   (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
 214
 215   ; `state' is a list of variables for recording model state
 216   (state
 217    ; bit mask of h-gr registers, =1 means value being loaded from memory
 218    (h-gr UINT)
 219    )
 220
 221   (unit u-exec "Execution Unit" ()
 222         1 1 ; issue done
 223         () ; state
 224         ((sr INT -1) (dr INT -1)) ; inputs
 225         ((dr INT -1)) ; outputs
 226         () ; profile action (default)
 227         )
 228   (unit u-cmp "Compare Unit" ()
 229         1 1 ; issue done
 230         () ; state
 231         ((src1 INT -1) (src2 INT -1)) ; inputs
 232         () ; outputs
 233         () ; profile action (default)
 234         )
 235   (unit u-mac "Multiply/Accumulate Unit" ()
 236         1 1 ; issue done
 237         () ; state
 238         ((src1 INT -1) (src2 INT -1)) ; inputs
 239         () ; outputs
 240         () ; profile action (default)
 241         )
 242   (unit u-cti "Branch Unit" ()
 243         1 1 ; issue done
 244         () ; state
 245         ((sr INT -1)) ; inputs
 246         ((pc)) ; outputs
 247         () ; profile action (default)
 248         )
 249   (unit u-load "Memory Load Unit" ()
 250         1 1 ; issue done
 251         () ; state
 252         ((sr INT)
 253          ;(ld-mem AI)
 254          ) ; inputs
 255         ((dr INT)) ; outputs
 256         () ; profile action (default)
 257         )
 258   (unit u-store "Memory Store Unit" ()
 259         1 1 ; issue done
 260         () ; state
 261         ((src1 INT) (src2 INT)) ; inputs
 262         () ; ((st-mem AI)) ; outputs
 263         () ; profile action (default)
 264         )
 265 )
 266
 267 (define-model
 268   (name test) (comment "test") (attrs)
 269   (mach m32r)
 270   (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
 271   (unit u-exec "Execution Unit" ()
 272         1 1 ; issue done
 273         () () () ())
 274 )
 275
 276 ; Each mach must have at least one model.
 277
 278 (define-model
 279   (name m32rx) (comment "m32rx") (attrs)
 280   (mach m32rx)
 281
 282   ; ??? It's 6 stages but I forget the details right now.
 283   (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
 284   (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
 285   (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
 286
 287   (unit u-exec "Execution Unit" ()
 288         1 1 ; issue done
 289         () ; state
 290         ((sr INT -1) (dr INT -1)) ; inputs
 291         ((dr INT -1)) ; outputs
 292         () ; profile action (default)
 293         )
 294   (unit u-cmp "Compare Unit" ()
 295         1 1 ; issue done
 296         () ; state
 297         ((src1 INT -1) (src2 INT -1)) ; inputs
 298         () ; outputs
 299         () ; profile action (default)
 300         )
 301   (unit u-mac "Multiply/Accumulate Unit" ()
 302         1 1 ; issue done
 303         () ; state
 304         ((src1 INT -1) (src2 INT -1)) ; inputs
 305         () ; outputs
 306         () ; profile action (default)
 307         )
 308   (unit u-cti "Branch Unit" ()
 309         1 1 ; issue done
 310         () ; state
 311         ((sr INT -1)) ; inputs
 312         ((pc)) ; outputs
 313         () ; profile action (default)
 314         )
 315   (unit u-load "Memory Load Unit" ()
 316         1 1 ; issue done
 317         () ; state
 318         ((sr INT)) ; inputs
 319         ((dr INT)) ; outputs
 320         () ; profile action (default)
 321         )
 322   (unit u-store "Memory Store Unit" ()
 323         1 1 ; issue done
 324         () ; state
 325         ((src1 INT) (src2 INT)) ; inputs
 326         () ; outputs
 327         () ; profile action (default)
 328         )
 329 )
 330 \f
 331 ; The instruction fetch/execute cycle.
 332 ; This is split into two parts as sometimes more than one instruction is
 333 ; decoded at once.
 334 ; The `const SI' argument to decode/execute is used to distinguish
 335 ; multiple instructions processed at the same time (e.g. m32r).
 336 ;
 337 ; ??? This is wip, and not currently used.
 338 ; ??? Needs to be moved to define-isa.
 339
 340 ; This is how to fetch and decode an instruction.
 341
 342 ;(define-extract
 343 ;  (sequence VOID
 344 ;           (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0))
 345 ;               (sequence VOID
 346 ;                         (set-quiet USI (scratch UHI insn1) (ifetch UHI pc))
 347 ;                         (decode VOID pc (and UHI insn1 (const UHI #x7fff))
 348 ;                                 (const SI 0)))
 349 ;               (sequence VOID
 350 ;                         (set-quiet USI (scratch USI insn) (ifetch USI pc))
 351 ;                         (if VOID (ne USI (and USI insn (const USI #x80000000))
 352 ;                                    (const USI 0))
 353 ;                             (decode VOID pc (srl USI insn (const WI 16)) (const SI 0))
 354 ;                             (sequence VOID
 355 ;                                       ; ??? parallel support
 356 ;                                       (decode VOID pc (srl USI insn (const WI 16))
 357 ;                                               (const SI 0))
 358 ;                                       (decode VOID (add AI pc (const AI 2))
 359 ;                                               (and USI insn (const WI #x7fff))
 360 ;                                               (const SI 1))))))
 361 ;           )
 362 ;)
 363
 364 ; This is how to execute a decoded instruction.
 365
 366 ;(define-execute
 367 ;  (sequence VOID () ; () is empty option list
 368 ;            ((AI new_pc))
 369 ;            (set AI new_pc (execute: AI (const 0)) #:quiet)
 370 ;            (set AI pc new_pc #:direct)
 371 ;            )
 372 ;)
 373
 374 ; FIXME: It might simplify things to separate the execute process from the
 375 ; one that updates the PC.
 376 \f
 377 ; Instruction fields.
 378 ;
 379 ; Attributes:
 380 ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
 381 ; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
 382 ; RESERVED: bits are not used to decode insn, must be all 0
 383 ; RELOC: there is a relocation associated with this field (experiment)
 384
 385 (define-attr
 386   (for ifield operand)
 387   (type boolean)
 388   (name RELOC)
 389   (comment "there is a reloc associated with this field (experiment)")
 390 )
 391
 392 (dnf f-op1       "op1"                 () 0 4)
 393 (dnf f-op2       "op2"                 () 8 4)
 394 (dnf f-cond      "cond"                () 4 4)
 395 (dnf f-r1        "r1"                  () 4 4)
 396 (dnf f-r2        "r2"                  () 12 4)
 397 (df f-simm8      "simm8"               () 8 8 INT #f #f)
 398 (df f-simm16     "simm16"              () 16 16 INT #f #f)
 399 (dnf f-shift-op2 "shift op2"           () 8 3)
 400 (dnf f-uimm4     "uimm4"               () 12 4)
 401 (dnf f-uimm5     "uimm5"               () 11 5)
 402 (dnf f-uimm16    "uimm16"              () 16 16)
 403 (dnf f-uimm24    "uimm24"              (ABS-ADDR RELOC) 8 24)
 404 (dnf f-hi16      "high 16 bits"        (SIGN-OPT) 16 16)
 405 (df f-disp8      "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT
 406     ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2)))
 407     ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4)))))
 408 (df f-disp16     "disp16"              (PCREL-ADDR RELOC) 16 16 INT
 409     ((value pc) (sra WI (sub WI value pc) (const 2)))
 410     ((value pc) (add WI (sll WI value (const 2)) pc)))
 411 (df f-disp24     "disp24"              (PCREL-ADDR RELOC) 8 24 INT
 412     ((value pc) (sra WI (sub WI value pc) (const 2)))
 413     ((value pc) (add WI (sll WI value (const 2)) pc)))
 414
 415 (dnf f-op23      "op2.3"               ()  9 3)
 416 (dnf f-op3       "op3"                 () 14 2)
 417 (dnf f-acc       "acc"                 ()  8 1)
 418 (dnf f-accs      "accs"                () 12 2)
 419 (dnf f-accd      "accd"                ()  4 2)
 420 (dnf f-bits67    "bits67"              ()  6 2)
 421 (dnf f-bit14     "bit14"               () 14 1)
 422
 423 (define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2")
 424   (attrs)
 425   (start 15) (length 1)
 426   (encode (value pc) (sub WI value (const WI 1)))
 427   (decode (value pc) (add WI value (const WI 1)))
 428 )
 429 \f
 430 ; Enums.
 431
 432 ; insn-op1: bits 0-3
 433 ; FIXME: should use die macro or some such
 434 (define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1
 435   ("0" "1" "2" "3" "4" "5" "6" "7"
 436    "8" "9" "10" "11" "12" "13" "14" "15")
 437 )
 438
 439 ; insn-op2: bits 8-11
 440 ; FIXME: should use die macro or some such
 441 (define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2
 442   ("0" "1" "2" "3" "4" "5" "6" "7"
 443    "8" "9" "10" "11" "12" "13" "14" "15")
 444 )
 445 \f
 446 ; Hardware pieces.
 447 ; These entries list the elements of the raw hardware.
 448 ; They're also used to provide tables and other elements of the assembly
 449 ; language.
 450
 451 (dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
 452
 453 (dnh h-hi16 "high 16 bits" ()
 454      (immediate (UINT 16))
 455      () () ()
 456 )
 457
 458 ; These two aren't technically needed.
 459 ; They're here for illustration sake mostly.
 460 ; Plus they cause the value to be stored in the extraction buffers to only
 461 ; be 16 bits wide (vs 32 or 64).  Whoopie ding.  But it's fun.
 462 (dnh h-slo16 "signed low 16 bits" ()
 463      (immediate (INT 16))
 464      () () ()
 465 )
 466 (dnh h-ulo16 "unsigned low 16 bits" ()
 467      (immediate (UINT 16))
 468      () () ()
 469 )
 470
 471 (define-keyword
 472   (name gr-names)
 473   (print-name h-gr)
 474   (prefix "")
 475   (values (fp 13) (lr 14) (sp 15)
 476           (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7)
 477           (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15))
 478 )
 479
 480 (define-hardware
 481   (name h-gr)
 482   (comment "general registers")
 483   (attrs PROFILE CACHE-ADDR)
 484   (type register WI (16))
 485   (indices extern-keyword gr-names)
 486 )
 487
 488 (define-keyword
 489   (name cr-names)
 490   (print-name h-cr)
 491   (prefix "")
 492   (values (psw 0)   (cbr 1)   (spi 2)   (spu 3)
 493           (bpc 6)   (bbpsw 8) (bbpc 14)
 494           (cr0 0)   (cr1 1)   (cr2 2)   (cr3 3)
 495           (cr4 4)   (cr5 5)   (cr6 6)   (cr7 7)
 496           (cr8 8)   (cr9 9)   (cr10 10) (cr11 11)
 497           (cr12 12) (cr13 13) (cr14 14) (cr15 15))
 498 )
 499
 500 (define-hardware
 501   (name h-cr)
 502   (comment "control registers")
 503   (type register UWI (16))
 504   (indices extern-keyword cr-names)
 505   (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index))
 506   (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval))
 507 )
 508
 509 ; The actual accumulator is only 56 bits.
 510 ; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0).
 511 ; To simplify the accumulator instructions, no attempt is made to keep the
 512 ; top 8 bits properly sign extended (currently there's no point since they
 513 ; all ignore them).  When the value is read it is properly sign extended
 514 ; [in the `get' handler].
 515 (define-hardware
 516   (name h-accum)
 517   (comment "accumulator")
 518   (type register DI)
 519   (get () (c-call DI "@cpu@_h_accum_get_handler"))
 520   (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval))
 521 )
 522
 523 ; FIXME: Revisit after sanitization can be removed.  Remove h-accum.
 524 (define-hardware
 525   (name h-accums)
 526   (comment "accumulators")
 527   (attrs (MACH m32rx))
 528   (type register DI (2))
 529   (indices keyword "" ((a0 0) (a1 1)))
 530   ; get/set so a0 accesses are redirected to h-accum.
 531   ; They're also so reads can properly sign extend the value.
 532   ; FIXME: Needn't be a function call.
 533   (get (index) (c-call DI "@cpu@_h_accums_get_handler" index))
 534   (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval))
 535 )
 536
 537 ; For condbit operand.  FIXME: Need to allow spec of get/set of operands.
 538 ; Having this separate from h-psw keeps the parts that use it simpler
 539 ; [since they greatly outnumber those that use h-psw].
 540 (dsh h-cond "condition bit" () (register BI))
 541
 542 ; The actual values of psw,bpsw,bbpsw are recorded here to allow access
 543 ; to them as a unit.
 544 (define-hardware
 545   (name h-psw)
 546   (comment "psw part of psw")
 547   (type register UQI)
 548   ; get/set to handle cond bit.
 549   ; FIXME: missing: use's and clobber's
 550   ; FIXME: remove c-call?
 551   (get () (c-call UQI "@cpu@_h_psw_get_handler"))
 552   (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval))
 553 )
 554 (dsh h-bpsw  "backup psw"      () (register UQI))
 555 (dsh h-bbpsw "backup bpsw"     () (register UQI))
 556
 557 ; FIXME: Later make add get/set specs and support SMP.
 558 (dsh h-lock  "lock"  () (register BI))
 559 \f
 560 ; Instruction Operands.
 561 ; These entries provide a layer between the assembler and the raw hardware
 562 ; description, and are used to refer to hardware elements in the semantic
 563 ; code.  Usually there's a bit of over-specification, but in more complicated
 564 ; instruction sets there isn't.
 565
 566 ; M32R specific operand attributes:
 567
 568 (define-attr
 569   (for operand)
 570   (type boolean)
 571   (name HASH-PREFIX)
 572   (comment "immediates have an optional '#' prefix")
 573 )
 574
 575 ; ??? Convention says this should be o-sr, but then the insn definitions
 576 ; should refer to o-sr which is clumsy.  The "o-" could be implicit, but
 577 ; then it should be implicit for all the symbols here, but then there would
 578 ; be confusion between (f-)simm8 and (h-)simm8.
 579 ; So for now the rule is exactly as it appears here.
 580
 581 (dnop sr     "source register"              () h-gr   f-r2)
 582 (dnop dr     "destination register"         () h-gr   f-r1)
 583 ;; The assembler relies upon the fact that dr and src1 are the same field.
 584 ;; FIXME: Revisit.
 585 (dnop src1   "source register 1"            () h-gr   f-r1)
 586 (dnop src2   "source register 2"            () h-gr   f-r2)
 587 (dnop scr    "source control register"      () h-cr   f-r2)
 588 (dnop dcr    "destination control register" () h-cr   f-r1)
 589
 590 (dnop simm8  "8 bit signed immediate"       (HASH-PREFIX) h-sint f-simm8)
 591 (dnop simm16 "16 bit signed immediate"      (HASH-PREFIX) h-sint f-simm16)
 592 (dnop uimm4  "4 bit trap number"            (HASH-PREFIX) h-uint f-uimm4)
 593 (dnop uimm5  "5 bit shift count"            (HASH-PREFIX) h-uint f-uimm5)
 594 (dnop uimm16 "16 bit unsigned immediate"    (HASH-PREFIX) h-uint f-uimm16)
 595
 596 (dnop imm1   "1 bit immediate"              ((MACH m32rx) HASH-PREFIX) h-uint f-imm1)
 597 (dnop accd   "accumulator destination register" ((MACH m32rx))        h-accums f-accd)
 598 (dnop accs   "accumulator source register"  ((MACH m32rx))            h-accums f-accs)
 599 (dnop acc    "accumulator reg (d)"          ((MACH m32rx))            h-accums f-acc)
 600
 601 ; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases.
 602 ; e.g. add3 r3,r3,#1 and ld r3,@(4,r4).  We could use HASH-PREFIX.
 603 ; Instead we create a fake operand `hash'.  The m32r is an illustration port,
 604 ; so we often try out various ways of doing things.
 605
 606 (define-operand (name hash) (comment "# prefix") (attrs)
 607   (type h-sint) ; doesn't really matter
 608   (index f-nil)
 609   (handlers (parse "hash") (print "hash"))
 610 )
 611
 612 ; For high(foo),shigh(foo).
 613 (define-operand
 614   (name hi16)
 615   (comment "high 16 bit immediate, sign optional")
 616   (attrs)
 617   (type h-hi16)
 618   (index f-hi16)
 619   (handlers (parse "hi16"))
 620 )
 621
 622 ; For low(foo),sda(foo).
 623 (define-operand
 624   (name slo16)
 625   (comment "16 bit signed immediate, for low()")
 626   (attrs)
 627   (type h-slo16)
 628   (index f-simm16)
 629   (handlers (parse "slo16"))
 630 )
 631
 632 ; For low(foo).
 633 (define-operand
 634   (name ulo16)
 635   (comment "16 bit unsigned immediate, for low()")
 636   (attrs)
 637   (type h-ulo16)
 638   (index f-uimm16)
 639   (handlers (parse "ulo16"))
 640 )
 641
 642 (dnop uimm24 "24 bit address" (HASH-PREFIX) h-addr f-uimm24)
 643
 644 (define-operand
 645   (name disp8)
 646   (comment "8 bit displacement")
 647   (attrs RELAX)
 648   (type h-iaddr)
 649   (index f-disp8)
 650   ; ??? Early experiments had insert/extract fields here.
 651   ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce
 652   ; fields here to handle more complicated cases.
 653 )
 654
 655 (dnop disp16 "16 bit displacement" () h-iaddr f-disp16)
 656 (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24)
 657
 658 ; These hardware elements are refered to frequently.
 659
 660 (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil)
 661 (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil)
 662 \f
 663 ; Instruction definitions.
 664 ;
 665 ; Notes while wip:
 666 ; - dni is a cover macro to the real "this is an instruction" keyword.
 667 ;   The syntax of the real one is yet to be determined.
 668 ;   At the lowest level (i.e. the "real" one) it will probably take a variable
 669 ;   list of arguments where each argument [perhaps after the standard three of
 670 ;   name, comment, attrs] is "(keyword arg-to-keyword)".  This syntax is simple
 671 ;   and yet completely upward extensible.  And given the macro facility, one
 672 ;   needn't code at that low a level so even though it'll be more verbose than
 673 ;   necessary it won't matter.  This same reasoning can be applied to most
 674 ;   types of entries in this file.
 675
 676 ; M32R specific instruction attributes:
 677
 678 ; FILL-SLOT: Need next insn to begin on 32 bit boundary.
 679 ; (A "slot" as used here is a 32 bit quantity that can either be filled with
 680 ; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right
 681 ; bin" where the left bin is the one with a lower address).
 682
 683 (define-attr
 684   (for insn)
 685   (type boolean)
 686   (name FILL-SLOT)
 687   (comment "fill right bin with `nop' if insn is in left bin")
 688 )
 689
 690 (define-attr
 691   (for insn)
 692   (type boolean)
 693   (name SPECIAL)
 694   (comment "non-public m32rx insn")
 695 )
 696
 697 ; IDOC attribute for instruction documentation.
 698
 699 (define-attr
 700   (for insn)
 701   (type enum)
 702   (name IDOC)
 703   (comment "insn kind for documentation")
 704   (attrs META)
 705   (values
 706    (MEM - () "Memory")
 707    (ALU - () "ALU")
 708    (BR - () "Branch")
 709    (ACCUM - () "Accumulator")
 710    (MAC - () "Multiply/Accumulate")
 711    (MISC - () "Miscellaneous")
 712   )
 713 )
 714
 715 (define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm)
 716   (begin
 717      (dni mnemonic
 718           (.str mnemonic " reg/reg")
 719           ((PIPE OS) (IDOC ALU))
 720           (.str mnemonic " $dr,$sr")
 721           (+ OP1_0 op2-op dr sr)
 722           (set dr (sem-op dr sr))
 723           ()
 724      )
 725      (dni (.sym mnemonic "3")
 726           (.str mnemonic " reg/" imm)
 727           ((IDOC ALU))
 728           (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm)
 729           (+ OP1_8 op2-op dr sr imm)
 730           (set dr (sem-op sr imm))
 731           ()
 732      )
 733    )
 734 )
 735 (bin-op add OP2_10 add "$hash" slo16)
 736 ; sub isn't present because sub3 doesn't exist.
 737 (bin-op and OP2_12 and "" uimm16)
 738 (bin-op or OP2_14 or "$hash" ulo16)
 739 (bin-op xor OP2_13 xor "" uimm16)
 740
 741 (dni addi "addi"
 742      ((PIPE OS) (IDOC ALU))
 743      ;#.(string-append "addi " "$dr,$simm8") ; #. experiment
 744      "addi $dr,$simm8"
 745      (+ OP1_4 dr simm8)
 746      (set dr (add dr simm8))
 747      ((m32r/d (unit u-exec))
 748       (m32rx (unit u-exec)))
 749 )
 750
 751 (dni addv "addv"
 752      ((PIPE OS) (IDOC ALU))
 753      "addv $dr,$sr"
 754      (+ OP1_0 OP2_8 dr sr)
 755      (parallel ()
 756                (set dr (add dr sr))
 757                (set condbit (add-oflag dr sr (const 0))))
 758      ()
 759 )
 760
 761 (dni addv3 "addv3"
 762      ((IDOC ALU))
 763      "addv3 $dr,$sr,$simm16"
 764      (+ OP1_8 OP2_8 dr sr simm16)
 765      (parallel ()
 766                (set dr (add sr simm16))
 767                (set condbit (add-oflag sr simm16 (const 0))))
 768      ()
 769 )
 770
 771 (dni addx "addx"
 772      ((PIPE OS) (IDOC ALU))
 773      "addx $dr,$sr"
 774      (+ OP1_0 OP2_9 dr sr)
 775      (parallel ()
 776                (set dr (addc dr sr condbit))
 777                (set condbit (add-cflag dr sr condbit)))
 778      ()
 779 )
 780
 781 (dni bc8 "bc with 8 bit displacement"
 782      (COND-CTI (PIPE O) (IDOC BR))
 783      "bc.s $disp8"
 784      (+ OP1_7 (f-r1 12) disp8)
 785      (if condbit (set pc disp8))
 786      ((m32r/d (unit u-cti))
 787       (m32rx (unit u-cti)))
 788 )
 789
 790 (dnmi bc8r "relaxable bc8"
 791      (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
 792      "bc $disp8"
 793      (emit bc8 disp8)
 794 )
 795
 796 (dni bc24 "bc with 24 bit displacement"
 797      (COND-CTI (IDOC BR))
 798      "bc.l $disp24"
 799      (+ OP1_15 (f-r1 12) disp24)
 800      (if condbit (set pc disp24))
 801      ((m32r/d (unit u-cti))
 802       (m32rx (unit u-cti)))
 803 )
 804
 805 (dnmi bc24r "relaxable bc24"
 806      (COND-CTI RELAXED (IDOC BR))
 807      "bc $disp24"
 808      (emit bc24 disp24)
 809 )
 810
 811 (dni beq "beq"
 812      (COND-CTI (IDOC BR))
 813      "beq $src1,$src2,$disp16"
 814      (+ OP1_11 OP2_0 src1 src2 disp16)
 815      (if (eq src1 src2) (set pc disp16))
 816      ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
 817       (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
 818 )
 819
 820 (define-pmacro (cbranch sym comment op2-op comp-op)
 821   (dni sym comment (COND-CTI (IDOC BR))
 822         (.str sym " $src2,$disp16")
 823         (+ OP1_11 op2-op (f-r1 0) src2 disp16)
 824         (if (comp-op src2 (const WI 0)) (set pc disp16))
 825         ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
 826          (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
 827         )
 828 )
 829 (cbranch beqz "beqz" OP2_8 eq)
 830 (cbranch bgez "bgez" OP2_11 ge)
 831 (cbranch bgtz "bgtz" OP2_13 gt)
 832 (cbranch blez "blez" OP2_12 le)
 833 (cbranch bltz "bltz" OP2_10 lt)
 834 (cbranch bnez "bnez" OP2_9 ne)
 835
 836 (dni bl8 "bl with 8 bit displacement"
 837      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
 838      "bl.s $disp8"
 839      (+ OP1_7 (f-r1 14) disp8)
 840      (sequence ()
 841                (set (reg h-gr 14)
 842                     (add (and pc (const -4)) (const 4)))
 843                (set pc disp8))
 844      ((m32r/d (unit u-cti))
 845       (m32rx (unit u-cti)))
 846 )
 847
 848 (dnmi bl8r "relaxable bl8"
 849      (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
 850      "bl $disp8"
 851      (emit bl8 disp8)
 852 )
 853
 854 (dni bl24 "bl with 24 bit displacement"
 855      (UNCOND-CTI (IDOC BR))
 856      "bl.l $disp24"
 857      (+ OP1_15 (f-r1 14) disp24)
 858      (sequence ()
 859                (set (reg h-gr 14) (add pc (const 4)))
 860                (set pc disp24))
 861      ((m32r/d (unit u-cti))
 862       (m32rx (unit u-cti)))
 863 )
 864
 865 (dnmi bl24r "relaxable bl24"
 866      (UNCOND-CTI RELAXED (IDOC BR))
 867      "bl $disp24"
 868      (emit bl24 disp24)
 869 )
 870
 871 (dni bcl8 "bcl with 8 bit displacement"
 872      (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
 873      "bcl.s $disp8"
 874      (+ OP1_7 (f-r1 8) disp8)
 875      (if condbit
 876          (sequence ()
 877                    (set (reg h-gr 14)
 878                         (add (and pc (const -4))
 879                              (const 4)))
 880                    (set pc disp8)))
 881      ((m32rx (unit u-cti)))
 882 )
 883
 884 (dnmi bcl8r "relaxable bcl8"
 885      (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
 886      "bcl $disp8"
 887      (emit bcl8 disp8)
 888 )
 889
 890 (dni bcl24 "bcl with 24 bit displacement"
 891      (COND-CTI (MACH m32rx) (IDOC BR))
 892      "bcl.l $disp24"
 893      (+ OP1_15 (f-r1 8) disp24)
 894      (if condbit
 895          (sequence ()
 896                    (set (reg h-gr 14) (add pc (const 4)))
 897                    (set pc disp24)))
 898      ((m32rx (unit u-cti)))
 899 )
 900
 901 (dnmi bcl24r "relaxable bcl24"
 902      (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
 903      "bcl $disp24"
 904      (emit bcl24 disp24)
 905 )
 906
 907 (dni bnc8 "bnc with 8 bit displacement"
 908      (COND-CTI (PIPE O) (IDOC BR))
 909      "bnc.s $disp8"
 910      (+ OP1_7 (f-r1 13) disp8)
 911      (if (not condbit) (set pc disp8))
 912      ((m32r/d (unit u-cti))
 913       (m32rx (unit u-cti)))
 914 )
 915
 916 (dnmi bnc8r "relaxable bnc8"
 917      (COND-CTI RELAXABLE (PIPE O) (IDOC BR))
 918      "bnc $disp8"
 919      (emit bnc8 disp8)
 920 )
 921
 922 (dni bnc24 "bnc with 24 bit displacement"
 923      (COND-CTI (IDOC BR))
 924      "bnc.l $disp24"
 925      (+ OP1_15 (f-r1 13) disp24)
 926      (if (not condbit) (set pc disp24))
 927      ((m32r/d (unit u-cti))
 928       (m32rx (unit u-cti)))
 929 )
 930
 931 (dnmi bnc24r "relaxable bnc24"
 932      (COND-CTI RELAXED (IDOC BR))
 933      "bnc $disp24"
 934      (emit bnc24 disp24)
 935 )
 936
 937 (dni bne "bne"
 938      (COND-CTI (IDOC BR))
 939      "bne $src1,$src2,$disp16"
 940      (+ OP1_11 OP2_1 src1 src2 disp16)
 941      (if (ne src1 src2) (set pc disp16))
 942      ((m32r/d (unit u-cti) (unit u-cmp (cycles 0)))
 943       (m32rx (unit u-cti) (unit u-cmp (cycles 0))))
 944 )
 945
 946 (dni bra8 "bra with 8 bit displacement"
 947      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
 948      "bra.s $disp8"
 949      (+ OP1_7 (f-r1 15) disp8)
 950      (set pc disp8)
 951      ((m32r/d (unit u-cti))
 952       (m32rx (unit u-cti)))
 953 )
 954
 955 (dnmi bra8r "relaxable bra8"
 956      (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR))
 957      "bra $disp8"
 958      (emit bra8 disp8)
 959 )
 960
 961 (dni bra24 "bra with 24 displacement"
 962      (UNCOND-CTI (IDOC BR))
 963      "bra.l $disp24"
 964      (+ OP1_15 (f-r1 15) disp24)
 965      (set pc disp24)
 966      ((m32r/d (unit u-cti))
 967       (m32rx (unit u-cti)))
 968 )
 969
 970 (dnmi bra24r "relaxable bra24"
 971      (UNCOND-CTI RELAXED (IDOC BR))
 972      "bra $disp24"
 973      (emit bra24 disp24)
 974 )
 975
 976 (dni bncl8 "bncl with 8 bit displacement"
 977      (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) (IDOC BR))
 978      "bncl.s $disp8"
 979      (+ OP1_7 (f-r1 9) disp8)
 980      (if (not condbit)
 981          (sequence ()
 982                    (set (reg h-gr 14)
 983                         (add (and pc (const -4))
 984                              (const 4)))
 985                    (set pc disp8)))
 986      ((m32rx (unit u-cti)))
 987 )
 988
 989 (dnmi bncl8r "relaxable bncl8"
 990      (COND-CTI FILL-SLOT (MACH m32rx) (PIPE O) RELAXABLE (IDOC BR))
 991      "bncl $disp8"
 992      (emit bncl8 disp8)
 993 )
 994
 995 (dni bncl24 "bncl with 24 bit displacement"
 996      (COND-CTI (MACH m32rx) (IDOC BR))
 997      "bncl.l $disp24"
 998      (+ OP1_15 (f-r1 9) disp24)
 999      (if (not condbit)
1000          (sequence ()
1001                    (set (reg h-gr 14) (add pc (const 4)))
1002                    (set pc disp24)))
1003      ((m32rx (unit u-cti)))
1004 )
1005
1006 (dnmi bncl24r "relaxable bncl24"
1007      (COND-CTI (MACH m32rx) RELAXED (IDOC BR))
1008      "bncl $disp24"
1009      (emit bncl24 disp24)
1010 )
1011
1012 (dni cmp "cmp"
1013      ((PIPE OS) (IDOC ALU))
1014      "cmp $src1,$src2"
1015      (+ OP1_0 OP2_4 src1 src2)
1016      (set condbit (lt src1 src2))
1017      ((m32r/d (unit u-cmp))
1018       (m32rx (unit u-cmp)))
1019 )
1020
1021 (dni cmpi "cmpi"
1022      ((IDOC ALU))
1023      "cmpi $src2,$simm16"
1024      (+ OP1_8 (f-r1 0) OP2_4 src2 simm16)
1025      (set condbit (lt src2 simm16))
1026      ((m32r/d (unit u-cmp))
1027       (m32rx (unit u-cmp)))
1028 )
1029
1030 (dni cmpu "cmpu"
1031      ((PIPE OS) (IDOC ALU))
1032      "cmpu $src1,$src2"
1033      (+ OP1_0 OP2_5 src1 src2)
1034      (set condbit (ltu src1 src2))
1035      ((m32r/d (unit u-cmp))
1036       (m32rx (unit u-cmp)))
1037 )
1038
1039 (dni cmpui "cmpui"
1040      ((IDOC ALU))
1041      "cmpui $src2,$simm16"
1042      (+ OP1_8 (f-r1 0) OP2_5 src2 simm16)
1043      (set condbit (ltu src2 simm16))
1044      ((m32r/d (unit u-cmp))
1045       (m32rx (unit u-cmp)))
1046 )
1047
1048 (dni cmpeq "cmpeq"
1049      ((MACH m32rx) (PIPE OS) (IDOC ALU))
1050      "cmpeq $src1,$src2"
1051      (+ OP1_0 OP2_6 src1 src2)
1052      (set condbit (eq src1 src2))
1053      ((m32rx (unit u-cmp)))
1054 )
1055
1056 (dni cmpz "cmpz"
1057      ((MACH m32rx) (PIPE OS) (IDOC ALU))
1058      "cmpz $src2"
1059      (+ OP1_0 OP2_7 (f-r1 0) src2)
1060      (set condbit (eq src2 (const 0)))
1061      ((m32rx (unit u-cmp)))
1062 )
1063
1064 (dni div "div"
1065      ((IDOC ALU))
1066      "div $dr,$sr"
1067      (+ OP1_9 OP2_0 dr sr (f-simm16 0))
1068      (if (ne sr (const 0)) (set dr (div dr sr)))
1069      ((m32r/d (unit u-exec (cycles 37)))
1070       (m32rx (unit u-exec (cycles 37))))
1071 )
1072
1073 (dni divu "divu"
1074      ((IDOC ALU))
1075      "divu $dr,$sr"
1076      (+ OP1_9 OP2_1 dr sr (f-simm16 0))
1077      (if (ne sr (const 0)) (set dr (udiv dr sr)))
1078      ((m32r/d (unit u-exec (cycles 37)))
1079       (m32rx (unit u-exec (cycles 37))))
1080 )
1081
1082 (dni rem "rem"
1083      ((IDOC ALU))
1084      "rem $dr,$sr"
1085      (+ OP1_9 OP2_2 dr sr (f-simm16 0))
1086      ; FIXME: Check rounding direction.
1087      (if (ne sr (const 0)) (set dr (mod dr sr)))
1088      ((m32r/d (unit u-exec (cycles 37)))
1089       (m32rx (unit u-exec (cycles 37))))
1090 )
1091
1092 (dni remu "remu"
1093      ((IDOC ALU))
1094      "remu $dr,$sr"
1095      (+ OP1_9 OP2_3 dr sr (f-simm16 0))
1096      ; FIXME: Check rounding direction.
1097      (if (ne sr (const 0)) (set dr (umod dr sr)))
1098      ((m32r/d (unit u-exec (cycles 37)))
1099       (m32rx (unit u-exec (cycles 37))))
1100 )
1101
1102 (dni divh "divh"
1103      ((MACH m32rx) (IDOC ALU))
1104      "divh $dr,$sr"
1105      (+ OP1_9 OP2_0 dr sr (f-simm16 #x10))
1106      (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr)))
1107      ((m32rx (unit u-exec (cycles 21))))
1108 )
1109
1110 (dni jc "jc"
1111      (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
1112      "jc $sr"
1113      (+ OP1_1 (f-r1 12) OP2_12 sr)
1114      (if condbit (set pc (and sr (const -4))))
1115      ((m32rx (unit u-cti)))
1116 )
1117
1118 (dni jnc "jnc"
1119      (COND-CTI (MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
1120      "jnc $sr"
1121      (+ OP1_1 (f-r1 13) OP2_12 sr)
1122      (if (not condbit) (set pc (and sr (const -4))))
1123      ((m32rx (unit u-cti)))
1124 )
1125
1126 (dni jl "jl"
1127      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR))
1128      "jl $sr"
1129      (+ OP1_1 (f-r1 14) OP2_12 sr)
1130      (parallel ()
1131                (set (reg h-gr 14)
1132                     (add (and pc (const -4)) (const 4)))
1133                (set pc (and sr (const -4))))
1134      ((m32r/d (unit u-cti))
1135       (m32rx (unit u-cti)))
1136 )
1137
1138 (dni jmp "jmp"
1139      (UNCOND-CTI (PIPE O) (IDOC BR))
1140      "jmp $sr"
1141      (+ OP1_1 (f-r1 15) OP2_12 sr)
1142      (set pc (and sr (const -4)))
1143      ; The above works now so this kludge has been commented out.
1144      ; It's kept around because the f-r1 reference in the semantic part
1145      ; should work.
1146      ; FIXME: kludge, instruction decoding not finished.
1147      ; But this should work, so that's another FIXME.
1148      ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14))
1149      ; FIXME: abuf->insn should be a macro of some sort.
1150      ;(sequence VOID
1151      ;         (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)")
1152      ;                    (const SI 14))
1153      ;             (set WI (reg WI h-gr 14)
1154      ;                  (add WI (and WI pc (const WI -4)) (const WI 4))))
1155      ;         (set WI pc sr))
1156      ((m32r/d (unit u-cti))
1157       (m32rx (unit u-cti)))
1158 )
1159
1160 (define-pmacro (no-ext-expr mode expr) expr)
1161 (define-pmacro (ext-expr mode expr) (ext mode expr))
1162 (define-pmacro (zext-expr mode expr) (zext mode expr))
1163
1164 (define-pmacro (load-op suffix op2-op mode ext-op)
1165   (begin
1166     (dni (.sym ld suffix) (.str "ld" suffix)
1167          ((PIPE O) (IDOC MEM))
1168          (.str "ld" suffix " $dr,@$sr")
1169          (+ OP1_2 op2-op dr sr)
1170          (set dr (ext-op WI (mem mode sr)))
1171          ((m32r/d (unit u-load))
1172           (m32rx (unit u-load)))
1173          )
1174     (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2")
1175           (NO-DIS (PIPE O) (IDOC MEM))
1176           (.str "ld" suffix " $dr,@($sr)")
1177           (emit (.sym ld suffix) dr sr))
1178     (dni (.sym ld suffix -d) (.str "ld" suffix "-d")
1179          ((IDOC MEM))
1180          (.str "ld" suffix " $dr,@($slo16,$sr)")
1181          (+ OP1_10 op2-op dr sr slo16)
1182          (set dr (ext-op WI (mem mode (add sr slo16))))
1183          ((m32r/d (unit u-load (cycles 2)))
1184           (m32rx (unit u-load (cycles 2))))
1185          )
1186     (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2")
1187           (NO-DIS (IDOC MEM))
1188           (.str "ld" suffix " $dr,@($sr,$slo16)")
1189           (emit (.sym ld suffix -d) dr sr slo16))
1190     )
1191 )
1192 (load-op "" OP2_12 WI no-ext-expr)
1193 (load-op b OP2_8 QI ext-expr)
1194 (load-op h OP2_10 HI ext-expr)
1195 (load-op ub OP2_9 QI zext-expr)
1196 (load-op uh OP2_11 HI zext-expr)
1197
1198 (dni ld-plus "ld+"
1199      ((PIPE O) (IDOC MEM))
1200      "ld $dr,@$sr+"
1201      (+ OP1_2 dr OP2_14 sr)
1202      (parallel ()
1203                ; wip: memory addresses in profiling support
1204                ;(set dr (name ld-mem (mem WI sr)))
1205                (set dr (mem WI sr))
1206                (set sr (add sr (const 4))))
1207      ; Note: `pred' is the constraint.  Also useful here is (ref name)
1208      ; and returns true if operand <name> was referenced
1209      ; (where "referenced" means _read_ if input operand and _written_ if
1210      ; output operand).
1211      ; args to unit are "unit-name (name1 value1) ..."
1212      ; - cycles(done),issue,pred are also specified this way
1213      ; - if unspecified, default is used
1214      ; - for ins/outs, extra arg is passed that says what was specified
1215      ;   - this is AND'd with `written' for outs
1216      ((m32r/d (unit u-load (pred (const 1)))
1217               (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1218       (m32rx (unit u-load)
1219              (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1))))
1220       )
1221 )
1222
1223 (dnmi pop "pop"
1224       ((IDOC MEM))
1225       "pop $dr"
1226       (emit ld-plus dr (sr 15)) ; "ld %0,@sp+"
1227 )
1228
1229 (dni ld24 "ld24"
1230      ((IDOC MEM))
1231      "ld24 $dr,$uimm24"
1232      (+ OP1_14 dr uimm24)
1233      (set dr uimm24)
1234      ()
1235 )
1236
1237 ; ldi8 appears before ldi16 so we try the shorter version first
1238
1239 (dni ldi8 "ldi8"
1240      ((PIPE OS) (IDOC ALU))
1241      "ldi8 $dr,$simm8"
1242      (+ OP1_6 dr simm8)
1243      (set dr simm8)
1244      ()
1245 )
1246
1247 (dnmi ldi8a "ldi8 alias"
1248      ((PIPE OS) (IDOC ALU))
1249      "ldi $dr,$simm8"
1250      (emit ldi8 dr simm8)
1251 )
1252
1253 (dni ldi16 "ldi16"
1254      ((IDOC ALU))
1255      "ldi16 $dr,$hash$slo16"
1256      (+ OP1_9 OP2_15 (f-r2 0) dr slo16)
1257      (set dr slo16)
1258      ()
1259 )
1260
1261 (dnmi ldi16a "ldi16 alias"
1262      ((IDOC ALU))
1263      "ldi $dr,$hash$slo16"
1264      (emit ldi16 dr slo16)
1265 )
1266
1267 (dni lock "lock"
1268      ((PIPE O) (IDOC MISC))
1269      "lock $dr,@$sr"
1270      (+ OP1_2 OP2_13 dr sr)
1271      (sequence ()
1272                (set (reg h-lock) (const BI 1))
1273                (set dr (mem WI sr)))
1274      ((m32r/d (unit u-load))
1275       (m32rx (unit u-load)))
1276 )
1277
1278 (dni machi "machi"
1279      (
1280       ; (MACH m32r) is a temporary hack.  This insn collides with machi-a
1281       ; in the simulator so disable it for m32rx.
1282       (MACH m32r) (PIPE S) (IDOC MAC)
1283      )
1284      "machi $src1,$src2"
1285      (+ OP1_3 OP2_4 src1 src2)
1286      ; FIXME: TRACE_RESULT will print the wrong thing since we
1287      ; alter one of the arguments.
1288      (set accum
1289           (sra DI
1290                (sll DI
1291                     (add DI
1292                          accum
1293                          (mul DI
1294                               (ext DI (and WI src1 (const #xffff0000)))
1295                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1296                     (const 8))
1297                (const 8)))
1298      ((m32r/d (unit u-mac)))
1299 )
1300
1301 (dni machi-a "machi-a"
1302      ((MACH m32rx) (PIPE S) (IDOC MAC))
1303      "machi $src1,$src2,$acc"
1304      (+ OP1_3 src1 acc (f-op23 4) src2)
1305      (set acc
1306           (sra DI
1307                (sll DI
1308                     (add DI
1309                          acc
1310                          (mul DI
1311                               (ext DI (and WI src1 (const #xffff0000)))
1312                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1313                     (const 8))
1314                (const 8)))
1315      ((m32rx (unit u-mac)))
1316 )
1317
1318 (dni maclo "maclo"
1319      ((MACH m32r) (PIPE S) (IDOC MAC))
1320      "maclo $src1,$src2"
1321      (+ OP1_3 OP2_5 src1 src2)
1322      (set accum
1323           (sra DI
1324                (sll DI
1325                     (add DI
1326                          accum
1327                          (mul DI
1328                               (ext DI (sll WI src1 (const 16)))
1329                               (ext DI (trunc HI src2))))
1330                     (const 8))
1331                (const 8)))
1332      ((m32r/d (unit u-mac)))
1333 )
1334
1335 (dni maclo-a "maclo-a"
1336      ((MACH m32rx) (PIPE S) (IDOC MAC))
1337      "maclo $src1,$src2,$acc"
1338      (+ OP1_3 src1 acc (f-op23 5) src2)
1339      (set acc
1340           (sra DI
1341                (sll DI
1342                     (add DI
1343                          acc
1344                          (mul DI
1345                               (ext DI (sll WI src1 (const 16)))
1346                               (ext DI (trunc HI src2))))
1347                     (const 8))
1348                (const 8)))
1349      ((m32rx (unit u-mac)))
1350 )
1351
1352 (dni macwhi "macwhi"
1353      ((MACH m32r) (PIPE S) (IDOC MAC))
1354      "macwhi $src1,$src2"
1355      (+ OP1_3 OP2_6 src1 src2)
1356      (set accum
1357           (sra DI
1358                (sll DI
1359                     (add DI
1360                          accum
1361                          (mul DI
1362                               (ext DI src1)
1363                               (ext DI (trunc HI (sra WI src2 (const 16))))))
1364                     (const 8))
1365                (const 8)))
1366      ((m32r/d (unit u-mac)))
1367 )
1368
1369 (dni macwhi-a "macwhi-a"
1370      ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
1371      "macwhi $src1,$src2,$acc"
1372      (+ OP1_3 src1 acc (f-op23 6) src2)
1373      ; Note that this doesn't do the sign extension, which is correct.
1374      (set acc
1375           (add acc
1376                (mul (ext DI src1)
1377                     (ext DI (trunc HI (sra src2 (const 16)))))))
1378      ((m32rx (unit u-mac)))
1379 )
1380
1381 (dni macwlo "macwlo"
1382      ((MACH m32r) (PIPE S) (IDOC MAC))
1383      "macwlo $src1,$src2"
1384      (+ OP1_3 OP2_7 src1 src2)
1385      (set accum
1386           (sra DI
1387                (sll DI
1388                     (add DI
1389                          accum
1390                          (mul DI
1391                               (ext DI src1)
1392                               (ext DI (trunc HI src2))))
1393                     (const 8))
1394                (const 8)))
1395      ((m32r/d (unit u-mac)))
1396 )
1397
1398 (dni macwlo-a "macwlo-a"
1399      ((MACH m32rx) (PIPE S) SPECIAL (IDOC MAC))
1400      "macwlo $src1,$src2,$acc"
1401      (+ OP1_3 src1 acc (f-op23 7) src2)
1402      ; Note that this doesn't do the sign extension, which is correct.
1403      (set acc
1404           (add acc
1405                (mul (ext DI src1)
1406                     (ext DI (trunc HI src2)))))
1407      ((m32rx (unit u-mac)))
1408 )
1409
1410 (dni mul "mul"
1411      ((PIPE S) (IDOC ALU))
1412      "mul $dr,$sr"
1413      (+ OP1_1 OP2_6 dr sr)
1414      (set dr (mul dr sr))
1415      ((m32r/d (unit u-exec (cycles 4)))
1416       (m32rx (unit u-exec (cycles 4))))
1417 )
1418
1419 (dni mulhi "mulhi"
1420      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1421      "mulhi $src1,$src2"
1422      (+ OP1_3 OP2_0 src1 src2)
1423      (set accum
1424           (sra DI
1425                (sll DI
1426                     (mul DI
1427                          (ext DI (and WI src1 (const #xffff0000)))
1428                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1429                     (const 16))
1430                (const 16)))
1431      ((m32r/d (unit u-mac)))
1432 )
1433
1434 (dni mulhi-a "mulhi-a"
1435      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1436      "mulhi $src1,$src2,$acc"
1437      (+ OP1_3 (f-op23 0) src1 acc src2)
1438      (set acc
1439           (sra DI
1440                (sll DI
1441                     (mul DI
1442                          (ext DI (and WI src1 (const #xffff0000)))
1443                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1444                     (const 16))
1445                (const 16)))
1446      ((m32rx (unit u-mac)))
1447 )
1448
1449 (dni mullo "mullo"
1450      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1451      "mullo $src1,$src2"
1452      (+ OP1_3 OP2_1 src1 src2)
1453      (set accum
1454           (sra DI
1455                (sll DI
1456                     (mul DI
1457                          (ext DI (sll WI src1 (const 16)))
1458                          (ext DI (trunc HI src2)))
1459                     (const 16))
1460                (const 16)))
1461      ((m32r/d (unit u-mac)))
1462 )
1463
1464 (dni mullo-a "mullo-a"
1465      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1466      "mullo $src1,$src2,$acc"
1467      (+ OP1_3 src1 acc (f-op23 1) src2)
1468      (set acc
1469           (sra DI
1470                (sll DI
1471                     (mul DI
1472                          (ext DI (sll WI src1 (const 16)))
1473                          (ext DI (trunc HI src2)))
1474                     (const 16))
1475                (const 16)))
1476      ((m32rx (unit u-mac)))
1477 )
1478
1479 (dni mulwhi "mulwhi"
1480      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1481      "mulwhi $src1,$src2"
1482      (+ OP1_3 OP2_2 src1 src2)
1483      (set accum
1484           (sra DI
1485                (sll DI
1486                     (mul DI
1487                          (ext DI src1)
1488                          (ext DI (trunc HI (sra WI src2 (const 16)))))
1489                     (const 8))
1490                (const 8)))
1491      ((m32r/d (unit u-mac)))
1492 )
1493
1494 (dni mulwhi-a "mulwhi-a"
1495      ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
1496      "mulwhi $src1,$src2,$acc"
1497      (+ OP1_3 src1 acc (f-op23 2) src2)
1498      ; Note that this doesn't do the sign extension, which is correct.
1499      (set acc
1500           (mul (ext DI src1)
1501                (ext DI (trunc HI (sra src2 (const 16))))))
1502      ((m32rx (unit u-mac)))
1503 )
1504
1505 (dni mulwlo "mulwlo"
1506      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1507      "mulwlo $src1,$src2"
1508      (+ OP1_3 OP2_3 src1 src2)
1509      (set accum
1510           (sra DI
1511                (sll DI
1512                     (mul DI
1513                          (ext DI src1)
1514                          (ext DI (trunc HI src2)))
1515                     (const 8))
1516                (const 8)))
1517      ((m32r/d (unit u-mac)))
1518 )
1519
1520 (dni mulwlo-a "mulwlo-a"
1521      ((MACH m32rx) (PIPE S) SPECIAL (IDOC ACCUM))
1522      "mulwlo $src1,$src2,$acc"
1523      (+ OP1_3 src1 acc (f-op23 3) src2)
1524      ; Note that this doesn't do the sign extension, which is correct.
1525      (set acc
1526           (mul (ext DI src1)
1527                (ext DI (trunc HI src2))))
1528      ((m32rx (unit u-mac)))
1529 )
1530
1531 (dni mv "mv"
1532      ((PIPE OS) (IDOC ALU))
1533      "mv $dr,$sr"
1534      (+ OP1_1 OP2_8 dr sr)
1535      (set dr sr)
1536      ()
1537 )
1538
1539 (dni mvfachi "mvfachi"
1540      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1541      "mvfachi $dr"
1542      (+ OP1_5 OP2_15 (f-r2 0) dr)
1543      (set dr (trunc WI (sra DI accum (const 32))))
1544      ((m32r/d (unit u-exec (cycles 2))))
1545 )
1546
1547 (dni mvfachi-a "mvfachi-a"
1548      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1549      "mvfachi $dr,$accs"
1550      (+ OP1_5 dr OP2_15 accs (f-op3 0))
1551      (set dr (trunc WI (sra DI accs (const 32))))
1552      ((m32rx (unit u-exec (cycles 2))))
1553 )
1554
1555 (dni mvfaclo "mvfaclo"
1556      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1557      "mvfaclo $dr"
1558      (+ OP1_5 OP2_15 (f-r2 1) dr)
1559      (set dr (trunc WI accum))
1560      ((m32r/d (unit u-exec (cycles 2))))
1561 )
1562
1563 (dni mvfaclo-a "mvfaclo-a"
1564      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1565      "mvfaclo $dr,$accs"
1566      (+ OP1_5 dr OP2_15 accs (f-op3 1))
1567      (set dr (trunc WI accs))
1568      ((m32rx (unit u-exec (cycles 2))))
1569 )
1570
1571 (dni mvfacmi "mvfacmi"
1572      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1573      "mvfacmi $dr"
1574      (+ OP1_5 OP2_15 (f-r2 2) dr)
1575      (set dr (trunc WI (sra DI accum (const 16))))
1576      ((m32r/d (unit u-exec (cycles 2))))
1577 )
1578
1579 (dni mvfacmi-a "mvfacmi-a"
1580      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1581      "mvfacmi $dr,$accs"
1582      (+ OP1_5 dr OP2_15 accs (f-op3 2))
1583      (set dr (trunc WI (sra DI accs (const 16))))
1584      ((m32rx (unit u-exec (cycles 2))))
1585 )
1586
1587 (dni mvfc "mvfc"
1588      ((PIPE O) (IDOC MISC))
1589      "mvfc $dr,$scr"
1590      (+ OP1_1 OP2_9 dr scr)
1591      (set dr scr)
1592      ()
1593 )
1594
1595 (dni mvtachi "mvtachi"
1596      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1597      "mvtachi $src1"
1598      (+ OP1_5 OP2_7 (f-r2 0) src1)
1599      (set accum
1600           (or DI
1601               (and DI accum (const DI #xffffffff))
1602               (sll DI (ext DI src1) (const 32))))
1603      ((m32r/d (unit u-exec (in sr src1))))
1604 )
1605
1606 (dni mvtachi-a "mvtachi-a"
1607      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1608      "mvtachi $src1,$accs"
1609      (+ OP1_5 src1 OP2_7 accs (f-op3 0))
1610      (set accs
1611           (or DI
1612               (and DI accs (const DI #xffffffff))
1613               (sll DI (ext DI src1) (const 32))))
1614      ((m32rx (unit u-exec (in sr src1))))
1615 )
1616
1617 (dni mvtaclo "mvtaclo"
1618      ((MACH m32r) (PIPE S) (IDOC ACCUM))
1619      "mvtaclo $src1"
1620      (+ OP1_5 OP2_7 (f-r2 1) src1)
1621      (set accum
1622           (or DI
1623               (and DI accum (const DI #xffffffff00000000))
1624               (zext DI src1)))
1625      ((m32r/d (unit u-exec (in sr src1))))
1626 )
1627
1628 (dni mvtaclo-a "mvtaclo-a"
1629      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
1630      "mvtaclo $src1,$accs"
1631      (+ OP1_5 src1 OP2_7 accs (f-op3 1))
1632      (set accs
1633           (or DI
1634               (and DI accs (const DI #xffffffff00000000))
1635               (zext DI src1)))
1636      ((m32rx (unit u-exec (in sr src1))))
1637 )
1638
1639 (dni mvtc "mvtc"
1640      ((PIPE O) (IDOC MISC))
1641      "mvtc $sr,$dcr"
1642      (+ OP1_1 OP2_10 dcr sr)
1643      (set dcr sr)
1644      ()
1645 )
1646
1647 (dni neg "neg"
1648      ((PIPE OS) (IDOC ALU))
1649      "neg $dr,$sr"
1650      (+ OP1_0 OP2_3 dr sr)
1651      (set dr (neg sr))
1652      ()
1653 )
1654
1655 (dni nop "nop"
1656      ((PIPE OS) (IDOC MISC))
1657      "nop"
1658      (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0))
1659      (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n")
1660      ; FIXME: quick hack: parallel nops don't contribute to cycle count.
1661      ; Other kinds of nops do however (which we currently ignore).
1662      ((m32r/d (unit u-exec (cycles 0)))
1663       (m32rx (unit u-exec (cycles 0))))
1664 )
1665
1666 (dni not "not"
1667      ((PIPE OS) (IDOC ALU))
1668      "not $dr,$sr"
1669      (+ OP1_0 OP2_11 dr sr)
1670      (set dr (inv sr))
1671      ()
1672 )
1673
1674 (dni rac "rac"
1675      ((MACH m32r) (PIPE S) (IDOC MAC))
1676      "rac"
1677      (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0))
1678      (sequence ((DI tmp1))
1679                (set tmp1 (sll DI accum (const 1)))
1680                (set tmp1 (add DI tmp1 (const DI #x8000)))
1681                (set accum
1682                     (cond DI
1683                           ((gt tmp1 (const DI #x00007fffffff0000))
1684                            (const DI #x00007fffffff0000))
1685                           ((lt tmp1 (const DI #xffff800000000000))
1686                            (const DI #xffff800000000000))
1687                           (else (and tmp1 (const DI #xffffffffffff0000)))))
1688                )
1689      ((m32r/d (unit u-mac)))
1690 )
1691
1692 (dni rac-dsi "rac-dsi"
1693      ((MACH m32rx) (PIPE S) (IDOC MAC))
1694      "rac $accd,$accs,$imm1"
1695      (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1)
1696      (sequence ((DI tmp1))
1697                (set tmp1 (sll accs imm1))
1698                (set tmp1 (add tmp1 (const DI #x8000)))
1699                (set accd
1700                     (cond DI
1701                           ((gt tmp1 (const DI #x00007fffffff0000))
1702                            (const DI #x00007fffffff0000))
1703                           ((lt tmp1 (const DI #xffff800000000000))
1704                            (const DI #xffff800000000000))
1705                           (else (and tmp1 (const DI #xffffffffffff0000)))))
1706                )
1707      ((m32rx (unit u-mac)))
1708 )
1709
1710 (dnmi rac-d "rac-d"
1711      ((MACH m32rx) (PIPE S) (IDOC MAC))
1712      "rac $accd"
1713      (emit rac-dsi accd (f-accs 0) (f-imm1 0))
1714 )
1715
1716 (dnmi rac-ds "rac-ds"
1717      ((MACH m32rx) (PIPE S) (IDOC MAC))
1718      "rac $accd,$accs"
1719      (emit rac-dsi accd accs (f-imm1 0))
1720 )
1721
1722
1723 (dni rach "rach"
1724      ((MACH m32r) (PIPE S) (IDOC MAC))
1725      "rach"
1726      (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0))
1727      (sequence ((DI tmp1))
1728                ; Lop off top 8 bits.
1729                ; The sign bit we want to use is bit 55 so the 64 bit value
1730                ; isn't properly signed which we deal with in the if's below.
1731                (set tmp1 (and accum (const DI #xffffffffffffff)))
1732                (if (andif (ge tmp1 (const DI #x003fff80000000))
1733                           (le tmp1 (const DI #x7fffffffffffff)))
1734                    (set tmp1 (const DI #x003fff80000000))
1735                    ; else part
1736                    (if (andif (ge tmp1 (const DI #x80000000000000))
1737                               (le tmp1 (const DI #xffc00000000000)))
1738                        (set tmp1 (const DI #xffc00000000000))
1739                        (set tmp1 (and (add accum (const DI #x40000000))
1740                                       (const DI #xffffffff80000000)))))
1741                (set tmp1 (sll tmp1 (const 1)))
1742                ; Sign extend top 8 bits.
1743                (set accum
1744                     ; FIXME: 7?
1745                     (sra DI (sll DI tmp1 (const 7)) (const 7)))
1746                )
1747      ((m32r/d (unit u-mac)))
1748 )
1749
1750 (dni rach-dsi "rach-dsi"
1751      ((MACH m32rx) (PIPE S) (IDOC MAC))
1752      "rach $accd,$accs,$imm1"
1753      (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1)
1754      (sequence ((DI tmp1))
1755                (set tmp1 (sll accs imm1))
1756                (set tmp1 (add tmp1 (const DI #x80000000)))
1757                (set accd
1758                     (cond DI
1759                           ((gt tmp1 (const DI #x00007fff00000000))
1760                            (const DI #x00007fff00000000))
1761                           ((lt tmp1 (const DI #xffff800000000000))
1762                            (const DI #xffff800000000000))
1763                           (else (and tmp1 (const DI #xffffffff00000000)))))
1764                )
1765      ((m32rx (unit u-mac)))
1766 )
1767
1768 (dnmi rach-d "rach-d"
1769      ((MACH m32rx) (PIPE S) (IDOC MAC))
1770      "rach $accd"
1771      (emit rach-dsi accd (f-accs 0) (f-imm1 0))
1772 )
1773
1774 (dnmi rach-ds "rach-ds"
1775      ((MACH m32rx) (PIPE S) (IDOC MAC))
1776      "rach $accd,$accs"
1777      (emit rach-dsi accd accs (f-imm1 0))
1778 )
1779
1780 (dni rte "rte"
1781      (UNCOND-CTI (PIPE O) (IDOC BR))
1782      "rte"
1783      (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6))
1784      (sequence ()
1785                ; pc = bpc & -4
1786                (set pc (and (reg h-cr 6) (const -4)))
1787                ; bpc = bbpc
1788                (set (reg h-cr 6) (reg h-cr 14))
1789                ; psw = bpsw
1790                (set (reg h-psw) (reg h-bpsw))
1791                ; bpsw = bbpsw
1792                (set (reg h-bpsw) (reg h-bbpsw))
1793      )
1794      ()
1795 )
1796
1797 (dni seth "seth"
1798      ((IDOC ALU))
1799      "seth $dr,$hash$hi16"
1800      (+ OP1_13 OP2_12 dr (f-r2 0) hi16)
1801      (set dr (sll WI hi16 (const 16)))
1802      ()
1803 )
1804
1805 (define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op)
1806   (begin
1807      (dni sym sym ((PIPE O) (IDOC ALU))
1808           (.str sym " $dr,$sr")
1809           (+ OP1_1 op2-r-op dr sr)
1810           (set dr (sem-op dr (and sr (const 31))))
1811           ()
1812      )
1813      (dni (.sym sym "3") sym ((IDOC ALU))
1814           (.str sym "3 $dr,$sr,$simm16")
1815           (+ OP1_9 op2-3-op dr sr simm16)
1816           (set dr (sem-op sr (and WI simm16 (const 31))))
1817           ()
1818      )
1819      (dni (.sym sym "i") sym ((PIPE O) (IDOC ALU))
1820           (.str sym "i $dr,$uimm5")
1821           (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5)
1822           (set dr (sem-op dr uimm5))
1823           ()
1824      )
1825    )
1826 )
1827 (shift-op sll OP2_4 OP2_12 2 sll)
1828 (shift-op sra OP2_2 OP2_10 1 sra)
1829 (shift-op srl OP2_0 OP2_8 0 srl)
1830
1831 (define-pmacro (store-op suffix op2-op mode)
1832   (begin
1833     (dni (.sym st suffix) (.str "st" suffix)
1834          ((PIPE O) (IDOC MEM))
1835          (.str "st" suffix " $src1,@$src2")
1836          (+ OP1_2 op2-op src1 src2)
1837          (set mode (mem mode src2) src1)
1838          ((m32r/d (unit u-store (cycles 1)))
1839           (m32rx (unit u-store (cycles 1))))
1840          )
1841     (dnmi (.sym st suffix "-2") (.str "st" suffix "-2")
1842           (NO-DIS (PIPE O) (IDOC MEM))
1843           (.str "st" suffix " $src1,@($src2)")
1844           (emit (.sym st suffix) src1 src2))
1845     (dni (.sym st suffix -d) (.str "st" suffix "-d")
1846          ((IDOC MEM))
1847          (.str "st" suffix " $src1,@($slo16,$src2)")
1848          (+ OP1_10 op2-op src1 src2 slo16)
1849          (set mode (mem mode (add src2 slo16)) src1)
1850          ((m32r/d (unit u-store (cycles 2)))
1851           (m32rx (unit u-store (cycles 2))))
1852          )
1853     (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2")
1854           (NO-DIS (IDOC MEM))
1855           (.str "st" suffix " $src1,@($src2,$slo16)")
1856           (emit (.sym st suffix -d) src1 src2 slo16))
1857     )
1858 )
1859 (store-op "" OP2_4 WI)
1860 (store-op b OP2_0 QI)
1861 (store-op h OP2_2 HI)
1862
1863 (dni st-plus "st+"
1864      ((PIPE O) (IDOC MEM))
1865      "st $src1,@+$src2"
1866      (+ OP1_2 OP2_6 src1 src2)
1867      ; This has to be coded carefully to avoid an "earlyclobber" of src2.
1868      (sequence ((WI new-src2))
1869                (set new-src2 (add WI src2 (const WI 4)))
1870                (set (mem WI new-src2) src1)
1871                (set src2 new-src2))
1872      ((m32r/d (unit u-store)
1873               (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
1874       (m32rx (unit u-store)
1875              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
1876       )
1877 )
1878
1879 (dni st-minus "st-"
1880      ((PIPE O) (IDOC MEM))
1881      "st $src1,@-$src2"
1882      (+ OP1_2 OP2_7 src1 src2)
1883      ; This is the original way.  It doesn't work for parallel execution
1884      ; because of the earlyclobber of src2.
1885      ;(sequence ()
1886      ;         (set src2 (sub src2 (const 4)))
1887      ;         (set (mem WI src2) src1))
1888      (sequence ((WI new-src2))
1889                (set new-src2 (sub src2 (const 4)))
1890                (set (mem WI new-src2) src1)
1891                (set src2 new-src2))
1892      ((m32r/d (unit u-store)
1893               (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
1894       (m32rx (unit u-store)
1895              (unit u-exec (in dr src2) (out dr src2) (cycles 0)))
1896       )
1897 )
1898
1899 (dnmi push "push" ((IDOC MEM))
1900   "push $src1"
1901   (emit st-minus src1 (src2 15)) ; "st %0,@-sp"
1902 )
1903
1904 (dni sub "sub"
1905      ((PIPE OS) (IDOC ALU))
1906      "sub $dr,$sr"
1907      (+ OP1_0 OP2_2 dr sr)
1908      (set dr (sub dr sr))
1909      ()
1910 )
1911
1912 (dni subv "sub:rv"
1913      ((PIPE OS) (IDOC ALU))
1914      "subv $dr,$sr"
1915      (+ OP1_0 OP2_0 dr sr)
1916      (parallel ()
1917                (set dr (sub dr sr))
1918                (set condbit (sub-oflag dr sr (const 0))))
1919      ()
1920 )
1921
1922 (dni subx "sub:rx"
1923      ((PIPE OS) (IDOC ALU))
1924      "subx $dr,$sr"
1925      (+ OP1_0 OP2_1 dr sr)
1926      (parallel ()
1927                (set dr (subc dr sr condbit))
1928                (set condbit (sub-cflag dr sr condbit)))
1929      ()
1930 )
1931
1932 (dni trap "trap"
1933      (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC))
1934      "trap $uimm4"
1935      (+ OP1_1 OP2_15 (f-r1 0) uimm4)
1936      (sequence ()
1937                ; bbpc = bpc
1938                (set (reg h-cr 14) (reg h-cr 6))
1939                ; Set bpc to the return address.  Actually it's not quite the
1940                ; return address as RTE rounds the address down to a word
1941                ; boundary.
1942                (set (reg h-cr 6) (add pc (const 4)))
1943                ; bbpsw = bpsw
1944                (set (reg h-bbpsw) (reg h-bpsw))
1945                ; bpsw = psw
1946                (set (reg h-bpsw) (reg h-psw))
1947                ; sm is unchanged, ie,c are set to zero.
1948                (set (reg h-psw) (and (reg h-psw) (const #x80)))
1949                ; m32r_trap handles operating vs user mode
1950                (set WI pc (c-call WI "m32r_trap" pc uimm4))
1951      )
1952      ()
1953 )
1954
1955 (dni unlock "unlock"
1956      ((PIPE O) (IDOC MISC))
1957      "unlock $src1,@$src2"
1958      (+ OP1_2 OP2_5 src1 src2)
1959      (sequence ()
1960                (if (reg h-lock)
1961                    (set (mem WI src2) src1))
1962                (set (reg h-lock) (const BI 0)))
1963      ((m32r/d (unit u-load))
1964       (m32rx (unit u-load)))
1965 )
1966
1967 ; Saturate into byte.
1968 (dni satb "satb"
1969      ((MACH m32rx) (IDOC ALU))
1970      "satb $dr,$sr"
1971      (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300))
1972      (set dr
1973           ; FIXME: min/max would simplify this nicely of course.
1974           (cond WI
1975                 ((ge sr (const 127)) (const 127))
1976                 ((le sr (const -128)) (const -128))
1977                 (else sr)))
1978      ()
1979 )
1980
1981 ; Saturate into half word.
1982 (dni sath "sath"
1983      ((MACH m32rx) (IDOC ALU))
1984      "sath $dr,$sr"
1985      (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200))
1986      (set dr
1987           (cond WI
1988                 ((ge sr (const 32767)) (const 32767))
1989                 ((le sr (const -32768)) (const -32768))
1990                 (else sr)))
1991      ()
1992 )
1993
1994 ; Saturate word.
1995 (dni sat "sat"
1996      ((MACH m32rx) SPECIAL (IDOC ALU))
1997      "sat $dr,$sr"
1998      (+ OP1_8 dr OP2_6 sr (f-uimm16 0))
1999      (set dr
2000           (if WI condbit
2001                (if WI (lt sr (const 0))
2002                     (const #x7fffffff)
2003                     (const #x80000000))
2004                sr))
2005      ()
2006 )
2007
2008 ; Parallel compare byte zeros.
2009 ; Set C bit in condition register if any byte in source register is zero.
2010 (dni pcmpbz "pcmpbz"
2011      ((MACH m32rx) (PIPE OS) SPECIAL (IDOC ALU))
2012      "pcmpbz $src2"
2013      (+ OP1_0 (f-r1 3) OP2_7 src2)
2014      (set condbit
2015           (cond BI
2016                  ((eq (and src2 (const #xff)) (const 0)) (const BI 1))
2017                  ((eq (and src2 (const #xff00)) (const 0)) (const BI 1))
2018                  ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1))
2019                  ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1))
2020                  (else (const BI 0))))
2021      ((m32rx (unit u-cmp)))
2022 )
2023
2024 ; Add accumulators
2025 (dni sadd "sadd"
2026      ((MACH m32rx) (PIPE S) (IDOC ACCUM))
2027      "sadd"
2028      (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4))
2029      (set (reg h-accums 0)
2030           (add (sra (reg h-accums 1) (const 16))
2031                (reg h-accums 0)))
2032      ((m32rx (unit u-mac)))
2033 )
2034
2035 ; Multiply and add into accumulator 1
2036 (dni macwu1 "macwu1"
2037      ((MACH m32rx) (PIPE S) (IDOC MAC))
2038      "macwu1 $src1,$src2"
2039      (+ OP1_5 src1 OP2_11 src2)
2040      (set (reg h-accums 1)
2041           (sra DI
2042                 (sll DI
2043                       (add DI
2044                             (reg h-accums 1)
2045                             (mul DI
2046                                   (ext DI src1)
2047                                   (ext DI (and src2 (const #xffff)))))
2048                       (const 8))
2049                 (const 8)))
2050      ((m32rx (unit u-mac)))
2051 )
2052
2053 ; Multiply and subtract from accumulator 0
2054 (dni msblo "msblo"
2055      ((MACH m32rx) (PIPE S) (IDOC MAC))
2056      "msblo $src1,$src2"
2057      (+ OP1_5 src1 OP2_13 src2)
2058      (set accum
2059           (sra DI
2060                 (sll DI
2061                       (sub accum
2062                            (sra DI
2063                                  (sll DI
2064                                        (mul DI
2065                                              (ext DI (trunc HI src1))
2066                                              (ext DI (trunc HI src2)))
2067                                        (const 32))
2068                                  (const 16)))
2069                       (const 8))
2070                 (const 8)))
2071      ((m32rx (unit u-mac)))
2072 )
2073
2074 ; Multiply into accumulator 1
2075 (dni mulwu1 "mulwu1"
2076      ((MACH m32rx) (PIPE S) (IDOC MAC))
2077      "mulwu1 $src1,$src2"
2078      (+ OP1_5 src1 OP2_10 src2)
2079      (set (reg h-accums 1)
2080           (sra DI
2081                 (sll DI
2082                       (mul DI
2083                             (ext DI src1)
2084                             (ext DI (and src2 (const #xffff))))
2085                       (const 16))
2086                 (const 16)))
2087      ((m32rx (unit u-mac)))
2088 )
2089
2090 ; Multiply and add into accumulator 1
2091 (dni maclh1 "maclh1"
2092      ((MACH m32rx) (PIPE S) (IDOC MAC))
2093      "maclh1 $src1,$src2"
2094      (+ OP1_5 src1 OP2_12 src2)
2095      (set (reg h-accums 1)
2096           (sra DI
2097                 (sll DI
2098                     (add DI
2099                           (reg h-accums 1)
2100                           (sll DI
2101                                 (ext DI
2102                                       (mul SI
2103                                             (ext SI (trunc HI src1))
2104                                             (sra SI src2 (const SI 16))))
2105                               (const 16)))
2106                     (const 8))
2107                (const 8)))
2108      ((m32rx (unit u-mac)))
2109 )
2110
2111 ; skip instruction if C
2112 (dni sc "sc"
2113      ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
2114      "sc"
2115      (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1))
2116      (skip (zext INT condbit))
2117      ()
2118 )
2119
2120 ; skip instruction if not C
2121 (dni snc "snc"
2122      ((MACH m32rx) (PIPE O) SPECIAL (IDOC BR))
2123      "snc"
2124      (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1))
2125      (skip (zext INT (not condbit)))
2126      ()
2127 )