2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
57 AHCI_MAX_SG
= 168, /* hardware max is 64K */
58 AHCI_DMA_BOUNDARY
= 0xffffffff,
59 AHCI_USE_CLUSTERING
= 0,
62 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
64 AHCI_CMD_TBL_CDB
= 0x40,
65 AHCI_CMD_TBL_HDR_SZ
= 0x80,
66 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
67 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
68 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
70 AHCI_IRQ_ON_SG
= (1 << 31),
71 AHCI_CMD_ATAPI
= (1 << 5),
72 AHCI_CMD_WRITE
= (1 << 6),
73 AHCI_CMD_PREFETCH
= (1 << 7),
74 AHCI_CMD_RESET
= (1 << 8),
75 AHCI_CMD_CLR_BUSY
= (1 << 10),
77 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
78 RX_FIS_SDB
= 0x58, /* offset of SDB FIS data */
79 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
83 board_ahci_vt8251
= 2,
84 board_ahci_ign_iferr
= 3,
86 /* global controller registers */
87 HOST_CAP
= 0x00, /* host capabilities */
88 HOST_CTL
= 0x04, /* global host control */
89 HOST_IRQ_STAT
= 0x08, /* interrupt status */
90 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
94 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
99 HOST_CAP_SSC
= (1 << 14), /* Slumber capable */
100 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS
= (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
103 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
105 /* registers for each SATA port */
106 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT
= 0x10, /* interrupt status */
111 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
112 PORT_CMD
= 0x18, /* port command */
113 PORT_TFDATA
= 0x20, /* taskfile data */
114 PORT_SIG
= 0x24, /* device TF signature */
115 PORT_CMD_ISSUE
= 0x38, /* command issue */
116 PORT_SCR
= 0x28, /* SATA phy register block */
117 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
132 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
142 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
147 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
149 PORT_IRQ_HBUS_DATA_ERR
,
150 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
151 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
152 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
155 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
156 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
159 PORT_CMD_CLO
= (1 << 3), /* Command list override */
160 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
162 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
164 PORT_CMD_ICC_MASK
= (0xf << 28), /* i/f ICC state mask */
165 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
169 /* hpriv->flags bits */
170 AHCI_FLAG_MSI
= (1 << 0),
173 AHCI_FLAG_NO_NCQ
= (1 << 24),
174 AHCI_FLAG_IGN_IRQ_IF_ERR
= (1 << 25), /* ignore IRQ_IF_ERR */
175 AHCI_FLAG_HONOR_PI
= (1 << 26), /* honor PORTS_IMPL */
178 struct ahci_cmd_hdr
{
193 struct ahci_host_priv
{
195 u32 cap
; /* cache of HOST_CAP register */
196 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
199 struct ahci_port_priv
{
200 struct ahci_cmd_hdr
*cmd_slot
;
201 dma_addr_t cmd_slot_dma
;
203 dma_addr_t cmd_tbl_dma
;
205 dma_addr_t rx_fis_dma
;
206 /* for NCQ spurious interrupt analysis */
207 int ncq_saw_spurious_sdb_cnt
;
208 unsigned int ncq_saw_d2h
:1;
209 unsigned int ncq_saw_dmas
:1;
212 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
213 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
214 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
215 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
216 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
);
217 static void ahci_irq_clear(struct ata_port
*ap
);
218 static int ahci_port_start(struct ata_port
*ap
);
219 static void ahci_port_stop(struct ata_port
*ap
);
220 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
221 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
222 static u8
ahci_check_status(struct ata_port
*ap
);
223 static void ahci_freeze(struct ata_port
*ap
);
224 static void ahci_thaw(struct ata_port
*ap
);
225 static void ahci_error_handler(struct ata_port
*ap
);
226 static void ahci_vt8251_error_handler(struct ata_port
*ap
);
227 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
228 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
229 static int ahci_port_resume(struct ata_port
*ap
);
230 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
231 static int ahci_pci_device_resume(struct pci_dev
*pdev
);
232 static void ahci_remove_one (struct pci_dev
*pdev
);
234 static struct scsi_host_template ahci_sht
= {
235 .module
= THIS_MODULE
,
237 .ioctl
= ata_scsi_ioctl
,
238 .queuecommand
= ata_scsi_queuecmd
,
239 .change_queue_depth
= ata_scsi_change_queue_depth
,
240 .can_queue
= AHCI_MAX_CMDS
- 1,
241 .this_id
= ATA_SHT_THIS_ID
,
242 .sg_tablesize
= AHCI_MAX_SG
,
243 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
244 .emulated
= ATA_SHT_EMULATED
,
245 .use_clustering
= AHCI_USE_CLUSTERING
,
246 .proc_name
= DRV_NAME
,
247 .dma_boundary
= AHCI_DMA_BOUNDARY
,
248 .slave_configure
= ata_scsi_slave_config
,
249 .slave_destroy
= ata_scsi_slave_destroy
,
250 .bios_param
= ata_std_bios_param
,
251 .suspend
= ata_scsi_device_suspend
,
252 .resume
= ata_scsi_device_resume
,
255 static const struct ata_port_operations ahci_ops
= {
256 .port_disable
= ata_port_disable
,
258 .check_status
= ahci_check_status
,
259 .check_altstatus
= ahci_check_status
,
260 .dev_select
= ata_noop_dev_select
,
262 .tf_read
= ahci_tf_read
,
264 .qc_prep
= ahci_qc_prep
,
265 .qc_issue
= ahci_qc_issue
,
267 .irq_handler
= ahci_interrupt
,
268 .irq_clear
= ahci_irq_clear
,
270 .scr_read
= ahci_scr_read
,
271 .scr_write
= ahci_scr_write
,
273 .freeze
= ahci_freeze
,
276 .error_handler
= ahci_error_handler
,
277 .post_internal_cmd
= ahci_post_internal_cmd
,
279 .port_suspend
= ahci_port_suspend
,
280 .port_resume
= ahci_port_resume
,
282 .port_start
= ahci_port_start
,
283 .port_stop
= ahci_port_stop
,
286 static const struct ata_port_operations ahci_vt8251_ops
= {
287 .port_disable
= ata_port_disable
,
289 .check_status
= ahci_check_status
,
290 .check_altstatus
= ahci_check_status
,
291 .dev_select
= ata_noop_dev_select
,
293 .tf_read
= ahci_tf_read
,
295 .qc_prep
= ahci_qc_prep
,
296 .qc_issue
= ahci_qc_issue
,
298 .irq_handler
= ahci_interrupt
,
299 .irq_clear
= ahci_irq_clear
,
301 .scr_read
= ahci_scr_read
,
302 .scr_write
= ahci_scr_write
,
304 .freeze
= ahci_freeze
,
307 .error_handler
= ahci_vt8251_error_handler
,
308 .post_internal_cmd
= ahci_post_internal_cmd
,
310 .port_suspend
= ahci_port_suspend
,
311 .port_resume
= ahci_port_resume
,
313 .port_start
= ahci_port_start
,
314 .port_stop
= ahci_port_stop
,
317 static const struct ata_port_info ahci_port_info
[] = {
321 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
322 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
323 ATA_FLAG_SKIP_D2H_BSY
,
324 .pio_mask
= 0x1f, /* pio0-4 */
325 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
326 .port_ops
= &ahci_ops
,
331 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
332 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
333 ATA_FLAG_SKIP_D2H_BSY
| AHCI_FLAG_HONOR_PI
,
334 .pio_mask
= 0x1f, /* pio0-4 */
335 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
336 .port_ops
= &ahci_ops
,
338 /* board_ahci_vt8251 */
341 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
342 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
343 ATA_FLAG_SKIP_D2H_BSY
|
344 ATA_FLAG_HRST_TO_RESUME
| AHCI_FLAG_NO_NCQ
,
345 .pio_mask
= 0x1f, /* pio0-4 */
346 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
347 .port_ops
= &ahci_vt8251_ops
,
349 /* board_ahci_ign_iferr */
352 .flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
353 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
354 ATA_FLAG_SKIP_D2H_BSY
|
355 AHCI_FLAG_IGN_IRQ_IF_ERR
,
356 .pio_mask
= 0x1f, /* pio0-4 */
357 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
358 .port_ops
= &ahci_ops
,
362 static const struct pci_device_id ahci_pci_tbl
[] = {
364 { PCI_VDEVICE(INTEL
, 0x2652), board_ahci
}, /* ICH6 */
365 { PCI_VDEVICE(INTEL
, 0x2653), board_ahci
}, /* ICH6M */
366 { PCI_VDEVICE(INTEL
, 0x27c1), board_ahci
}, /* ICH7 */
367 { PCI_VDEVICE(INTEL
, 0x27c5), board_ahci
}, /* ICH7M */
368 { PCI_VDEVICE(INTEL
, 0x27c3), board_ahci
}, /* ICH7R */
369 { PCI_VDEVICE(AL
, 0x5288), board_ahci_ign_iferr
}, /* ULi M5288 */
370 { PCI_VDEVICE(INTEL
, 0x2681), board_ahci
}, /* ESB2 */
371 { PCI_VDEVICE(INTEL
, 0x2682), board_ahci
}, /* ESB2 */
372 { PCI_VDEVICE(INTEL
, 0x2683), board_ahci
}, /* ESB2 */
373 { PCI_VDEVICE(INTEL
, 0x27c6), board_ahci
}, /* ICH7-M DH */
374 { PCI_VDEVICE(INTEL
, 0x2821), board_ahci_pi
}, /* ICH8 */
375 { PCI_VDEVICE(INTEL
, 0x2822), board_ahci_pi
}, /* ICH8 */
376 { PCI_VDEVICE(INTEL
, 0x2824), board_ahci_pi
}, /* ICH8 */
377 { PCI_VDEVICE(INTEL
, 0x2829), board_ahci_pi
}, /* ICH8M */
378 { PCI_VDEVICE(INTEL
, 0x282a), board_ahci_pi
}, /* ICH8M */
379 { PCI_VDEVICE(INTEL
, 0x2922), board_ahci_pi
}, /* ICH9 */
380 { PCI_VDEVICE(INTEL
, 0x2923), board_ahci_pi
}, /* ICH9 */
381 { PCI_VDEVICE(INTEL
, 0x2924), board_ahci_pi
}, /* ICH9 */
382 { PCI_VDEVICE(INTEL
, 0x2925), board_ahci_pi
}, /* ICH9 */
383 { PCI_VDEVICE(INTEL
, 0x2927), board_ahci_pi
}, /* ICH9 */
384 { PCI_VDEVICE(INTEL
, 0x2929), board_ahci_pi
}, /* ICH9M */
385 { PCI_VDEVICE(INTEL
, 0x292a), board_ahci_pi
}, /* ICH9M */
386 { PCI_VDEVICE(INTEL
, 0x292b), board_ahci_pi
}, /* ICH9M */
387 { PCI_VDEVICE(INTEL
, 0x292f), board_ahci_pi
}, /* ICH9M */
388 { PCI_VDEVICE(INTEL
, 0x294d), board_ahci_pi
}, /* ICH9 */
389 { PCI_VDEVICE(INTEL
, 0x294e), board_ahci_pi
}, /* ICH9M */
392 { PCI_VDEVICE(JMICRON
, 0x2360), board_ahci_ign_iferr
}, /* JMB360 */
393 { PCI_VDEVICE(JMICRON
, 0x2361), board_ahci_ign_iferr
}, /* JMB361 */
394 { PCI_VDEVICE(JMICRON
, 0x2363), board_ahci_ign_iferr
}, /* JMB363 */
395 { PCI_VDEVICE(JMICRON
, 0x2365), board_ahci_ign_iferr
}, /* JMB365 */
396 { PCI_VDEVICE(JMICRON
, 0x2366), board_ahci_ign_iferr
}, /* JMB366 */
399 { PCI_VDEVICE(ATI
, 0x4380), board_ahci
}, /* ATI SB600 non-raid */
400 { PCI_VDEVICE(ATI
, 0x4381), board_ahci
}, /* ATI SB600 raid */
403 { PCI_VDEVICE(VIA
, 0x3349), board_ahci_vt8251
}, /* VIA VT8251 */
406 { PCI_VDEVICE(NVIDIA
, 0x044c), board_ahci
}, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA
, 0x044d), board_ahci
}, /* MCP65 */
408 { PCI_VDEVICE(NVIDIA
, 0x044e), board_ahci
}, /* MCP65 */
409 { PCI_VDEVICE(NVIDIA
, 0x044f), board_ahci
}, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA
, 0x045c), board_ahci
}, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA
, 0x045d), board_ahci
}, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA
, 0x045e), board_ahci
}, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA
, 0x045f), board_ahci
}, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA
, 0x0550), board_ahci
}, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA
, 0x0551), board_ahci
}, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA
, 0x0552), board_ahci
}, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA
, 0x0553), board_ahci
}, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA
, 0x0554), board_ahci
}, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA
, 0x0555), board_ahci
}, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA
, 0x0556), board_ahci
}, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA
, 0x0557), board_ahci
}, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA
, 0x0558), board_ahci
}, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA
, 0x0559), board_ahci
}, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA
, 0x055a), board_ahci
}, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA
, 0x055b), board_ahci
}, /* MCP67 */
428 { PCI_VDEVICE(SI
, 0x1184), board_ahci
}, /* SiS 966 */
429 { PCI_VDEVICE(SI
, 0x1185), board_ahci
}, /* SiS 966 */
430 { PCI_VDEVICE(SI
, 0x0186), board_ahci
}, /* SiS 968 */
432 /* Generic, PCI class code for AHCI */
433 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
434 0x010601, 0xffffff, board_ahci
},
436 { } /* terminate list */
440 static struct pci_driver ahci_pci_driver
= {
442 .id_table
= ahci_pci_tbl
,
443 .probe
= ahci_init_one
,
444 .suspend
= ahci_pci_device_suspend
,
445 .resume
= ahci_pci_device_resume
,
446 .remove
= ahci_remove_one
,
450 static inline int ahci_nr_ports(u32 cap
)
452 return (cap
& 0x1f) + 1;
455 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
457 return base
+ 0x100 + (port
* 0x80);
460 static inline void __iomem
*ahci_port_base (void __iomem
*base
, unsigned int port
)
462 return (void __iomem
*) ahci_port_base_ul((unsigned long)base
, port
);
465 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
470 case SCR_STATUS
: sc_reg
= 0; break;
471 case SCR_CONTROL
: sc_reg
= 1; break;
472 case SCR_ERROR
: sc_reg
= 2; break;
473 case SCR_ACTIVE
: sc_reg
= 3; break;
478 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
482 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
488 case SCR_STATUS
: sc_reg
= 0; break;
489 case SCR_CONTROL
: sc_reg
= 1; break;
490 case SCR_ERROR
: sc_reg
= 2; break;
491 case SCR_ACTIVE
: sc_reg
= 3; break;
496 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
499 static void ahci_start_engine(void __iomem
*port_mmio
)
504 tmp
= readl(port_mmio
+ PORT_CMD
);
505 tmp
|= PORT_CMD_START
;
506 writel(tmp
, port_mmio
+ PORT_CMD
);
507 readl(port_mmio
+ PORT_CMD
); /* flush */
510 static int ahci_stop_engine(void __iomem
*port_mmio
)
514 tmp
= readl(port_mmio
+ PORT_CMD
);
516 /* check if the HBA is idle */
517 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
520 /* setting HBA to idle */
521 tmp
&= ~PORT_CMD_START
;
522 writel(tmp
, port_mmio
+ PORT_CMD
);
524 /* wait for engine to stop. This could be as long as 500 msec */
525 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
526 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
527 if (tmp
& PORT_CMD_LIST_ON
)
533 static void ahci_start_fis_rx(void __iomem
*port_mmio
, u32 cap
,
534 dma_addr_t cmd_slot_dma
, dma_addr_t rx_fis_dma
)
538 /* set FIS registers */
539 if (cap
& HOST_CAP_64
)
540 writel((cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
541 writel(cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
543 if (cap
& HOST_CAP_64
)
544 writel((rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
545 writel(rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
547 /* enable FIS reception */
548 tmp
= readl(port_mmio
+ PORT_CMD
);
549 tmp
|= PORT_CMD_FIS_RX
;
550 writel(tmp
, port_mmio
+ PORT_CMD
);
553 readl(port_mmio
+ PORT_CMD
);
556 static int ahci_stop_fis_rx(void __iomem
*port_mmio
)
560 /* disable FIS reception */
561 tmp
= readl(port_mmio
+ PORT_CMD
);
562 tmp
&= ~PORT_CMD_FIS_RX
;
563 writel(tmp
, port_mmio
+ PORT_CMD
);
565 /* wait for completion, spec says 500ms, give it 1000 */
566 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
567 PORT_CMD_FIS_ON
, 10, 1000);
568 if (tmp
& PORT_CMD_FIS_ON
)
574 static void ahci_power_up(void __iomem
*port_mmio
, u32 cap
)
578 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
581 if (cap
& HOST_CAP_SSS
) {
582 cmd
|= PORT_CMD_SPIN_UP
;
583 writel(cmd
, port_mmio
+ PORT_CMD
);
587 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
590 static void ahci_power_down(void __iomem
*port_mmio
, u32 cap
)
594 if (!(cap
& HOST_CAP_SSS
))
597 /* put device into listen mode, first set PxSCTL.DET to 0 */
598 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
600 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
602 /* then set PxCMD.SUD to 0 */
603 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
604 cmd
&= ~PORT_CMD_SPIN_UP
;
605 writel(cmd
, port_mmio
+ PORT_CMD
);
608 static void ahci_init_port(void __iomem
*port_mmio
, u32 cap
,
609 dma_addr_t cmd_slot_dma
, dma_addr_t rx_fis_dma
)
611 /* enable FIS reception */
612 ahci_start_fis_rx(port_mmio
, cap
, cmd_slot_dma
, rx_fis_dma
);
615 ahci_start_engine(port_mmio
);
618 static int ahci_deinit_port(void __iomem
*port_mmio
, u32 cap
, const char **emsg
)
623 rc
= ahci_stop_engine(port_mmio
);
625 *emsg
= "failed to stop engine";
629 /* disable FIS reception */
630 rc
= ahci_stop_fis_rx(port_mmio
);
632 *emsg
= "failed stop FIS RX";
639 static int ahci_reset_controller(void __iomem
*mmio
, struct pci_dev
*pdev
)
641 u32 cap_save
, impl_save
, tmp
;
643 cap_save
= readl(mmio
+ HOST_CAP
);
644 impl_save
= readl(mmio
+ HOST_PORTS_IMPL
);
646 /* global controller reset */
647 tmp
= readl(mmio
+ HOST_CTL
);
648 if ((tmp
& HOST_RESET
) == 0) {
649 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
650 readl(mmio
+ HOST_CTL
); /* flush */
653 /* reset must complete within 1 second, or
654 * the hardware should be considered fried.
658 tmp
= readl(mmio
+ HOST_CTL
);
659 if (tmp
& HOST_RESET
) {
660 dev_printk(KERN_ERR
, &pdev
->dev
,
661 "controller reset failed (0x%x)\n", tmp
);
665 /* turn on AHCI mode */
666 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
667 (void) readl(mmio
+ HOST_CTL
); /* flush */
669 /* These write-once registers are normally cleared on reset.
670 * Restore BIOS values... which we HOPE were present before
674 impl_save
= (1 << ahci_nr_ports(cap_save
)) - 1;
675 dev_printk(KERN_WARNING
, &pdev
->dev
,
676 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save
);
678 writel(cap_save
, mmio
+ HOST_CAP
);
679 writel(impl_save
, mmio
+ HOST_PORTS_IMPL
);
680 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
682 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
686 pci_read_config_word(pdev
, 0x92, &tmp16
);
688 pci_write_config_word(pdev
, 0x92, tmp16
);
694 static void ahci_init_controller(void __iomem
*mmio
, struct pci_dev
*pdev
,
695 int n_ports
, unsigned int port_flags
,
696 struct ahci_host_priv
*hpriv
)
701 for (i
= 0; i
< n_ports
; i
++) {
702 void __iomem
*port_mmio
= ahci_port_base(mmio
, i
);
703 const char *emsg
= NULL
;
705 if ((port_flags
& AHCI_FLAG_HONOR_PI
) &&
706 !(hpriv
->port_map
& (1 << i
)))
709 /* make sure port is not active */
710 rc
= ahci_deinit_port(port_mmio
, hpriv
->cap
, &emsg
);
712 dev_printk(KERN_WARNING
, &pdev
->dev
,
713 "%s (%d)\n", emsg
, rc
);
716 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
717 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
718 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
721 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
722 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
724 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
726 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
729 tmp
= readl(mmio
+ HOST_CTL
);
730 VPRINTK("HOST_CTL 0x%x\n", tmp
);
731 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
732 tmp
= readl(mmio
+ HOST_CTL
);
733 VPRINTK("HOST_CTL 0x%x\n", tmp
);
736 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
738 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
739 struct ata_taskfile tf
;
742 tmp
= readl(port_mmio
+ PORT_SIG
);
743 tf
.lbah
= (tmp
>> 24) & 0xff;
744 tf
.lbam
= (tmp
>> 16) & 0xff;
745 tf
.lbal
= (tmp
>> 8) & 0xff;
746 tf
.nsect
= (tmp
) & 0xff;
748 return ata_dev_classify(&tf
);
751 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
754 dma_addr_t cmd_tbl_dma
;
756 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
758 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
759 pp
->cmd_slot
[tag
].status
= 0;
760 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
761 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
764 static int ahci_clo(struct ata_port
*ap
)
766 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
767 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
770 if (!(hpriv
->cap
& HOST_CAP_CLO
))
773 tmp
= readl(port_mmio
+ PORT_CMD
);
775 writel(tmp
, port_mmio
+ PORT_CMD
);
777 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
778 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
779 if (tmp
& PORT_CMD_CLO
)
785 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class)
787 struct ahci_port_priv
*pp
= ap
->private_data
;
788 void __iomem
*mmio
= ap
->host
->mmio_base
;
789 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
790 const u32 cmd_fis_len
= 5; /* five dwords */
791 const char *reason
= NULL
;
792 struct ata_taskfile tf
;
799 if (ata_port_offline(ap
)) {
800 DPRINTK("PHY reports no device\n");
801 *class = ATA_DEV_NONE
;
805 /* prepare for SRST (AHCI-1.1 10.4.1) */
806 rc
= ahci_stop_engine(port_mmio
);
808 reason
= "failed to stop engine";
812 /* check BUSY/DRQ, perform Command List Override if necessary */
813 if (ahci_check_status(ap
) & (ATA_BUSY
| ATA_DRQ
)) {
816 if (rc
== -EOPNOTSUPP
) {
817 reason
= "port busy but CLO unavailable";
820 reason
= "port busy but CLO failed";
826 ahci_start_engine(port_mmio
);
828 ata_tf_init(ap
->device
, &tf
);
831 /* issue the first D2H Register FIS */
832 ahci_fill_cmd_slot(pp
, 0,
833 cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
836 ata_tf_to_fis(&tf
, fis
, 0);
837 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
839 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
841 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
844 reason
= "1st FIS failed";
848 /* spec says at least 5us, but be generous and sleep for 1ms */
851 /* issue the second D2H Register FIS */
852 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
);
855 ata_tf_to_fis(&tf
, fis
, 0);
856 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
858 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
859 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
861 /* spec mandates ">= 2ms" before checking status.
862 * We wait 150ms, because that was the magic delay used for
863 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
864 * between when the ATA command register is written, and then
865 * status is checked. Because waiting for "a while" before
866 * checking status is fine, post SRST, we perform this magic
867 * delay here as well.
871 *class = ATA_DEV_NONE
;
872 if (ata_port_online(ap
)) {
873 if (ata_busy_sleep(ap
, ATA_TMOUT_BOOT_QUICK
, ATA_TMOUT_BOOT
)) {
875 reason
= "device not ready";
878 *class = ahci_dev_classify(ap
);
881 DPRINTK("EXIT, class=%u\n", *class);
885 ahci_start_engine(port_mmio
);
887 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
891 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class)
893 struct ahci_port_priv
*pp
= ap
->private_data
;
894 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
895 struct ata_taskfile tf
;
896 void __iomem
*mmio
= ap
->host
->mmio_base
;
897 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
902 ahci_stop_engine(port_mmio
);
904 /* clear D2H reception area to properly wait for D2H FIS */
905 ata_tf_init(ap
->device
, &tf
);
907 ata_tf_to_fis(&tf
, d2h_fis
, 0);
909 rc
= sata_std_hardreset(ap
, class);
911 ahci_start_engine(port_mmio
);
913 if (rc
== 0 && ata_port_online(ap
))
914 *class = ahci_dev_classify(ap
);
915 if (*class == ATA_DEV_UNKNOWN
)
916 *class = ATA_DEV_NONE
;
918 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
922 static int ahci_vt8251_hardreset(struct ata_port
*ap
, unsigned int *class)
924 void __iomem
*mmio
= ap
->host
->mmio_base
;
925 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
930 ahci_stop_engine(port_mmio
);
932 rc
= sata_port_hardreset(ap
, sata_ehc_deb_timing(&ap
->eh_context
));
934 /* vt8251 needs SError cleared for the port to operate */
935 ahci_scr_write(ap
, SCR_ERROR
, ahci_scr_read(ap
, SCR_ERROR
));
937 ahci_start_engine(port_mmio
);
939 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
941 /* vt8251 doesn't clear BSY on signature FIS reception,
942 * request follow-up softreset.
944 return rc
?: -EAGAIN
;
947 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
949 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
952 ata_std_postreset(ap
, class);
954 /* Make sure port's ATAPI bit is set appropriately */
955 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
956 if (*class == ATA_DEV_ATAPI
)
957 new_tmp
|= PORT_CMD_ATAPI
;
959 new_tmp
&= ~PORT_CMD_ATAPI
;
960 if (new_tmp
!= tmp
) {
961 writel(new_tmp
, port_mmio
+ PORT_CMD
);
962 readl(port_mmio
+ PORT_CMD
); /* flush */
966 static u8
ahci_check_status(struct ata_port
*ap
)
968 void __iomem
*mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
970 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
973 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
975 struct ahci_port_priv
*pp
= ap
->private_data
;
976 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
978 ata_tf_from_fis(d2h_fis
, tf
);
981 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
983 struct scatterlist
*sg
;
984 struct ahci_sg
*ahci_sg
;
985 unsigned int n_sg
= 0;
990 * Next, the S/G list.
992 ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
993 ata_for_each_sg(sg
, qc
) {
994 dma_addr_t addr
= sg_dma_address(sg
);
995 u32 sg_len
= sg_dma_len(sg
);
997 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
998 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
999 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
1008 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1010 struct ata_port
*ap
= qc
->ap
;
1011 struct ahci_port_priv
*pp
= ap
->private_data
;
1012 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
1015 const u32 cmd_fis_len
= 5; /* five dwords */
1016 unsigned int n_elem
;
1019 * Fill in command table information. First, the header,
1020 * a SATA Register - Host to Device command FIS.
1022 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1024 ata_tf_to_fis(&qc
->tf
, cmd_tbl
, 0);
1026 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1027 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1031 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1032 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1035 * Fill in command slot information.
1037 opts
= cmd_fis_len
| n_elem
<< 16;
1038 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1039 opts
|= AHCI_CMD_WRITE
;
1041 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1043 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1046 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1048 struct ahci_port_priv
*pp
= ap
->private_data
;
1049 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1050 unsigned int err_mask
= 0, action
= 0;
1051 struct ata_queued_cmd
*qc
;
1054 ata_ehi_clear_desc(ehi
);
1056 /* AHCI needs SError cleared; otherwise, it might lock up */
1057 serror
= ahci_scr_read(ap
, SCR_ERROR
);
1058 ahci_scr_write(ap
, SCR_ERROR
, serror
);
1060 /* analyze @irq_stat */
1061 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
1063 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1064 if (ap
->flags
& AHCI_FLAG_IGN_IRQ_IF_ERR
)
1065 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1067 if (irq_stat
& PORT_IRQ_TF_ERR
)
1068 err_mask
|= AC_ERR_DEV
;
1070 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1071 err_mask
|= AC_ERR_HOST_BUS
;
1072 action
|= ATA_EH_SOFTRESET
;
1075 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1076 err_mask
|= AC_ERR_ATA_BUS
;
1077 action
|= ATA_EH_SOFTRESET
;
1078 ata_ehi_push_desc(ehi
, ", interface fatal error");
1081 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1082 ata_ehi_hotplugged(ehi
);
1083 ata_ehi_push_desc(ehi
, ", %s", irq_stat
& PORT_IRQ_CONNECT
?
1084 "connection status changed" : "PHY RDY changed");
1087 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1088 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1090 err_mask
|= AC_ERR_HSM
;
1091 action
|= ATA_EH_SOFTRESET
;
1092 ata_ehi_push_desc(ehi
, ", unknown FIS %08x %08x %08x %08x",
1093 unk
[0], unk
[1], unk
[2], unk
[3]);
1096 /* okay, let's hand over to EH */
1097 ehi
->serror
|= serror
;
1098 ehi
->action
|= action
;
1100 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1102 qc
->err_mask
|= err_mask
;
1104 ehi
->err_mask
|= err_mask
;
1106 if (irq_stat
& PORT_IRQ_FREEZE
)
1107 ata_port_freeze(ap
);
1112 static void ahci_host_intr(struct ata_port
*ap
)
1114 void __iomem
*mmio
= ap
->host
->mmio_base
;
1115 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1116 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1117 struct ahci_port_priv
*pp
= ap
->private_data
;
1118 u32 status
, qc_active
;
1119 int rc
, known_irq
= 0;
1121 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1122 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1124 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1125 ahci_error_intr(ap
, status
);
1130 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1132 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1134 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
1138 ehi
->err_mask
|= AC_ERR_HSM
;
1139 ehi
->action
|= ATA_EH_SOFTRESET
;
1140 ata_port_freeze(ap
);
1144 /* hmmm... a spurious interupt */
1146 /* if !NCQ, ignore. No modern ATA device has broken HSM
1147 * implementation for non-NCQ commands.
1152 if (status
& PORT_IRQ_D2H_REG_FIS
) {
1153 if (!pp
->ncq_saw_d2h
)
1154 ata_port_printk(ap
, KERN_INFO
,
1155 "D2H reg with I during NCQ, "
1156 "this message won't be printed again\n");
1157 pp
->ncq_saw_d2h
= 1;
1161 if (status
& PORT_IRQ_DMAS_FIS
) {
1162 if (!pp
->ncq_saw_dmas
)
1163 ata_port_printk(ap
, KERN_INFO
,
1164 "DMAS FIS during NCQ, "
1165 "this message won't be printed again\n");
1166 pp
->ncq_saw_dmas
= 1;
1170 if (status
& PORT_IRQ_SDB_FIS
&&
1171 pp
->ncq_saw_spurious_sdb_cnt
< 10) {
1172 /* SDB FIS containing spurious completions might be
1173 * dangerous, we need to know more about them. Print
1176 const u32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1178 ata_port_printk(ap
, KERN_INFO
, "Spurious SDB FIS during NCQ "
1179 "issue=0x%x SAct=0x%x FIS=%08x:%08x%s\n",
1180 readl(port_mmio
+ PORT_CMD_ISSUE
),
1181 readl(port_mmio
+ PORT_SCR_ACT
),
1182 le32_to_cpu(f
[0]), le32_to_cpu(f
[1]),
1183 pp
->ncq_saw_spurious_sdb_cnt
< 10 ?
1184 "" : ", shutting up");
1186 pp
->ncq_saw_spurious_sdb_cnt
++;
1191 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
1192 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1193 status
, ap
->active_tag
, ap
->sactive
);
1196 static void ahci_irq_clear(struct ata_port
*ap
)
1201 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1203 struct ata_host
*host
= dev_instance
;
1204 struct ahci_host_priv
*hpriv
;
1205 unsigned int i
, handled
= 0;
1207 u32 irq_stat
, irq_ack
= 0;
1211 hpriv
= host
->private_data
;
1212 mmio
= host
->mmio_base
;
1214 /* sigh. 0xffffffff is a valid return from h/w */
1215 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1216 irq_stat
&= hpriv
->port_map
;
1220 spin_lock(&host
->lock
);
1222 for (i
= 0; i
< host
->n_ports
; i
++) {
1223 struct ata_port
*ap
;
1225 if (!(irq_stat
& (1 << i
)))
1228 ap
= host
->ports
[i
];
1231 VPRINTK("port %u\n", i
);
1233 VPRINTK("port %u (no irq)\n", i
);
1234 if (ata_ratelimit())
1235 dev_printk(KERN_WARNING
, host
->dev
,
1236 "interrupt on disabled port %u\n", i
);
1239 irq_ack
|= (1 << i
);
1243 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1247 spin_unlock(&host
->lock
);
1251 return IRQ_RETVAL(handled
);
1254 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1256 struct ata_port
*ap
= qc
->ap
;
1257 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
1259 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1260 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1261 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1262 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1267 static void ahci_freeze(struct ata_port
*ap
)
1269 void __iomem
*mmio
= ap
->host
->mmio_base
;
1270 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1273 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1276 static void ahci_thaw(struct ata_port
*ap
)
1278 void __iomem
*mmio
= ap
->host
->mmio_base
;
1279 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1283 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1284 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1285 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1287 /* turn IRQ back on */
1288 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1291 static void ahci_error_handler(struct ata_port
*ap
)
1293 void __iomem
*mmio
= ap
->host
->mmio_base
;
1294 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1296 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1297 /* restart engine */
1298 ahci_stop_engine(port_mmio
);
1299 ahci_start_engine(port_mmio
);
1302 /* perform recovery */
1303 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_hardreset
,
1307 static void ahci_vt8251_error_handler(struct ata_port
*ap
)
1309 void __iomem
*mmio
= ap
->host
->mmio_base
;
1310 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1312 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1313 /* restart engine */
1314 ahci_stop_engine(port_mmio
);
1315 ahci_start_engine(port_mmio
);
1318 /* perform recovery */
1319 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_vt8251_hardreset
,
1323 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1325 struct ata_port
*ap
= qc
->ap
;
1326 void __iomem
*mmio
= ap
->host
->mmio_base
;
1327 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1329 if (qc
->flags
& ATA_QCFLAG_FAILED
)
1330 qc
->err_mask
|= AC_ERR_OTHER
;
1333 /* make DMA engine forget about the failed command */
1334 ahci_stop_engine(port_mmio
);
1335 ahci_start_engine(port_mmio
);
1339 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
1341 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1342 struct ahci_port_priv
*pp
= ap
->private_data
;
1343 void __iomem
*mmio
= ap
->host
->mmio_base
;
1344 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1345 const char *emsg
= NULL
;
1348 rc
= ahci_deinit_port(port_mmio
, hpriv
->cap
, &emsg
);
1350 ahci_power_down(port_mmio
, hpriv
->cap
);
1352 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
1353 ahci_init_port(port_mmio
, hpriv
->cap
,
1354 pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1360 static int ahci_port_resume(struct ata_port
*ap
)
1362 struct ahci_port_priv
*pp
= ap
->private_data
;
1363 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1364 void __iomem
*mmio
= ap
->host
->mmio_base
;
1365 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1367 ahci_power_up(port_mmio
, hpriv
->cap
);
1368 ahci_init_port(port_mmio
, hpriv
->cap
, pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1373 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1375 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1376 void __iomem
*mmio
= host
->mmio_base
;
1379 if (mesg
.event
== PM_EVENT_SUSPEND
) {
1380 /* AHCI spec rev1.1 section 8.3.3:
1381 * Software must disable interrupts prior to requesting a
1382 * transition of the HBA to D3 state.
1384 ctl
= readl(mmio
+ HOST_CTL
);
1385 ctl
&= ~HOST_IRQ_EN
;
1386 writel(ctl
, mmio
+ HOST_CTL
);
1387 readl(mmio
+ HOST_CTL
); /* flush */
1390 return ata_pci_device_suspend(pdev
, mesg
);
1393 static int ahci_pci_device_resume(struct pci_dev
*pdev
)
1395 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1396 struct ahci_host_priv
*hpriv
= host
->private_data
;
1397 void __iomem
*mmio
= host
->mmio_base
;
1400 ata_pci_device_do_resume(pdev
);
1402 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
1403 rc
= ahci_reset_controller(mmio
, pdev
);
1407 ahci_init_controller(mmio
, pdev
, host
->n_ports
,
1408 host
->ports
[0]->flags
, hpriv
);
1411 ata_host_resume(host
);
1416 static int ahci_port_start(struct ata_port
*ap
)
1418 struct device
*dev
= ap
->host
->dev
;
1419 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1420 struct ahci_port_priv
*pp
;
1421 void __iomem
*mmio
= ap
->host
->mmio_base
;
1422 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1427 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
1430 memset(pp
, 0, sizeof(*pp
));
1432 rc
= ata_pad_alloc(ap
, dev
);
1438 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
1440 ata_pad_free(ap
, dev
);
1444 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
1447 * First item in chunk of DMA memory: 32-slot command table,
1448 * 32 bytes each in size
1451 pp
->cmd_slot_dma
= mem_dma
;
1453 mem
+= AHCI_CMD_SLOT_SZ
;
1454 mem_dma
+= AHCI_CMD_SLOT_SZ
;
1457 * Second item: Received-FIS area
1460 pp
->rx_fis_dma
= mem_dma
;
1462 mem
+= AHCI_RX_FIS_SZ
;
1463 mem_dma
+= AHCI_RX_FIS_SZ
;
1466 * Third item: data area for storing a single command
1467 * and its scatter-gather table
1470 pp
->cmd_tbl_dma
= mem_dma
;
1472 ap
->private_data
= pp
;
1475 ahci_power_up(port_mmio
, hpriv
->cap
);
1477 /* initialize port */
1478 ahci_init_port(port_mmio
, hpriv
->cap
, pp
->cmd_slot_dma
, pp
->rx_fis_dma
);
1483 static void ahci_port_stop(struct ata_port
*ap
)
1485 struct device
*dev
= ap
->host
->dev
;
1486 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
1487 struct ahci_port_priv
*pp
= ap
->private_data
;
1488 void __iomem
*mmio
= ap
->host
->mmio_base
;
1489 void __iomem
*port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
1490 const char *emsg
= NULL
;
1493 /* de-initialize port */
1494 rc
= ahci_deinit_port(port_mmio
, hpriv
->cap
, &emsg
);
1496 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
1498 ap
->private_data
= NULL
;
1499 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
1500 pp
->cmd_slot
, pp
->cmd_slot_dma
);
1501 ata_pad_free(ap
, dev
);
1505 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
1506 unsigned int port_idx
)
1508 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
1509 base
= ahci_port_base_ul(base
, port_idx
);
1510 VPRINTK("base now==0x%lx\n", base
);
1512 port
->cmd_addr
= base
;
1513 port
->scr_addr
= base
+ PORT_SCR
;
1518 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
1520 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1521 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1522 void __iomem
*mmio
= probe_ent
->mmio_base
;
1523 unsigned int i
, cap_n_ports
, using_dac
;
1526 rc
= ahci_reset_controller(mmio
, pdev
);
1530 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
1531 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
1532 cap_n_ports
= ahci_nr_ports(hpriv
->cap
);
1534 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1535 hpriv
->cap
, hpriv
->port_map
, cap_n_ports
);
1537 if (probe_ent
->port_flags
& AHCI_FLAG_HONOR_PI
) {
1538 unsigned int n_ports
= cap_n_ports
;
1539 u32 port_map
= hpriv
->port_map
;
1542 for (i
= 0; i
< AHCI_MAX_PORTS
&& n_ports
; i
++) {
1543 if (port_map
& (1 << i
)) {
1545 port_map
&= ~(1 << i
);
1548 probe_ent
->dummy_port_mask
|= 1 << i
;
1551 if (n_ports
|| port_map
)
1552 dev_printk(KERN_WARNING
, &pdev
->dev
,
1553 "nr_ports (%u) and implemented port map "
1554 "(0x%x) don't match\n",
1555 cap_n_ports
, hpriv
->port_map
);
1557 probe_ent
->n_ports
= max_port
+ 1;
1559 probe_ent
->n_ports
= cap_n_ports
;
1561 using_dac
= hpriv
->cap
& HOST_CAP_64
;
1563 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1564 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1566 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1568 dev_printk(KERN_ERR
, &pdev
->dev
,
1569 "64-bit DMA enable failed\n");
1574 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1576 dev_printk(KERN_ERR
, &pdev
->dev
,
1577 "32-bit DMA enable failed\n");
1580 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1582 dev_printk(KERN_ERR
, &pdev
->dev
,
1583 "32-bit consistent DMA enable failed\n");
1588 for (i
= 0; i
< probe_ent
->n_ports
; i
++)
1589 ahci_setup_port(&probe_ent
->port
[i
], (unsigned long) mmio
, i
);
1591 ahci_init_controller(mmio
, pdev
, probe_ent
->n_ports
,
1592 probe_ent
->port_flags
, hpriv
);
1594 pci_set_master(pdev
);
1599 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
1601 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
1602 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
1603 void __iomem
*mmio
= probe_ent
->mmio_base
;
1604 u32 vers
, cap
, impl
, speed
;
1605 const char *speed_s
;
1609 vers
= readl(mmio
+ HOST_VERSION
);
1611 impl
= hpriv
->port_map
;
1613 speed
= (cap
>> 20) & 0xf;
1616 else if (speed
== 2)
1621 pci_read_config_word(pdev
, 0x0a, &cc
);
1624 else if (cc
== 0x0106)
1626 else if (cc
== 0x0104)
1631 dev_printk(KERN_INFO
, &pdev
->dev
,
1632 "AHCI %02x%02x.%02x%02x "
1633 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1636 (vers
>> 24) & 0xff,
1637 (vers
>> 16) & 0xff,
1641 ((cap
>> 8) & 0x1f) + 1,
1647 dev_printk(KERN_INFO
, &pdev
->dev
,
1653 cap
& (1 << 31) ? "64bit " : "",
1654 cap
& (1 << 30) ? "ncq " : "",
1655 cap
& (1 << 28) ? "ilck " : "",
1656 cap
& (1 << 27) ? "stag " : "",
1657 cap
& (1 << 26) ? "pm " : "",
1658 cap
& (1 << 25) ? "led " : "",
1660 cap
& (1 << 24) ? "clo " : "",
1661 cap
& (1 << 19) ? "nz " : "",
1662 cap
& (1 << 18) ? "only " : "",
1663 cap
& (1 << 17) ? "pmp " : "",
1664 cap
& (1 << 15) ? "pio " : "",
1665 cap
& (1 << 14) ? "slum " : "",
1666 cap
& (1 << 13) ? "part " : ""
1670 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1672 static int printed_version
;
1673 struct ata_probe_ent
*probe_ent
= NULL
;
1674 struct ahci_host_priv
*hpriv
;
1676 void __iomem
*mmio_base
;
1677 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1678 int have_msi
, pci_dev_busy
= 0;
1683 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
1685 if (!printed_version
++)
1686 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1688 /* JMicron-specific fixup: make sure we're in AHCI mode */
1689 /* This is protected from races with ata_jmicron by the pci probe
1691 if (pdev
->vendor
== PCI_VENDOR_ID_JMICRON
) {
1692 /* AHCI enable, AHCI on function 0 */
1693 pci_write_config_byte(pdev
, 0x41, 0xa1);
1694 /* Function 1 is the PATA controller */
1695 if (PCI_FUNC(pdev
->devfn
))
1699 rc
= pci_enable_device(pdev
);
1703 rc
= pci_request_regions(pdev
, DRV_NAME
);
1709 if (pci_enable_msi(pdev
) == 0)
1716 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1717 if (probe_ent
== NULL
) {
1722 memset(probe_ent
, 0, sizeof(*probe_ent
));
1723 probe_ent
->dev
= pci_dev_to_dev(pdev
);
1724 INIT_LIST_HEAD(&probe_ent
->node
);
1726 mmio_base
= pci_iomap(pdev
, AHCI_PCI_BAR
, 0);
1727 if (mmio_base
== NULL
) {
1729 goto err_out_free_ent
;
1731 base
= (unsigned long) mmio_base
;
1733 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1736 goto err_out_iounmap
;
1738 memset(hpriv
, 0, sizeof(*hpriv
));
1740 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1741 probe_ent
->port_flags
= ahci_port_info
[board_idx
].flags
;
1742 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1743 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1744 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1746 probe_ent
->irq
= pdev
->irq
;
1747 probe_ent
->irq_flags
= IRQF_SHARED
;
1748 probe_ent
->mmio_base
= mmio_base
;
1749 probe_ent
->private_data
= hpriv
;
1752 hpriv
->flags
|= AHCI_FLAG_MSI
;
1754 /* initialize adapter */
1755 rc
= ahci_host_init(probe_ent
);
1759 if (!(probe_ent
->port_flags
& AHCI_FLAG_NO_NCQ
) &&
1760 (hpriv
->cap
& HOST_CAP_NCQ
))
1761 probe_ent
->port_flags
|= ATA_FLAG_NCQ
;
1763 ahci_print_info(probe_ent
);
1765 /* FIXME: check ata_device_add return value */
1766 ata_device_add(probe_ent
);
1774 pci_iounmap(pdev
, mmio_base
);
1779 pci_disable_msi(pdev
);
1782 pci_release_regions(pdev
);
1785 pci_disable_device(pdev
);
1789 static void ahci_remove_one (struct pci_dev
*pdev
)
1791 struct device
*dev
= pci_dev_to_dev(pdev
);
1792 struct ata_host
*host
= dev_get_drvdata(dev
);
1793 struct ahci_host_priv
*hpriv
= host
->private_data
;
1797 for (i
= 0; i
< host
->n_ports
; i
++)
1798 ata_port_detach(host
->ports
[i
]);
1800 have_msi
= hpriv
->flags
& AHCI_FLAG_MSI
;
1801 free_irq(host
->irq
, host
);
1803 for (i
= 0; i
< host
->n_ports
; i
++) {
1804 struct ata_port
*ap
= host
->ports
[i
];
1806 ata_scsi_release(ap
->scsi_host
);
1807 scsi_host_put(ap
->scsi_host
);
1811 pci_iounmap(pdev
, host
->mmio_base
);
1815 pci_disable_msi(pdev
);
1818 pci_release_regions(pdev
);
1819 pci_disable_device(pdev
);
1820 dev_set_drvdata(dev
, NULL
);
1823 static int __init
ahci_init(void)
1825 return pci_register_driver(&ahci_pci_driver
);
1828 static void __exit
ahci_exit(void)
1830 pci_unregister_driver(&ahci_pci_driver
);
1834 MODULE_AUTHOR("Jeff Garzik");
1835 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1836 MODULE_LICENSE("GPL");
1837 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1838 MODULE_VERSION(DRV_VERSION
);
1840 module_init(ahci_init
);
1841 module_exit(ahci_exit
);