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ahci: Store interrupt value
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83 board_ahci_sb600 = 4,
84 board_ahci_mv = 5,
85
86 /* global controller registers */
87 HOST_CAP = 0x00, /* host capabilities */
88 HOST_CTL = 0x04, /* global host control */
89 HOST_IRQ_STAT = 0x08, /* interrupt status */
90 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
91 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92
93 /* HOST_CTL bits */
94 HOST_RESET = (1 << 0), /* reset controller; self-clear */
95 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
96 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97
98 /* HOST_CAP bits */
99 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
122
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
144 PORT_IRQ_IF_ERR |
145 PORT_IRQ_CONNECT |
146 PORT_IRQ_PHYRDY |
147 PORT_IRQ_UNK_FIS,
148 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_TF_ERR |
150 PORT_IRQ_HBUS_DATA_ERR,
151 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
152 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
153 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154
155 /* PORT_CMD bits */
156 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
157 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
158 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
159 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
160 PORT_CMD_CLO = (1 << 3), /* Command list override */
161 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
162 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
163 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164
165 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
166 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
167 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
168 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
169
170 /* ap->flags bits */
171 AHCI_FLAG_NO_NCQ = (1 << 24),
172 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
173 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
174 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
175 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
176 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
177 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
178 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
179
180 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
181 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
182 ATA_FLAG_ACPI_SATA,
183 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
184 };
185
186 struct ahci_cmd_hdr {
187 u32 opts;
188 u32 status;
189 u32 tbl_addr;
190 u32 tbl_addr_hi;
191 u32 reserved[4];
192 };
193
194 struct ahci_sg {
195 u32 addr;
196 u32 addr_hi;
197 u32 reserved;
198 u32 flags_size;
199 };
200
201 struct ahci_host_priv {
202 u32 cap; /* cap to use */
203 u32 port_map; /* port map to use */
204 u32 saved_cap; /* saved initial cap */
205 u32 saved_port_map; /* saved initial port_map */
206 };
207
208 struct ahci_port_priv {
209 struct ahci_cmd_hdr *cmd_slot;
210 dma_addr_t cmd_slot_dma;
211 void *cmd_tbl;
212 dma_addr_t cmd_tbl_dma;
213 void *rx_fis;
214 dma_addr_t rx_fis_dma;
215 /* for NCQ spurious interrupt analysis */
216 unsigned int ncq_saw_d2h:1;
217 unsigned int ncq_saw_dmas:1;
218 unsigned int ncq_saw_sdb:1;
219 u32 intr_mask; /* interrupts to enable */
220 };
221
222 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
223 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
224 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
225 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
226 static void ahci_irq_clear(struct ata_port *ap);
227 static int ahci_port_start(struct ata_port *ap);
228 static void ahci_port_stop(struct ata_port *ap);
229 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
230 static void ahci_qc_prep(struct ata_queued_cmd *qc);
231 static u8 ahci_check_status(struct ata_port *ap);
232 static void ahci_freeze(struct ata_port *ap);
233 static void ahci_thaw(struct ata_port *ap);
234 static void ahci_error_handler(struct ata_port *ap);
235 static void ahci_vt8251_error_handler(struct ata_port *ap);
236 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
237 static int ahci_port_resume(struct ata_port *ap);
238 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
239 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
240 u32 opts);
241 #ifdef CONFIG_PM
242 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
243 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
244 static int ahci_pci_device_resume(struct pci_dev *pdev);
245 #endif
246
247 static struct scsi_host_template ahci_sht = {
248 .module = THIS_MODULE,
249 .name = DRV_NAME,
250 .ioctl = ata_scsi_ioctl,
251 .queuecommand = ata_scsi_queuecmd,
252 .change_queue_depth = ata_scsi_change_queue_depth,
253 .can_queue = AHCI_MAX_CMDS - 1,
254 .this_id = ATA_SHT_THIS_ID,
255 .sg_tablesize = AHCI_MAX_SG,
256 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
257 .emulated = ATA_SHT_EMULATED,
258 .use_clustering = AHCI_USE_CLUSTERING,
259 .proc_name = DRV_NAME,
260 .dma_boundary = AHCI_DMA_BOUNDARY,
261 .slave_configure = ata_scsi_slave_config,
262 .slave_destroy = ata_scsi_slave_destroy,
263 .bios_param = ata_std_bios_param,
264 };
265
266 static const struct ata_port_operations ahci_ops = {
267 .port_disable = ata_port_disable,
268
269 .check_status = ahci_check_status,
270 .check_altstatus = ahci_check_status,
271 .dev_select = ata_noop_dev_select,
272
273 .tf_read = ahci_tf_read,
274
275 .qc_prep = ahci_qc_prep,
276 .qc_issue = ahci_qc_issue,
277
278 .irq_clear = ahci_irq_clear,
279 .irq_on = ata_dummy_irq_on,
280 .irq_ack = ata_dummy_irq_ack,
281
282 .scr_read = ahci_scr_read,
283 .scr_write = ahci_scr_write,
284
285 .freeze = ahci_freeze,
286 .thaw = ahci_thaw,
287
288 .error_handler = ahci_error_handler,
289 .post_internal_cmd = ahci_post_internal_cmd,
290
291 #ifdef CONFIG_PM
292 .port_suspend = ahci_port_suspend,
293 .port_resume = ahci_port_resume,
294 #endif
295
296 .port_start = ahci_port_start,
297 .port_stop = ahci_port_stop,
298 };
299
300 static const struct ata_port_operations ahci_vt8251_ops = {
301 .port_disable = ata_port_disable,
302
303 .check_status = ahci_check_status,
304 .check_altstatus = ahci_check_status,
305 .dev_select = ata_noop_dev_select,
306
307 .tf_read = ahci_tf_read,
308
309 .qc_prep = ahci_qc_prep,
310 .qc_issue = ahci_qc_issue,
311
312 .irq_clear = ahci_irq_clear,
313 .irq_on = ata_dummy_irq_on,
314 .irq_ack = ata_dummy_irq_ack,
315
316 .scr_read = ahci_scr_read,
317 .scr_write = ahci_scr_write,
318
319 .freeze = ahci_freeze,
320 .thaw = ahci_thaw,
321
322 .error_handler = ahci_vt8251_error_handler,
323 .post_internal_cmd = ahci_post_internal_cmd,
324
325 #ifdef CONFIG_PM
326 .port_suspend = ahci_port_suspend,
327 .port_resume = ahci_port_resume,
328 #endif
329
330 .port_start = ahci_port_start,
331 .port_stop = ahci_port_stop,
332 };
333
334 static const struct ata_port_info ahci_port_info[] = {
335 /* board_ahci */
336 {
337 .flags = AHCI_FLAG_COMMON,
338 .link_flags = AHCI_LFLAG_COMMON,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = ATA_UDMA6,
341 .port_ops = &ahci_ops,
342 },
343 /* board_ahci_pi */
344 {
345 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
346 .link_flags = AHCI_LFLAG_COMMON,
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = ATA_UDMA6,
349 .port_ops = &ahci_ops,
350 },
351 /* board_ahci_vt8251 */
352 {
353 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
354 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
355 .pio_mask = 0x1f, /* pio0-4 */
356 .udma_mask = ATA_UDMA6,
357 .port_ops = &ahci_vt8251_ops,
358 },
359 /* board_ahci_ign_iferr */
360 {
361 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
362 .link_flags = AHCI_LFLAG_COMMON,
363 .pio_mask = 0x1f, /* pio0-4 */
364 .udma_mask = ATA_UDMA6,
365 .port_ops = &ahci_ops,
366 },
367 /* board_ahci_sb600 */
368 {
369 .flags = AHCI_FLAG_COMMON |
370 AHCI_FLAG_IGN_SERR_INTERNAL |
371 AHCI_FLAG_32BIT_ONLY,
372 .link_flags = AHCI_LFLAG_COMMON,
373 .pio_mask = 0x1f, /* pio0-4 */
374 .udma_mask = ATA_UDMA6,
375 .port_ops = &ahci_ops,
376 },
377 /* board_ahci_mv */
378 {
379 .sht = &ahci_sht,
380 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
381 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
382 AHCI_FLAG_HONOR_PI | AHCI_FLAG_NO_NCQ |
383 AHCI_FLAG_NO_MSI | AHCI_FLAG_MV_PATA,
384 .link_flags = AHCI_LFLAG_COMMON,
385 .pio_mask = 0x1f, /* pio0-4 */
386 .udma_mask = ATA_UDMA6,
387 .port_ops = &ahci_ops,
388 },
389 };
390
391 static const struct pci_device_id ahci_pci_tbl[] = {
392 /* Intel */
393 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
394 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
395 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
396 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
397 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
398 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
399 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
400 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
401 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
402 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
403 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
404 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
405 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
406 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
407 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
408 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
409 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
410 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
411 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
412 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
413 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
414 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
415 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
416 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
417 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
418 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
420
421 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
422 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
423 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
424
425 /* ATI */
426 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
427 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
428 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
429 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
430 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
431 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
432 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
433
434 /* VIA */
435 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
436 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
437
438 /* NVIDIA */
439 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
440 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
441 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
442 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
443 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
444 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
445 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
446 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
447 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
448 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
449 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
450 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
451 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
452 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
453 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
454 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
455 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
456 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
457 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
467 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
468 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
469 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
479 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
480 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
481 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
483
484 /* SiS */
485 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
486 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
487 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
488
489 /* Marvell */
490 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
491
492 /* Generic, PCI class code for AHCI */
493 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
495
496 { } /* terminate list */
497 };
498
499
500 static struct pci_driver ahci_pci_driver = {
501 .name = DRV_NAME,
502 .id_table = ahci_pci_tbl,
503 .probe = ahci_init_one,
504 .remove = ata_pci_remove_one,
505 #ifdef CONFIG_PM
506 .suspend = ahci_pci_device_suspend,
507 .resume = ahci_pci_device_resume,
508 #endif
509 };
510
511
512 static inline int ahci_nr_ports(u32 cap)
513 {
514 return (cap & 0x1f) + 1;
515 }
516
517 static inline void __iomem *__ahci_port_base(struct ata_host *host,
518 unsigned int port_no)
519 {
520 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
521
522 return mmio + 0x100 + (port_no * 0x80);
523 }
524
525 static inline void __iomem *ahci_port_base(struct ata_port *ap)
526 {
527 return __ahci_port_base(ap->host, ap->port_no);
528 }
529
530 /**
531 * ahci_save_initial_config - Save and fixup initial config values
532 * @pdev: target PCI device
533 * @pi: associated ATA port info
534 * @hpriv: host private area to store config values
535 *
536 * Some registers containing configuration info might be setup by
537 * BIOS and might be cleared on reset. This function saves the
538 * initial values of those registers into @hpriv such that they
539 * can be restored after controller reset.
540 *
541 * If inconsistent, config values are fixed up by this function.
542 *
543 * LOCKING:
544 * None.
545 */
546 static void ahci_save_initial_config(struct pci_dev *pdev,
547 const struct ata_port_info *pi,
548 struct ahci_host_priv *hpriv)
549 {
550 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
551 u32 cap, port_map;
552 int i;
553
554 /* Values prefixed with saved_ are written back to host after
555 * reset. Values without are used for driver operation.
556 */
557 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
558 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
559
560 /* some chips have errata preventing 64bit use */
561 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
562 dev_printk(KERN_INFO, &pdev->dev,
563 "controller can't do 64bit DMA, forcing 32bit\n");
564 cap &= ~HOST_CAP_64;
565 }
566
567 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
568 dev_printk(KERN_INFO, &pdev->dev,
569 "controller can't do NCQ, turning off CAP_NCQ\n");
570 cap &= ~HOST_CAP_NCQ;
571 }
572
573 /* fixup zero port_map */
574 if (!port_map) {
575 port_map = (1 << ahci_nr_ports(cap)) - 1;
576 dev_printk(KERN_WARNING, &pdev->dev,
577 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
578
579 /* write the fixed up value to the PI register */
580 hpriv->saved_port_map = port_map;
581 }
582
583 /*
584 * Temporary Marvell 6145 hack: PATA port presence
585 * is asserted through the standard AHCI port
586 * presence register, as bit 4 (counting from 0)
587 */
588 if (pi->flags & AHCI_FLAG_MV_PATA) {
589 dev_printk(KERN_ERR, &pdev->dev,
590 "MV_AHCI HACK: port_map %x -> %x\n",
591 hpriv->port_map,
592 hpriv->port_map & 0xf);
593
594 port_map &= 0xf;
595 }
596
597 /* cross check port_map and cap.n_ports */
598 if (pi->flags & AHCI_FLAG_HONOR_PI) {
599 u32 tmp_port_map = port_map;
600 int n_ports = ahci_nr_ports(cap);
601
602 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
603 if (tmp_port_map & (1 << i)) {
604 n_ports--;
605 tmp_port_map &= ~(1 << i);
606 }
607 }
608
609 /* Whine if inconsistent. No need to update cap.
610 * port_map is used to determine number of ports.
611 */
612 if (n_ports || tmp_port_map)
613 dev_printk(KERN_WARNING, &pdev->dev,
614 "nr_ports (%u) and implemented port map "
615 "(0x%x) don't match\n",
616 ahci_nr_ports(cap), port_map);
617 } else {
618 /* fabricate port_map from cap.nr_ports */
619 port_map = (1 << ahci_nr_ports(cap)) - 1;
620 }
621
622 /* record values to use during operation */
623 hpriv->cap = cap;
624 hpriv->port_map = port_map;
625 }
626
627 /**
628 * ahci_restore_initial_config - Restore initial config
629 * @host: target ATA host
630 *
631 * Restore initial config stored by ahci_save_initial_config().
632 *
633 * LOCKING:
634 * None.
635 */
636 static void ahci_restore_initial_config(struct ata_host *host)
637 {
638 struct ahci_host_priv *hpriv = host->private_data;
639 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
640
641 writel(hpriv->saved_cap, mmio + HOST_CAP);
642 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
643 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
644 }
645
646 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
647 {
648 static const int offset[] = {
649 [SCR_STATUS] = PORT_SCR_STAT,
650 [SCR_CONTROL] = PORT_SCR_CTL,
651 [SCR_ERROR] = PORT_SCR_ERR,
652 [SCR_ACTIVE] = PORT_SCR_ACT,
653 [SCR_NOTIFICATION] = PORT_SCR_NTF,
654 };
655 struct ahci_host_priv *hpriv = ap->host->private_data;
656
657 if (sc_reg < ARRAY_SIZE(offset) &&
658 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
659 return offset[sc_reg];
660 return 0;
661 }
662
663 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
664 {
665 void __iomem *port_mmio = ahci_port_base(ap);
666 int offset = ahci_scr_offset(ap, sc_reg);
667
668 if (offset) {
669 *val = readl(port_mmio + offset);
670 return 0;
671 }
672 return -EINVAL;
673 }
674
675 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
676 {
677 void __iomem *port_mmio = ahci_port_base(ap);
678 int offset = ahci_scr_offset(ap, sc_reg);
679
680 if (offset) {
681 writel(val, port_mmio + offset);
682 return 0;
683 }
684 return -EINVAL;
685 }
686
687 static void ahci_start_engine(struct ata_port *ap)
688 {
689 void __iomem *port_mmio = ahci_port_base(ap);
690 u32 tmp;
691
692 /* start DMA */
693 tmp = readl(port_mmio + PORT_CMD);
694 tmp |= PORT_CMD_START;
695 writel(tmp, port_mmio + PORT_CMD);
696 readl(port_mmio + PORT_CMD); /* flush */
697 }
698
699 static int ahci_stop_engine(struct ata_port *ap)
700 {
701 void __iomem *port_mmio = ahci_port_base(ap);
702 u32 tmp;
703
704 tmp = readl(port_mmio + PORT_CMD);
705
706 /* check if the HBA is idle */
707 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
708 return 0;
709
710 /* setting HBA to idle */
711 tmp &= ~PORT_CMD_START;
712 writel(tmp, port_mmio + PORT_CMD);
713
714 /* wait for engine to stop. This could be as long as 500 msec */
715 tmp = ata_wait_register(port_mmio + PORT_CMD,
716 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
717 if (tmp & PORT_CMD_LIST_ON)
718 return -EIO;
719
720 return 0;
721 }
722
723 static void ahci_start_fis_rx(struct ata_port *ap)
724 {
725 void __iomem *port_mmio = ahci_port_base(ap);
726 struct ahci_host_priv *hpriv = ap->host->private_data;
727 struct ahci_port_priv *pp = ap->private_data;
728 u32 tmp;
729
730 /* set FIS registers */
731 if (hpriv->cap & HOST_CAP_64)
732 writel((pp->cmd_slot_dma >> 16) >> 16,
733 port_mmio + PORT_LST_ADDR_HI);
734 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
735
736 if (hpriv->cap & HOST_CAP_64)
737 writel((pp->rx_fis_dma >> 16) >> 16,
738 port_mmio + PORT_FIS_ADDR_HI);
739 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
740
741 /* enable FIS reception */
742 tmp = readl(port_mmio + PORT_CMD);
743 tmp |= PORT_CMD_FIS_RX;
744 writel(tmp, port_mmio + PORT_CMD);
745
746 /* flush */
747 readl(port_mmio + PORT_CMD);
748 }
749
750 static int ahci_stop_fis_rx(struct ata_port *ap)
751 {
752 void __iomem *port_mmio = ahci_port_base(ap);
753 u32 tmp;
754
755 /* disable FIS reception */
756 tmp = readl(port_mmio + PORT_CMD);
757 tmp &= ~PORT_CMD_FIS_RX;
758 writel(tmp, port_mmio + PORT_CMD);
759
760 /* wait for completion, spec says 500ms, give it 1000 */
761 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
762 PORT_CMD_FIS_ON, 10, 1000);
763 if (tmp & PORT_CMD_FIS_ON)
764 return -EBUSY;
765
766 return 0;
767 }
768
769 static void ahci_power_up(struct ata_port *ap)
770 {
771 struct ahci_host_priv *hpriv = ap->host->private_data;
772 void __iomem *port_mmio = ahci_port_base(ap);
773 u32 cmd;
774
775 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
776
777 /* spin up device */
778 if (hpriv->cap & HOST_CAP_SSS) {
779 cmd |= PORT_CMD_SPIN_UP;
780 writel(cmd, port_mmio + PORT_CMD);
781 }
782
783 /* wake up link */
784 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
785 }
786
787 #ifdef CONFIG_PM
788 static void ahci_power_down(struct ata_port *ap)
789 {
790 struct ahci_host_priv *hpriv = ap->host->private_data;
791 void __iomem *port_mmio = ahci_port_base(ap);
792 u32 cmd, scontrol;
793
794 if (!(hpriv->cap & HOST_CAP_SSS))
795 return;
796
797 /* put device into listen mode, first set PxSCTL.DET to 0 */
798 scontrol = readl(port_mmio + PORT_SCR_CTL);
799 scontrol &= ~0xf;
800 writel(scontrol, port_mmio + PORT_SCR_CTL);
801
802 /* then set PxCMD.SUD to 0 */
803 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
804 cmd &= ~PORT_CMD_SPIN_UP;
805 writel(cmd, port_mmio + PORT_CMD);
806 }
807 #endif
808
809 static void ahci_start_port(struct ata_port *ap)
810 {
811 /* enable FIS reception */
812 ahci_start_fis_rx(ap);
813
814 /* enable DMA */
815 ahci_start_engine(ap);
816 }
817
818 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
819 {
820 int rc;
821
822 /* disable DMA */
823 rc = ahci_stop_engine(ap);
824 if (rc) {
825 *emsg = "failed to stop engine";
826 return rc;
827 }
828
829 /* disable FIS reception */
830 rc = ahci_stop_fis_rx(ap);
831 if (rc) {
832 *emsg = "failed stop FIS RX";
833 return rc;
834 }
835
836 return 0;
837 }
838
839 static int ahci_reset_controller(struct ata_host *host)
840 {
841 struct pci_dev *pdev = to_pci_dev(host->dev);
842 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
843 u32 tmp;
844
845 /* global controller reset */
846 tmp = readl(mmio + HOST_CTL);
847 if ((tmp & HOST_RESET) == 0) {
848 writel(tmp | HOST_RESET, mmio + HOST_CTL);
849 readl(mmio + HOST_CTL); /* flush */
850 }
851
852 /* reset must complete within 1 second, or
853 * the hardware should be considered fried.
854 */
855 ssleep(1);
856
857 tmp = readl(mmio + HOST_CTL);
858 if (tmp & HOST_RESET) {
859 dev_printk(KERN_ERR, host->dev,
860 "controller reset failed (0x%x)\n", tmp);
861 return -EIO;
862 }
863
864 /* turn on AHCI mode */
865 writel(HOST_AHCI_EN, mmio + HOST_CTL);
866 (void) readl(mmio + HOST_CTL); /* flush */
867
868 /* some registers might be cleared on reset. restore initial values */
869 ahci_restore_initial_config(host);
870
871 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
872 u16 tmp16;
873
874 /* configure PCS */
875 pci_read_config_word(pdev, 0x92, &tmp16);
876 tmp16 |= 0xf;
877 pci_write_config_word(pdev, 0x92, tmp16);
878 }
879
880 return 0;
881 }
882
883 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
884 int port_no, void __iomem *mmio,
885 void __iomem *port_mmio)
886 {
887 const char *emsg = NULL;
888 int rc;
889 u32 tmp;
890
891 /* make sure port is not active */
892 rc = ahci_deinit_port(ap, &emsg);
893 if (rc)
894 dev_printk(KERN_WARNING, &pdev->dev,
895 "%s (%d)\n", emsg, rc);
896
897 /* clear SError */
898 tmp = readl(port_mmio + PORT_SCR_ERR);
899 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
900 writel(tmp, port_mmio + PORT_SCR_ERR);
901
902 /* clear port IRQ */
903 tmp = readl(port_mmio + PORT_IRQ_STAT);
904 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
905 if (tmp)
906 writel(tmp, port_mmio + PORT_IRQ_STAT);
907
908 writel(1 << port_no, mmio + HOST_IRQ_STAT);
909 }
910
911 static void ahci_init_controller(struct ata_host *host)
912 {
913 struct pci_dev *pdev = to_pci_dev(host->dev);
914 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
915 int i;
916 void __iomem *port_mmio;
917 u32 tmp;
918
919 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
920 port_mmio = __ahci_port_base(host, 4);
921
922 writel(0, port_mmio + PORT_IRQ_MASK);
923
924 /* clear port IRQ */
925 tmp = readl(port_mmio + PORT_IRQ_STAT);
926 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
927 if (tmp)
928 writel(tmp, port_mmio + PORT_IRQ_STAT);
929 }
930
931 for (i = 0; i < host->n_ports; i++) {
932 struct ata_port *ap = host->ports[i];
933
934 port_mmio = ahci_port_base(ap);
935 if (ata_port_is_dummy(ap))
936 continue;
937
938 ahci_port_init(pdev, ap, i, mmio, port_mmio);
939 }
940
941 tmp = readl(mmio + HOST_CTL);
942 VPRINTK("HOST_CTL 0x%x\n", tmp);
943 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
944 tmp = readl(mmio + HOST_CTL);
945 VPRINTK("HOST_CTL 0x%x\n", tmp);
946 }
947
948 static unsigned int ahci_dev_classify(struct ata_port *ap)
949 {
950 void __iomem *port_mmio = ahci_port_base(ap);
951 struct ata_taskfile tf;
952 u32 tmp;
953
954 tmp = readl(port_mmio + PORT_SIG);
955 tf.lbah = (tmp >> 24) & 0xff;
956 tf.lbam = (tmp >> 16) & 0xff;
957 tf.lbal = (tmp >> 8) & 0xff;
958 tf.nsect = (tmp) & 0xff;
959
960 return ata_dev_classify(&tf);
961 }
962
963 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
964 u32 opts)
965 {
966 dma_addr_t cmd_tbl_dma;
967
968 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
969
970 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
971 pp->cmd_slot[tag].status = 0;
972 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
973 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
974 }
975
976 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
977 {
978 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
979 struct ahci_host_priv *hpriv = ap->host->private_data;
980 u32 tmp;
981 int busy, rc;
982
983 /* do we need to kick the port? */
984 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
985 if (!busy && !force_restart)
986 return 0;
987
988 /* stop engine */
989 rc = ahci_stop_engine(ap);
990 if (rc)
991 goto out_restart;
992
993 /* need to do CLO? */
994 if (!busy) {
995 rc = 0;
996 goto out_restart;
997 }
998
999 if (!(hpriv->cap & HOST_CAP_CLO)) {
1000 rc = -EOPNOTSUPP;
1001 goto out_restart;
1002 }
1003
1004 /* perform CLO */
1005 tmp = readl(port_mmio + PORT_CMD);
1006 tmp |= PORT_CMD_CLO;
1007 writel(tmp, port_mmio + PORT_CMD);
1008
1009 rc = 0;
1010 tmp = ata_wait_register(port_mmio + PORT_CMD,
1011 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1012 if (tmp & PORT_CMD_CLO)
1013 rc = -EIO;
1014
1015 /* restart engine */
1016 out_restart:
1017 ahci_start_engine(ap);
1018 return rc;
1019 }
1020
1021 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1022 struct ata_taskfile *tf, int is_cmd, u16 flags,
1023 unsigned long timeout_msec)
1024 {
1025 const u32 cmd_fis_len = 5; /* five dwords */
1026 struct ahci_port_priv *pp = ap->private_data;
1027 void __iomem *port_mmio = ahci_port_base(ap);
1028 u8 *fis = pp->cmd_tbl;
1029 u32 tmp;
1030
1031 /* prep the command */
1032 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1033 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1034
1035 /* issue & wait */
1036 writel(1, port_mmio + PORT_CMD_ISSUE);
1037
1038 if (timeout_msec) {
1039 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1040 1, timeout_msec);
1041 if (tmp & 0x1) {
1042 ahci_kick_engine(ap, 1);
1043 return -EBUSY;
1044 }
1045 } else
1046 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1047
1048 return 0;
1049 }
1050
1051 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1052 int pmp, unsigned long deadline)
1053 {
1054 struct ata_port *ap = link->ap;
1055 const char *reason = NULL;
1056 unsigned long now, msecs;
1057 struct ata_taskfile tf;
1058 int rc;
1059
1060 DPRINTK("ENTER\n");
1061
1062 if (ata_link_offline(link)) {
1063 DPRINTK("PHY reports no device\n");
1064 *class = ATA_DEV_NONE;
1065 return 0;
1066 }
1067
1068 /* prepare for SRST (AHCI-1.1 10.4.1) */
1069 rc = ahci_kick_engine(ap, 1);
1070 if (rc)
1071 ata_link_printk(link, KERN_WARNING,
1072 "failed to reset engine (errno=%d)", rc);
1073
1074 ata_tf_init(link->device, &tf);
1075
1076 /* issue the first D2H Register FIS */
1077 msecs = 0;
1078 now = jiffies;
1079 if (time_after(now, deadline))
1080 msecs = jiffies_to_msecs(deadline - now);
1081
1082 tf.ctl |= ATA_SRST;
1083 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1084 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1085 rc = -EIO;
1086 reason = "1st FIS failed";
1087 goto fail;
1088 }
1089
1090 /* spec says at least 5us, but be generous and sleep for 1ms */
1091 msleep(1);
1092
1093 /* issue the second D2H Register FIS */
1094 tf.ctl &= ~ATA_SRST;
1095 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1096
1097 /* spec mandates ">= 2ms" before checking status.
1098 * We wait 150ms, because that was the magic delay used for
1099 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1100 * between when the ATA command register is written, and then
1101 * status is checked. Because waiting for "a while" before
1102 * checking status is fine, post SRST, we perform this magic
1103 * delay here as well.
1104 */
1105 msleep(150);
1106
1107 rc = ata_wait_ready(ap, deadline);
1108 /* link occupied, -ENODEV too is an error */
1109 if (rc) {
1110 reason = "device not ready";
1111 goto fail;
1112 }
1113 *class = ahci_dev_classify(ap);
1114
1115 DPRINTK("EXIT, class=%u\n", *class);
1116 return 0;
1117
1118 fail:
1119 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1120 return rc;
1121 }
1122
1123 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1124 unsigned long deadline)
1125 {
1126 return ahci_do_softreset(link, class, 0, deadline);
1127 }
1128
1129 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1130 unsigned long deadline)
1131 {
1132 struct ata_port *ap = link->ap;
1133 struct ahci_port_priv *pp = ap->private_data;
1134 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1135 struct ata_taskfile tf;
1136 int rc;
1137
1138 DPRINTK("ENTER\n");
1139
1140 ahci_stop_engine(ap);
1141
1142 /* clear D2H reception area to properly wait for D2H FIS */
1143 ata_tf_init(link->device, &tf);
1144 tf.command = 0x80;
1145 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1146
1147 rc = sata_std_hardreset(link, class, deadline);
1148
1149 ahci_start_engine(ap);
1150
1151 if (rc == 0 && ata_link_online(link))
1152 *class = ahci_dev_classify(ap);
1153 if (*class == ATA_DEV_UNKNOWN)
1154 *class = ATA_DEV_NONE;
1155
1156 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1157 return rc;
1158 }
1159
1160 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1161 unsigned long deadline)
1162 {
1163 struct ata_port *ap = link->ap;
1164 u32 serror;
1165 int rc;
1166
1167 DPRINTK("ENTER\n");
1168
1169 ahci_stop_engine(ap);
1170
1171 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1172 deadline);
1173
1174 /* vt8251 needs SError cleared for the port to operate */
1175 ahci_scr_read(ap, SCR_ERROR, &serror);
1176 ahci_scr_write(ap, SCR_ERROR, serror);
1177
1178 ahci_start_engine(ap);
1179
1180 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1181
1182 /* vt8251 doesn't clear BSY on signature FIS reception,
1183 * request follow-up softreset.
1184 */
1185 return rc ?: -EAGAIN;
1186 }
1187
1188 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1189 {
1190 struct ata_port *ap = link->ap;
1191 void __iomem *port_mmio = ahci_port_base(ap);
1192 u32 new_tmp, tmp;
1193
1194 ata_std_postreset(link, class);
1195
1196 /* Make sure port's ATAPI bit is set appropriately */
1197 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1198 if (*class == ATA_DEV_ATAPI)
1199 new_tmp |= PORT_CMD_ATAPI;
1200 else
1201 new_tmp &= ~PORT_CMD_ATAPI;
1202 if (new_tmp != tmp) {
1203 writel(new_tmp, port_mmio + PORT_CMD);
1204 readl(port_mmio + PORT_CMD); /* flush */
1205 }
1206 }
1207
1208 static u8 ahci_check_status(struct ata_port *ap)
1209 {
1210 void __iomem *mmio = ap->ioaddr.cmd_addr;
1211
1212 return readl(mmio + PORT_TFDATA) & 0xFF;
1213 }
1214
1215 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1216 {
1217 struct ahci_port_priv *pp = ap->private_data;
1218 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1219
1220 ata_tf_from_fis(d2h_fis, tf);
1221 }
1222
1223 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1224 {
1225 struct scatterlist *sg;
1226 struct ahci_sg *ahci_sg;
1227 unsigned int n_sg = 0;
1228
1229 VPRINTK("ENTER\n");
1230
1231 /*
1232 * Next, the S/G list.
1233 */
1234 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1235 ata_for_each_sg(sg, qc) {
1236 dma_addr_t addr = sg_dma_address(sg);
1237 u32 sg_len = sg_dma_len(sg);
1238
1239 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1240 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1241 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1242
1243 ahci_sg++;
1244 n_sg++;
1245 }
1246
1247 return n_sg;
1248 }
1249
1250 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1251 {
1252 struct ata_port *ap = qc->ap;
1253 struct ahci_port_priv *pp = ap->private_data;
1254 int is_atapi = is_atapi_taskfile(&qc->tf);
1255 void *cmd_tbl;
1256 u32 opts;
1257 const u32 cmd_fis_len = 5; /* five dwords */
1258 unsigned int n_elem;
1259
1260 /*
1261 * Fill in command table information. First, the header,
1262 * a SATA Register - Host to Device command FIS.
1263 */
1264 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1265
1266 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
1267 if (is_atapi) {
1268 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1269 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1270 }
1271
1272 n_elem = 0;
1273 if (qc->flags & ATA_QCFLAG_DMAMAP)
1274 n_elem = ahci_fill_sg(qc, cmd_tbl);
1275
1276 /*
1277 * Fill in command slot information.
1278 */
1279 opts = cmd_fis_len | n_elem << 16;
1280 if (qc->tf.flags & ATA_TFLAG_WRITE)
1281 opts |= AHCI_CMD_WRITE;
1282 if (is_atapi)
1283 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1284
1285 ahci_fill_cmd_slot(pp, qc->tag, opts);
1286 }
1287
1288 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1289 {
1290 struct ahci_port_priv *pp = ap->private_data;
1291 struct ata_eh_info *ehi = &ap->link.eh_info;
1292 unsigned int err_mask = 0, action = 0;
1293 struct ata_queued_cmd *qc;
1294 u32 serror;
1295
1296 ata_ehi_clear_desc(ehi);
1297
1298 /* AHCI needs SError cleared; otherwise, it might lock up */
1299 ahci_scr_read(ap, SCR_ERROR, &serror);
1300 ahci_scr_write(ap, SCR_ERROR, serror);
1301
1302 /* analyze @irq_stat */
1303 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1304
1305 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1306 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1307 irq_stat &= ~PORT_IRQ_IF_ERR;
1308
1309 if (irq_stat & PORT_IRQ_TF_ERR) {
1310 err_mask |= AC_ERR_DEV;
1311 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1312 serror &= ~SERR_INTERNAL;
1313 }
1314
1315 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1316 err_mask |= AC_ERR_HOST_BUS;
1317 action |= ATA_EH_SOFTRESET;
1318 }
1319
1320 if (irq_stat & PORT_IRQ_IF_ERR) {
1321 err_mask |= AC_ERR_ATA_BUS;
1322 action |= ATA_EH_SOFTRESET;
1323 ata_ehi_push_desc(ehi, "interface fatal error");
1324 }
1325
1326 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1327 ata_ehi_hotplugged(ehi);
1328 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
1329 "connection status changed" : "PHY RDY changed");
1330 }
1331
1332 if (irq_stat & PORT_IRQ_UNK_FIS) {
1333 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1334
1335 err_mask |= AC_ERR_HSM;
1336 action |= ATA_EH_SOFTRESET;
1337 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
1338 unk[0], unk[1], unk[2], unk[3]);
1339 }
1340
1341 /* okay, let's hand over to EH */
1342 ehi->serror |= serror;
1343 ehi->action |= action;
1344
1345 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1346 if (qc)
1347 qc->err_mask |= err_mask;
1348 else
1349 ehi->err_mask |= err_mask;
1350
1351 if (irq_stat & PORT_IRQ_FREEZE)
1352 ata_port_freeze(ap);
1353 else
1354 ata_port_abort(ap);
1355 }
1356
1357 static void ahci_port_intr(struct ata_port *ap)
1358 {
1359 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1360 struct ata_eh_info *ehi = &ap->link.eh_info;
1361 struct ahci_port_priv *pp = ap->private_data;
1362 u32 status, qc_active;
1363 int rc, known_irq = 0;
1364
1365 status = readl(port_mmio + PORT_IRQ_STAT);
1366 writel(status, port_mmio + PORT_IRQ_STAT);
1367
1368 if (unlikely(status & PORT_IRQ_ERROR)) {
1369 ahci_error_intr(ap, status);
1370 return;
1371 }
1372
1373 if (status & PORT_IRQ_SDB_FIS) {
1374 /*
1375 * if this is an ATAPI device with AN turned on,
1376 * then we should interrogate the device to
1377 * determine the cause of the interrupt
1378 *
1379 * for AN - this we should check the SDB FIS
1380 * and find the I and N bits set
1381 */
1382 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1383 u32 f0 = le32_to_cpu(f[0]);
1384
1385 /* check the 'N' bit in word 0 of the FIS */
1386 if (f0 & (1 << 15)) {
1387 int port_addr = ((f0 & 0x00000f00) >> 8);
1388 struct ata_device *adev;
1389 if (port_addr < ATA_MAX_DEVICES) {
1390 adev = &ap->link.device[port_addr];
1391 if (adev->flags & ATA_DFLAG_AN)
1392 ata_scsi_media_change_notify(adev);
1393 }
1394 }
1395 }
1396
1397 if (ap->link.sactive)
1398 qc_active = readl(port_mmio + PORT_SCR_ACT);
1399 else
1400 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1401
1402 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1403 if (rc > 0)
1404 return;
1405 if (rc < 0) {
1406 ehi->err_mask |= AC_ERR_HSM;
1407 ehi->action |= ATA_EH_SOFTRESET;
1408 ata_port_freeze(ap);
1409 return;
1410 }
1411
1412 /* hmmm... a spurious interupt */
1413
1414 /* if !NCQ, ignore. No modern ATA device has broken HSM
1415 * implementation for non-NCQ commands.
1416 */
1417 if (!ap->link.sactive)
1418 return;
1419
1420 if (status & PORT_IRQ_D2H_REG_FIS) {
1421 if (!pp->ncq_saw_d2h)
1422 ata_port_printk(ap, KERN_INFO,
1423 "D2H reg with I during NCQ, "
1424 "this message won't be printed again\n");
1425 pp->ncq_saw_d2h = 1;
1426 known_irq = 1;
1427 }
1428
1429 if (status & PORT_IRQ_DMAS_FIS) {
1430 if (!pp->ncq_saw_dmas)
1431 ata_port_printk(ap, KERN_INFO,
1432 "DMAS FIS during NCQ, "
1433 "this message won't be printed again\n");
1434 pp->ncq_saw_dmas = 1;
1435 known_irq = 1;
1436 }
1437
1438 if (status & PORT_IRQ_SDB_FIS) {
1439 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1440
1441 if (le32_to_cpu(f[1])) {
1442 /* SDB FIS containing spurious completions
1443 * might be dangerous, whine and fail commands
1444 * with HSM violation. EH will turn off NCQ
1445 * after several such failures.
1446 */
1447 ata_ehi_push_desc(ehi,
1448 "spurious completions during NCQ "
1449 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1450 readl(port_mmio + PORT_CMD_ISSUE),
1451 readl(port_mmio + PORT_SCR_ACT),
1452 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1453 ehi->err_mask |= AC_ERR_HSM;
1454 ehi->action |= ATA_EH_SOFTRESET;
1455 ata_port_freeze(ap);
1456 } else {
1457 if (!pp->ncq_saw_sdb)
1458 ata_port_printk(ap, KERN_INFO,
1459 "spurious SDB FIS %08x:%08x during NCQ, "
1460 "this message won't be printed again\n",
1461 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1462 pp->ncq_saw_sdb = 1;
1463 }
1464 known_irq = 1;
1465 }
1466
1467 if (!known_irq)
1468 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1469 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1470 status, ap->link.active_tag, ap->link.sactive);
1471 }
1472
1473 static void ahci_irq_clear(struct ata_port *ap)
1474 {
1475 /* TODO */
1476 }
1477
1478 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1479 {
1480 struct ata_host *host = dev_instance;
1481 struct ahci_host_priv *hpriv;
1482 unsigned int i, handled = 0;
1483 void __iomem *mmio;
1484 u32 irq_stat, irq_ack = 0;
1485
1486 VPRINTK("ENTER\n");
1487
1488 hpriv = host->private_data;
1489 mmio = host->iomap[AHCI_PCI_BAR];
1490
1491 /* sigh. 0xffffffff is a valid return from h/w */
1492 irq_stat = readl(mmio + HOST_IRQ_STAT);
1493 irq_stat &= hpriv->port_map;
1494 if (!irq_stat)
1495 return IRQ_NONE;
1496
1497 spin_lock(&host->lock);
1498
1499 for (i = 0; i < host->n_ports; i++) {
1500 struct ata_port *ap;
1501
1502 if (!(irq_stat & (1 << i)))
1503 continue;
1504
1505 ap = host->ports[i];
1506 if (ap) {
1507 ahci_port_intr(ap);
1508 VPRINTK("port %u\n", i);
1509 } else {
1510 VPRINTK("port %u (no irq)\n", i);
1511 if (ata_ratelimit())
1512 dev_printk(KERN_WARNING, host->dev,
1513 "interrupt on disabled port %u\n", i);
1514 }
1515
1516 irq_ack |= (1 << i);
1517 }
1518
1519 if (irq_ack) {
1520 writel(irq_ack, mmio + HOST_IRQ_STAT);
1521 handled = 1;
1522 }
1523
1524 spin_unlock(&host->lock);
1525
1526 VPRINTK("EXIT\n");
1527
1528 return IRQ_RETVAL(handled);
1529 }
1530
1531 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1532 {
1533 struct ata_port *ap = qc->ap;
1534 void __iomem *port_mmio = ahci_port_base(ap);
1535
1536 if (qc->tf.protocol == ATA_PROT_NCQ)
1537 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1538 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1539 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1540
1541 return 0;
1542 }
1543
1544 static void ahci_freeze(struct ata_port *ap)
1545 {
1546 void __iomem *port_mmio = ahci_port_base(ap);
1547
1548 /* turn IRQ off */
1549 writel(0, port_mmio + PORT_IRQ_MASK);
1550 }
1551
1552 static void ahci_thaw(struct ata_port *ap)
1553 {
1554 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1555 void __iomem *port_mmio = ahci_port_base(ap);
1556 u32 tmp;
1557 struct ahci_port_priv *pp = ap->private_data;
1558
1559 /* clear IRQ */
1560 tmp = readl(port_mmio + PORT_IRQ_STAT);
1561 writel(tmp, port_mmio + PORT_IRQ_STAT);
1562 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1563
1564 /* turn IRQ back on */
1565 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1566 }
1567
1568 static void ahci_error_handler(struct ata_port *ap)
1569 {
1570 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1571 /* restart engine */
1572 ahci_stop_engine(ap);
1573 ahci_start_engine(ap);
1574 }
1575
1576 /* perform recovery */
1577 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1578 ahci_postreset);
1579 }
1580
1581 static void ahci_vt8251_error_handler(struct ata_port *ap)
1582 {
1583 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1584 /* restart engine */
1585 ahci_stop_engine(ap);
1586 ahci_start_engine(ap);
1587 }
1588
1589 /* perform recovery */
1590 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1591 ahci_postreset);
1592 }
1593
1594 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1595 {
1596 struct ata_port *ap = qc->ap;
1597
1598 /* make DMA engine forget about the failed command */
1599 if (qc->flags & ATA_QCFLAG_FAILED)
1600 ahci_kick_engine(ap, 1);
1601 }
1602
1603 static int ahci_port_resume(struct ata_port *ap)
1604 {
1605 ahci_power_up(ap);
1606 ahci_start_port(ap);
1607
1608 return 0;
1609 }
1610
1611 #ifdef CONFIG_PM
1612 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1613 {
1614 const char *emsg = NULL;
1615 int rc;
1616
1617 rc = ahci_deinit_port(ap, &emsg);
1618 if (rc == 0)
1619 ahci_power_down(ap);
1620 else {
1621 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1622 ahci_start_port(ap);
1623 }
1624
1625 return rc;
1626 }
1627
1628 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1629 {
1630 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1631 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1632 u32 ctl;
1633
1634 if (mesg.event == PM_EVENT_SUSPEND) {
1635 /* AHCI spec rev1.1 section 8.3.3:
1636 * Software must disable interrupts prior to requesting a
1637 * transition of the HBA to D3 state.
1638 */
1639 ctl = readl(mmio + HOST_CTL);
1640 ctl &= ~HOST_IRQ_EN;
1641 writel(ctl, mmio + HOST_CTL);
1642 readl(mmio + HOST_CTL); /* flush */
1643 }
1644
1645 return ata_pci_device_suspend(pdev, mesg);
1646 }
1647
1648 static int ahci_pci_device_resume(struct pci_dev *pdev)
1649 {
1650 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1651 int rc;
1652
1653 rc = ata_pci_device_do_resume(pdev);
1654 if (rc)
1655 return rc;
1656
1657 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1658 rc = ahci_reset_controller(host);
1659 if (rc)
1660 return rc;
1661
1662 ahci_init_controller(host);
1663 }
1664
1665 ata_host_resume(host);
1666
1667 return 0;
1668 }
1669 #endif
1670
1671 static int ahci_port_start(struct ata_port *ap)
1672 {
1673 struct device *dev = ap->host->dev;
1674 struct ahci_port_priv *pp;
1675 void *mem;
1676 dma_addr_t mem_dma;
1677 int rc;
1678
1679 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1680 if (!pp)
1681 return -ENOMEM;
1682
1683 rc = ata_pad_alloc(ap, dev);
1684 if (rc)
1685 return rc;
1686
1687 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1688 GFP_KERNEL);
1689 if (!mem)
1690 return -ENOMEM;
1691 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1692
1693 /*
1694 * First item in chunk of DMA memory: 32-slot command table,
1695 * 32 bytes each in size
1696 */
1697 pp->cmd_slot = mem;
1698 pp->cmd_slot_dma = mem_dma;
1699
1700 mem += AHCI_CMD_SLOT_SZ;
1701 mem_dma += AHCI_CMD_SLOT_SZ;
1702
1703 /*
1704 * Second item: Received-FIS area
1705 */
1706 pp->rx_fis = mem;
1707 pp->rx_fis_dma = mem_dma;
1708
1709 mem += AHCI_RX_FIS_SZ;
1710 mem_dma += AHCI_RX_FIS_SZ;
1711
1712 /*
1713 * Third item: data area for storing a single command
1714 * and its scatter-gather table
1715 */
1716 pp->cmd_tbl = mem;
1717 pp->cmd_tbl_dma = mem_dma;
1718
1719 /*
1720 * Save off initial list of interrupts to be enabled.
1721 * This could be changed later
1722 */
1723 pp->intr_mask = DEF_PORT_IRQ;
1724
1725 ap->private_data = pp;
1726
1727 /* engage engines, captain */
1728 return ahci_port_resume(ap);
1729 }
1730
1731 static void ahci_port_stop(struct ata_port *ap)
1732 {
1733 const char *emsg = NULL;
1734 int rc;
1735
1736 /* de-initialize port */
1737 rc = ahci_deinit_port(ap, &emsg);
1738 if (rc)
1739 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1740 }
1741
1742 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1743 {
1744 int rc;
1745
1746 if (using_dac &&
1747 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1748 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1749 if (rc) {
1750 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1751 if (rc) {
1752 dev_printk(KERN_ERR, &pdev->dev,
1753 "64-bit DMA enable failed\n");
1754 return rc;
1755 }
1756 }
1757 } else {
1758 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1759 if (rc) {
1760 dev_printk(KERN_ERR, &pdev->dev,
1761 "32-bit DMA enable failed\n");
1762 return rc;
1763 }
1764 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1765 if (rc) {
1766 dev_printk(KERN_ERR, &pdev->dev,
1767 "32-bit consistent DMA enable failed\n");
1768 return rc;
1769 }
1770 }
1771 return 0;
1772 }
1773
1774 static void ahci_print_info(struct ata_host *host)
1775 {
1776 struct ahci_host_priv *hpriv = host->private_data;
1777 struct pci_dev *pdev = to_pci_dev(host->dev);
1778 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1779 u32 vers, cap, impl, speed;
1780 const char *speed_s;
1781 u16 cc;
1782 const char *scc_s;
1783
1784 vers = readl(mmio + HOST_VERSION);
1785 cap = hpriv->cap;
1786 impl = hpriv->port_map;
1787
1788 speed = (cap >> 20) & 0xf;
1789 if (speed == 1)
1790 speed_s = "1.5";
1791 else if (speed == 2)
1792 speed_s = "3";
1793 else
1794 speed_s = "?";
1795
1796 pci_read_config_word(pdev, 0x0a, &cc);
1797 if (cc == PCI_CLASS_STORAGE_IDE)
1798 scc_s = "IDE";
1799 else if (cc == PCI_CLASS_STORAGE_SATA)
1800 scc_s = "SATA";
1801 else if (cc == PCI_CLASS_STORAGE_RAID)
1802 scc_s = "RAID";
1803 else
1804 scc_s = "unknown";
1805
1806 dev_printk(KERN_INFO, &pdev->dev,
1807 "AHCI %02x%02x.%02x%02x "
1808 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1809 ,
1810
1811 (vers >> 24) & 0xff,
1812 (vers >> 16) & 0xff,
1813 (vers >> 8) & 0xff,
1814 vers & 0xff,
1815
1816 ((cap >> 8) & 0x1f) + 1,
1817 (cap & 0x1f) + 1,
1818 speed_s,
1819 impl,
1820 scc_s);
1821
1822 dev_printk(KERN_INFO, &pdev->dev,
1823 "flags: "
1824 "%s%s%s%s%s%s%s"
1825 "%s%s%s%s%s%s%s\n"
1826 ,
1827
1828 cap & (1 << 31) ? "64bit " : "",
1829 cap & (1 << 30) ? "ncq " : "",
1830 cap & (1 << 29) ? "sntf " : "",
1831 cap & (1 << 28) ? "ilck " : "",
1832 cap & (1 << 27) ? "stag " : "",
1833 cap & (1 << 26) ? "pm " : "",
1834 cap & (1 << 25) ? "led " : "",
1835
1836 cap & (1 << 24) ? "clo " : "",
1837 cap & (1 << 19) ? "nz " : "",
1838 cap & (1 << 18) ? "only " : "",
1839 cap & (1 << 17) ? "pmp " : "",
1840 cap & (1 << 15) ? "pio " : "",
1841 cap & (1 << 14) ? "slum " : "",
1842 cap & (1 << 13) ? "part " : ""
1843 );
1844 }
1845
1846 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1847 {
1848 static int printed_version;
1849 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1850 const struct ata_port_info *ppi[] = { &pi, NULL };
1851 struct device *dev = &pdev->dev;
1852 struct ahci_host_priv *hpriv;
1853 struct ata_host *host;
1854 int i, rc;
1855
1856 VPRINTK("ENTER\n");
1857
1858 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1859
1860 if (!printed_version++)
1861 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1862
1863 /* acquire resources */
1864 rc = pcim_enable_device(pdev);
1865 if (rc)
1866 return rc;
1867
1868 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1869 if (rc == -EBUSY)
1870 pcim_pin_device(pdev);
1871 if (rc)
1872 return rc;
1873
1874 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1875 pci_intx(pdev, 1);
1876
1877 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1878 if (!hpriv)
1879 return -ENOMEM;
1880
1881 /* save initial config */
1882 ahci_save_initial_config(pdev, &pi, hpriv);
1883
1884 /* prepare host */
1885 if (hpriv->cap & HOST_CAP_NCQ)
1886 pi.flags |= ATA_FLAG_NCQ;
1887
1888 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1889 if (!host)
1890 return -ENOMEM;
1891 host->iomap = pcim_iomap_table(pdev);
1892 host->private_data = hpriv;
1893
1894 for (i = 0; i < host->n_ports; i++) {
1895 struct ata_port *ap = host->ports[i];
1896 void __iomem *port_mmio = ahci_port_base(ap);
1897
1898 /* standard SATA port setup */
1899 if (hpriv->port_map & (1 << i))
1900 ap->ioaddr.cmd_addr = port_mmio;
1901
1902 /* disabled/not-implemented port */
1903 else
1904 ap->ops = &ata_dummy_port_ops;
1905 }
1906
1907 /* initialize adapter */
1908 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1909 if (rc)
1910 return rc;
1911
1912 rc = ahci_reset_controller(host);
1913 if (rc)
1914 return rc;
1915
1916 ahci_init_controller(host);
1917 ahci_print_info(host);
1918
1919 pci_set_master(pdev);
1920 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1921 &ahci_sht);
1922 }
1923
1924 static int __init ahci_init(void)
1925 {
1926 return pci_register_driver(&ahci_pci_driver);
1927 }
1928
1929 static void __exit ahci_exit(void)
1930 {
1931 pci_unregister_driver(&ahci_pci_driver);
1932 }
1933
1934
1935 MODULE_AUTHOR("Jeff Garzik");
1936 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1937 MODULE_LICENSE("GPL");
1938 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1939 MODULE_VERSION(DRV_VERSION);
1940
1941 module_init(ahci_init);
1942 module_exit(ahci_exit);
Linux kernel - Deliverables
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