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[PATCH] ahci: ignore PORT_IRQ_IF_ERR on JMB controllers
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82
83 /* global controller registers */
84 HOST_CAP = 0x00, /* host capabilities */
85 HOST_CTL = 0x04, /* global host control */
86 HOST_IRQ_STAT = 0x08, /* interrupt status */
87 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
88 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
89
90 /* HOST_CTL bits */
91 HOST_RESET = (1 << 0), /* reset controller; self-clear */
92 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
94
95 /* HOST_CAP bits */
96 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
97 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
99 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
100 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
101
102 /* registers for each SATA port */
103 PORT_LST_ADDR = 0x00, /* command list DMA addr */
104 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
105 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
106 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
107 PORT_IRQ_STAT = 0x10, /* interrupt status */
108 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
109 PORT_CMD = 0x18, /* port command */
110 PORT_TFDATA = 0x20, /* taskfile data */
111 PORT_SIG = 0x24, /* device TF signature */
112 PORT_CMD_ISSUE = 0x38, /* command issue */
113 PORT_SCR = 0x28, /* SATA phy register block */
114 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
115 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
116 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
117 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
118
119 /* PORT_IRQ_{STAT,MASK} bits */
120 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
121 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
122 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
123 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
124 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
125 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
126 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
127 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
128
129 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
130 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
131 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
132 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
133 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
134 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
135 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
136 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
137 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
138
139 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
140 PORT_IRQ_IF_ERR |
141 PORT_IRQ_CONNECT |
142 PORT_IRQ_PHYRDY |
143 PORT_IRQ_UNK_FIS,
144 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
145 PORT_IRQ_TF_ERR |
146 PORT_IRQ_HBUS_DATA_ERR,
147 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
148 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
149 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
150
151 /* PORT_CMD bits */
152 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
153 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
154 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
155 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
156 PORT_CMD_CLO = (1 << 3), /* Command list override */
157 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
158 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
159 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
160
161 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
162 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
163 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
164 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
165
166 /* hpriv->flags bits */
167 AHCI_FLAG_MSI = (1 << 0),
168
169 /* ap->flags bits */
170 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
171 AHCI_FLAG_NO_NCQ = (1 << 25),
172 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 26), /* ignore IRQ_IF_ERR */
173 };
174
175 struct ahci_cmd_hdr {
176 u32 opts;
177 u32 status;
178 u32 tbl_addr;
179 u32 tbl_addr_hi;
180 u32 reserved[4];
181 };
182
183 struct ahci_sg {
184 u32 addr;
185 u32 addr_hi;
186 u32 reserved;
187 u32 flags_size;
188 };
189
190 struct ahci_host_priv {
191 unsigned long flags;
192 u32 cap; /* cache of HOST_CAP register */
193 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
194 };
195
196 struct ahci_port_priv {
197 struct ahci_cmd_hdr *cmd_slot;
198 dma_addr_t cmd_slot_dma;
199 void *cmd_tbl;
200 dma_addr_t cmd_tbl_dma;
201 void *rx_fis;
202 dma_addr_t rx_fis_dma;
203 };
204
205 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
206 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
207 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
208 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
209 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
210 static void ahci_irq_clear(struct ata_port *ap);
211 static int ahci_port_start(struct ata_port *ap);
212 static void ahci_port_stop(struct ata_port *ap);
213 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
214 static void ahci_qc_prep(struct ata_queued_cmd *qc);
215 static u8 ahci_check_status(struct ata_port *ap);
216 static void ahci_freeze(struct ata_port *ap);
217 static void ahci_thaw(struct ata_port *ap);
218 static void ahci_error_handler(struct ata_port *ap);
219 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
220 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
221 static int ahci_port_resume(struct ata_port *ap);
222 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
223 static int ahci_pci_device_resume(struct pci_dev *pdev);
224 static void ahci_remove_one (struct pci_dev *pdev);
225
226 static struct scsi_host_template ahci_sht = {
227 .module = THIS_MODULE,
228 .name = DRV_NAME,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
231 .change_queue_depth = ata_scsi_change_queue_depth,
232 .can_queue = AHCI_MAX_CMDS - 1,
233 .this_id = ATA_SHT_THIS_ID,
234 .sg_tablesize = AHCI_MAX_SG,
235 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
236 .emulated = ATA_SHT_EMULATED,
237 .use_clustering = AHCI_USE_CLUSTERING,
238 .proc_name = DRV_NAME,
239 .dma_boundary = AHCI_DMA_BOUNDARY,
240 .slave_configure = ata_scsi_slave_config,
241 .slave_destroy = ata_scsi_slave_destroy,
242 .bios_param = ata_std_bios_param,
243 .suspend = ata_scsi_device_suspend,
244 .resume = ata_scsi_device_resume,
245 };
246
247 static const struct ata_port_operations ahci_ops = {
248 .port_disable = ata_port_disable,
249
250 .check_status = ahci_check_status,
251 .check_altstatus = ahci_check_status,
252 .dev_select = ata_noop_dev_select,
253
254 .tf_read = ahci_tf_read,
255
256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
258
259 .irq_handler = ahci_interrupt,
260 .irq_clear = ahci_irq_clear,
261
262 .scr_read = ahci_scr_read,
263 .scr_write = ahci_scr_write,
264
265 .freeze = ahci_freeze,
266 .thaw = ahci_thaw,
267
268 .error_handler = ahci_error_handler,
269 .post_internal_cmd = ahci_post_internal_cmd,
270
271 .port_suspend = ahci_port_suspend,
272 .port_resume = ahci_port_resume,
273
274 .port_start = ahci_port_start,
275 .port_stop = ahci_port_stop,
276 };
277
278 static const struct ata_port_info ahci_port_info[] = {
279 /* board_ahci */
280 {
281 .sht = &ahci_sht,
282 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
283 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
284 ATA_FLAG_SKIP_D2H_BSY,
285 .pio_mask = 0x1f, /* pio0-4 */
286 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
287 .port_ops = &ahci_ops,
288 },
289 /* board_ahci_vt8251 */
290 {
291 .sht = &ahci_sht,
292 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
293 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
294 ATA_FLAG_SKIP_D2H_BSY |
295 AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
296 .pio_mask = 0x1f, /* pio0-4 */
297 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
298 .port_ops = &ahci_ops,
299 },
300 /* board_ahci_ign_iferr */
301 {
302 .sht = &ahci_sht,
303 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
304 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
305 ATA_FLAG_SKIP_D2H_BSY |
306 AHCI_FLAG_IGN_IRQ_IF_ERR,
307 .pio_mask = 0x1f, /* pio0-4 */
308 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
309 .port_ops = &ahci_ops,
310 },
311 };
312
313 static const struct pci_device_id ahci_pci_tbl[] = {
314 /* Intel */
315 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
316 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
317 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
318 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
319 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
320 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
321 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
322 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
323 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
324 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
325 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
326 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
327 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
328 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
329 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
330 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
331 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
332 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
333 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
334 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
335 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
336 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
337 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
338 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
339 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
340 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
341
342 /* JMicron */
343 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
344 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
345 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
346 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
347 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
348
349 /* ATI */
350 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
351 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
352
353 /* VIA */
354 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
355
356 /* NVIDIA */
357 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
358 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
360 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
366 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
367 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
368 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
369
370 /* SiS */
371 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
372 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
373 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
374
375 { } /* terminate list */
376 };
377
378
379 static struct pci_driver ahci_pci_driver = {
380 .name = DRV_NAME,
381 .id_table = ahci_pci_tbl,
382 .probe = ahci_init_one,
383 .suspend = ahci_pci_device_suspend,
384 .resume = ahci_pci_device_resume,
385 .remove = ahci_remove_one,
386 };
387
388
389 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
390 {
391 return base + 0x100 + (port * 0x80);
392 }
393
394 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
395 {
396 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
397 }
398
399 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
400 {
401 unsigned int sc_reg;
402
403 switch (sc_reg_in) {
404 case SCR_STATUS: sc_reg = 0; break;
405 case SCR_CONTROL: sc_reg = 1; break;
406 case SCR_ERROR: sc_reg = 2; break;
407 case SCR_ACTIVE: sc_reg = 3; break;
408 default:
409 return 0xffffffffU;
410 }
411
412 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
413 }
414
415
416 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
417 u32 val)
418 {
419 unsigned int sc_reg;
420
421 switch (sc_reg_in) {
422 case SCR_STATUS: sc_reg = 0; break;
423 case SCR_CONTROL: sc_reg = 1; break;
424 case SCR_ERROR: sc_reg = 2; break;
425 case SCR_ACTIVE: sc_reg = 3; break;
426 default:
427 return;
428 }
429
430 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
431 }
432
433 static void ahci_start_engine(void __iomem *port_mmio)
434 {
435 u32 tmp;
436
437 /* start DMA */
438 tmp = readl(port_mmio + PORT_CMD);
439 tmp |= PORT_CMD_START;
440 writel(tmp, port_mmio + PORT_CMD);
441 readl(port_mmio + PORT_CMD); /* flush */
442 }
443
444 static int ahci_stop_engine(void __iomem *port_mmio)
445 {
446 u32 tmp;
447
448 tmp = readl(port_mmio + PORT_CMD);
449
450 /* check if the HBA is idle */
451 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
452 return 0;
453
454 /* setting HBA to idle */
455 tmp &= ~PORT_CMD_START;
456 writel(tmp, port_mmio + PORT_CMD);
457
458 /* wait for engine to stop. This could be as long as 500 msec */
459 tmp = ata_wait_register(port_mmio + PORT_CMD,
460 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
461 if (tmp & PORT_CMD_LIST_ON)
462 return -EIO;
463
464 return 0;
465 }
466
467 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
468 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
469 {
470 u32 tmp;
471
472 /* set FIS registers */
473 if (cap & HOST_CAP_64)
474 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
475 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
476
477 if (cap & HOST_CAP_64)
478 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
479 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
480
481 /* enable FIS reception */
482 tmp = readl(port_mmio + PORT_CMD);
483 tmp |= PORT_CMD_FIS_RX;
484 writel(tmp, port_mmio + PORT_CMD);
485
486 /* flush */
487 readl(port_mmio + PORT_CMD);
488 }
489
490 static int ahci_stop_fis_rx(void __iomem *port_mmio)
491 {
492 u32 tmp;
493
494 /* disable FIS reception */
495 tmp = readl(port_mmio + PORT_CMD);
496 tmp &= ~PORT_CMD_FIS_RX;
497 writel(tmp, port_mmio + PORT_CMD);
498
499 /* wait for completion, spec says 500ms, give it 1000 */
500 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
501 PORT_CMD_FIS_ON, 10, 1000);
502 if (tmp & PORT_CMD_FIS_ON)
503 return -EBUSY;
504
505 return 0;
506 }
507
508 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
509 {
510 u32 cmd;
511
512 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
513
514 /* spin up device */
515 if (cap & HOST_CAP_SSS) {
516 cmd |= PORT_CMD_SPIN_UP;
517 writel(cmd, port_mmio + PORT_CMD);
518 }
519
520 /* wake up link */
521 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
522 }
523
524 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
525 {
526 u32 cmd, scontrol;
527
528 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
529
530 if (cap & HOST_CAP_SSC) {
531 /* enable transitions to slumber mode */
532 scontrol = readl(port_mmio + PORT_SCR_CTL);
533 if ((scontrol & 0x0f00) > 0x100) {
534 scontrol &= ~0xf00;
535 writel(scontrol, port_mmio + PORT_SCR_CTL);
536 }
537
538 /* put device into slumber mode */
539 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
540
541 /* wait for the transition to complete */
542 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
543 PORT_CMD_ICC_SLUMBER, 1, 50);
544 }
545
546 /* put device into listen mode */
547 if (cap & HOST_CAP_SSS) {
548 /* first set PxSCTL.DET to 0 */
549 scontrol = readl(port_mmio + PORT_SCR_CTL);
550 scontrol &= ~0xf;
551 writel(scontrol, port_mmio + PORT_SCR_CTL);
552
553 /* then set PxCMD.SUD to 0 */
554 cmd &= ~PORT_CMD_SPIN_UP;
555 writel(cmd, port_mmio + PORT_CMD);
556 }
557 }
558
559 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
560 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
561 {
562 /* power up */
563 ahci_power_up(port_mmio, cap);
564
565 /* enable FIS reception */
566 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
567
568 /* enable DMA */
569 ahci_start_engine(port_mmio);
570 }
571
572 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
573 {
574 int rc;
575
576 /* disable DMA */
577 rc = ahci_stop_engine(port_mmio);
578 if (rc) {
579 *emsg = "failed to stop engine";
580 return rc;
581 }
582
583 /* disable FIS reception */
584 rc = ahci_stop_fis_rx(port_mmio);
585 if (rc) {
586 *emsg = "failed stop FIS RX";
587 return rc;
588 }
589
590 /* put device into slumber mode */
591 ahci_power_down(port_mmio, cap);
592
593 return 0;
594 }
595
596 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
597 {
598 u32 cap_save, tmp;
599
600 cap_save = readl(mmio + HOST_CAP);
601 cap_save &= ( (1<<28) | (1<<17) );
602 cap_save |= (1 << 27);
603
604 /* global controller reset */
605 tmp = readl(mmio + HOST_CTL);
606 if ((tmp & HOST_RESET) == 0) {
607 writel(tmp | HOST_RESET, mmio + HOST_CTL);
608 readl(mmio + HOST_CTL); /* flush */
609 }
610
611 /* reset must complete within 1 second, or
612 * the hardware should be considered fried.
613 */
614 ssleep(1);
615
616 tmp = readl(mmio + HOST_CTL);
617 if (tmp & HOST_RESET) {
618 dev_printk(KERN_ERR, &pdev->dev,
619 "controller reset failed (0x%x)\n", tmp);
620 return -EIO;
621 }
622
623 writel(HOST_AHCI_EN, mmio + HOST_CTL);
624 (void) readl(mmio + HOST_CTL); /* flush */
625 writel(cap_save, mmio + HOST_CAP);
626 writel(0xf, mmio + HOST_PORTS_IMPL);
627 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
628
629 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
630 u16 tmp16;
631
632 /* configure PCS */
633 pci_read_config_word(pdev, 0x92, &tmp16);
634 tmp16 |= 0xf;
635 pci_write_config_word(pdev, 0x92, tmp16);
636 }
637
638 return 0;
639 }
640
641 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
642 int n_ports, u32 cap)
643 {
644 int i, rc;
645 u32 tmp;
646
647 for (i = 0; i < n_ports; i++) {
648 void __iomem *port_mmio = ahci_port_base(mmio, i);
649 const char *emsg = NULL;
650
651 #if 0 /* BIOSen initialize this incorrectly */
652 if (!(hpriv->port_map & (1 << i)))
653 continue;
654 #endif
655
656 /* make sure port is not active */
657 rc = ahci_deinit_port(port_mmio, cap, &emsg);
658 if (rc)
659 dev_printk(KERN_WARNING, &pdev->dev,
660 "%s (%d)\n", emsg, rc);
661
662 /* clear SError */
663 tmp = readl(port_mmio + PORT_SCR_ERR);
664 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
665 writel(tmp, port_mmio + PORT_SCR_ERR);
666
667 /* clear port IRQ */
668 tmp = readl(port_mmio + PORT_IRQ_STAT);
669 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
670 if (tmp)
671 writel(tmp, port_mmio + PORT_IRQ_STAT);
672
673 writel(1 << i, mmio + HOST_IRQ_STAT);
674 }
675
676 tmp = readl(mmio + HOST_CTL);
677 VPRINTK("HOST_CTL 0x%x\n", tmp);
678 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
679 tmp = readl(mmio + HOST_CTL);
680 VPRINTK("HOST_CTL 0x%x\n", tmp);
681 }
682
683 static unsigned int ahci_dev_classify(struct ata_port *ap)
684 {
685 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
686 struct ata_taskfile tf;
687 u32 tmp;
688
689 tmp = readl(port_mmio + PORT_SIG);
690 tf.lbah = (tmp >> 24) & 0xff;
691 tf.lbam = (tmp >> 16) & 0xff;
692 tf.lbal = (tmp >> 8) & 0xff;
693 tf.nsect = (tmp) & 0xff;
694
695 return ata_dev_classify(&tf);
696 }
697
698 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
699 u32 opts)
700 {
701 dma_addr_t cmd_tbl_dma;
702
703 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
704
705 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
706 pp->cmd_slot[tag].status = 0;
707 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
708 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
709 }
710
711 static int ahci_clo(struct ata_port *ap)
712 {
713 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
714 struct ahci_host_priv *hpriv = ap->host->private_data;
715 u32 tmp;
716
717 if (!(hpriv->cap & HOST_CAP_CLO))
718 return -EOPNOTSUPP;
719
720 tmp = readl(port_mmio + PORT_CMD);
721 tmp |= PORT_CMD_CLO;
722 writel(tmp, port_mmio + PORT_CMD);
723
724 tmp = ata_wait_register(port_mmio + PORT_CMD,
725 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
726 if (tmp & PORT_CMD_CLO)
727 return -EIO;
728
729 return 0;
730 }
731
732 static int ahci_prereset(struct ata_port *ap)
733 {
734 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
735 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
736 /* ATA_BUSY hasn't cleared, so send a CLO */
737 ahci_clo(ap);
738 }
739
740 return ata_std_prereset(ap);
741 }
742
743 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
744 {
745 struct ahci_port_priv *pp = ap->private_data;
746 void __iomem *mmio = ap->host->mmio_base;
747 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
748 const u32 cmd_fis_len = 5; /* five dwords */
749 const char *reason = NULL;
750 struct ata_taskfile tf;
751 u32 tmp;
752 u8 *fis;
753 int rc;
754
755 DPRINTK("ENTER\n");
756
757 if (ata_port_offline(ap)) {
758 DPRINTK("PHY reports no device\n");
759 *class = ATA_DEV_NONE;
760 return 0;
761 }
762
763 /* prepare for SRST (AHCI-1.1 10.4.1) */
764 rc = ahci_stop_engine(port_mmio);
765 if (rc) {
766 reason = "failed to stop engine";
767 goto fail_restart;
768 }
769
770 /* check BUSY/DRQ, perform Command List Override if necessary */
771 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
772 rc = ahci_clo(ap);
773
774 if (rc == -EOPNOTSUPP) {
775 reason = "port busy but CLO unavailable";
776 goto fail_restart;
777 } else if (rc) {
778 reason = "port busy but CLO failed";
779 goto fail_restart;
780 }
781 }
782
783 /* restart engine */
784 ahci_start_engine(port_mmio);
785
786 ata_tf_init(ap->device, &tf);
787 fis = pp->cmd_tbl;
788
789 /* issue the first D2H Register FIS */
790 ahci_fill_cmd_slot(pp, 0,
791 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
792
793 tf.ctl |= ATA_SRST;
794 ata_tf_to_fis(&tf, fis, 0);
795 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
796
797 writel(1, port_mmio + PORT_CMD_ISSUE);
798
799 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
800 if (tmp & 0x1) {
801 rc = -EIO;
802 reason = "1st FIS failed";
803 goto fail;
804 }
805
806 /* spec says at least 5us, but be generous and sleep for 1ms */
807 msleep(1);
808
809 /* issue the second D2H Register FIS */
810 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
811
812 tf.ctl &= ~ATA_SRST;
813 ata_tf_to_fis(&tf, fis, 0);
814 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
815
816 writel(1, port_mmio + PORT_CMD_ISSUE);
817 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
818
819 /* spec mandates ">= 2ms" before checking status.
820 * We wait 150ms, because that was the magic delay used for
821 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
822 * between when the ATA command register is written, and then
823 * status is checked. Because waiting for "a while" before
824 * checking status is fine, post SRST, we perform this magic
825 * delay here as well.
826 */
827 msleep(150);
828
829 *class = ATA_DEV_NONE;
830 if (ata_port_online(ap)) {
831 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
832 rc = -EIO;
833 reason = "device not ready";
834 goto fail;
835 }
836 *class = ahci_dev_classify(ap);
837 }
838
839 DPRINTK("EXIT, class=%u\n", *class);
840 return 0;
841
842 fail_restart:
843 ahci_start_engine(port_mmio);
844 fail:
845 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
846 return rc;
847 }
848
849 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
850 {
851 struct ahci_port_priv *pp = ap->private_data;
852 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
853 struct ata_taskfile tf;
854 void __iomem *mmio = ap->host->mmio_base;
855 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
856 int rc;
857
858 DPRINTK("ENTER\n");
859
860 ahci_stop_engine(port_mmio);
861
862 /* clear D2H reception area to properly wait for D2H FIS */
863 ata_tf_init(ap->device, &tf);
864 tf.command = 0xff;
865 ata_tf_to_fis(&tf, d2h_fis, 0);
866
867 rc = sata_std_hardreset(ap, class);
868
869 ahci_start_engine(port_mmio);
870
871 if (rc == 0 && ata_port_online(ap))
872 *class = ahci_dev_classify(ap);
873 if (*class == ATA_DEV_UNKNOWN)
874 *class = ATA_DEV_NONE;
875
876 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
877 return rc;
878 }
879
880 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
881 {
882 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
883 u32 new_tmp, tmp;
884
885 ata_std_postreset(ap, class);
886
887 /* Make sure port's ATAPI bit is set appropriately */
888 new_tmp = tmp = readl(port_mmio + PORT_CMD);
889 if (*class == ATA_DEV_ATAPI)
890 new_tmp |= PORT_CMD_ATAPI;
891 else
892 new_tmp &= ~PORT_CMD_ATAPI;
893 if (new_tmp != tmp) {
894 writel(new_tmp, port_mmio + PORT_CMD);
895 readl(port_mmio + PORT_CMD); /* flush */
896 }
897 }
898
899 static u8 ahci_check_status(struct ata_port *ap)
900 {
901 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
902
903 return readl(mmio + PORT_TFDATA) & 0xFF;
904 }
905
906 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
907 {
908 struct ahci_port_priv *pp = ap->private_data;
909 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
910
911 ata_tf_from_fis(d2h_fis, tf);
912 }
913
914 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
915 {
916 struct scatterlist *sg;
917 struct ahci_sg *ahci_sg;
918 unsigned int n_sg = 0;
919
920 VPRINTK("ENTER\n");
921
922 /*
923 * Next, the S/G list.
924 */
925 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
926 ata_for_each_sg(sg, qc) {
927 dma_addr_t addr = sg_dma_address(sg);
928 u32 sg_len = sg_dma_len(sg);
929
930 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
931 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
932 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
933
934 ahci_sg++;
935 n_sg++;
936 }
937
938 return n_sg;
939 }
940
941 static void ahci_qc_prep(struct ata_queued_cmd *qc)
942 {
943 struct ata_port *ap = qc->ap;
944 struct ahci_port_priv *pp = ap->private_data;
945 int is_atapi = is_atapi_taskfile(&qc->tf);
946 void *cmd_tbl;
947 u32 opts;
948 const u32 cmd_fis_len = 5; /* five dwords */
949 unsigned int n_elem;
950
951 /*
952 * Fill in command table information. First, the header,
953 * a SATA Register - Host to Device command FIS.
954 */
955 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
956
957 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
958 if (is_atapi) {
959 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
960 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
961 }
962
963 n_elem = 0;
964 if (qc->flags & ATA_QCFLAG_DMAMAP)
965 n_elem = ahci_fill_sg(qc, cmd_tbl);
966
967 /*
968 * Fill in command slot information.
969 */
970 opts = cmd_fis_len | n_elem << 16;
971 if (qc->tf.flags & ATA_TFLAG_WRITE)
972 opts |= AHCI_CMD_WRITE;
973 if (is_atapi)
974 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
975
976 ahci_fill_cmd_slot(pp, qc->tag, opts);
977 }
978
979 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
980 {
981 struct ahci_port_priv *pp = ap->private_data;
982 struct ata_eh_info *ehi = &ap->eh_info;
983 unsigned int err_mask = 0, action = 0;
984 struct ata_queued_cmd *qc;
985 u32 serror;
986
987 ata_ehi_clear_desc(ehi);
988
989 /* AHCI needs SError cleared; otherwise, it might lock up */
990 serror = ahci_scr_read(ap, SCR_ERROR);
991 ahci_scr_write(ap, SCR_ERROR, serror);
992
993 /* analyze @irq_stat */
994 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
995
996 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
997 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
998 irq_stat &= ~PORT_IRQ_IF_ERR;
999
1000 if (irq_stat & PORT_IRQ_TF_ERR)
1001 err_mask |= AC_ERR_DEV;
1002
1003 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1004 err_mask |= AC_ERR_HOST_BUS;
1005 action |= ATA_EH_SOFTRESET;
1006 }
1007
1008 if (irq_stat & PORT_IRQ_IF_ERR) {
1009 err_mask |= AC_ERR_ATA_BUS;
1010 action |= ATA_EH_SOFTRESET;
1011 ata_ehi_push_desc(ehi, ", interface fatal error");
1012 }
1013
1014 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1015 ata_ehi_hotplugged(ehi);
1016 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1017 "connection status changed" : "PHY RDY changed");
1018 }
1019
1020 if (irq_stat & PORT_IRQ_UNK_FIS) {
1021 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1022
1023 err_mask |= AC_ERR_HSM;
1024 action |= ATA_EH_SOFTRESET;
1025 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1026 unk[0], unk[1], unk[2], unk[3]);
1027 }
1028
1029 /* okay, let's hand over to EH */
1030 ehi->serror |= serror;
1031 ehi->action |= action;
1032
1033 qc = ata_qc_from_tag(ap, ap->active_tag);
1034 if (qc)
1035 qc->err_mask |= err_mask;
1036 else
1037 ehi->err_mask |= err_mask;
1038
1039 if (irq_stat & PORT_IRQ_FREEZE)
1040 ata_port_freeze(ap);
1041 else
1042 ata_port_abort(ap);
1043 }
1044
1045 static void ahci_host_intr(struct ata_port *ap)
1046 {
1047 void __iomem *mmio = ap->host->mmio_base;
1048 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1049 struct ata_eh_info *ehi = &ap->eh_info;
1050 u32 status, qc_active;
1051 int rc;
1052
1053 status = readl(port_mmio + PORT_IRQ_STAT);
1054 writel(status, port_mmio + PORT_IRQ_STAT);
1055
1056 if (unlikely(status & PORT_IRQ_ERROR)) {
1057 ahci_error_intr(ap, status);
1058 return;
1059 }
1060
1061 if (ap->sactive)
1062 qc_active = readl(port_mmio + PORT_SCR_ACT);
1063 else
1064 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1065
1066 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1067 if (rc > 0)
1068 return;
1069 if (rc < 0) {
1070 ehi->err_mask |= AC_ERR_HSM;
1071 ehi->action |= ATA_EH_SOFTRESET;
1072 ata_port_freeze(ap);
1073 return;
1074 }
1075
1076 /* hmmm... a spurious interupt */
1077
1078 /* some devices send D2H reg with I bit set during NCQ command phase */
1079 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1080 return;
1081
1082 /* ignore interim PIO setup fis interrupts */
1083 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1084 return;
1085
1086 if (ata_ratelimit())
1087 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1088 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1089 status, ap->active_tag, ap->sactive);
1090 }
1091
1092 static void ahci_irq_clear(struct ata_port *ap)
1093 {
1094 /* TODO */
1095 }
1096
1097 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1098 {
1099 struct ata_host *host = dev_instance;
1100 struct ahci_host_priv *hpriv;
1101 unsigned int i, handled = 0;
1102 void __iomem *mmio;
1103 u32 irq_stat, irq_ack = 0;
1104
1105 VPRINTK("ENTER\n");
1106
1107 hpriv = host->private_data;
1108 mmio = host->mmio_base;
1109
1110 /* sigh. 0xffffffff is a valid return from h/w */
1111 irq_stat = readl(mmio + HOST_IRQ_STAT);
1112 irq_stat &= hpriv->port_map;
1113 if (!irq_stat)
1114 return IRQ_NONE;
1115
1116 spin_lock(&host->lock);
1117
1118 for (i = 0; i < host->n_ports; i++) {
1119 struct ata_port *ap;
1120
1121 if (!(irq_stat & (1 << i)))
1122 continue;
1123
1124 ap = host->ports[i];
1125 if (ap) {
1126 ahci_host_intr(ap);
1127 VPRINTK("port %u\n", i);
1128 } else {
1129 VPRINTK("port %u (no irq)\n", i);
1130 if (ata_ratelimit())
1131 dev_printk(KERN_WARNING, host->dev,
1132 "interrupt on disabled port %u\n", i);
1133 }
1134
1135 irq_ack |= (1 << i);
1136 }
1137
1138 if (irq_ack) {
1139 writel(irq_ack, mmio + HOST_IRQ_STAT);
1140 handled = 1;
1141 }
1142
1143 spin_unlock(&host->lock);
1144
1145 VPRINTK("EXIT\n");
1146
1147 return IRQ_RETVAL(handled);
1148 }
1149
1150 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1151 {
1152 struct ata_port *ap = qc->ap;
1153 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1154
1155 if (qc->tf.protocol == ATA_PROT_NCQ)
1156 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1157 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1158 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1159
1160 return 0;
1161 }
1162
1163 static void ahci_freeze(struct ata_port *ap)
1164 {
1165 void __iomem *mmio = ap->host->mmio_base;
1166 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1167
1168 /* turn IRQ off */
1169 writel(0, port_mmio + PORT_IRQ_MASK);
1170 }
1171
1172 static void ahci_thaw(struct ata_port *ap)
1173 {
1174 void __iomem *mmio = ap->host->mmio_base;
1175 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1176 u32 tmp;
1177
1178 /* clear IRQ */
1179 tmp = readl(port_mmio + PORT_IRQ_STAT);
1180 writel(tmp, port_mmio + PORT_IRQ_STAT);
1181 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1182
1183 /* turn IRQ back on */
1184 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1185 }
1186
1187 static void ahci_error_handler(struct ata_port *ap)
1188 {
1189 void __iomem *mmio = ap->host->mmio_base;
1190 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1191
1192 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1193 /* restart engine */
1194 ahci_stop_engine(port_mmio);
1195 ahci_start_engine(port_mmio);
1196 }
1197
1198 /* perform recovery */
1199 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
1200 ahci_postreset);
1201 }
1202
1203 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1204 {
1205 struct ata_port *ap = qc->ap;
1206 void __iomem *mmio = ap->host->mmio_base;
1207 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1208
1209 if (qc->flags & ATA_QCFLAG_FAILED)
1210 qc->err_mask |= AC_ERR_OTHER;
1211
1212 if (qc->err_mask) {
1213 /* make DMA engine forget about the failed command */
1214 ahci_stop_engine(port_mmio);
1215 ahci_start_engine(port_mmio);
1216 }
1217 }
1218
1219 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1220 {
1221 struct ahci_host_priv *hpriv = ap->host->private_data;
1222 struct ahci_port_priv *pp = ap->private_data;
1223 void __iomem *mmio = ap->host->mmio_base;
1224 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1225 const char *emsg = NULL;
1226 int rc;
1227
1228 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1229 if (rc) {
1230 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1231 ahci_init_port(port_mmio, hpriv->cap,
1232 pp->cmd_slot_dma, pp->rx_fis_dma);
1233 }
1234
1235 return rc;
1236 }
1237
1238 static int ahci_port_resume(struct ata_port *ap)
1239 {
1240 struct ahci_port_priv *pp = ap->private_data;
1241 struct ahci_host_priv *hpriv = ap->host->private_data;
1242 void __iomem *mmio = ap->host->mmio_base;
1243 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1244
1245 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1246
1247 return 0;
1248 }
1249
1250 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1251 {
1252 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1253 void __iomem *mmio = host->mmio_base;
1254 u32 ctl;
1255
1256 if (mesg.event == PM_EVENT_SUSPEND) {
1257 /* AHCI spec rev1.1 section 8.3.3:
1258 * Software must disable interrupts prior to requesting a
1259 * transition of the HBA to D3 state.
1260 */
1261 ctl = readl(mmio + HOST_CTL);
1262 ctl &= ~HOST_IRQ_EN;
1263 writel(ctl, mmio + HOST_CTL);
1264 readl(mmio + HOST_CTL); /* flush */
1265 }
1266
1267 return ata_pci_device_suspend(pdev, mesg);
1268 }
1269
1270 static int ahci_pci_device_resume(struct pci_dev *pdev)
1271 {
1272 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1273 struct ahci_host_priv *hpriv = host->private_data;
1274 void __iomem *mmio = host->mmio_base;
1275 int rc;
1276
1277 ata_pci_device_do_resume(pdev);
1278
1279 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1280 rc = ahci_reset_controller(mmio, pdev);
1281 if (rc)
1282 return rc;
1283
1284 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
1285 }
1286
1287 ata_host_resume(host);
1288
1289 return 0;
1290 }
1291
1292 static int ahci_port_start(struct ata_port *ap)
1293 {
1294 struct device *dev = ap->host->dev;
1295 struct ahci_host_priv *hpriv = ap->host->private_data;
1296 struct ahci_port_priv *pp;
1297 void __iomem *mmio = ap->host->mmio_base;
1298 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1299 void *mem;
1300 dma_addr_t mem_dma;
1301 int rc;
1302
1303 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1304 if (!pp)
1305 return -ENOMEM;
1306 memset(pp, 0, sizeof(*pp));
1307
1308 rc = ata_pad_alloc(ap, dev);
1309 if (rc) {
1310 kfree(pp);
1311 return rc;
1312 }
1313
1314 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1315 if (!mem) {
1316 ata_pad_free(ap, dev);
1317 kfree(pp);
1318 return -ENOMEM;
1319 }
1320 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1321
1322 /*
1323 * First item in chunk of DMA memory: 32-slot command table,
1324 * 32 bytes each in size
1325 */
1326 pp->cmd_slot = mem;
1327 pp->cmd_slot_dma = mem_dma;
1328
1329 mem += AHCI_CMD_SLOT_SZ;
1330 mem_dma += AHCI_CMD_SLOT_SZ;
1331
1332 /*
1333 * Second item: Received-FIS area
1334 */
1335 pp->rx_fis = mem;
1336 pp->rx_fis_dma = mem_dma;
1337
1338 mem += AHCI_RX_FIS_SZ;
1339 mem_dma += AHCI_RX_FIS_SZ;
1340
1341 /*
1342 * Third item: data area for storing a single command
1343 * and its scatter-gather table
1344 */
1345 pp->cmd_tbl = mem;
1346 pp->cmd_tbl_dma = mem_dma;
1347
1348 ap->private_data = pp;
1349
1350 /* initialize port */
1351 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1352
1353 return 0;
1354 }
1355
1356 static void ahci_port_stop(struct ata_port *ap)
1357 {
1358 struct device *dev = ap->host->dev;
1359 struct ahci_host_priv *hpriv = ap->host->private_data;
1360 struct ahci_port_priv *pp = ap->private_data;
1361 void __iomem *mmio = ap->host->mmio_base;
1362 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1363 const char *emsg = NULL;
1364 int rc;
1365
1366 /* de-initialize port */
1367 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1368 if (rc)
1369 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1370
1371 ap->private_data = NULL;
1372 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1373 pp->cmd_slot, pp->cmd_slot_dma);
1374 ata_pad_free(ap, dev);
1375 kfree(pp);
1376 }
1377
1378 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1379 unsigned int port_idx)
1380 {
1381 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1382 base = ahci_port_base_ul(base, port_idx);
1383 VPRINTK("base now==0x%lx\n", base);
1384
1385 port->cmd_addr = base;
1386 port->scr_addr = base + PORT_SCR;
1387
1388 VPRINTK("EXIT\n");
1389 }
1390
1391 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1392 {
1393 struct ahci_host_priv *hpriv = probe_ent->private_data;
1394 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1395 void __iomem *mmio = probe_ent->mmio_base;
1396 unsigned int i, using_dac;
1397 int rc;
1398
1399 rc = ahci_reset_controller(mmio, pdev);
1400 if (rc)
1401 return rc;
1402
1403 hpriv->cap = readl(mmio + HOST_CAP);
1404 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1405 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1406
1407 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1408 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1409
1410 using_dac = hpriv->cap & HOST_CAP_64;
1411 if (using_dac &&
1412 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1413 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1414 if (rc) {
1415 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1416 if (rc) {
1417 dev_printk(KERN_ERR, &pdev->dev,
1418 "64-bit DMA enable failed\n");
1419 return rc;
1420 }
1421 }
1422 } else {
1423 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1424 if (rc) {
1425 dev_printk(KERN_ERR, &pdev->dev,
1426 "32-bit DMA enable failed\n");
1427 return rc;
1428 }
1429 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1430 if (rc) {
1431 dev_printk(KERN_ERR, &pdev->dev,
1432 "32-bit consistent DMA enable failed\n");
1433 return rc;
1434 }
1435 }
1436
1437 for (i = 0; i < probe_ent->n_ports; i++)
1438 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1439
1440 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1441
1442 pci_set_master(pdev);
1443
1444 return 0;
1445 }
1446
1447 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1448 {
1449 struct ahci_host_priv *hpriv = probe_ent->private_data;
1450 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1451 void __iomem *mmio = probe_ent->mmio_base;
1452 u32 vers, cap, impl, speed;
1453 const char *speed_s;
1454 u16 cc;
1455 const char *scc_s;
1456
1457 vers = readl(mmio + HOST_VERSION);
1458 cap = hpriv->cap;
1459 impl = hpriv->port_map;
1460
1461 speed = (cap >> 20) & 0xf;
1462 if (speed == 1)
1463 speed_s = "1.5";
1464 else if (speed == 2)
1465 speed_s = "3";
1466 else
1467 speed_s = "?";
1468
1469 pci_read_config_word(pdev, 0x0a, &cc);
1470 if (cc == 0x0101)
1471 scc_s = "IDE";
1472 else if (cc == 0x0106)
1473 scc_s = "SATA";
1474 else if (cc == 0x0104)
1475 scc_s = "RAID";
1476 else
1477 scc_s = "unknown";
1478
1479 dev_printk(KERN_INFO, &pdev->dev,
1480 "AHCI %02x%02x.%02x%02x "
1481 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1482 ,
1483
1484 (vers >> 24) & 0xff,
1485 (vers >> 16) & 0xff,
1486 (vers >> 8) & 0xff,
1487 vers & 0xff,
1488
1489 ((cap >> 8) & 0x1f) + 1,
1490 (cap & 0x1f) + 1,
1491 speed_s,
1492 impl,
1493 scc_s);
1494
1495 dev_printk(KERN_INFO, &pdev->dev,
1496 "flags: "
1497 "%s%s%s%s%s%s"
1498 "%s%s%s%s%s%s%s\n"
1499 ,
1500
1501 cap & (1 << 31) ? "64bit " : "",
1502 cap & (1 << 30) ? "ncq " : "",
1503 cap & (1 << 28) ? "ilck " : "",
1504 cap & (1 << 27) ? "stag " : "",
1505 cap & (1 << 26) ? "pm " : "",
1506 cap & (1 << 25) ? "led " : "",
1507
1508 cap & (1 << 24) ? "clo " : "",
1509 cap & (1 << 19) ? "nz " : "",
1510 cap & (1 << 18) ? "only " : "",
1511 cap & (1 << 17) ? "pmp " : "",
1512 cap & (1 << 15) ? "pio " : "",
1513 cap & (1 << 14) ? "slum " : "",
1514 cap & (1 << 13) ? "part " : ""
1515 );
1516 }
1517
1518 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1519 {
1520 static int printed_version;
1521 struct ata_probe_ent *probe_ent = NULL;
1522 struct ahci_host_priv *hpriv;
1523 unsigned long base;
1524 void __iomem *mmio_base;
1525 unsigned int board_idx = (unsigned int) ent->driver_data;
1526 int have_msi, pci_dev_busy = 0;
1527 int rc;
1528
1529 VPRINTK("ENTER\n");
1530
1531 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1532
1533 if (!printed_version++)
1534 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1535
1536 /* JMicron-specific fixup: make sure we're in AHCI mode */
1537 /* This is protected from races with ata_jmicron by the pci probe
1538 locking */
1539 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1540 /* AHCI enable, AHCI on function 0 */
1541 pci_write_config_byte(pdev, 0x41, 0xa1);
1542 /* Function 1 is the PATA controller */
1543 if (PCI_FUNC(pdev->devfn))
1544 return -ENODEV;
1545 }
1546
1547 rc = pci_enable_device(pdev);
1548 if (rc)
1549 return rc;
1550
1551 rc = pci_request_regions(pdev, DRV_NAME);
1552 if (rc) {
1553 pci_dev_busy = 1;
1554 goto err_out;
1555 }
1556
1557 if (pci_enable_msi(pdev) == 0)
1558 have_msi = 1;
1559 else {
1560 pci_intx(pdev, 1);
1561 have_msi = 0;
1562 }
1563
1564 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1565 if (probe_ent == NULL) {
1566 rc = -ENOMEM;
1567 goto err_out_msi;
1568 }
1569
1570 memset(probe_ent, 0, sizeof(*probe_ent));
1571 probe_ent->dev = pci_dev_to_dev(pdev);
1572 INIT_LIST_HEAD(&probe_ent->node);
1573
1574 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1575 if (mmio_base == NULL) {
1576 rc = -ENOMEM;
1577 goto err_out_free_ent;
1578 }
1579 base = (unsigned long) mmio_base;
1580
1581 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1582 if (!hpriv) {
1583 rc = -ENOMEM;
1584 goto err_out_iounmap;
1585 }
1586 memset(hpriv, 0, sizeof(*hpriv));
1587
1588 probe_ent->sht = ahci_port_info[board_idx].sht;
1589 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1590 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1591 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1592 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1593
1594 probe_ent->irq = pdev->irq;
1595 probe_ent->irq_flags = IRQF_SHARED;
1596 probe_ent->mmio_base = mmio_base;
1597 probe_ent->private_data = hpriv;
1598
1599 if (have_msi)
1600 hpriv->flags |= AHCI_FLAG_MSI;
1601
1602 /* initialize adapter */
1603 rc = ahci_host_init(probe_ent);
1604 if (rc)
1605 goto err_out_hpriv;
1606
1607 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1608 (hpriv->cap & HOST_CAP_NCQ))
1609 probe_ent->port_flags |= ATA_FLAG_NCQ;
1610
1611 ahci_print_info(probe_ent);
1612
1613 /* FIXME: check ata_device_add return value */
1614 ata_device_add(probe_ent);
1615 kfree(probe_ent);
1616
1617 return 0;
1618
1619 err_out_hpriv:
1620 kfree(hpriv);
1621 err_out_iounmap:
1622 pci_iounmap(pdev, mmio_base);
1623 err_out_free_ent:
1624 kfree(probe_ent);
1625 err_out_msi:
1626 if (have_msi)
1627 pci_disable_msi(pdev);
1628 else
1629 pci_intx(pdev, 0);
1630 pci_release_regions(pdev);
1631 err_out:
1632 if (!pci_dev_busy)
1633 pci_disable_device(pdev);
1634 return rc;
1635 }
1636
1637 static void ahci_remove_one (struct pci_dev *pdev)
1638 {
1639 struct device *dev = pci_dev_to_dev(pdev);
1640 struct ata_host *host = dev_get_drvdata(dev);
1641 struct ahci_host_priv *hpriv = host->private_data;
1642 unsigned int i;
1643 int have_msi;
1644
1645 for (i = 0; i < host->n_ports; i++)
1646 ata_port_detach(host->ports[i]);
1647
1648 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1649 free_irq(host->irq, host);
1650
1651 for (i = 0; i < host->n_ports; i++) {
1652 struct ata_port *ap = host->ports[i];
1653
1654 ata_scsi_release(ap->scsi_host);
1655 scsi_host_put(ap->scsi_host);
1656 }
1657
1658 kfree(hpriv);
1659 pci_iounmap(pdev, host->mmio_base);
1660 kfree(host);
1661
1662 if (have_msi)
1663 pci_disable_msi(pdev);
1664 else
1665 pci_intx(pdev, 0);
1666 pci_release_regions(pdev);
1667 pci_disable_device(pdev);
1668 dev_set_drvdata(dev, NULL);
1669 }
1670
1671 static int __init ahci_init(void)
1672 {
1673 return pci_register_driver(&ahci_pci_driver);
1674 }
1675
1676 static void __exit ahci_exit(void)
1677 {
1678 pci_unregister_driver(&ahci_pci_driver);
1679 }
1680
1681
1682 MODULE_AUTHOR("Jeff Garzik");
1683 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1684 MODULE_LICENSE("GPL");
1685 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1686 MODULE_VERSION(DRV_VERSION);
1687
1688 module_init(ahci_init);
1689 module_exit(ahci_exit);
Linux kernel - Deliverables
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