2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.2"
55 AHCI_MAX_SG
= 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY
= 0xffffffff,
57 AHCI_USE_CLUSTERING
= 0,
60 AHCI_CMD_SLOT_SZ
= AHCI_MAX_CMDS
* AHCI_CMD_SZ
,
62 AHCI_CMD_TBL_CDB
= 0x40,
63 AHCI_CMD_TBL_HDR_SZ
= 0x80,
64 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR_SZ
+ (AHCI_MAX_SG
* 16),
65 AHCI_CMD_TBL_AR_SZ
= AHCI_CMD_TBL_SZ
* AHCI_MAX_CMDS
,
66 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_AR_SZ
+
68 AHCI_IRQ_ON_SG
= (1 << 31),
69 AHCI_CMD_ATAPI
= (1 << 5),
70 AHCI_CMD_WRITE
= (1 << 6),
71 AHCI_CMD_PREFETCH
= (1 << 7),
72 AHCI_CMD_RESET
= (1 << 8),
73 AHCI_CMD_CLR_BUSY
= (1 << 10),
75 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB
= 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK
= 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251
= 2,
82 board_ahci_ign_iferr
= 3,
85 /* global controller registers */
86 HOST_CAP
= 0x00, /* host capabilities */
87 HOST_CTL
= 0x04, /* global host control */
88 HOST_IRQ_STAT
= 0x08, /* interrupt status */
89 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC
= (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO
= (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS
= (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ
= (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
104 /* registers for each SATA port */
105 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT
= 0x10, /* interrupt status */
110 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
111 PORT_CMD
= 0x18, /* port command */
112 PORT_TFDATA
= 0x20, /* taskfile data */
113 PORT_SIG
= 0x24, /* device TF signature */
114 PORT_CMD_ISSUE
= 0x38, /* command issue */
115 PORT_SCR
= 0x28, /* SATA phy register block */
116 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
131 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
141 PORT_IRQ_FREEZE
= PORT_IRQ_HBUS_ERR
|
146 PORT_IRQ_ERROR
= PORT_IRQ_FREEZE
|
148 PORT_IRQ_HBUS_DATA_ERR
,
149 DEF_PORT_IRQ
= PORT_IRQ_ERROR
| PORT_IRQ_SG_DONE
|
150 PORT_IRQ_SDB_FIS
| PORT_IRQ_DMAS_FIS
|
151 PORT_IRQ_PIOS_FIS
| PORT_IRQ_D2H_REG_FIS
,
154 PORT_CMD_ATAPI
= (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO
= (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
161 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
163 PORT_CMD_ICC_MASK
= (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
169 AHCI_FLAG_NO_NCQ
= (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR
= (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI
= (1 << 26), /* honor PORTS_IMPL */
172 AHCI_FLAG_IGN_SERR_INTERNAL
= (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY
= (1 << 28), /* force 32bit */
175 AHCI_FLAG_COMMON
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
176 ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
|
177 ATA_FLAG_SKIP_D2H_BSY
|
181 struct ahci_cmd_hdr
{
196 struct ahci_host_priv
{
197 u32 cap
; /* cap to use */
198 u32 port_map
; /* port map to use */
199 u32 saved_cap
; /* saved initial cap */
200 u32 saved_port_map
; /* saved initial port_map */
203 struct ahci_port_priv
{
204 struct ahci_cmd_hdr
*cmd_slot
;
205 dma_addr_t cmd_slot_dma
;
207 dma_addr_t cmd_tbl_dma
;
209 dma_addr_t rx_fis_dma
;
210 /* for NCQ spurious interrupt analysis */
211 unsigned int ncq_saw_d2h
:1;
212 unsigned int ncq_saw_dmas
:1;
213 unsigned int ncq_saw_sdb
:1;
216 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
217 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
218 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
219 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
);
220 static void ahci_irq_clear(struct ata_port
*ap
);
221 static int ahci_port_start(struct ata_port
*ap
);
222 static void ahci_port_stop(struct ata_port
*ap
);
223 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
224 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
225 static u8
ahci_check_status(struct ata_port
*ap
);
226 static void ahci_freeze(struct ata_port
*ap
);
227 static void ahci_thaw(struct ata_port
*ap
);
228 static void ahci_error_handler(struct ata_port
*ap
);
229 static void ahci_vt8251_error_handler(struct ata_port
*ap
);
230 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
);
232 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
);
233 static int ahci_port_resume(struct ata_port
*ap
);
234 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
);
235 static int ahci_pci_device_resume(struct pci_dev
*pdev
);
238 static struct scsi_host_template ahci_sht
= {
239 .module
= THIS_MODULE
,
241 .ioctl
= ata_scsi_ioctl
,
242 .queuecommand
= ata_scsi_queuecmd
,
243 .change_queue_depth
= ata_scsi_change_queue_depth
,
244 .can_queue
= AHCI_MAX_CMDS
- 1,
245 .this_id
= ATA_SHT_THIS_ID
,
246 .sg_tablesize
= AHCI_MAX_SG
,
247 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
248 .emulated
= ATA_SHT_EMULATED
,
249 .use_clustering
= AHCI_USE_CLUSTERING
,
250 .proc_name
= DRV_NAME
,
251 .dma_boundary
= AHCI_DMA_BOUNDARY
,
252 .slave_configure
= ata_scsi_slave_config
,
253 .slave_destroy
= ata_scsi_slave_destroy
,
254 .bios_param
= ata_std_bios_param
,
257 static const struct ata_port_operations ahci_ops
= {
258 .port_disable
= ata_port_disable
,
260 .check_status
= ahci_check_status
,
261 .check_altstatus
= ahci_check_status
,
262 .dev_select
= ata_noop_dev_select
,
264 .tf_read
= ahci_tf_read
,
266 .qc_prep
= ahci_qc_prep
,
267 .qc_issue
= ahci_qc_issue
,
269 .irq_clear
= ahci_irq_clear
,
270 .irq_on
= ata_dummy_irq_on
,
271 .irq_ack
= ata_dummy_irq_ack
,
273 .scr_read
= ahci_scr_read
,
274 .scr_write
= ahci_scr_write
,
276 .freeze
= ahci_freeze
,
279 .error_handler
= ahci_error_handler
,
280 .post_internal_cmd
= ahci_post_internal_cmd
,
283 .port_suspend
= ahci_port_suspend
,
284 .port_resume
= ahci_port_resume
,
287 .port_start
= ahci_port_start
,
288 .port_stop
= ahci_port_stop
,
291 static const struct ata_port_operations ahci_vt8251_ops
= {
292 .port_disable
= ata_port_disable
,
294 .check_status
= ahci_check_status
,
295 .check_altstatus
= ahci_check_status
,
296 .dev_select
= ata_noop_dev_select
,
298 .tf_read
= ahci_tf_read
,
300 .qc_prep
= ahci_qc_prep
,
301 .qc_issue
= ahci_qc_issue
,
303 .irq_clear
= ahci_irq_clear
,
304 .irq_on
= ata_dummy_irq_on
,
305 .irq_ack
= ata_dummy_irq_ack
,
307 .scr_read
= ahci_scr_read
,
308 .scr_write
= ahci_scr_write
,
310 .freeze
= ahci_freeze
,
313 .error_handler
= ahci_vt8251_error_handler
,
314 .post_internal_cmd
= ahci_post_internal_cmd
,
317 .port_suspend
= ahci_port_suspend
,
318 .port_resume
= ahci_port_resume
,
321 .port_start
= ahci_port_start
,
322 .port_stop
= ahci_port_stop
,
325 static const struct ata_port_info ahci_port_info
[] = {
328 .flags
= AHCI_FLAG_COMMON
,
329 .pio_mask
= 0x1f, /* pio0-4 */
330 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
331 .port_ops
= &ahci_ops
,
335 .flags
= AHCI_FLAG_COMMON
| AHCI_FLAG_HONOR_PI
,
336 .pio_mask
= 0x1f, /* pio0-4 */
337 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
338 .port_ops
= &ahci_ops
,
340 /* board_ahci_vt8251 */
342 .flags
= AHCI_FLAG_COMMON
| ATA_FLAG_HRST_TO_RESUME
|
344 .pio_mask
= 0x1f, /* pio0-4 */
345 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
346 .port_ops
= &ahci_vt8251_ops
,
348 /* board_ahci_ign_iferr */
350 .flags
= AHCI_FLAG_COMMON
| AHCI_FLAG_IGN_IRQ_IF_ERR
,
351 .pio_mask
= 0x1f, /* pio0-4 */
352 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
353 .port_ops
= &ahci_ops
,
355 /* board_ahci_sb600 */
357 .flags
= AHCI_FLAG_COMMON
|
358 AHCI_FLAG_IGN_SERR_INTERNAL
|
359 AHCI_FLAG_32BIT_ONLY
,
360 .pio_mask
= 0x1f, /* pio0-4 */
361 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
362 .port_ops
= &ahci_ops
,
366 static const struct pci_device_id ahci_pci_tbl
[] = {
368 { PCI_VDEVICE(INTEL
, 0x2652), board_ahci
}, /* ICH6 */
369 { PCI_VDEVICE(INTEL
, 0x2653), board_ahci
}, /* ICH6M */
370 { PCI_VDEVICE(INTEL
, 0x27c1), board_ahci
}, /* ICH7 */
371 { PCI_VDEVICE(INTEL
, 0x27c5), board_ahci
}, /* ICH7M */
372 { PCI_VDEVICE(INTEL
, 0x27c3), board_ahci
}, /* ICH7R */
373 { PCI_VDEVICE(AL
, 0x5288), board_ahci_ign_iferr
}, /* ULi M5288 */
374 { PCI_VDEVICE(INTEL
, 0x2681), board_ahci
}, /* ESB2 */
375 { PCI_VDEVICE(INTEL
, 0x2682), board_ahci
}, /* ESB2 */
376 { PCI_VDEVICE(INTEL
, 0x2683), board_ahci
}, /* ESB2 */
377 { PCI_VDEVICE(INTEL
, 0x27c6), board_ahci
}, /* ICH7-M DH */
378 { PCI_VDEVICE(INTEL
, 0x2821), board_ahci_pi
}, /* ICH8 */
379 { PCI_VDEVICE(INTEL
, 0x2822), board_ahci_pi
}, /* ICH8 */
380 { PCI_VDEVICE(INTEL
, 0x2824), board_ahci_pi
}, /* ICH8 */
381 { PCI_VDEVICE(INTEL
, 0x2829), board_ahci_pi
}, /* ICH8M */
382 { PCI_VDEVICE(INTEL
, 0x282a), board_ahci_pi
}, /* ICH8M */
383 { PCI_VDEVICE(INTEL
, 0x2922), board_ahci_pi
}, /* ICH9 */
384 { PCI_VDEVICE(INTEL
, 0x2923), board_ahci_pi
}, /* ICH9 */
385 { PCI_VDEVICE(INTEL
, 0x2924), board_ahci_pi
}, /* ICH9 */
386 { PCI_VDEVICE(INTEL
, 0x2925), board_ahci_pi
}, /* ICH9 */
387 { PCI_VDEVICE(INTEL
, 0x2927), board_ahci_pi
}, /* ICH9 */
388 { PCI_VDEVICE(INTEL
, 0x2929), board_ahci_pi
}, /* ICH9M */
389 { PCI_VDEVICE(INTEL
, 0x292a), board_ahci_pi
}, /* ICH9M */
390 { PCI_VDEVICE(INTEL
, 0x292b), board_ahci_pi
}, /* ICH9M */
391 { PCI_VDEVICE(INTEL
, 0x292c), board_ahci_pi
}, /* ICH9M */
392 { PCI_VDEVICE(INTEL
, 0x292f), board_ahci_pi
}, /* ICH9M */
393 { PCI_VDEVICE(INTEL
, 0x294d), board_ahci_pi
}, /* ICH9 */
394 { PCI_VDEVICE(INTEL
, 0x294e), board_ahci_pi
}, /* ICH9M */
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
398 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci_ign_iferr
},
401 { PCI_VDEVICE(ATI
, 0x4380), board_ahci_sb600
}, /* ATI SB600 */
402 { PCI_VDEVICE(ATI
, 0x4390), board_ahci_sb600
}, /* ATI SB700 */
405 { PCI_VDEVICE(VIA
, 0x3349), board_ahci_vt8251
}, /* VIA VT8251 */
406 { PCI_VDEVICE(VIA
, 0x6287), board_ahci_vt8251
}, /* VIA VT8251 */
409 { PCI_VDEVICE(NVIDIA
, 0x044c), board_ahci
}, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA
, 0x044d), board_ahci
}, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA
, 0x044e), board_ahci
}, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA
, 0x044f), board_ahci
}, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA
, 0x045c), board_ahci
}, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA
, 0x045d), board_ahci
}, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA
, 0x045e), board_ahci
}, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA
, 0x045f), board_ahci
}, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA
, 0x0550), board_ahci
}, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA
, 0x0551), board_ahci
}, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA
, 0x0552), board_ahci
}, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA
, 0x0553), board_ahci
}, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA
, 0x0554), board_ahci
}, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA
, 0x0555), board_ahci
}, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA
, 0x0556), board_ahci
}, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA
, 0x0557), board_ahci
}, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA
, 0x0558), board_ahci
}, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA
, 0x0559), board_ahci
}, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA
, 0x055a), board_ahci
}, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA
, 0x055b), board_ahci
}, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA
, 0x07f0), board_ahci
}, /* MCP73 */
430 { PCI_VDEVICE(NVIDIA
, 0x07f1), board_ahci
}, /* MCP73 */
431 { PCI_VDEVICE(NVIDIA
, 0x07f2), board_ahci
}, /* MCP73 */
432 { PCI_VDEVICE(NVIDIA
, 0x07f3), board_ahci
}, /* MCP73 */
433 { PCI_VDEVICE(NVIDIA
, 0x07f4), board_ahci
}, /* MCP73 */
434 { PCI_VDEVICE(NVIDIA
, 0x07f5), board_ahci
}, /* MCP73 */
435 { PCI_VDEVICE(NVIDIA
, 0x07f6), board_ahci
}, /* MCP73 */
436 { PCI_VDEVICE(NVIDIA
, 0x07f7), board_ahci
}, /* MCP73 */
437 { PCI_VDEVICE(NVIDIA
, 0x07f8), board_ahci
}, /* MCP73 */
438 { PCI_VDEVICE(NVIDIA
, 0x07f9), board_ahci
}, /* MCP73 */
439 { PCI_VDEVICE(NVIDIA
, 0x07fa), board_ahci
}, /* MCP73 */
440 { PCI_VDEVICE(NVIDIA
, 0x07fb), board_ahci
}, /* MCP73 */
441 { PCI_VDEVICE(NVIDIA
, 0x0ad0), board_ahci
}, /* MCP77 */
442 { PCI_VDEVICE(NVIDIA
, 0x0ad1), board_ahci
}, /* MCP77 */
443 { PCI_VDEVICE(NVIDIA
, 0x0ad2), board_ahci
}, /* MCP77 */
444 { PCI_VDEVICE(NVIDIA
, 0x0ad3), board_ahci
}, /* MCP77 */
445 { PCI_VDEVICE(NVIDIA
, 0x0ad4), board_ahci
}, /* MCP77 */
446 { PCI_VDEVICE(NVIDIA
, 0x0ad5), board_ahci
}, /* MCP77 */
447 { PCI_VDEVICE(NVIDIA
, 0x0ad6), board_ahci
}, /* MCP77 */
448 { PCI_VDEVICE(NVIDIA
, 0x0ad7), board_ahci
}, /* MCP77 */
449 { PCI_VDEVICE(NVIDIA
, 0x0ad8), board_ahci
}, /* MCP77 */
450 { PCI_VDEVICE(NVIDIA
, 0x0ad9), board_ahci
}, /* MCP77 */
451 { PCI_VDEVICE(NVIDIA
, 0x0ada), board_ahci
}, /* MCP77 */
452 { PCI_VDEVICE(NVIDIA
, 0x0adb), board_ahci
}, /* MCP77 */
455 { PCI_VDEVICE(SI
, 0x1184), board_ahci
}, /* SiS 966 */
456 { PCI_VDEVICE(SI
, 0x1185), board_ahci
}, /* SiS 966 */
457 { PCI_VDEVICE(SI
, 0x0186), board_ahci
}, /* SiS 968 */
459 /* Generic, PCI class code for AHCI */
460 { PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
461 PCI_CLASS_STORAGE_SATA_AHCI
, 0xffffff, board_ahci
},
463 { } /* terminate list */
467 static struct pci_driver ahci_pci_driver
= {
469 .id_table
= ahci_pci_tbl
,
470 .probe
= ahci_init_one
,
471 .remove
= ata_pci_remove_one
,
473 .suspend
= ahci_pci_device_suspend
,
474 .resume
= ahci_pci_device_resume
,
479 static inline int ahci_nr_ports(u32 cap
)
481 return (cap
& 0x1f) + 1;
484 static inline void __iomem
*ahci_port_base(struct ata_port
*ap
)
486 void __iomem
*mmio
= ap
->host
->iomap
[AHCI_PCI_BAR
];
488 return mmio
+ 0x100 + (ap
->port_no
* 0x80);
492 * ahci_save_initial_config - Save and fixup initial config values
493 * @pdev: target PCI device
494 * @pi: associated ATA port info
495 * @hpriv: host private area to store config values
497 * Some registers containing configuration info might be setup by
498 * BIOS and might be cleared on reset. This function saves the
499 * initial values of those registers into @hpriv such that they
500 * can be restored after controller reset.
502 * If inconsistent, config values are fixed up by this function.
507 static void ahci_save_initial_config(struct pci_dev
*pdev
,
508 const struct ata_port_info
*pi
,
509 struct ahci_host_priv
*hpriv
)
511 void __iomem
*mmio
= pcim_iomap_table(pdev
)[AHCI_PCI_BAR
];
515 /* Values prefixed with saved_ are written back to host after
516 * reset. Values without are used for driver operation.
518 hpriv
->saved_cap
= cap
= readl(mmio
+ HOST_CAP
);
519 hpriv
->saved_port_map
= port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
521 /* some chips lie about 64bit support */
522 if ((cap
& HOST_CAP_64
) && (pi
->flags
& AHCI_FLAG_32BIT_ONLY
)) {
523 dev_printk(KERN_INFO
, &pdev
->dev
,
524 "controller can't do 64bit DMA, forcing 32bit\n");
528 /* fixup zero port_map */
530 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
531 dev_printk(KERN_WARNING
, &pdev
->dev
,
532 "PORTS_IMPL is zero, forcing 0x%x\n", port_map
);
534 /* write the fixed up value to the PI register */
535 hpriv
->saved_port_map
= port_map
;
538 /* cross check port_map and cap.n_ports */
539 if (pi
->flags
& AHCI_FLAG_HONOR_PI
) {
540 u32 tmp_port_map
= port_map
;
541 int n_ports
= ahci_nr_ports(cap
);
543 for (i
= 0; i
< AHCI_MAX_PORTS
&& n_ports
; i
++) {
544 if (tmp_port_map
& (1 << i
)) {
546 tmp_port_map
&= ~(1 << i
);
550 /* Whine if inconsistent. No need to update cap.
551 * port_map is used to determine number of ports.
553 if (n_ports
|| tmp_port_map
)
554 dev_printk(KERN_WARNING
, &pdev
->dev
,
555 "nr_ports (%u) and implemented port map "
556 "(0x%x) don't match\n",
557 ahci_nr_ports(cap
), port_map
);
559 /* fabricate port_map from cap.nr_ports */
560 port_map
= (1 << ahci_nr_ports(cap
)) - 1;
563 /* record values to use during operation */
565 hpriv
->port_map
= port_map
;
569 * ahci_restore_initial_config - Restore initial config
570 * @host: target ATA host
572 * Restore initial config stored by ahci_save_initial_config().
577 static void ahci_restore_initial_config(struct ata_host
*host
)
579 struct ahci_host_priv
*hpriv
= host
->private_data
;
580 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
582 writel(hpriv
->saved_cap
, mmio
+ HOST_CAP
);
583 writel(hpriv
->saved_port_map
, mmio
+ HOST_PORTS_IMPL
);
584 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
587 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
592 case SCR_STATUS
: sc_reg
= 0; break;
593 case SCR_CONTROL
: sc_reg
= 1; break;
594 case SCR_ERROR
: sc_reg
= 2; break;
595 case SCR_ACTIVE
: sc_reg
= 3; break;
600 return readl(ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
604 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
610 case SCR_STATUS
: sc_reg
= 0; break;
611 case SCR_CONTROL
: sc_reg
= 1; break;
612 case SCR_ERROR
: sc_reg
= 2; break;
613 case SCR_ACTIVE
: sc_reg
= 3; break;
618 writel(val
, ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
621 static void ahci_start_engine(struct ata_port
*ap
)
623 void __iomem
*port_mmio
= ahci_port_base(ap
);
627 tmp
= readl(port_mmio
+ PORT_CMD
);
628 tmp
|= PORT_CMD_START
;
629 writel(tmp
, port_mmio
+ PORT_CMD
);
630 readl(port_mmio
+ PORT_CMD
); /* flush */
633 static int ahci_stop_engine(struct ata_port
*ap
)
635 void __iomem
*port_mmio
= ahci_port_base(ap
);
638 tmp
= readl(port_mmio
+ PORT_CMD
);
640 /* check if the HBA is idle */
641 if ((tmp
& (PORT_CMD_START
| PORT_CMD_LIST_ON
)) == 0)
644 /* setting HBA to idle */
645 tmp
&= ~PORT_CMD_START
;
646 writel(tmp
, port_mmio
+ PORT_CMD
);
648 /* wait for engine to stop. This could be as long as 500 msec */
649 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
650 PORT_CMD_LIST_ON
, PORT_CMD_LIST_ON
, 1, 500);
651 if (tmp
& PORT_CMD_LIST_ON
)
657 static void ahci_start_fis_rx(struct ata_port
*ap
)
659 void __iomem
*port_mmio
= ahci_port_base(ap
);
660 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
661 struct ahci_port_priv
*pp
= ap
->private_data
;
664 /* set FIS registers */
665 if (hpriv
->cap
& HOST_CAP_64
)
666 writel((pp
->cmd_slot_dma
>> 16) >> 16,
667 port_mmio
+ PORT_LST_ADDR_HI
);
668 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
670 if (hpriv
->cap
& HOST_CAP_64
)
671 writel((pp
->rx_fis_dma
>> 16) >> 16,
672 port_mmio
+ PORT_FIS_ADDR_HI
);
673 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
675 /* enable FIS reception */
676 tmp
= readl(port_mmio
+ PORT_CMD
);
677 tmp
|= PORT_CMD_FIS_RX
;
678 writel(tmp
, port_mmio
+ PORT_CMD
);
681 readl(port_mmio
+ PORT_CMD
);
684 static int ahci_stop_fis_rx(struct ata_port
*ap
)
686 void __iomem
*port_mmio
= ahci_port_base(ap
);
689 /* disable FIS reception */
690 tmp
= readl(port_mmio
+ PORT_CMD
);
691 tmp
&= ~PORT_CMD_FIS_RX
;
692 writel(tmp
, port_mmio
+ PORT_CMD
);
694 /* wait for completion, spec says 500ms, give it 1000 */
695 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
, PORT_CMD_FIS_ON
,
696 PORT_CMD_FIS_ON
, 10, 1000);
697 if (tmp
& PORT_CMD_FIS_ON
)
703 static void ahci_power_up(struct ata_port
*ap
)
705 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
706 void __iomem
*port_mmio
= ahci_port_base(ap
);
709 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
712 if (hpriv
->cap
& HOST_CAP_SSS
) {
713 cmd
|= PORT_CMD_SPIN_UP
;
714 writel(cmd
, port_mmio
+ PORT_CMD
);
718 writel(cmd
| PORT_CMD_ICC_ACTIVE
, port_mmio
+ PORT_CMD
);
722 static void ahci_power_down(struct ata_port
*ap
)
724 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
725 void __iomem
*port_mmio
= ahci_port_base(ap
);
728 if (!(hpriv
->cap
& HOST_CAP_SSS
))
731 /* put device into listen mode, first set PxSCTL.DET to 0 */
732 scontrol
= readl(port_mmio
+ PORT_SCR_CTL
);
734 writel(scontrol
, port_mmio
+ PORT_SCR_CTL
);
736 /* then set PxCMD.SUD to 0 */
737 cmd
= readl(port_mmio
+ PORT_CMD
) & ~PORT_CMD_ICC_MASK
;
738 cmd
&= ~PORT_CMD_SPIN_UP
;
739 writel(cmd
, port_mmio
+ PORT_CMD
);
743 static void ahci_init_port(struct ata_port
*ap
)
745 /* enable FIS reception */
746 ahci_start_fis_rx(ap
);
749 ahci_start_engine(ap
);
752 static int ahci_deinit_port(struct ata_port
*ap
, const char **emsg
)
757 rc
= ahci_stop_engine(ap
);
759 *emsg
= "failed to stop engine";
763 /* disable FIS reception */
764 rc
= ahci_stop_fis_rx(ap
);
766 *emsg
= "failed stop FIS RX";
773 static int ahci_reset_controller(struct ata_host
*host
)
775 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
776 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
779 /* global controller reset */
780 tmp
= readl(mmio
+ HOST_CTL
);
781 if ((tmp
& HOST_RESET
) == 0) {
782 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
783 readl(mmio
+ HOST_CTL
); /* flush */
786 /* reset must complete within 1 second, or
787 * the hardware should be considered fried.
791 tmp
= readl(mmio
+ HOST_CTL
);
792 if (tmp
& HOST_RESET
) {
793 dev_printk(KERN_ERR
, host
->dev
,
794 "controller reset failed (0x%x)\n", tmp
);
798 /* turn on AHCI mode */
799 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
800 (void) readl(mmio
+ HOST_CTL
); /* flush */
802 /* some registers might be cleared on reset. restore initial values */
803 ahci_restore_initial_config(host
);
805 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
809 pci_read_config_word(pdev
, 0x92, &tmp16
);
811 pci_write_config_word(pdev
, 0x92, tmp16
);
817 static void ahci_init_controller(struct ata_host
*host
)
819 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
820 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
824 for (i
= 0; i
< host
->n_ports
; i
++) {
825 struct ata_port
*ap
= host
->ports
[i
];
826 void __iomem
*port_mmio
= ahci_port_base(ap
);
827 const char *emsg
= NULL
;
829 if (ata_port_is_dummy(ap
))
832 /* make sure port is not active */
833 rc
= ahci_deinit_port(ap
, &emsg
);
835 dev_printk(KERN_WARNING
, &pdev
->dev
,
836 "%s (%d)\n", emsg
, rc
);
839 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
840 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
841 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
844 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
845 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
847 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
849 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
852 tmp
= readl(mmio
+ HOST_CTL
);
853 VPRINTK("HOST_CTL 0x%x\n", tmp
);
854 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
855 tmp
= readl(mmio
+ HOST_CTL
);
856 VPRINTK("HOST_CTL 0x%x\n", tmp
);
859 static unsigned int ahci_dev_classify(struct ata_port
*ap
)
861 void __iomem
*port_mmio
= ahci_port_base(ap
);
862 struct ata_taskfile tf
;
865 tmp
= readl(port_mmio
+ PORT_SIG
);
866 tf
.lbah
= (tmp
>> 24) & 0xff;
867 tf
.lbam
= (tmp
>> 16) & 0xff;
868 tf
.lbal
= (tmp
>> 8) & 0xff;
869 tf
.nsect
= (tmp
) & 0xff;
871 return ata_dev_classify(&tf
);
874 static void ahci_fill_cmd_slot(struct ahci_port_priv
*pp
, unsigned int tag
,
877 dma_addr_t cmd_tbl_dma
;
879 cmd_tbl_dma
= pp
->cmd_tbl_dma
+ tag
* AHCI_CMD_TBL_SZ
;
881 pp
->cmd_slot
[tag
].opts
= cpu_to_le32(opts
);
882 pp
->cmd_slot
[tag
].status
= 0;
883 pp
->cmd_slot
[tag
].tbl_addr
= cpu_to_le32(cmd_tbl_dma
& 0xffffffff);
884 pp
->cmd_slot
[tag
].tbl_addr_hi
= cpu_to_le32((cmd_tbl_dma
>> 16) >> 16);
887 static int ahci_clo(struct ata_port
*ap
)
889 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
890 struct ahci_host_priv
*hpriv
= ap
->host
->private_data
;
893 if (!(hpriv
->cap
& HOST_CAP_CLO
))
896 tmp
= readl(port_mmio
+ PORT_CMD
);
898 writel(tmp
, port_mmio
+ PORT_CMD
);
900 tmp
= ata_wait_register(port_mmio
+ PORT_CMD
,
901 PORT_CMD_CLO
, PORT_CMD_CLO
, 1, 500);
902 if (tmp
& PORT_CMD_CLO
)
908 static int ahci_softreset(struct ata_port
*ap
, unsigned int *class,
909 unsigned long deadline
)
911 struct ahci_port_priv
*pp
= ap
->private_data
;
912 void __iomem
*port_mmio
= ahci_port_base(ap
);
913 const u32 cmd_fis_len
= 5; /* five dwords */
914 const char *reason
= NULL
;
915 struct ata_taskfile tf
;
922 if (ata_port_offline(ap
)) {
923 DPRINTK("PHY reports no device\n");
924 *class = ATA_DEV_NONE
;
928 /* prepare for SRST (AHCI-1.1 10.4.1) */
929 rc
= ahci_stop_engine(ap
);
931 reason
= "failed to stop engine";
935 /* check BUSY/DRQ, perform Command List Override if necessary */
936 if (ahci_check_status(ap
) & (ATA_BUSY
| ATA_DRQ
)) {
939 if (rc
== -EOPNOTSUPP
) {
940 reason
= "port busy but CLO unavailable";
943 reason
= "port busy but CLO failed";
949 ahci_start_engine(ap
);
951 ata_tf_init(ap
->device
, &tf
);
954 /* issue the first D2H Register FIS */
955 ahci_fill_cmd_slot(pp
, 0,
956 cmd_fis_len
| AHCI_CMD_RESET
| AHCI_CMD_CLR_BUSY
);
959 ata_tf_to_fis(&tf
, fis
, 0);
960 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
962 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
964 tmp
= ata_wait_register(port_mmio
+ PORT_CMD_ISSUE
, 0x1, 0x1, 1, 500);
967 reason
= "1st FIS failed";
971 /* spec says at least 5us, but be generous and sleep for 1ms */
974 /* issue the second D2H Register FIS */
975 ahci_fill_cmd_slot(pp
, 0, cmd_fis_len
);
978 ata_tf_to_fis(&tf
, fis
, 0);
979 fis
[1] &= ~(1 << 7); /* turn off Command FIS bit */
981 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
982 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
984 /* spec mandates ">= 2ms" before checking status.
985 * We wait 150ms, because that was the magic delay used for
986 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
987 * between when the ATA command register is written, and then
988 * status is checked. Because waiting for "a while" before
989 * checking status is fine, post SRST, we perform this magic
990 * delay here as well.
994 rc
= ata_wait_ready(ap
, deadline
);
995 /* link occupied, -ENODEV too is an error */
997 reason
= "device not ready";
1000 *class = ahci_dev_classify(ap
);
1002 DPRINTK("EXIT, class=%u\n", *class);
1006 ahci_start_engine(ap
);
1008 ata_port_printk(ap
, KERN_ERR
, "softreset failed (%s)\n", reason
);
1012 static int ahci_hardreset(struct ata_port
*ap
, unsigned int *class,
1013 unsigned long deadline
)
1015 struct ahci_port_priv
*pp
= ap
->private_data
;
1016 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1017 struct ata_taskfile tf
;
1022 ahci_stop_engine(ap
);
1024 /* clear D2H reception area to properly wait for D2H FIS */
1025 ata_tf_init(ap
->device
, &tf
);
1027 ata_tf_to_fis(&tf
, d2h_fis
, 0);
1029 rc
= sata_std_hardreset(ap
, class, deadline
);
1031 ahci_start_engine(ap
);
1033 if (rc
== 0 && ata_port_online(ap
))
1034 *class = ahci_dev_classify(ap
);
1035 if (*class == ATA_DEV_UNKNOWN
)
1036 *class = ATA_DEV_NONE
;
1038 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1042 static int ahci_vt8251_hardreset(struct ata_port
*ap
, unsigned int *class,
1043 unsigned long deadline
)
1049 ahci_stop_engine(ap
);
1051 rc
= sata_port_hardreset(ap
, sata_ehc_deb_timing(&ap
->eh_context
),
1054 /* vt8251 needs SError cleared for the port to operate */
1055 ahci_scr_write(ap
, SCR_ERROR
, ahci_scr_read(ap
, SCR_ERROR
));
1057 ahci_start_engine(ap
);
1059 DPRINTK("EXIT, rc=%d, class=%u\n", rc
, *class);
1061 /* vt8251 doesn't clear BSY on signature FIS reception,
1062 * request follow-up softreset.
1064 return rc
?: -EAGAIN
;
1067 static void ahci_postreset(struct ata_port
*ap
, unsigned int *class)
1069 void __iomem
*port_mmio
= ahci_port_base(ap
);
1072 ata_std_postreset(ap
, class);
1074 /* Make sure port's ATAPI bit is set appropriately */
1075 new_tmp
= tmp
= readl(port_mmio
+ PORT_CMD
);
1076 if (*class == ATA_DEV_ATAPI
)
1077 new_tmp
|= PORT_CMD_ATAPI
;
1079 new_tmp
&= ~PORT_CMD_ATAPI
;
1080 if (new_tmp
!= tmp
) {
1081 writel(new_tmp
, port_mmio
+ PORT_CMD
);
1082 readl(port_mmio
+ PORT_CMD
); /* flush */
1086 static u8
ahci_check_status(struct ata_port
*ap
)
1088 void __iomem
*mmio
= ap
->ioaddr
.cmd_addr
;
1090 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
1093 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
1095 struct ahci_port_priv
*pp
= ap
->private_data
;
1096 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
1098 ata_tf_from_fis(d2h_fis
, tf
);
1101 static unsigned int ahci_fill_sg(struct ata_queued_cmd
*qc
, void *cmd_tbl
)
1103 struct scatterlist
*sg
;
1104 struct ahci_sg
*ahci_sg
;
1105 unsigned int n_sg
= 0;
1110 * Next, the S/G list.
1112 ahci_sg
= cmd_tbl
+ AHCI_CMD_TBL_HDR_SZ
;
1113 ata_for_each_sg(sg
, qc
) {
1114 dma_addr_t addr
= sg_dma_address(sg
);
1115 u32 sg_len
= sg_dma_len(sg
);
1117 ahci_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
1118 ahci_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1119 ahci_sg
->flags_size
= cpu_to_le32(sg_len
- 1);
1128 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
1130 struct ata_port
*ap
= qc
->ap
;
1131 struct ahci_port_priv
*pp
= ap
->private_data
;
1132 int is_atapi
= is_atapi_taskfile(&qc
->tf
);
1135 const u32 cmd_fis_len
= 5; /* five dwords */
1136 unsigned int n_elem
;
1139 * Fill in command table information. First, the header,
1140 * a SATA Register - Host to Device command FIS.
1142 cmd_tbl
= pp
->cmd_tbl
+ qc
->tag
* AHCI_CMD_TBL_SZ
;
1144 ata_tf_to_fis(&qc
->tf
, cmd_tbl
, 0);
1146 memset(cmd_tbl
+ AHCI_CMD_TBL_CDB
, 0, 32);
1147 memcpy(cmd_tbl
+ AHCI_CMD_TBL_CDB
, qc
->cdb
, qc
->dev
->cdb_len
);
1151 if (qc
->flags
& ATA_QCFLAG_DMAMAP
)
1152 n_elem
= ahci_fill_sg(qc
, cmd_tbl
);
1155 * Fill in command slot information.
1157 opts
= cmd_fis_len
| n_elem
<< 16;
1158 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
1159 opts
|= AHCI_CMD_WRITE
;
1161 opts
|= AHCI_CMD_ATAPI
| AHCI_CMD_PREFETCH
;
1163 ahci_fill_cmd_slot(pp
, qc
->tag
, opts
);
1166 static void ahci_error_intr(struct ata_port
*ap
, u32 irq_stat
)
1168 struct ahci_port_priv
*pp
= ap
->private_data
;
1169 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1170 unsigned int err_mask
= 0, action
= 0;
1171 struct ata_queued_cmd
*qc
;
1174 ata_ehi_clear_desc(ehi
);
1176 /* AHCI needs SError cleared; otherwise, it might lock up */
1177 serror
= ahci_scr_read(ap
, SCR_ERROR
);
1178 ahci_scr_write(ap
, SCR_ERROR
, serror
);
1180 /* analyze @irq_stat */
1181 ata_ehi_push_desc(ehi
, "irq_stat 0x%08x", irq_stat
);
1183 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1184 if (ap
->flags
& AHCI_FLAG_IGN_IRQ_IF_ERR
)
1185 irq_stat
&= ~PORT_IRQ_IF_ERR
;
1187 if (irq_stat
& PORT_IRQ_TF_ERR
) {
1188 err_mask
|= AC_ERR_DEV
;
1189 if (ap
->flags
& AHCI_FLAG_IGN_SERR_INTERNAL
)
1190 serror
&= ~SERR_INTERNAL
;
1193 if (irq_stat
& (PORT_IRQ_HBUS_ERR
| PORT_IRQ_HBUS_DATA_ERR
)) {
1194 err_mask
|= AC_ERR_HOST_BUS
;
1195 action
|= ATA_EH_SOFTRESET
;
1198 if (irq_stat
& PORT_IRQ_IF_ERR
) {
1199 err_mask
|= AC_ERR_ATA_BUS
;
1200 action
|= ATA_EH_SOFTRESET
;
1201 ata_ehi_push_desc(ehi
, ", interface fatal error");
1204 if (irq_stat
& (PORT_IRQ_CONNECT
| PORT_IRQ_PHYRDY
)) {
1205 ata_ehi_hotplugged(ehi
);
1206 ata_ehi_push_desc(ehi
, ", %s", irq_stat
& PORT_IRQ_CONNECT
?
1207 "connection status changed" : "PHY RDY changed");
1210 if (irq_stat
& PORT_IRQ_UNK_FIS
) {
1211 u32
*unk
= (u32
*)(pp
->rx_fis
+ RX_FIS_UNK
);
1213 err_mask
|= AC_ERR_HSM
;
1214 action
|= ATA_EH_SOFTRESET
;
1215 ata_ehi_push_desc(ehi
, ", unknown FIS %08x %08x %08x %08x",
1216 unk
[0], unk
[1], unk
[2], unk
[3]);
1219 /* okay, let's hand over to EH */
1220 ehi
->serror
|= serror
;
1221 ehi
->action
|= action
;
1223 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
1225 qc
->err_mask
|= err_mask
;
1227 ehi
->err_mask
|= err_mask
;
1229 if (irq_stat
& PORT_IRQ_FREEZE
)
1230 ata_port_freeze(ap
);
1235 static void ahci_host_intr(struct ata_port
*ap
)
1237 void __iomem
*port_mmio
= ap
->ioaddr
.cmd_addr
;
1238 struct ata_eh_info
*ehi
= &ap
->eh_info
;
1239 struct ahci_port_priv
*pp
= ap
->private_data
;
1240 u32 status
, qc_active
;
1241 int rc
, known_irq
= 0;
1243 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
1244 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
1246 if (unlikely(status
& PORT_IRQ_ERROR
)) {
1247 ahci_error_intr(ap
, status
);
1252 qc_active
= readl(port_mmio
+ PORT_SCR_ACT
);
1254 qc_active
= readl(port_mmio
+ PORT_CMD_ISSUE
);
1256 rc
= ata_qc_complete_multiple(ap
, qc_active
, NULL
);
1260 ehi
->err_mask
|= AC_ERR_HSM
;
1261 ehi
->action
|= ATA_EH_SOFTRESET
;
1262 ata_port_freeze(ap
);
1266 /* hmmm... a spurious interupt */
1268 /* if !NCQ, ignore. No modern ATA device has broken HSM
1269 * implementation for non-NCQ commands.
1274 if (status
& PORT_IRQ_D2H_REG_FIS
) {
1275 if (!pp
->ncq_saw_d2h
)
1276 ata_port_printk(ap
, KERN_INFO
,
1277 "D2H reg with I during NCQ, "
1278 "this message won't be printed again\n");
1279 pp
->ncq_saw_d2h
= 1;
1283 if (status
& PORT_IRQ_DMAS_FIS
) {
1284 if (!pp
->ncq_saw_dmas
)
1285 ata_port_printk(ap
, KERN_INFO
,
1286 "DMAS FIS during NCQ, "
1287 "this message won't be printed again\n");
1288 pp
->ncq_saw_dmas
= 1;
1292 if (status
& PORT_IRQ_SDB_FIS
) {
1293 const __le32
*f
= pp
->rx_fis
+ RX_FIS_SDB
;
1295 if (le32_to_cpu(f
[1])) {
1296 /* SDB FIS containing spurious completions
1297 * might be dangerous, whine and fail commands
1298 * with HSM violation. EH will turn off NCQ
1299 * after several such failures.
1301 ata_ehi_push_desc(ehi
,
1302 "spurious completions during NCQ "
1303 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1304 readl(port_mmio
+ PORT_CMD_ISSUE
),
1305 readl(port_mmio
+ PORT_SCR_ACT
),
1306 le32_to_cpu(f
[0]), le32_to_cpu(f
[1]));
1307 ehi
->err_mask
|= AC_ERR_HSM
;
1308 ehi
->action
|= ATA_EH_SOFTRESET
;
1309 ata_port_freeze(ap
);
1311 if (!pp
->ncq_saw_sdb
)
1312 ata_port_printk(ap
, KERN_INFO
,
1313 "spurious SDB FIS %08x:%08x during NCQ, "
1314 "this message won't be printed again\n",
1315 le32_to_cpu(f
[0]), le32_to_cpu(f
[1]));
1316 pp
->ncq_saw_sdb
= 1;
1322 ata_port_printk(ap
, KERN_INFO
, "spurious interrupt "
1323 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1324 status
, ap
->active_tag
, ap
->sactive
);
1327 static void ahci_irq_clear(struct ata_port
*ap
)
1332 static irqreturn_t
ahci_interrupt(int irq
, void *dev_instance
)
1334 struct ata_host
*host
= dev_instance
;
1335 struct ahci_host_priv
*hpriv
;
1336 unsigned int i
, handled
= 0;
1338 u32 irq_stat
, irq_ack
= 0;
1342 hpriv
= host
->private_data
;
1343 mmio
= host
->iomap
[AHCI_PCI_BAR
];
1345 /* sigh. 0xffffffff is a valid return from h/w */
1346 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
1347 irq_stat
&= hpriv
->port_map
;
1351 spin_lock(&host
->lock
);
1353 for (i
= 0; i
< host
->n_ports
; i
++) {
1354 struct ata_port
*ap
;
1356 if (!(irq_stat
& (1 << i
)))
1359 ap
= host
->ports
[i
];
1362 VPRINTK("port %u\n", i
);
1364 VPRINTK("port %u (no irq)\n", i
);
1365 if (ata_ratelimit())
1366 dev_printk(KERN_WARNING
, host
->dev
,
1367 "interrupt on disabled port %u\n", i
);
1370 irq_ack
|= (1 << i
);
1374 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
1378 spin_unlock(&host
->lock
);
1382 return IRQ_RETVAL(handled
);
1385 static unsigned int ahci_qc_issue(struct ata_queued_cmd
*qc
)
1387 struct ata_port
*ap
= qc
->ap
;
1388 void __iomem
*port_mmio
= ahci_port_base(ap
);
1390 if (qc
->tf
.protocol
== ATA_PROT_NCQ
)
1391 writel(1 << qc
->tag
, port_mmio
+ PORT_SCR_ACT
);
1392 writel(1 << qc
->tag
, port_mmio
+ PORT_CMD_ISSUE
);
1393 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
1398 static void ahci_freeze(struct ata_port
*ap
)
1400 void __iomem
*port_mmio
= ahci_port_base(ap
);
1403 writel(0, port_mmio
+ PORT_IRQ_MASK
);
1406 static void ahci_thaw(struct ata_port
*ap
)
1408 void __iomem
*mmio
= ap
->host
->iomap
[AHCI_PCI_BAR
];
1409 void __iomem
*port_mmio
= ahci_port_base(ap
);
1413 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
1414 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
1415 writel(1 << ap
->port_no
, mmio
+ HOST_IRQ_STAT
);
1417 /* turn IRQ back on */
1418 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
1421 static void ahci_error_handler(struct ata_port
*ap
)
1423 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1424 /* restart engine */
1425 ahci_stop_engine(ap
);
1426 ahci_start_engine(ap
);
1429 /* perform recovery */
1430 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_hardreset
,
1434 static void ahci_vt8251_error_handler(struct ata_port
*ap
)
1436 if (!(ap
->pflags
& ATA_PFLAG_FROZEN
)) {
1437 /* restart engine */
1438 ahci_stop_engine(ap
);
1439 ahci_start_engine(ap
);
1442 /* perform recovery */
1443 ata_do_eh(ap
, ata_std_prereset
, ahci_softreset
, ahci_vt8251_hardreset
,
1447 static void ahci_post_internal_cmd(struct ata_queued_cmd
*qc
)
1449 struct ata_port
*ap
= qc
->ap
;
1451 if (qc
->flags
& ATA_QCFLAG_FAILED
) {
1452 /* make DMA engine forget about the failed command */
1453 ahci_stop_engine(ap
);
1454 ahci_start_engine(ap
);
1459 static int ahci_port_suspend(struct ata_port
*ap
, pm_message_t mesg
)
1461 const char *emsg
= NULL
;
1464 rc
= ahci_deinit_port(ap
, &emsg
);
1466 ahci_power_down(ap
);
1468 ata_port_printk(ap
, KERN_ERR
, "%s (%d)\n", emsg
, rc
);
1475 static int ahci_port_resume(struct ata_port
*ap
)
1483 static int ahci_pci_device_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1485 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1486 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1489 if (mesg
.event
== PM_EVENT_SUSPEND
) {
1490 /* AHCI spec rev1.1 section 8.3.3:
1491 * Software must disable interrupts prior to requesting a
1492 * transition of the HBA to D3 state.
1494 ctl
= readl(mmio
+ HOST_CTL
);
1495 ctl
&= ~HOST_IRQ_EN
;
1496 writel(ctl
, mmio
+ HOST_CTL
);
1497 readl(mmio
+ HOST_CTL
); /* flush */
1500 return ata_pci_device_suspend(pdev
, mesg
);
1503 static int ahci_pci_device_resume(struct pci_dev
*pdev
)
1505 struct ata_host
*host
= dev_get_drvdata(&pdev
->dev
);
1508 rc
= ata_pci_device_do_resume(pdev
);
1512 if (pdev
->dev
.power
.power_state
.event
== PM_EVENT_SUSPEND
) {
1513 rc
= ahci_reset_controller(host
);
1517 ahci_init_controller(host
);
1520 ata_host_resume(host
);
1526 static int ahci_port_start(struct ata_port
*ap
)
1528 struct device
*dev
= ap
->host
->dev
;
1529 struct ahci_port_priv
*pp
;
1534 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
1538 rc
= ata_pad_alloc(ap
, dev
);
1542 mem
= dmam_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
,
1546 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
1549 * First item in chunk of DMA memory: 32-slot command table,
1550 * 32 bytes each in size
1553 pp
->cmd_slot_dma
= mem_dma
;
1555 mem
+= AHCI_CMD_SLOT_SZ
;
1556 mem_dma
+= AHCI_CMD_SLOT_SZ
;
1559 * Second item: Received-FIS area
1562 pp
->rx_fis_dma
= mem_dma
;
1564 mem
+= AHCI_RX_FIS_SZ
;
1565 mem_dma
+= AHCI_RX_FIS_SZ
;
1568 * Third item: data area for storing a single command
1569 * and its scatter-gather table
1572 pp
->cmd_tbl_dma
= mem_dma
;
1574 ap
->private_data
= pp
;
1579 /* initialize port */
1585 static void ahci_port_stop(struct ata_port
*ap
)
1587 const char *emsg
= NULL
;
1590 /* de-initialize port */
1591 rc
= ahci_deinit_port(ap
, &emsg
);
1593 ata_port_printk(ap
, KERN_WARNING
, "%s (%d)\n", emsg
, rc
);
1596 static int ahci_configure_dma_masks(struct pci_dev
*pdev
, int using_dac
)
1601 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
1602 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
1604 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1606 dev_printk(KERN_ERR
, &pdev
->dev
,
1607 "64-bit DMA enable failed\n");
1612 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
1614 dev_printk(KERN_ERR
, &pdev
->dev
,
1615 "32-bit DMA enable failed\n");
1618 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
1620 dev_printk(KERN_ERR
, &pdev
->dev
,
1621 "32-bit consistent DMA enable failed\n");
1628 static void ahci_print_info(struct ata_host
*host
)
1630 struct ahci_host_priv
*hpriv
= host
->private_data
;
1631 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1632 void __iomem
*mmio
= host
->iomap
[AHCI_PCI_BAR
];
1633 u32 vers
, cap
, impl
, speed
;
1634 const char *speed_s
;
1638 vers
= readl(mmio
+ HOST_VERSION
);
1640 impl
= hpriv
->port_map
;
1642 speed
= (cap
>> 20) & 0xf;
1645 else if (speed
== 2)
1650 pci_read_config_word(pdev
, 0x0a, &cc
);
1651 if (cc
== PCI_CLASS_STORAGE_IDE
)
1653 else if (cc
== PCI_CLASS_STORAGE_SATA
)
1655 else if (cc
== PCI_CLASS_STORAGE_RAID
)
1660 dev_printk(KERN_INFO
, &pdev
->dev
,
1661 "AHCI %02x%02x.%02x%02x "
1662 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1665 (vers
>> 24) & 0xff,
1666 (vers
>> 16) & 0xff,
1670 ((cap
>> 8) & 0x1f) + 1,
1676 dev_printk(KERN_INFO
, &pdev
->dev
,
1682 cap
& (1 << 31) ? "64bit " : "",
1683 cap
& (1 << 30) ? "ncq " : "",
1684 cap
& (1 << 28) ? "ilck " : "",
1685 cap
& (1 << 27) ? "stag " : "",
1686 cap
& (1 << 26) ? "pm " : "",
1687 cap
& (1 << 25) ? "led " : "",
1689 cap
& (1 << 24) ? "clo " : "",
1690 cap
& (1 << 19) ? "nz " : "",
1691 cap
& (1 << 18) ? "only " : "",
1692 cap
& (1 << 17) ? "pmp " : "",
1693 cap
& (1 << 15) ? "pio " : "",
1694 cap
& (1 << 14) ? "slum " : "",
1695 cap
& (1 << 13) ? "part " : ""
1699 static int ahci_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1701 static int printed_version
;
1702 struct ata_port_info pi
= ahci_port_info
[ent
->driver_data
];
1703 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
1704 struct device
*dev
= &pdev
->dev
;
1705 struct ahci_host_priv
*hpriv
;
1706 struct ata_host
*host
;
1711 WARN_ON(ATA_MAX_QUEUE
> AHCI_MAX_CMDS
);
1713 if (!printed_version
++)
1714 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
1716 /* acquire resources */
1717 rc
= pcim_enable_device(pdev
);
1721 rc
= pcim_iomap_regions(pdev
, 1 << AHCI_PCI_BAR
, DRV_NAME
);
1723 pcim_pin_device(pdev
);
1727 if (pci_enable_msi(pdev
))
1730 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
1734 /* save initial config */
1735 ahci_save_initial_config(pdev
, &pi
, hpriv
);
1738 if (!(pi
.flags
& AHCI_FLAG_NO_NCQ
) && (hpriv
->cap
& HOST_CAP_NCQ
))
1739 pi
.flags
|= ATA_FLAG_NCQ
;
1741 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, fls(hpriv
->port_map
));
1744 host
->iomap
= pcim_iomap_table(pdev
);
1745 host
->private_data
= hpriv
;
1747 for (i
= 0; i
< host
->n_ports
; i
++) {
1748 if (hpriv
->port_map
& (1 << i
)) {
1749 struct ata_port
*ap
= host
->ports
[i
];
1750 void __iomem
*port_mmio
= ahci_port_base(ap
);
1752 ap
->ioaddr
.cmd_addr
= port_mmio
;
1753 ap
->ioaddr
.scr_addr
= port_mmio
+ PORT_SCR
;
1755 host
->ports
[i
]->ops
= &ata_dummy_port_ops
;
1758 /* initialize adapter */
1759 rc
= ahci_configure_dma_masks(pdev
, hpriv
->cap
& HOST_CAP_64
);
1763 rc
= ahci_reset_controller(host
);
1767 ahci_init_controller(host
);
1768 ahci_print_info(host
);
1770 pci_set_master(pdev
);
1771 return ata_host_activate(host
, pdev
->irq
, ahci_interrupt
, IRQF_SHARED
,
1775 static int __init
ahci_init(void)
1777 return pci_register_driver(&ahci_pci_driver
);
1780 static void __exit
ahci_exit(void)
1782 pci_unregister_driver(&ahci_pci_driver
);
1786 MODULE_AUTHOR("Jeff Garzik");
1787 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1788 MODULE_LICENSE("GPL");
1789 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1790 MODULE_VERSION(DRV_VERSION
);
1792 module_init(ahci_init
);
1793 module_exit(ahci_exit
);