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Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
95 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
96 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
97 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
98 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
99 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
100
101 /* registers for each SATA port */
102 PORT_LST_ADDR = 0x00, /* command list DMA addr */
103 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
104 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
105 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
106 PORT_IRQ_STAT = 0x10, /* interrupt status */
107 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
108 PORT_CMD = 0x18, /* port command */
109 PORT_TFDATA = 0x20, /* taskfile data */
110 PORT_SIG = 0x24, /* device TF signature */
111 PORT_CMD_ISSUE = 0x38, /* command issue */
112 PORT_SCR = 0x28, /* SATA phy register block */
113 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
114 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
115 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
116 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
117
118 /* PORT_IRQ_{STAT,MASK} bits */
119 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
120 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
121 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
122 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
123 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
124 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
125 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
126 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
127
128 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
129 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
130 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
131 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
132 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
133 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
134 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
135 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
136 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
137
138 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
139 PORT_IRQ_IF_ERR |
140 PORT_IRQ_CONNECT |
141 PORT_IRQ_PHYRDY |
142 PORT_IRQ_UNK_FIS,
143 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
144 PORT_IRQ_TF_ERR |
145 PORT_IRQ_HBUS_DATA_ERR,
146 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
147 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
148 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
149
150 /* PORT_CMD bits */
151 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
152 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
153 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
154 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
155 PORT_CMD_CLO = (1 << 3), /* Command list override */
156 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
157 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
158 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
159
160 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
161 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
162 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
163 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
164
165 /* hpriv->flags bits */
166 AHCI_FLAG_MSI = (1 << 0),
167
168 /* ap->flags bits */
169 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
170 AHCI_FLAG_NO_NCQ = (1 << 25),
171 };
172
173 struct ahci_cmd_hdr {
174 u32 opts;
175 u32 status;
176 u32 tbl_addr;
177 u32 tbl_addr_hi;
178 u32 reserved[4];
179 };
180
181 struct ahci_sg {
182 u32 addr;
183 u32 addr_hi;
184 u32 reserved;
185 u32 flags_size;
186 };
187
188 struct ahci_host_priv {
189 unsigned long flags;
190 u32 cap; /* cache of HOST_CAP register */
191 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
192 };
193
194 struct ahci_port_priv {
195 struct ahci_cmd_hdr *cmd_slot;
196 dma_addr_t cmd_slot_dma;
197 void *cmd_tbl;
198 dma_addr_t cmd_tbl_dma;
199 void *rx_fis;
200 dma_addr_t rx_fis_dma;
201 };
202
203 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
204 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
205 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
206 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
207 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
208 static void ahci_irq_clear(struct ata_port *ap);
209 static int ahci_port_start(struct ata_port *ap);
210 static void ahci_port_stop(struct ata_port *ap);
211 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
212 static void ahci_qc_prep(struct ata_queued_cmd *qc);
213 static u8 ahci_check_status(struct ata_port *ap);
214 static void ahci_freeze(struct ata_port *ap);
215 static void ahci_thaw(struct ata_port *ap);
216 static void ahci_error_handler(struct ata_port *ap);
217 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
218 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
219 static int ahci_port_resume(struct ata_port *ap);
220 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
221 static int ahci_pci_device_resume(struct pci_dev *pdev);
222 static void ahci_remove_one (struct pci_dev *pdev);
223
224 static struct scsi_host_template ahci_sht = {
225 .module = THIS_MODULE,
226 .name = DRV_NAME,
227 .ioctl = ata_scsi_ioctl,
228 .queuecommand = ata_scsi_queuecmd,
229 .change_queue_depth = ata_scsi_change_queue_depth,
230 .can_queue = AHCI_MAX_CMDS - 1,
231 .this_id = ATA_SHT_THIS_ID,
232 .sg_tablesize = AHCI_MAX_SG,
233 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
234 .emulated = ATA_SHT_EMULATED,
235 .use_clustering = AHCI_USE_CLUSTERING,
236 .proc_name = DRV_NAME,
237 .dma_boundary = AHCI_DMA_BOUNDARY,
238 .slave_configure = ata_scsi_slave_config,
239 .slave_destroy = ata_scsi_slave_destroy,
240 .bios_param = ata_std_bios_param,
241 .suspend = ata_scsi_device_suspend,
242 .resume = ata_scsi_device_resume,
243 };
244
245 static const struct ata_port_operations ahci_ops = {
246 .port_disable = ata_port_disable,
247
248 .check_status = ahci_check_status,
249 .check_altstatus = ahci_check_status,
250 .dev_select = ata_noop_dev_select,
251
252 .tf_read = ahci_tf_read,
253
254 .qc_prep = ahci_qc_prep,
255 .qc_issue = ahci_qc_issue,
256
257 .irq_handler = ahci_interrupt,
258 .irq_clear = ahci_irq_clear,
259
260 .scr_read = ahci_scr_read,
261 .scr_write = ahci_scr_write,
262
263 .freeze = ahci_freeze,
264 .thaw = ahci_thaw,
265
266 .error_handler = ahci_error_handler,
267 .post_internal_cmd = ahci_post_internal_cmd,
268
269 .port_suspend = ahci_port_suspend,
270 .port_resume = ahci_port_resume,
271
272 .port_start = ahci_port_start,
273 .port_stop = ahci_port_stop,
274 };
275
276 static const struct ata_port_info ahci_port_info[] = {
277 /* board_ahci */
278 {
279 .sht = &ahci_sht,
280 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
281 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
282 ATA_FLAG_SKIP_D2H_BSY,
283 .pio_mask = 0x1f, /* pio0-4 */
284 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
285 .port_ops = &ahci_ops,
286 },
287 /* board_ahci_vt8251 */
288 {
289 .sht = &ahci_sht,
290 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
291 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
292 ATA_FLAG_SKIP_D2H_BSY |
293 AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
294 .pio_mask = 0x1f, /* pio0-4 */
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &ahci_ops,
297 },
298 };
299
300 static const struct pci_device_id ahci_pci_tbl[] = {
301 /* Intel */
302 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
303 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
304 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
305 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
306 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
307 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
308 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
309 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
310 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
311 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
312 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
313 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
314 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
315 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
316 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
317
318 /* JMicron */
319 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci }, /* JMicron JMB360 */
320 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci }, /* JMicron JMB361 */
321 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci }, /* JMicron JMB363 */
322 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci }, /* JMicron JMB365 */
323 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci }, /* JMicron JMB366 */
324
325 /* ATI */
326 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
327 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
328
329 /* VIA */
330 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
331
332 /* NVIDIA */
333 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
337
338 /* SiS */
339 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
340 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
341 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
342
343 { } /* terminate list */
344 };
345
346
347 static struct pci_driver ahci_pci_driver = {
348 .name = DRV_NAME,
349 .id_table = ahci_pci_tbl,
350 .probe = ahci_init_one,
351 .suspend = ahci_pci_device_suspend,
352 .resume = ahci_pci_device_resume,
353 .remove = ahci_remove_one,
354 };
355
356
357 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
358 {
359 return base + 0x100 + (port * 0x80);
360 }
361
362 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
363 {
364 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
365 }
366
367 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
368 {
369 unsigned int sc_reg;
370
371 switch (sc_reg_in) {
372 case SCR_STATUS: sc_reg = 0; break;
373 case SCR_CONTROL: sc_reg = 1; break;
374 case SCR_ERROR: sc_reg = 2; break;
375 case SCR_ACTIVE: sc_reg = 3; break;
376 default:
377 return 0xffffffffU;
378 }
379
380 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
381 }
382
383
384 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
385 u32 val)
386 {
387 unsigned int sc_reg;
388
389 switch (sc_reg_in) {
390 case SCR_STATUS: sc_reg = 0; break;
391 case SCR_CONTROL: sc_reg = 1; break;
392 case SCR_ERROR: sc_reg = 2; break;
393 case SCR_ACTIVE: sc_reg = 3; break;
394 default:
395 return;
396 }
397
398 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
399 }
400
401 static void ahci_start_engine(void __iomem *port_mmio)
402 {
403 u32 tmp;
404
405 /* start DMA */
406 tmp = readl(port_mmio + PORT_CMD);
407 tmp |= PORT_CMD_START;
408 writel(tmp, port_mmio + PORT_CMD);
409 readl(port_mmio + PORT_CMD); /* flush */
410 }
411
412 static int ahci_stop_engine(void __iomem *port_mmio)
413 {
414 u32 tmp;
415
416 tmp = readl(port_mmio + PORT_CMD);
417
418 /* check if the HBA is idle */
419 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
420 return 0;
421
422 /* setting HBA to idle */
423 tmp &= ~PORT_CMD_START;
424 writel(tmp, port_mmio + PORT_CMD);
425
426 /* wait for engine to stop. This could be as long as 500 msec */
427 tmp = ata_wait_register(port_mmio + PORT_CMD,
428 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
429 if (tmp & PORT_CMD_LIST_ON)
430 return -EIO;
431
432 return 0;
433 }
434
435 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
436 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
437 {
438 u32 tmp;
439
440 /* set FIS registers */
441 if (cap & HOST_CAP_64)
442 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
443 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
444
445 if (cap & HOST_CAP_64)
446 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
447 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
448
449 /* enable FIS reception */
450 tmp = readl(port_mmio + PORT_CMD);
451 tmp |= PORT_CMD_FIS_RX;
452 writel(tmp, port_mmio + PORT_CMD);
453
454 /* flush */
455 readl(port_mmio + PORT_CMD);
456 }
457
458 static int ahci_stop_fis_rx(void __iomem *port_mmio)
459 {
460 u32 tmp;
461
462 /* disable FIS reception */
463 tmp = readl(port_mmio + PORT_CMD);
464 tmp &= ~PORT_CMD_FIS_RX;
465 writel(tmp, port_mmio + PORT_CMD);
466
467 /* wait for completion, spec says 500ms, give it 1000 */
468 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
469 PORT_CMD_FIS_ON, 10, 1000);
470 if (tmp & PORT_CMD_FIS_ON)
471 return -EBUSY;
472
473 return 0;
474 }
475
476 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
477 {
478 u32 cmd;
479
480 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
481
482 /* spin up device */
483 if (cap & HOST_CAP_SSS) {
484 cmd |= PORT_CMD_SPIN_UP;
485 writel(cmd, port_mmio + PORT_CMD);
486 }
487
488 /* wake up link */
489 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
490 }
491
492 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
493 {
494 u32 cmd, scontrol;
495
496 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
497
498 if (cap & HOST_CAP_SSC) {
499 /* enable transitions to slumber mode */
500 scontrol = readl(port_mmio + PORT_SCR_CTL);
501 if ((scontrol & 0x0f00) > 0x100) {
502 scontrol &= ~0xf00;
503 writel(scontrol, port_mmio + PORT_SCR_CTL);
504 }
505
506 /* put device into slumber mode */
507 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
508
509 /* wait for the transition to complete */
510 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
511 PORT_CMD_ICC_SLUMBER, 1, 50);
512 }
513
514 /* put device into listen mode */
515 if (cap & HOST_CAP_SSS) {
516 /* first set PxSCTL.DET to 0 */
517 scontrol = readl(port_mmio + PORT_SCR_CTL);
518 scontrol &= ~0xf;
519 writel(scontrol, port_mmio + PORT_SCR_CTL);
520
521 /* then set PxCMD.SUD to 0 */
522 cmd &= ~PORT_CMD_SPIN_UP;
523 writel(cmd, port_mmio + PORT_CMD);
524 }
525 }
526
527 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
528 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
529 {
530 /* power up */
531 ahci_power_up(port_mmio, cap);
532
533 /* enable FIS reception */
534 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
535
536 /* enable DMA */
537 ahci_start_engine(port_mmio);
538 }
539
540 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
541 {
542 int rc;
543
544 /* disable DMA */
545 rc = ahci_stop_engine(port_mmio);
546 if (rc) {
547 *emsg = "failed to stop engine";
548 return rc;
549 }
550
551 /* disable FIS reception */
552 rc = ahci_stop_fis_rx(port_mmio);
553 if (rc) {
554 *emsg = "failed stop FIS RX";
555 return rc;
556 }
557
558 /* put device into slumber mode */
559 ahci_power_down(port_mmio, cap);
560
561 return 0;
562 }
563
564 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
565 {
566 u32 cap_save, tmp;
567
568 cap_save = readl(mmio + HOST_CAP);
569 cap_save &= ( (1<<28) | (1<<17) );
570 cap_save |= (1 << 27);
571
572 /* global controller reset */
573 tmp = readl(mmio + HOST_CTL);
574 if ((tmp & HOST_RESET) == 0) {
575 writel(tmp | HOST_RESET, mmio + HOST_CTL);
576 readl(mmio + HOST_CTL); /* flush */
577 }
578
579 /* reset must complete within 1 second, or
580 * the hardware should be considered fried.
581 */
582 ssleep(1);
583
584 tmp = readl(mmio + HOST_CTL);
585 if (tmp & HOST_RESET) {
586 dev_printk(KERN_ERR, &pdev->dev,
587 "controller reset failed (0x%x)\n", tmp);
588 return -EIO;
589 }
590
591 writel(HOST_AHCI_EN, mmio + HOST_CTL);
592 (void) readl(mmio + HOST_CTL); /* flush */
593 writel(cap_save, mmio + HOST_CAP);
594 writel(0xf, mmio + HOST_PORTS_IMPL);
595 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
596
597 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
598 u16 tmp16;
599
600 /* configure PCS */
601 pci_read_config_word(pdev, 0x92, &tmp16);
602 tmp16 |= 0xf;
603 pci_write_config_word(pdev, 0x92, tmp16);
604 }
605
606 return 0;
607 }
608
609 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
610 int n_ports, u32 cap)
611 {
612 int i, rc;
613 u32 tmp;
614
615 for (i = 0; i < n_ports; i++) {
616 void __iomem *port_mmio = ahci_port_base(mmio, i);
617 const char *emsg = NULL;
618
619 #if 0 /* BIOSen initialize this incorrectly */
620 if (!(hpriv->port_map & (1 << i)))
621 continue;
622 #endif
623
624 /* make sure port is not active */
625 rc = ahci_deinit_port(port_mmio, cap, &emsg);
626 if (rc)
627 dev_printk(KERN_WARNING, &pdev->dev,
628 "%s (%d)\n", emsg, rc);
629
630 /* clear SError */
631 tmp = readl(port_mmio + PORT_SCR_ERR);
632 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
633 writel(tmp, port_mmio + PORT_SCR_ERR);
634
635 /* clear port IRQ */
636 tmp = readl(port_mmio + PORT_IRQ_STAT);
637 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
638 if (tmp)
639 writel(tmp, port_mmio + PORT_IRQ_STAT);
640
641 writel(1 << i, mmio + HOST_IRQ_STAT);
642 }
643
644 tmp = readl(mmio + HOST_CTL);
645 VPRINTK("HOST_CTL 0x%x\n", tmp);
646 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
647 tmp = readl(mmio + HOST_CTL);
648 VPRINTK("HOST_CTL 0x%x\n", tmp);
649 }
650
651 static unsigned int ahci_dev_classify(struct ata_port *ap)
652 {
653 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
654 struct ata_taskfile tf;
655 u32 tmp;
656
657 tmp = readl(port_mmio + PORT_SIG);
658 tf.lbah = (tmp >> 24) & 0xff;
659 tf.lbam = (tmp >> 16) & 0xff;
660 tf.lbal = (tmp >> 8) & 0xff;
661 tf.nsect = (tmp) & 0xff;
662
663 return ata_dev_classify(&tf);
664 }
665
666 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
667 u32 opts)
668 {
669 dma_addr_t cmd_tbl_dma;
670
671 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
672
673 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
674 pp->cmd_slot[tag].status = 0;
675 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
676 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
677 }
678
679 static int ahci_clo(struct ata_port *ap)
680 {
681 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
682 struct ahci_host_priv *hpriv = ap->host->private_data;
683 u32 tmp;
684
685 if (!(hpriv->cap & HOST_CAP_CLO))
686 return -EOPNOTSUPP;
687
688 tmp = readl(port_mmio + PORT_CMD);
689 tmp |= PORT_CMD_CLO;
690 writel(tmp, port_mmio + PORT_CMD);
691
692 tmp = ata_wait_register(port_mmio + PORT_CMD,
693 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
694 if (tmp & PORT_CMD_CLO)
695 return -EIO;
696
697 return 0;
698 }
699
700 static int ahci_prereset(struct ata_port *ap)
701 {
702 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
703 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
704 /* ATA_BUSY hasn't cleared, so send a CLO */
705 ahci_clo(ap);
706 }
707
708 return ata_std_prereset(ap);
709 }
710
711 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
712 {
713 struct ahci_port_priv *pp = ap->private_data;
714 void __iomem *mmio = ap->host->mmio_base;
715 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
716 const u32 cmd_fis_len = 5; /* five dwords */
717 const char *reason = NULL;
718 struct ata_taskfile tf;
719 u32 tmp;
720 u8 *fis;
721 int rc;
722
723 DPRINTK("ENTER\n");
724
725 if (ata_port_offline(ap)) {
726 DPRINTK("PHY reports no device\n");
727 *class = ATA_DEV_NONE;
728 return 0;
729 }
730
731 /* prepare for SRST (AHCI-1.1 10.4.1) */
732 rc = ahci_stop_engine(port_mmio);
733 if (rc) {
734 reason = "failed to stop engine";
735 goto fail_restart;
736 }
737
738 /* check BUSY/DRQ, perform Command List Override if necessary */
739 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
740 rc = ahci_clo(ap);
741
742 if (rc == -EOPNOTSUPP) {
743 reason = "port busy but CLO unavailable";
744 goto fail_restart;
745 } else if (rc) {
746 reason = "port busy but CLO failed";
747 goto fail_restart;
748 }
749 }
750
751 /* restart engine */
752 ahci_start_engine(port_mmio);
753
754 ata_tf_init(ap->device, &tf);
755 fis = pp->cmd_tbl;
756
757 /* issue the first D2H Register FIS */
758 ahci_fill_cmd_slot(pp, 0,
759 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
760
761 tf.ctl |= ATA_SRST;
762 ata_tf_to_fis(&tf, fis, 0);
763 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
764
765 writel(1, port_mmio + PORT_CMD_ISSUE);
766
767 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
768 if (tmp & 0x1) {
769 rc = -EIO;
770 reason = "1st FIS failed";
771 goto fail;
772 }
773
774 /* spec says at least 5us, but be generous and sleep for 1ms */
775 msleep(1);
776
777 /* issue the second D2H Register FIS */
778 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
779
780 tf.ctl &= ~ATA_SRST;
781 ata_tf_to_fis(&tf, fis, 0);
782 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
783
784 writel(1, port_mmio + PORT_CMD_ISSUE);
785 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
786
787 /* spec mandates ">= 2ms" before checking status.
788 * We wait 150ms, because that was the magic delay used for
789 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
790 * between when the ATA command register is written, and then
791 * status is checked. Because waiting for "a while" before
792 * checking status is fine, post SRST, we perform this magic
793 * delay here as well.
794 */
795 msleep(150);
796
797 *class = ATA_DEV_NONE;
798 if (ata_port_online(ap)) {
799 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
800 rc = -EIO;
801 reason = "device not ready";
802 goto fail;
803 }
804 *class = ahci_dev_classify(ap);
805 }
806
807 DPRINTK("EXIT, class=%u\n", *class);
808 return 0;
809
810 fail_restart:
811 ahci_start_engine(port_mmio);
812 fail:
813 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
814 return rc;
815 }
816
817 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
818 {
819 struct ahci_port_priv *pp = ap->private_data;
820 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
821 struct ata_taskfile tf;
822 void __iomem *mmio = ap->host->mmio_base;
823 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
824 int rc;
825
826 DPRINTK("ENTER\n");
827
828 ahci_stop_engine(port_mmio);
829
830 /* clear D2H reception area to properly wait for D2H FIS */
831 ata_tf_init(ap->device, &tf);
832 tf.command = 0xff;
833 ata_tf_to_fis(&tf, d2h_fis, 0);
834
835 rc = sata_std_hardreset(ap, class);
836
837 ahci_start_engine(port_mmio);
838
839 if (rc == 0 && ata_port_online(ap))
840 *class = ahci_dev_classify(ap);
841 if (*class == ATA_DEV_UNKNOWN)
842 *class = ATA_DEV_NONE;
843
844 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
845 return rc;
846 }
847
848 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
849 {
850 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
851 u32 new_tmp, tmp;
852
853 ata_std_postreset(ap, class);
854
855 /* Make sure port's ATAPI bit is set appropriately */
856 new_tmp = tmp = readl(port_mmio + PORT_CMD);
857 if (*class == ATA_DEV_ATAPI)
858 new_tmp |= PORT_CMD_ATAPI;
859 else
860 new_tmp &= ~PORT_CMD_ATAPI;
861 if (new_tmp != tmp) {
862 writel(new_tmp, port_mmio + PORT_CMD);
863 readl(port_mmio + PORT_CMD); /* flush */
864 }
865 }
866
867 static u8 ahci_check_status(struct ata_port *ap)
868 {
869 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
870
871 return readl(mmio + PORT_TFDATA) & 0xFF;
872 }
873
874 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
875 {
876 struct ahci_port_priv *pp = ap->private_data;
877 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
878
879 ata_tf_from_fis(d2h_fis, tf);
880 }
881
882 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
883 {
884 struct scatterlist *sg;
885 struct ahci_sg *ahci_sg;
886 unsigned int n_sg = 0;
887
888 VPRINTK("ENTER\n");
889
890 /*
891 * Next, the S/G list.
892 */
893 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
894 ata_for_each_sg(sg, qc) {
895 dma_addr_t addr = sg_dma_address(sg);
896 u32 sg_len = sg_dma_len(sg);
897
898 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
899 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
900 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
901
902 ahci_sg++;
903 n_sg++;
904 }
905
906 return n_sg;
907 }
908
909 static void ahci_qc_prep(struct ata_queued_cmd *qc)
910 {
911 struct ata_port *ap = qc->ap;
912 struct ahci_port_priv *pp = ap->private_data;
913 int is_atapi = is_atapi_taskfile(&qc->tf);
914 void *cmd_tbl;
915 u32 opts;
916 const u32 cmd_fis_len = 5; /* five dwords */
917 unsigned int n_elem;
918
919 /*
920 * Fill in command table information. First, the header,
921 * a SATA Register - Host to Device command FIS.
922 */
923 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
924
925 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
926 if (is_atapi) {
927 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
928 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
929 }
930
931 n_elem = 0;
932 if (qc->flags & ATA_QCFLAG_DMAMAP)
933 n_elem = ahci_fill_sg(qc, cmd_tbl);
934
935 /*
936 * Fill in command slot information.
937 */
938 opts = cmd_fis_len | n_elem << 16;
939 if (qc->tf.flags & ATA_TFLAG_WRITE)
940 opts |= AHCI_CMD_WRITE;
941 if (is_atapi)
942 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
943
944 ahci_fill_cmd_slot(pp, qc->tag, opts);
945 }
946
947 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
948 {
949 struct ahci_port_priv *pp = ap->private_data;
950 struct ata_eh_info *ehi = &ap->eh_info;
951 unsigned int err_mask = 0, action = 0;
952 struct ata_queued_cmd *qc;
953 u32 serror;
954
955 ata_ehi_clear_desc(ehi);
956
957 /* AHCI needs SError cleared; otherwise, it might lock up */
958 serror = ahci_scr_read(ap, SCR_ERROR);
959 ahci_scr_write(ap, SCR_ERROR, serror);
960
961 /* analyze @irq_stat */
962 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
963
964 if (irq_stat & PORT_IRQ_TF_ERR)
965 err_mask |= AC_ERR_DEV;
966
967 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
968 err_mask |= AC_ERR_HOST_BUS;
969 action |= ATA_EH_SOFTRESET;
970 }
971
972 if (irq_stat & PORT_IRQ_IF_ERR) {
973 err_mask |= AC_ERR_ATA_BUS;
974 action |= ATA_EH_SOFTRESET;
975 ata_ehi_push_desc(ehi, ", interface fatal error");
976 }
977
978 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
979 ata_ehi_hotplugged(ehi);
980 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
981 "connection status changed" : "PHY RDY changed");
982 }
983
984 if (irq_stat & PORT_IRQ_UNK_FIS) {
985 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
986
987 err_mask |= AC_ERR_HSM;
988 action |= ATA_EH_SOFTRESET;
989 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
990 unk[0], unk[1], unk[2], unk[3]);
991 }
992
993 /* okay, let's hand over to EH */
994 ehi->serror |= serror;
995 ehi->action |= action;
996
997 qc = ata_qc_from_tag(ap, ap->active_tag);
998 if (qc)
999 qc->err_mask |= err_mask;
1000 else
1001 ehi->err_mask |= err_mask;
1002
1003 if (irq_stat & PORT_IRQ_FREEZE)
1004 ata_port_freeze(ap);
1005 else
1006 ata_port_abort(ap);
1007 }
1008
1009 static void ahci_host_intr(struct ata_port *ap)
1010 {
1011 void __iomem *mmio = ap->host->mmio_base;
1012 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1013 struct ata_eh_info *ehi = &ap->eh_info;
1014 u32 status, qc_active;
1015 int rc;
1016
1017 status = readl(port_mmio + PORT_IRQ_STAT);
1018 writel(status, port_mmio + PORT_IRQ_STAT);
1019
1020 if (unlikely(status & PORT_IRQ_ERROR)) {
1021 ahci_error_intr(ap, status);
1022 return;
1023 }
1024
1025 if (ap->sactive)
1026 qc_active = readl(port_mmio + PORT_SCR_ACT);
1027 else
1028 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1029
1030 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1031 if (rc > 0)
1032 return;
1033 if (rc < 0) {
1034 ehi->err_mask |= AC_ERR_HSM;
1035 ehi->action |= ATA_EH_SOFTRESET;
1036 ata_port_freeze(ap);
1037 return;
1038 }
1039
1040 /* hmmm... a spurious interupt */
1041
1042 /* some devices send D2H reg with I bit set during NCQ command phase */
1043 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1044 return;
1045
1046 /* ignore interim PIO setup fis interrupts */
1047 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1048 return;
1049
1050 if (ata_ratelimit())
1051 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1052 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1053 status, ap->active_tag, ap->sactive);
1054 }
1055
1056 static void ahci_irq_clear(struct ata_port *ap)
1057 {
1058 /* TODO */
1059 }
1060
1061 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1062 {
1063 struct ata_host *host = dev_instance;
1064 struct ahci_host_priv *hpriv;
1065 unsigned int i, handled = 0;
1066 void __iomem *mmio;
1067 u32 irq_stat, irq_ack = 0;
1068
1069 VPRINTK("ENTER\n");
1070
1071 hpriv = host->private_data;
1072 mmio = host->mmio_base;
1073
1074 /* sigh. 0xffffffff is a valid return from h/w */
1075 irq_stat = readl(mmio + HOST_IRQ_STAT);
1076 irq_stat &= hpriv->port_map;
1077 if (!irq_stat)
1078 return IRQ_NONE;
1079
1080 spin_lock(&host->lock);
1081
1082 for (i = 0; i < host->n_ports; i++) {
1083 struct ata_port *ap;
1084
1085 if (!(irq_stat & (1 << i)))
1086 continue;
1087
1088 ap = host->ports[i];
1089 if (ap) {
1090 ahci_host_intr(ap);
1091 VPRINTK("port %u\n", i);
1092 } else {
1093 VPRINTK("port %u (no irq)\n", i);
1094 if (ata_ratelimit())
1095 dev_printk(KERN_WARNING, host->dev,
1096 "interrupt on disabled port %u\n", i);
1097 }
1098
1099 irq_ack |= (1 << i);
1100 }
1101
1102 if (irq_ack) {
1103 writel(irq_ack, mmio + HOST_IRQ_STAT);
1104 handled = 1;
1105 }
1106
1107 spin_unlock(&host->lock);
1108
1109 VPRINTK("EXIT\n");
1110
1111 return IRQ_RETVAL(handled);
1112 }
1113
1114 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1115 {
1116 struct ata_port *ap = qc->ap;
1117 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1118
1119 if (qc->tf.protocol == ATA_PROT_NCQ)
1120 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1121 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1122 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1123
1124 return 0;
1125 }
1126
1127 static void ahci_freeze(struct ata_port *ap)
1128 {
1129 void __iomem *mmio = ap->host->mmio_base;
1130 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1131
1132 /* turn IRQ off */
1133 writel(0, port_mmio + PORT_IRQ_MASK);
1134 }
1135
1136 static void ahci_thaw(struct ata_port *ap)
1137 {
1138 void __iomem *mmio = ap->host->mmio_base;
1139 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1140 u32 tmp;
1141
1142 /* clear IRQ */
1143 tmp = readl(port_mmio + PORT_IRQ_STAT);
1144 writel(tmp, port_mmio + PORT_IRQ_STAT);
1145 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1146
1147 /* turn IRQ back on */
1148 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1149 }
1150
1151 static void ahci_error_handler(struct ata_port *ap)
1152 {
1153 void __iomem *mmio = ap->host->mmio_base;
1154 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1155
1156 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1157 /* restart engine */
1158 ahci_stop_engine(port_mmio);
1159 ahci_start_engine(port_mmio);
1160 }
1161
1162 /* perform recovery */
1163 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
1164 ahci_postreset);
1165 }
1166
1167 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1168 {
1169 struct ata_port *ap = qc->ap;
1170 void __iomem *mmio = ap->host->mmio_base;
1171 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1172
1173 if (qc->flags & ATA_QCFLAG_FAILED)
1174 qc->err_mask |= AC_ERR_OTHER;
1175
1176 if (qc->err_mask) {
1177 /* make DMA engine forget about the failed command */
1178 ahci_stop_engine(port_mmio);
1179 ahci_start_engine(port_mmio);
1180 }
1181 }
1182
1183 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1184 {
1185 struct ahci_host_priv *hpriv = ap->host->private_data;
1186 struct ahci_port_priv *pp = ap->private_data;
1187 void __iomem *mmio = ap->host->mmio_base;
1188 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1189 const char *emsg = NULL;
1190 int rc;
1191
1192 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1193 if (rc) {
1194 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1195 ahci_init_port(port_mmio, hpriv->cap,
1196 pp->cmd_slot_dma, pp->rx_fis_dma);
1197 }
1198
1199 return rc;
1200 }
1201
1202 static int ahci_port_resume(struct ata_port *ap)
1203 {
1204 struct ahci_port_priv *pp = ap->private_data;
1205 struct ahci_host_priv *hpriv = ap->host->private_data;
1206 void __iomem *mmio = ap->host->mmio_base;
1207 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1208
1209 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1210
1211 return 0;
1212 }
1213
1214 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1215 {
1216 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1217 void __iomem *mmio = host->mmio_base;
1218 u32 ctl;
1219
1220 if (mesg.event == PM_EVENT_SUSPEND) {
1221 /* AHCI spec rev1.1 section 8.3.3:
1222 * Software must disable interrupts prior to requesting a
1223 * transition of the HBA to D3 state.
1224 */
1225 ctl = readl(mmio + HOST_CTL);
1226 ctl &= ~HOST_IRQ_EN;
1227 writel(ctl, mmio + HOST_CTL);
1228 readl(mmio + HOST_CTL); /* flush */
1229 }
1230
1231 return ata_pci_device_suspend(pdev, mesg);
1232 }
1233
1234 static int ahci_pci_device_resume(struct pci_dev *pdev)
1235 {
1236 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1237 struct ahci_host_priv *hpriv = host->private_data;
1238 void __iomem *mmio = host->mmio_base;
1239 int rc;
1240
1241 ata_pci_device_do_resume(pdev);
1242
1243 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1244 rc = ahci_reset_controller(mmio, pdev);
1245 if (rc)
1246 return rc;
1247
1248 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
1249 }
1250
1251 ata_host_resume(host);
1252
1253 return 0;
1254 }
1255
1256 static int ahci_port_start(struct ata_port *ap)
1257 {
1258 struct device *dev = ap->host->dev;
1259 struct ahci_host_priv *hpriv = ap->host->private_data;
1260 struct ahci_port_priv *pp;
1261 void __iomem *mmio = ap->host->mmio_base;
1262 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1263 void *mem;
1264 dma_addr_t mem_dma;
1265 int rc;
1266
1267 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1268 if (!pp)
1269 return -ENOMEM;
1270 memset(pp, 0, sizeof(*pp));
1271
1272 rc = ata_pad_alloc(ap, dev);
1273 if (rc) {
1274 kfree(pp);
1275 return rc;
1276 }
1277
1278 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1279 if (!mem) {
1280 ata_pad_free(ap, dev);
1281 kfree(pp);
1282 return -ENOMEM;
1283 }
1284 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1285
1286 /*
1287 * First item in chunk of DMA memory: 32-slot command table,
1288 * 32 bytes each in size
1289 */
1290 pp->cmd_slot = mem;
1291 pp->cmd_slot_dma = mem_dma;
1292
1293 mem += AHCI_CMD_SLOT_SZ;
1294 mem_dma += AHCI_CMD_SLOT_SZ;
1295
1296 /*
1297 * Second item: Received-FIS area
1298 */
1299 pp->rx_fis = mem;
1300 pp->rx_fis_dma = mem_dma;
1301
1302 mem += AHCI_RX_FIS_SZ;
1303 mem_dma += AHCI_RX_FIS_SZ;
1304
1305 /*
1306 * Third item: data area for storing a single command
1307 * and its scatter-gather table
1308 */
1309 pp->cmd_tbl = mem;
1310 pp->cmd_tbl_dma = mem_dma;
1311
1312 ap->private_data = pp;
1313
1314 /* initialize port */
1315 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1316
1317 return 0;
1318 }
1319
1320 static void ahci_port_stop(struct ata_port *ap)
1321 {
1322 struct device *dev = ap->host->dev;
1323 struct ahci_host_priv *hpriv = ap->host->private_data;
1324 struct ahci_port_priv *pp = ap->private_data;
1325 void __iomem *mmio = ap->host->mmio_base;
1326 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1327 const char *emsg = NULL;
1328 int rc;
1329
1330 /* de-initialize port */
1331 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1332 if (rc)
1333 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1334
1335 ap->private_data = NULL;
1336 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1337 pp->cmd_slot, pp->cmd_slot_dma);
1338 ata_pad_free(ap, dev);
1339 kfree(pp);
1340 }
1341
1342 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1343 unsigned int port_idx)
1344 {
1345 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1346 base = ahci_port_base_ul(base, port_idx);
1347 VPRINTK("base now==0x%lx\n", base);
1348
1349 port->cmd_addr = base;
1350 port->scr_addr = base + PORT_SCR;
1351
1352 VPRINTK("EXIT\n");
1353 }
1354
1355 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1356 {
1357 struct ahci_host_priv *hpriv = probe_ent->private_data;
1358 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1359 void __iomem *mmio = probe_ent->mmio_base;
1360 unsigned int i, using_dac;
1361 int rc;
1362
1363 rc = ahci_reset_controller(mmio, pdev);
1364 if (rc)
1365 return rc;
1366
1367 hpriv->cap = readl(mmio + HOST_CAP);
1368 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1369 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1370
1371 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1372 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1373
1374 using_dac = hpriv->cap & HOST_CAP_64;
1375 if (using_dac &&
1376 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1377 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1378 if (rc) {
1379 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1380 if (rc) {
1381 dev_printk(KERN_ERR, &pdev->dev,
1382 "64-bit DMA enable failed\n");
1383 return rc;
1384 }
1385 }
1386 } else {
1387 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1388 if (rc) {
1389 dev_printk(KERN_ERR, &pdev->dev,
1390 "32-bit DMA enable failed\n");
1391 return rc;
1392 }
1393 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1394 if (rc) {
1395 dev_printk(KERN_ERR, &pdev->dev,
1396 "32-bit consistent DMA enable failed\n");
1397 return rc;
1398 }
1399 }
1400
1401 for (i = 0; i < probe_ent->n_ports; i++)
1402 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1403
1404 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1405
1406 pci_set_master(pdev);
1407
1408 return 0;
1409 }
1410
1411 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1412 {
1413 struct ahci_host_priv *hpriv = probe_ent->private_data;
1414 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1415 void __iomem *mmio = probe_ent->mmio_base;
1416 u32 vers, cap, impl, speed;
1417 const char *speed_s;
1418 u16 cc;
1419 const char *scc_s;
1420
1421 vers = readl(mmio + HOST_VERSION);
1422 cap = hpriv->cap;
1423 impl = hpriv->port_map;
1424
1425 speed = (cap >> 20) & 0xf;
1426 if (speed == 1)
1427 speed_s = "1.5";
1428 else if (speed == 2)
1429 speed_s = "3";
1430 else
1431 speed_s = "?";
1432
1433 pci_read_config_word(pdev, 0x0a, &cc);
1434 if (cc == 0x0101)
1435 scc_s = "IDE";
1436 else if (cc == 0x0106)
1437 scc_s = "SATA";
1438 else if (cc == 0x0104)
1439 scc_s = "RAID";
1440 else
1441 scc_s = "unknown";
1442
1443 dev_printk(KERN_INFO, &pdev->dev,
1444 "AHCI %02x%02x.%02x%02x "
1445 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1446 ,
1447
1448 (vers >> 24) & 0xff,
1449 (vers >> 16) & 0xff,
1450 (vers >> 8) & 0xff,
1451 vers & 0xff,
1452
1453 ((cap >> 8) & 0x1f) + 1,
1454 (cap & 0x1f) + 1,
1455 speed_s,
1456 impl,
1457 scc_s);
1458
1459 dev_printk(KERN_INFO, &pdev->dev,
1460 "flags: "
1461 "%s%s%s%s%s%s"
1462 "%s%s%s%s%s%s%s\n"
1463 ,
1464
1465 cap & (1 << 31) ? "64bit " : "",
1466 cap & (1 << 30) ? "ncq " : "",
1467 cap & (1 << 28) ? "ilck " : "",
1468 cap & (1 << 27) ? "stag " : "",
1469 cap & (1 << 26) ? "pm " : "",
1470 cap & (1 << 25) ? "led " : "",
1471
1472 cap & (1 << 24) ? "clo " : "",
1473 cap & (1 << 19) ? "nz " : "",
1474 cap & (1 << 18) ? "only " : "",
1475 cap & (1 << 17) ? "pmp " : "",
1476 cap & (1 << 15) ? "pio " : "",
1477 cap & (1 << 14) ? "slum " : "",
1478 cap & (1 << 13) ? "part " : ""
1479 );
1480 }
1481
1482 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1483 {
1484 static int printed_version;
1485 struct ata_probe_ent *probe_ent = NULL;
1486 struct ahci_host_priv *hpriv;
1487 unsigned long base;
1488 void __iomem *mmio_base;
1489 unsigned int board_idx = (unsigned int) ent->driver_data;
1490 int have_msi, pci_dev_busy = 0;
1491 int rc;
1492
1493 VPRINTK("ENTER\n");
1494
1495 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1496
1497 if (!printed_version++)
1498 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1499
1500 /* JMicron-specific fixup: make sure we're in AHCI mode */
1501 /* This is protected from races with ata_jmicron by the pci probe
1502 locking */
1503 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1504 /* AHCI enable, AHCI on function 0 */
1505 pci_write_config_byte(pdev, 0x41, 0xa1);
1506 /* Function 1 is the PATA controller */
1507 if (PCI_FUNC(pdev->devfn))
1508 return -ENODEV;
1509 }
1510
1511 rc = pci_enable_device(pdev);
1512 if (rc)
1513 return rc;
1514
1515 rc = pci_request_regions(pdev, DRV_NAME);
1516 if (rc) {
1517 pci_dev_busy = 1;
1518 goto err_out;
1519 }
1520
1521 if (pci_enable_msi(pdev) == 0)
1522 have_msi = 1;
1523 else {
1524 pci_intx(pdev, 1);
1525 have_msi = 0;
1526 }
1527
1528 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1529 if (probe_ent == NULL) {
1530 rc = -ENOMEM;
1531 goto err_out_msi;
1532 }
1533
1534 memset(probe_ent, 0, sizeof(*probe_ent));
1535 probe_ent->dev = pci_dev_to_dev(pdev);
1536 INIT_LIST_HEAD(&probe_ent->node);
1537
1538 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1539 if (mmio_base == NULL) {
1540 rc = -ENOMEM;
1541 goto err_out_free_ent;
1542 }
1543 base = (unsigned long) mmio_base;
1544
1545 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1546 if (!hpriv) {
1547 rc = -ENOMEM;
1548 goto err_out_iounmap;
1549 }
1550 memset(hpriv, 0, sizeof(*hpriv));
1551
1552 probe_ent->sht = ahci_port_info[board_idx].sht;
1553 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1554 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1555 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1556 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1557
1558 probe_ent->irq = pdev->irq;
1559 probe_ent->irq_flags = IRQF_SHARED;
1560 probe_ent->mmio_base = mmio_base;
1561 probe_ent->private_data = hpriv;
1562
1563 if (have_msi)
1564 hpriv->flags |= AHCI_FLAG_MSI;
1565
1566 /* initialize adapter */
1567 rc = ahci_host_init(probe_ent);
1568 if (rc)
1569 goto err_out_hpriv;
1570
1571 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1572 (hpriv->cap & HOST_CAP_NCQ))
1573 probe_ent->port_flags |= ATA_FLAG_NCQ;
1574
1575 ahci_print_info(probe_ent);
1576
1577 /* FIXME: check ata_device_add return value */
1578 ata_device_add(probe_ent);
1579 kfree(probe_ent);
1580
1581 return 0;
1582
1583 err_out_hpriv:
1584 kfree(hpriv);
1585 err_out_iounmap:
1586 pci_iounmap(pdev, mmio_base);
1587 err_out_free_ent:
1588 kfree(probe_ent);
1589 err_out_msi:
1590 if (have_msi)
1591 pci_disable_msi(pdev);
1592 else
1593 pci_intx(pdev, 0);
1594 pci_release_regions(pdev);
1595 err_out:
1596 if (!pci_dev_busy)
1597 pci_disable_device(pdev);
1598 return rc;
1599 }
1600
1601 static void ahci_remove_one (struct pci_dev *pdev)
1602 {
1603 struct device *dev = pci_dev_to_dev(pdev);
1604 struct ata_host *host = dev_get_drvdata(dev);
1605 struct ahci_host_priv *hpriv = host->private_data;
1606 unsigned int i;
1607 int have_msi;
1608
1609 for (i = 0; i < host->n_ports; i++)
1610 ata_port_detach(host->ports[i]);
1611
1612 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1613 free_irq(host->irq, host);
1614
1615 for (i = 0; i < host->n_ports; i++) {
1616 struct ata_port *ap = host->ports[i];
1617
1618 ata_scsi_release(ap->scsi_host);
1619 scsi_host_put(ap->scsi_host);
1620 }
1621
1622 kfree(hpriv);
1623 pci_iounmap(pdev, host->mmio_base);
1624 kfree(host);
1625
1626 if (have_msi)
1627 pci_disable_msi(pdev);
1628 else
1629 pci_intx(pdev, 0);
1630 pci_release_regions(pdev);
1631 pci_disable_device(pdev);
1632 dev_set_drvdata(dev, NULL);
1633 }
1634
1635 static int __init ahci_init(void)
1636 {
1637 return pci_register_driver(&ahci_pci_driver);
1638 }
1639
1640 static void __exit ahci_exit(void)
1641 {
1642 pci_unregister_driver(&ahci_pci_driver);
1643 }
1644
1645
1646 MODULE_AUTHOR("Jeff Garzik");
1647 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1648 MODULE_LICENSE("GPL");
1649 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1650 MODULE_VERSION(DRV_VERSION);
1651
1652 module_init(ahci_init);
1653 module_exit(ahci_exit);
Linux kernel - Deliverables
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