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ahci: Gigabyte GA-MA69VM-S2 can't do 64bit DMA
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 /* Enclosure Management Control */
53 #define EM_CTRL_MSG_TYPE 0x000f0000
54
55 /* Enclosure Management LED Message Type */
56 #define EM_MSG_LED_HBA_PORT 0x0000000f
57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
58 #define EM_MSG_LED_VALUE 0xffff0000
59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60 #define EM_MSG_LED_VALUE_OFF 0xfff80000
61 #define EM_MSG_LED_VALUE_ON 0x00010000
62
63 static int ahci_skip_host_reset;
64 static int ahci_ignore_sss;
65
66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
72 static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74 static void ahci_disable_alpm(struct ata_port *ap);
75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
80
81 enum {
82 AHCI_PCI_BAR = 5,
83 AHCI_MAX_PORTS = 32,
84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
86 AHCI_MAX_CMDS = 32,
87 AHCI_CMD_SZ = 32,
88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
89 AHCI_RX_FIS_SZ = 256,
90 AHCI_CMD_TBL_CDB = 0x40,
91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
95 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
99 AHCI_CMD_PREFETCH = (1 << 7),
100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
106
107 board_ahci = 0,
108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
113 board_ahci_mcp65 = 6,
114 board_ahci_nopmp = 7,
115 board_ahci_yesncq = 8,
116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
182 PORT_IRQ_PHYRDY |
183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
191
192 /* PORT_CMD bits */
193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
200 PORT_CMD_CLO = (1 << 3), /* Command list override */
201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
209
210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
223 link offline */
224
225 /* ap->flags bits */
226
227 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
229 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
230 ATA_FLAG_IPM,
231
232 ICH_MAP = 0x90, /* ICH MAP register */
233
234 /* em constants */
235 EM_MAX_SLOTS = 8,
236 EM_MAX_RETRY = 5,
237
238 /* em_ctl bits */
239 EM_CTL_RST = (1 << 9), /* Reset */
240 EM_CTL_TM = (1 << 8), /* Transmit Message */
241 EM_CTL_ALHD = (1 << 26), /* Activity LED */
242 };
243
244 struct ahci_cmd_hdr {
245 __le32 opts;
246 __le32 status;
247 __le32 tbl_addr;
248 __le32 tbl_addr_hi;
249 __le32 reserved[4];
250 };
251
252 struct ahci_sg {
253 __le32 addr;
254 __le32 addr_hi;
255 __le32 reserved;
256 __le32 flags_size;
257 };
258
259 struct ahci_em_priv {
260 enum sw_activity blink_policy;
261 struct timer_list timer;
262 unsigned long saved_activity;
263 unsigned long activity;
264 unsigned long led_state;
265 };
266
267 struct ahci_host_priv {
268 unsigned int flags; /* AHCI_HFLAG_* */
269 u32 cap; /* cap to use */
270 u32 port_map; /* port map to use */
271 u32 saved_cap; /* saved initial cap */
272 u32 saved_port_map; /* saved initial port_map */
273 u32 em_loc; /* enclosure management location */
274 };
275
276 struct ahci_port_priv {
277 struct ata_link *active_link;
278 struct ahci_cmd_hdr *cmd_slot;
279 dma_addr_t cmd_slot_dma;
280 void *cmd_tbl;
281 dma_addr_t cmd_tbl_dma;
282 void *rx_fis;
283 dma_addr_t rx_fis_dma;
284 /* for NCQ spurious interrupt analysis */
285 unsigned int ncq_saw_d2h:1;
286 unsigned int ncq_saw_dmas:1;
287 unsigned int ncq_saw_sdb:1;
288 u32 intr_mask; /* interrupts to enable */
289 /* enclosure management info per PM slot */
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
291 };
292
293 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
294 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
295 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
296 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
297 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
298 static int ahci_port_start(struct ata_port *ap);
299 static void ahci_port_stop(struct ata_port *ap);
300 static void ahci_qc_prep(struct ata_queued_cmd *qc);
301 static void ahci_freeze(struct ata_port *ap);
302 static void ahci_thaw(struct ata_port *ap);
303 static void ahci_pmp_attach(struct ata_port *ap);
304 static void ahci_pmp_detach(struct ata_port *ap);
305 static int ahci_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
307 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
309 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
311 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline);
313 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
314 unsigned long deadline);
315 static void ahci_postreset(struct ata_link *link, unsigned int *class);
316 static void ahci_error_handler(struct ata_port *ap);
317 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
318 static int ahci_port_resume(struct ata_port *ap);
319 static void ahci_dev_config(struct ata_device *dev);
320 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
321 u32 opts);
322 #ifdef CONFIG_PM
323 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
324 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
325 static int ahci_pci_device_resume(struct pci_dev *pdev);
326 #endif
327 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
328 static ssize_t ahci_activity_store(struct ata_device *dev,
329 enum sw_activity val);
330 static void ahci_init_sw_activity(struct ata_link *link);
331
332 static ssize_t ahci_show_host_caps(struct device *dev,
333 struct device_attribute *attr, char *buf);
334 static ssize_t ahci_show_host_version(struct device *dev,
335 struct device_attribute *attr, char *buf);
336 static ssize_t ahci_show_port_cmd(struct device *dev,
337 struct device_attribute *attr, char *buf);
338
339 DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
340 DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
341 DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
342
343 static struct device_attribute *ahci_shost_attrs[] = {
344 &dev_attr_link_power_management_policy,
345 &dev_attr_em_message_type,
346 &dev_attr_em_message,
347 &dev_attr_ahci_host_caps,
348 &dev_attr_ahci_host_version,
349 &dev_attr_ahci_port_cmd,
350 NULL
351 };
352
353 static struct device_attribute *ahci_sdev_attrs[] = {
354 &dev_attr_sw_activity,
355 &dev_attr_unload_heads,
356 NULL
357 };
358
359 static struct scsi_host_template ahci_sht = {
360 ATA_NCQ_SHT(DRV_NAME),
361 .can_queue = AHCI_MAX_CMDS - 1,
362 .sg_tablesize = AHCI_MAX_SG,
363 .dma_boundary = AHCI_DMA_BOUNDARY,
364 .shost_attrs = ahci_shost_attrs,
365 .sdev_attrs = ahci_sdev_attrs,
366 };
367
368 static struct ata_port_operations ahci_ops = {
369 .inherits = &sata_pmp_port_ops,
370
371 .qc_defer = sata_pmp_qc_defer_cmd_switch,
372 .qc_prep = ahci_qc_prep,
373 .qc_issue = ahci_qc_issue,
374 .qc_fill_rtf = ahci_qc_fill_rtf,
375
376 .freeze = ahci_freeze,
377 .thaw = ahci_thaw,
378 .softreset = ahci_softreset,
379 .hardreset = ahci_hardreset,
380 .postreset = ahci_postreset,
381 .pmp_softreset = ahci_softreset,
382 .error_handler = ahci_error_handler,
383 .post_internal_cmd = ahci_post_internal_cmd,
384 .dev_config = ahci_dev_config,
385
386 .scr_read = ahci_scr_read,
387 .scr_write = ahci_scr_write,
388 .pmp_attach = ahci_pmp_attach,
389 .pmp_detach = ahci_pmp_detach,
390
391 .enable_pm = ahci_enable_alpm,
392 .disable_pm = ahci_disable_alpm,
393 .em_show = ahci_led_show,
394 .em_store = ahci_led_store,
395 .sw_activity_show = ahci_activity_show,
396 .sw_activity_store = ahci_activity_store,
397 #ifdef CONFIG_PM
398 .port_suspend = ahci_port_suspend,
399 .port_resume = ahci_port_resume,
400 #endif
401 .port_start = ahci_port_start,
402 .port_stop = ahci_port_stop,
403 };
404
405 static struct ata_port_operations ahci_vt8251_ops = {
406 .inherits = &ahci_ops,
407 .hardreset = ahci_vt8251_hardreset,
408 };
409
410 static struct ata_port_operations ahci_p5wdh_ops = {
411 .inherits = &ahci_ops,
412 .hardreset = ahci_p5wdh_hardreset,
413 };
414
415 static struct ata_port_operations ahci_sb600_ops = {
416 .inherits = &ahci_ops,
417 .softreset = ahci_sb600_softreset,
418 .pmp_softreset = ahci_sb600_softreset,
419 };
420
421 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
422
423 static const struct ata_port_info ahci_port_info[] = {
424 [board_ahci] =
425 {
426 .flags = AHCI_FLAG_COMMON,
427 .pio_mask = ATA_PIO4,
428 .udma_mask = ATA_UDMA6,
429 .port_ops = &ahci_ops,
430 },
431 [board_ahci_vt8251] =
432 {
433 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
434 .flags = AHCI_FLAG_COMMON,
435 .pio_mask = ATA_PIO4,
436 .udma_mask = ATA_UDMA6,
437 .port_ops = &ahci_vt8251_ops,
438 },
439 [board_ahci_ign_iferr] =
440 {
441 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
442 .flags = AHCI_FLAG_COMMON,
443 .pio_mask = ATA_PIO4,
444 .udma_mask = ATA_UDMA6,
445 .port_ops = &ahci_ops,
446 },
447 [board_ahci_sb600] =
448 {
449 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
450 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
451 .flags = AHCI_FLAG_COMMON,
452 .pio_mask = ATA_PIO4,
453 .udma_mask = ATA_UDMA6,
454 .port_ops = &ahci_sb600_ops,
455 },
456 [board_ahci_mv] =
457 {
458 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
459 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
460 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
461 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
462 .pio_mask = ATA_PIO4,
463 .udma_mask = ATA_UDMA6,
464 .port_ops = &ahci_ops,
465 },
466 [board_ahci_sb700] = /* for SB700 and SB800 */
467 {
468 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
469 .flags = AHCI_FLAG_COMMON,
470 .pio_mask = ATA_PIO4,
471 .udma_mask = ATA_UDMA6,
472 .port_ops = &ahci_sb600_ops,
473 },
474 [board_ahci_mcp65] =
475 {
476 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
477 .flags = AHCI_FLAG_COMMON,
478 .pio_mask = ATA_PIO4,
479 .udma_mask = ATA_UDMA6,
480 .port_ops = &ahci_ops,
481 },
482 [board_ahci_nopmp] =
483 {
484 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
485 .flags = AHCI_FLAG_COMMON,
486 .pio_mask = ATA_PIO4,
487 .udma_mask = ATA_UDMA6,
488 .port_ops = &ahci_ops,
489 },
490 /* board_ahci_yesncq */
491 {
492 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
493 .flags = AHCI_FLAG_COMMON,
494 .pio_mask = ATA_PIO4,
495 .udma_mask = ATA_UDMA6,
496 .port_ops = &ahci_ops,
497 },
498 };
499
500 static const struct pci_device_id ahci_pci_tbl[] = {
501 /* Intel */
502 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
503 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
504 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
505 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
506 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
507 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
508 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
509 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
510 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
511 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
512 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
513 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
514 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
515 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
516 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
517 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
518 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
519 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
520 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
521 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
522 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
523 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
524 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
525 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
526 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
527 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
528 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
529 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
530 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
531 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
532 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
533 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
534 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
535 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
536 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
537 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
538 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
539 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
540 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
541 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
542
543 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
544 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
545 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
546
547 /* ATI */
548 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
549 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
550 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
551 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
552 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
553 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
554 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
555
556 /* VIA */
557 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
558 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
559
560 /* NVIDIA */
561 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
562 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
563 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
564 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
565 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
566 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
567 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
568 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
569 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
570 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
571 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
572 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
573 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
574 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
575 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
576 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
577 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
578 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
579 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
580 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
581 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
582 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
583 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
584 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
585 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
586 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
587 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
588 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
589 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
590 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
591 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
592 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
593 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
594 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
595 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
596 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
597 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
598 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
599 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
600 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
601 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
602 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
603 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
604 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
605 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
606 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
607 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
608 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
609 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
610 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
611 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
612 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
613 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
614 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
615 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
616 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
617 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
618 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
619 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
620 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
621 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
622 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
623 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
624 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
625 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
626 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
627 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
628 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
629
630 /* SiS */
631 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
632 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
633 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
634
635 /* Marvell */
636 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
637 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
638
639 /* Promise */
640 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
641
642 /* Generic, PCI class code for AHCI */
643 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
644 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
645
646 { } /* terminate list */
647 };
648
649
650 static struct pci_driver ahci_pci_driver = {
651 .name = DRV_NAME,
652 .id_table = ahci_pci_tbl,
653 .probe = ahci_init_one,
654 .remove = ata_pci_remove_one,
655 #ifdef CONFIG_PM
656 .suspend = ahci_pci_device_suspend,
657 .resume = ahci_pci_device_resume,
658 #endif
659 };
660
661 static int ahci_em_messages = 1;
662 module_param(ahci_em_messages, int, 0444);
663 /* add other LED protocol types when they become supported */
664 MODULE_PARM_DESC(ahci_em_messages,
665 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
666
667 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
668 static int marvell_enable;
669 #else
670 static int marvell_enable = 1;
671 #endif
672 module_param(marvell_enable, int, 0644);
673 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
674
675
676 static inline int ahci_nr_ports(u32 cap)
677 {
678 return (cap & 0x1f) + 1;
679 }
680
681 static inline void __iomem *__ahci_port_base(struct ata_host *host,
682 unsigned int port_no)
683 {
684 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
685
686 return mmio + 0x100 + (port_no * 0x80);
687 }
688
689 static inline void __iomem *ahci_port_base(struct ata_port *ap)
690 {
691 return __ahci_port_base(ap->host, ap->port_no);
692 }
693
694 static void ahci_enable_ahci(void __iomem *mmio)
695 {
696 int i;
697 u32 tmp;
698
699 /* turn on AHCI_EN */
700 tmp = readl(mmio + HOST_CTL);
701 if (tmp & HOST_AHCI_EN)
702 return;
703
704 /* Some controllers need AHCI_EN to be written multiple times.
705 * Try a few times before giving up.
706 */
707 for (i = 0; i < 5; i++) {
708 tmp |= HOST_AHCI_EN;
709 writel(tmp, mmio + HOST_CTL);
710 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
711 if (tmp & HOST_AHCI_EN)
712 return;
713 msleep(10);
714 }
715
716 WARN_ON(1);
717 }
718
719 static ssize_t ahci_show_host_caps(struct device *dev,
720 struct device_attribute *attr, char *buf)
721 {
722 struct Scsi_Host *shost = class_to_shost(dev);
723 struct ata_port *ap = ata_shost_to_port(shost);
724 struct ahci_host_priv *hpriv = ap->host->private_data;
725
726 return sprintf(buf, "%x\n", hpriv->cap);
727 }
728
729 static ssize_t ahci_show_host_version(struct device *dev,
730 struct device_attribute *attr, char *buf)
731 {
732 struct Scsi_Host *shost = class_to_shost(dev);
733 struct ata_port *ap = ata_shost_to_port(shost);
734 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
735
736 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
737 }
738
739 static ssize_t ahci_show_port_cmd(struct device *dev,
740 struct device_attribute *attr, char *buf)
741 {
742 struct Scsi_Host *shost = class_to_shost(dev);
743 struct ata_port *ap = ata_shost_to_port(shost);
744 void __iomem *port_mmio = ahci_port_base(ap);
745
746 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
747 }
748
749 /**
750 * ahci_save_initial_config - Save and fixup initial config values
751 * @pdev: target PCI device
752 * @hpriv: host private area to store config values
753 *
754 * Some registers containing configuration info might be setup by
755 * BIOS and might be cleared on reset. This function saves the
756 * initial values of those registers into @hpriv such that they
757 * can be restored after controller reset.
758 *
759 * If inconsistent, config values are fixed up by this function.
760 *
761 * LOCKING:
762 * None.
763 */
764 static void ahci_save_initial_config(struct pci_dev *pdev,
765 struct ahci_host_priv *hpriv)
766 {
767 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
768 u32 cap, port_map;
769 int i;
770 int mv;
771
772 /* make sure AHCI mode is enabled before accessing CAP */
773 ahci_enable_ahci(mmio);
774
775 /* Values prefixed with saved_ are written back to host after
776 * reset. Values without are used for driver operation.
777 */
778 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
779 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
780
781 /* some chips have errata preventing 64bit use */
782 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
783 dev_printk(KERN_INFO, &pdev->dev,
784 "controller can't do 64bit DMA, forcing 32bit\n");
785 cap &= ~HOST_CAP_64;
786 }
787
788 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
789 dev_printk(KERN_INFO, &pdev->dev,
790 "controller can't do NCQ, turning off CAP_NCQ\n");
791 cap &= ~HOST_CAP_NCQ;
792 }
793
794 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
795 dev_printk(KERN_INFO, &pdev->dev,
796 "controller can do NCQ, turning on CAP_NCQ\n");
797 cap |= HOST_CAP_NCQ;
798 }
799
800 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
801 dev_printk(KERN_INFO, &pdev->dev,
802 "controller can't do PMP, turning off CAP_PMP\n");
803 cap &= ~HOST_CAP_PMP;
804 }
805
806 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
807 port_map != 1) {
808 dev_printk(KERN_INFO, &pdev->dev,
809 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
810 port_map, 1);
811 port_map = 1;
812 }
813
814 /*
815 * Temporary Marvell 6145 hack: PATA port presence
816 * is asserted through the standard AHCI port
817 * presence register, as bit 4 (counting from 0)
818 */
819 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
820 if (pdev->device == 0x6121)
821 mv = 0x3;
822 else
823 mv = 0xf;
824 dev_printk(KERN_ERR, &pdev->dev,
825 "MV_AHCI HACK: port_map %x -> %x\n",
826 port_map,
827 port_map & mv);
828 dev_printk(KERN_ERR, &pdev->dev,
829 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
830
831 port_map &= mv;
832 }
833
834 /* cross check port_map and cap.n_ports */
835 if (port_map) {
836 int map_ports = 0;
837
838 for (i = 0; i < AHCI_MAX_PORTS; i++)
839 if (port_map & (1 << i))
840 map_ports++;
841
842 /* If PI has more ports than n_ports, whine, clear
843 * port_map and let it be generated from n_ports.
844 */
845 if (map_ports > ahci_nr_ports(cap)) {
846 dev_printk(KERN_WARNING, &pdev->dev,
847 "implemented port map (0x%x) contains more "
848 "ports than nr_ports (%u), using nr_ports\n",
849 port_map, ahci_nr_ports(cap));
850 port_map = 0;
851 }
852 }
853
854 /* fabricate port_map from cap.nr_ports */
855 if (!port_map) {
856 port_map = (1 << ahci_nr_ports(cap)) - 1;
857 dev_printk(KERN_WARNING, &pdev->dev,
858 "forcing PORTS_IMPL to 0x%x\n", port_map);
859
860 /* write the fixed up value to the PI register */
861 hpriv->saved_port_map = port_map;
862 }
863
864 /* record values to use during operation */
865 hpriv->cap = cap;
866 hpriv->port_map = port_map;
867 }
868
869 /**
870 * ahci_restore_initial_config - Restore initial config
871 * @host: target ATA host
872 *
873 * Restore initial config stored by ahci_save_initial_config().
874 *
875 * LOCKING:
876 * None.
877 */
878 static void ahci_restore_initial_config(struct ata_host *host)
879 {
880 struct ahci_host_priv *hpriv = host->private_data;
881 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
882
883 writel(hpriv->saved_cap, mmio + HOST_CAP);
884 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
885 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
886 }
887
888 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
889 {
890 static const int offset[] = {
891 [SCR_STATUS] = PORT_SCR_STAT,
892 [SCR_CONTROL] = PORT_SCR_CTL,
893 [SCR_ERROR] = PORT_SCR_ERR,
894 [SCR_ACTIVE] = PORT_SCR_ACT,
895 [SCR_NOTIFICATION] = PORT_SCR_NTF,
896 };
897 struct ahci_host_priv *hpriv = ap->host->private_data;
898
899 if (sc_reg < ARRAY_SIZE(offset) &&
900 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
901 return offset[sc_reg];
902 return 0;
903 }
904
905 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
906 {
907 void __iomem *port_mmio = ahci_port_base(link->ap);
908 int offset = ahci_scr_offset(link->ap, sc_reg);
909
910 if (offset) {
911 *val = readl(port_mmio + offset);
912 return 0;
913 }
914 return -EINVAL;
915 }
916
917 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
918 {
919 void __iomem *port_mmio = ahci_port_base(link->ap);
920 int offset = ahci_scr_offset(link->ap, sc_reg);
921
922 if (offset) {
923 writel(val, port_mmio + offset);
924 return 0;
925 }
926 return -EINVAL;
927 }
928
929 static void ahci_start_engine(struct ata_port *ap)
930 {
931 void __iomem *port_mmio = ahci_port_base(ap);
932 u32 tmp;
933
934 /* start DMA */
935 tmp = readl(port_mmio + PORT_CMD);
936 tmp |= PORT_CMD_START;
937 writel(tmp, port_mmio + PORT_CMD);
938 readl(port_mmio + PORT_CMD); /* flush */
939 }
940
941 static int ahci_stop_engine(struct ata_port *ap)
942 {
943 void __iomem *port_mmio = ahci_port_base(ap);
944 u32 tmp;
945
946 tmp = readl(port_mmio + PORT_CMD);
947
948 /* check if the HBA is idle */
949 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
950 return 0;
951
952 /* setting HBA to idle */
953 tmp &= ~PORT_CMD_START;
954 writel(tmp, port_mmio + PORT_CMD);
955
956 /* wait for engine to stop. This could be as long as 500 msec */
957 tmp = ata_wait_register(port_mmio + PORT_CMD,
958 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
959 if (tmp & PORT_CMD_LIST_ON)
960 return -EIO;
961
962 return 0;
963 }
964
965 static void ahci_start_fis_rx(struct ata_port *ap)
966 {
967 void __iomem *port_mmio = ahci_port_base(ap);
968 struct ahci_host_priv *hpriv = ap->host->private_data;
969 struct ahci_port_priv *pp = ap->private_data;
970 u32 tmp;
971
972 /* set FIS registers */
973 if (hpriv->cap & HOST_CAP_64)
974 writel((pp->cmd_slot_dma >> 16) >> 16,
975 port_mmio + PORT_LST_ADDR_HI);
976 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
977
978 if (hpriv->cap & HOST_CAP_64)
979 writel((pp->rx_fis_dma >> 16) >> 16,
980 port_mmio + PORT_FIS_ADDR_HI);
981 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
982
983 /* enable FIS reception */
984 tmp = readl(port_mmio + PORT_CMD);
985 tmp |= PORT_CMD_FIS_RX;
986 writel(tmp, port_mmio + PORT_CMD);
987
988 /* flush */
989 readl(port_mmio + PORT_CMD);
990 }
991
992 static int ahci_stop_fis_rx(struct ata_port *ap)
993 {
994 void __iomem *port_mmio = ahci_port_base(ap);
995 u32 tmp;
996
997 /* disable FIS reception */
998 tmp = readl(port_mmio + PORT_CMD);
999 tmp &= ~PORT_CMD_FIS_RX;
1000 writel(tmp, port_mmio + PORT_CMD);
1001
1002 /* wait for completion, spec says 500ms, give it 1000 */
1003 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1004 PORT_CMD_FIS_ON, 10, 1000);
1005 if (tmp & PORT_CMD_FIS_ON)
1006 return -EBUSY;
1007
1008 return 0;
1009 }
1010
1011 static void ahci_power_up(struct ata_port *ap)
1012 {
1013 struct ahci_host_priv *hpriv = ap->host->private_data;
1014 void __iomem *port_mmio = ahci_port_base(ap);
1015 u32 cmd;
1016
1017 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1018
1019 /* spin up device */
1020 if (hpriv->cap & HOST_CAP_SSS) {
1021 cmd |= PORT_CMD_SPIN_UP;
1022 writel(cmd, port_mmio + PORT_CMD);
1023 }
1024
1025 /* wake up link */
1026 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1027 }
1028
1029 static void ahci_disable_alpm(struct ata_port *ap)
1030 {
1031 struct ahci_host_priv *hpriv = ap->host->private_data;
1032 void __iomem *port_mmio = ahci_port_base(ap);
1033 u32 cmd;
1034 struct ahci_port_priv *pp = ap->private_data;
1035
1036 /* IPM bits should be disabled by libata-core */
1037 /* get the existing command bits */
1038 cmd = readl(port_mmio + PORT_CMD);
1039
1040 /* disable ALPM and ASP */
1041 cmd &= ~PORT_CMD_ASP;
1042 cmd &= ~PORT_CMD_ALPE;
1043
1044 /* force the interface back to active */
1045 cmd |= PORT_CMD_ICC_ACTIVE;
1046
1047 /* write out new cmd value */
1048 writel(cmd, port_mmio + PORT_CMD);
1049 cmd = readl(port_mmio + PORT_CMD);
1050
1051 /* wait 10ms to be sure we've come out of any low power state */
1052 msleep(10);
1053
1054 /* clear out any PhyRdy stuff from interrupt status */
1055 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1056
1057 /* go ahead and clean out PhyRdy Change from Serror too */
1058 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1059
1060 /*
1061 * Clear flag to indicate that we should ignore all PhyRdy
1062 * state changes
1063 */
1064 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1065
1066 /*
1067 * Enable interrupts on Phy Ready.
1068 */
1069 pp->intr_mask |= PORT_IRQ_PHYRDY;
1070 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1071
1072 /*
1073 * don't change the link pm policy - we can be called
1074 * just to turn of link pm temporarily
1075 */
1076 }
1077
1078 static int ahci_enable_alpm(struct ata_port *ap,
1079 enum link_pm policy)
1080 {
1081 struct ahci_host_priv *hpriv = ap->host->private_data;
1082 void __iomem *port_mmio = ahci_port_base(ap);
1083 u32 cmd;
1084 struct ahci_port_priv *pp = ap->private_data;
1085 u32 asp;
1086
1087 /* Make sure the host is capable of link power management */
1088 if (!(hpriv->cap & HOST_CAP_ALPM))
1089 return -EINVAL;
1090
1091 switch (policy) {
1092 case MAX_PERFORMANCE:
1093 case NOT_AVAILABLE:
1094 /*
1095 * if we came here with NOT_AVAILABLE,
1096 * it just means this is the first time we
1097 * have tried to enable - default to max performance,
1098 * and let the user go to lower power modes on request.
1099 */
1100 ahci_disable_alpm(ap);
1101 return 0;
1102 case MIN_POWER:
1103 /* configure HBA to enter SLUMBER */
1104 asp = PORT_CMD_ASP;
1105 break;
1106 case MEDIUM_POWER:
1107 /* configure HBA to enter PARTIAL */
1108 asp = 0;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113
1114 /*
1115 * Disable interrupts on Phy Ready. This keeps us from
1116 * getting woken up due to spurious phy ready interrupts
1117 * TBD - Hot plug should be done via polling now, is
1118 * that even supported?
1119 */
1120 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1121 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1122
1123 /*
1124 * Set a flag to indicate that we should ignore all PhyRdy
1125 * state changes since these can happen now whenever we
1126 * change link state
1127 */
1128 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1129
1130 /* get the existing command bits */
1131 cmd = readl(port_mmio + PORT_CMD);
1132
1133 /*
1134 * Set ASP based on Policy
1135 */
1136 cmd |= asp;
1137
1138 /*
1139 * Setting this bit will instruct the HBA to aggressively
1140 * enter a lower power link state when it's appropriate and
1141 * based on the value set above for ASP
1142 */
1143 cmd |= PORT_CMD_ALPE;
1144
1145 /* write out new cmd value */
1146 writel(cmd, port_mmio + PORT_CMD);
1147 cmd = readl(port_mmio + PORT_CMD);
1148
1149 /* IPM bits should be set by libata-core */
1150 return 0;
1151 }
1152
1153 #ifdef CONFIG_PM
1154 static void ahci_power_down(struct ata_port *ap)
1155 {
1156 struct ahci_host_priv *hpriv = ap->host->private_data;
1157 void __iomem *port_mmio = ahci_port_base(ap);
1158 u32 cmd, scontrol;
1159
1160 if (!(hpriv->cap & HOST_CAP_SSS))
1161 return;
1162
1163 /* put device into listen mode, first set PxSCTL.DET to 0 */
1164 scontrol = readl(port_mmio + PORT_SCR_CTL);
1165 scontrol &= ~0xf;
1166 writel(scontrol, port_mmio + PORT_SCR_CTL);
1167
1168 /* then set PxCMD.SUD to 0 */
1169 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1170 cmd &= ~PORT_CMD_SPIN_UP;
1171 writel(cmd, port_mmio + PORT_CMD);
1172 }
1173 #endif
1174
1175 static void ahci_start_port(struct ata_port *ap)
1176 {
1177 struct ahci_port_priv *pp = ap->private_data;
1178 struct ata_link *link;
1179 struct ahci_em_priv *emp;
1180 ssize_t rc;
1181 int i;
1182
1183 /* enable FIS reception */
1184 ahci_start_fis_rx(ap);
1185
1186 /* enable DMA */
1187 ahci_start_engine(ap);
1188
1189 /* turn on LEDs */
1190 if (ap->flags & ATA_FLAG_EM) {
1191 ata_for_each_link(link, ap, EDGE) {
1192 emp = &pp->em_priv[link->pmp];
1193
1194 /* EM Transmit bit maybe busy during init */
1195 for (i = 0; i < EM_MAX_RETRY; i++) {
1196 rc = ahci_transmit_led_message(ap,
1197 emp->led_state,
1198 4);
1199 if (rc == -EBUSY)
1200 msleep(1);
1201 else
1202 break;
1203 }
1204 }
1205 }
1206
1207 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1208 ata_for_each_link(link, ap, EDGE)
1209 ahci_init_sw_activity(link);
1210
1211 }
1212
1213 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1214 {
1215 int rc;
1216
1217 /* disable DMA */
1218 rc = ahci_stop_engine(ap);
1219 if (rc) {
1220 *emsg = "failed to stop engine";
1221 return rc;
1222 }
1223
1224 /* disable FIS reception */
1225 rc = ahci_stop_fis_rx(ap);
1226 if (rc) {
1227 *emsg = "failed stop FIS RX";
1228 return rc;
1229 }
1230
1231 return 0;
1232 }
1233
1234 static int ahci_reset_controller(struct ata_host *host)
1235 {
1236 struct pci_dev *pdev = to_pci_dev(host->dev);
1237 struct ahci_host_priv *hpriv = host->private_data;
1238 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1239 u32 tmp;
1240
1241 /* we must be in AHCI mode, before using anything
1242 * AHCI-specific, such as HOST_RESET.
1243 */
1244 ahci_enable_ahci(mmio);
1245
1246 /* global controller reset */
1247 if (!ahci_skip_host_reset) {
1248 tmp = readl(mmio + HOST_CTL);
1249 if ((tmp & HOST_RESET) == 0) {
1250 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1251 readl(mmio + HOST_CTL); /* flush */
1252 }
1253
1254 /*
1255 * to perform host reset, OS should set HOST_RESET
1256 * and poll until this bit is read to be "0".
1257 * reset must complete within 1 second, or
1258 * the hardware should be considered fried.
1259 */
1260 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1261 HOST_RESET, 10, 1000);
1262
1263 if (tmp & HOST_RESET) {
1264 dev_printk(KERN_ERR, host->dev,
1265 "controller reset failed (0x%x)\n", tmp);
1266 return -EIO;
1267 }
1268
1269 /* turn on AHCI mode */
1270 ahci_enable_ahci(mmio);
1271
1272 /* Some registers might be cleared on reset. Restore
1273 * initial values.
1274 */
1275 ahci_restore_initial_config(host);
1276 } else
1277 dev_printk(KERN_INFO, host->dev,
1278 "skipping global host reset\n");
1279
1280 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1281 u16 tmp16;
1282
1283 /* configure PCS */
1284 pci_read_config_word(pdev, 0x92, &tmp16);
1285 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1286 tmp16 |= hpriv->port_map;
1287 pci_write_config_word(pdev, 0x92, tmp16);
1288 }
1289 }
1290
1291 return 0;
1292 }
1293
1294 static void ahci_sw_activity(struct ata_link *link)
1295 {
1296 struct ata_port *ap = link->ap;
1297 struct ahci_port_priv *pp = ap->private_data;
1298 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1299
1300 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1301 return;
1302
1303 emp->activity++;
1304 if (!timer_pending(&emp->timer))
1305 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1306 }
1307
1308 static void ahci_sw_activity_blink(unsigned long arg)
1309 {
1310 struct ata_link *link = (struct ata_link *)arg;
1311 struct ata_port *ap = link->ap;
1312 struct ahci_port_priv *pp = ap->private_data;
1313 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1314 unsigned long led_message = emp->led_state;
1315 u32 activity_led_state;
1316 unsigned long flags;
1317
1318 led_message &= EM_MSG_LED_VALUE;
1319 led_message |= ap->port_no | (link->pmp << 8);
1320
1321 /* check to see if we've had activity. If so,
1322 * toggle state of LED and reset timer. If not,
1323 * turn LED to desired idle state.
1324 */
1325 spin_lock_irqsave(ap->lock, flags);
1326 if (emp->saved_activity != emp->activity) {
1327 emp->saved_activity = emp->activity;
1328 /* get the current LED state */
1329 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1330
1331 if (activity_led_state)
1332 activity_led_state = 0;
1333 else
1334 activity_led_state = 1;
1335
1336 /* clear old state */
1337 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1338
1339 /* toggle state */
1340 led_message |= (activity_led_state << 16);
1341 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1342 } else {
1343 /* switch to idle */
1344 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1345 if (emp->blink_policy == BLINK_OFF)
1346 led_message |= (1 << 16);
1347 }
1348 spin_unlock_irqrestore(ap->lock, flags);
1349 ahci_transmit_led_message(ap, led_message, 4);
1350 }
1351
1352 static void ahci_init_sw_activity(struct ata_link *link)
1353 {
1354 struct ata_port *ap = link->ap;
1355 struct ahci_port_priv *pp = ap->private_data;
1356 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1357
1358 /* init activity stats, setup timer */
1359 emp->saved_activity = emp->activity = 0;
1360 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1361
1362 /* check our blink policy and set flag for link if it's enabled */
1363 if (emp->blink_policy)
1364 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1365 }
1366
1367 static int ahci_reset_em(struct ata_host *host)
1368 {
1369 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1370 u32 em_ctl;
1371
1372 em_ctl = readl(mmio + HOST_EM_CTL);
1373 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1374 return -EINVAL;
1375
1376 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1377 return 0;
1378 }
1379
1380 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1381 ssize_t size)
1382 {
1383 struct ahci_host_priv *hpriv = ap->host->private_data;
1384 struct ahci_port_priv *pp = ap->private_data;
1385 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1386 u32 em_ctl;
1387 u32 message[] = {0, 0};
1388 unsigned long flags;
1389 int pmp;
1390 struct ahci_em_priv *emp;
1391
1392 /* get the slot number from the message */
1393 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1394 if (pmp < EM_MAX_SLOTS)
1395 emp = &pp->em_priv[pmp];
1396 else
1397 return -EINVAL;
1398
1399 spin_lock_irqsave(ap->lock, flags);
1400
1401 /*
1402 * if we are still busy transmitting a previous message,
1403 * do not allow
1404 */
1405 em_ctl = readl(mmio + HOST_EM_CTL);
1406 if (em_ctl & EM_CTL_TM) {
1407 spin_unlock_irqrestore(ap->lock, flags);
1408 return -EBUSY;
1409 }
1410
1411 /*
1412 * create message header - this is all zero except for
1413 * the message size, which is 4 bytes.
1414 */
1415 message[0] |= (4 << 8);
1416
1417 /* ignore 0:4 of byte zero, fill in port info yourself */
1418 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1419
1420 /* write message to EM_LOC */
1421 writel(message[0], mmio + hpriv->em_loc);
1422 writel(message[1], mmio + hpriv->em_loc+4);
1423
1424 /* save off new led state for port/slot */
1425 emp->led_state = state;
1426
1427 /*
1428 * tell hardware to transmit the message
1429 */
1430 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1431
1432 spin_unlock_irqrestore(ap->lock, flags);
1433 return size;
1434 }
1435
1436 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1437 {
1438 struct ahci_port_priv *pp = ap->private_data;
1439 struct ata_link *link;
1440 struct ahci_em_priv *emp;
1441 int rc = 0;
1442
1443 ata_for_each_link(link, ap, EDGE) {
1444 emp = &pp->em_priv[link->pmp];
1445 rc += sprintf(buf, "%lx\n", emp->led_state);
1446 }
1447 return rc;
1448 }
1449
1450 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1451 size_t size)
1452 {
1453 int state;
1454 int pmp;
1455 struct ahci_port_priv *pp = ap->private_data;
1456 struct ahci_em_priv *emp;
1457
1458 state = simple_strtoul(buf, NULL, 0);
1459
1460 /* get the slot number from the message */
1461 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1462 if (pmp < EM_MAX_SLOTS)
1463 emp = &pp->em_priv[pmp];
1464 else
1465 return -EINVAL;
1466
1467 /* mask off the activity bits if we are in sw_activity
1468 * mode, user should turn off sw_activity before setting
1469 * activity led through em_message
1470 */
1471 if (emp->blink_policy)
1472 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1473
1474 return ahci_transmit_led_message(ap, state, size);
1475 }
1476
1477 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1478 {
1479 struct ata_link *link = dev->link;
1480 struct ata_port *ap = link->ap;
1481 struct ahci_port_priv *pp = ap->private_data;
1482 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1483 u32 port_led_state = emp->led_state;
1484
1485 /* save the desired Activity LED behavior */
1486 if (val == OFF) {
1487 /* clear LFLAG */
1488 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1489
1490 /* set the LED to OFF */
1491 port_led_state &= EM_MSG_LED_VALUE_OFF;
1492 port_led_state |= (ap->port_no | (link->pmp << 8));
1493 ahci_transmit_led_message(ap, port_led_state, 4);
1494 } else {
1495 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1496 if (val == BLINK_OFF) {
1497 /* set LED to ON for idle */
1498 port_led_state &= EM_MSG_LED_VALUE_OFF;
1499 port_led_state |= (ap->port_no | (link->pmp << 8));
1500 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1501 ahci_transmit_led_message(ap, port_led_state, 4);
1502 }
1503 }
1504 emp->blink_policy = val;
1505 return 0;
1506 }
1507
1508 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1509 {
1510 struct ata_link *link = dev->link;
1511 struct ata_port *ap = link->ap;
1512 struct ahci_port_priv *pp = ap->private_data;
1513 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1514
1515 /* display the saved value of activity behavior for this
1516 * disk.
1517 */
1518 return sprintf(buf, "%d\n", emp->blink_policy);
1519 }
1520
1521 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1522 int port_no, void __iomem *mmio,
1523 void __iomem *port_mmio)
1524 {
1525 const char *emsg = NULL;
1526 int rc;
1527 u32 tmp;
1528
1529 /* make sure port is not active */
1530 rc = ahci_deinit_port(ap, &emsg);
1531 if (rc)
1532 dev_printk(KERN_WARNING, &pdev->dev,
1533 "%s (%d)\n", emsg, rc);
1534
1535 /* clear SError */
1536 tmp = readl(port_mmio + PORT_SCR_ERR);
1537 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1538 writel(tmp, port_mmio + PORT_SCR_ERR);
1539
1540 /* clear port IRQ */
1541 tmp = readl(port_mmio + PORT_IRQ_STAT);
1542 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1543 if (tmp)
1544 writel(tmp, port_mmio + PORT_IRQ_STAT);
1545
1546 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1547 }
1548
1549 static void ahci_init_controller(struct ata_host *host)
1550 {
1551 struct ahci_host_priv *hpriv = host->private_data;
1552 struct pci_dev *pdev = to_pci_dev(host->dev);
1553 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1554 int i;
1555 void __iomem *port_mmio;
1556 u32 tmp;
1557 int mv;
1558
1559 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1560 if (pdev->device == 0x6121)
1561 mv = 2;
1562 else
1563 mv = 4;
1564 port_mmio = __ahci_port_base(host, mv);
1565
1566 writel(0, port_mmio + PORT_IRQ_MASK);
1567
1568 /* clear port IRQ */
1569 tmp = readl(port_mmio + PORT_IRQ_STAT);
1570 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1571 if (tmp)
1572 writel(tmp, port_mmio + PORT_IRQ_STAT);
1573 }
1574
1575 for (i = 0; i < host->n_ports; i++) {
1576 struct ata_port *ap = host->ports[i];
1577
1578 port_mmio = ahci_port_base(ap);
1579 if (ata_port_is_dummy(ap))
1580 continue;
1581
1582 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1583 }
1584
1585 tmp = readl(mmio + HOST_CTL);
1586 VPRINTK("HOST_CTL 0x%x\n", tmp);
1587 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1588 tmp = readl(mmio + HOST_CTL);
1589 VPRINTK("HOST_CTL 0x%x\n", tmp);
1590 }
1591
1592 static void ahci_dev_config(struct ata_device *dev)
1593 {
1594 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1595
1596 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1597 dev->max_sectors = 255;
1598 ata_dev_printk(dev, KERN_INFO,
1599 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1600 }
1601 }
1602
1603 static unsigned int ahci_dev_classify(struct ata_port *ap)
1604 {
1605 void __iomem *port_mmio = ahci_port_base(ap);
1606 struct ata_taskfile tf;
1607 u32 tmp;
1608
1609 tmp = readl(port_mmio + PORT_SIG);
1610 tf.lbah = (tmp >> 24) & 0xff;
1611 tf.lbam = (tmp >> 16) & 0xff;
1612 tf.lbal = (tmp >> 8) & 0xff;
1613 tf.nsect = (tmp) & 0xff;
1614
1615 return ata_dev_classify(&tf);
1616 }
1617
1618 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1619 u32 opts)
1620 {
1621 dma_addr_t cmd_tbl_dma;
1622
1623 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1624
1625 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1626 pp->cmd_slot[tag].status = 0;
1627 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1628 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1629 }
1630
1631 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1632 {
1633 void __iomem *port_mmio = ahci_port_base(ap);
1634 struct ahci_host_priv *hpriv = ap->host->private_data;
1635 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1636 u32 tmp;
1637 int busy, rc;
1638
1639 /* do we need to kick the port? */
1640 busy = status & (ATA_BUSY | ATA_DRQ);
1641 if (!busy && !force_restart)
1642 return 0;
1643
1644 /* stop engine */
1645 rc = ahci_stop_engine(ap);
1646 if (rc)
1647 goto out_restart;
1648
1649 /* need to do CLO? */
1650 if (!busy) {
1651 rc = 0;
1652 goto out_restart;
1653 }
1654
1655 if (!(hpriv->cap & HOST_CAP_CLO)) {
1656 rc = -EOPNOTSUPP;
1657 goto out_restart;
1658 }
1659
1660 /* perform CLO */
1661 tmp = readl(port_mmio + PORT_CMD);
1662 tmp |= PORT_CMD_CLO;
1663 writel(tmp, port_mmio + PORT_CMD);
1664
1665 rc = 0;
1666 tmp = ata_wait_register(port_mmio + PORT_CMD,
1667 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1668 if (tmp & PORT_CMD_CLO)
1669 rc = -EIO;
1670
1671 /* restart engine */
1672 out_restart:
1673 ahci_start_engine(ap);
1674 return rc;
1675 }
1676
1677 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1678 struct ata_taskfile *tf, int is_cmd, u16 flags,
1679 unsigned long timeout_msec)
1680 {
1681 const u32 cmd_fis_len = 5; /* five dwords */
1682 struct ahci_port_priv *pp = ap->private_data;
1683 void __iomem *port_mmio = ahci_port_base(ap);
1684 u8 *fis = pp->cmd_tbl;
1685 u32 tmp;
1686
1687 /* prep the command */
1688 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1689 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1690
1691 /* issue & wait */
1692 writel(1, port_mmio + PORT_CMD_ISSUE);
1693
1694 if (timeout_msec) {
1695 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1696 1, timeout_msec);
1697 if (tmp & 0x1) {
1698 ahci_kick_engine(ap, 1);
1699 return -EBUSY;
1700 }
1701 } else
1702 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1703
1704 return 0;
1705 }
1706
1707 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1708 int pmp, unsigned long deadline,
1709 int (*check_ready)(struct ata_link *link))
1710 {
1711 struct ata_port *ap = link->ap;
1712 struct ahci_host_priv *hpriv = ap->host->private_data;
1713 const char *reason = NULL;
1714 unsigned long now, msecs;
1715 struct ata_taskfile tf;
1716 int rc;
1717
1718 DPRINTK("ENTER\n");
1719
1720 /* prepare for SRST (AHCI-1.1 10.4.1) */
1721 rc = ahci_kick_engine(ap, 1);
1722 if (rc && rc != -EOPNOTSUPP)
1723 ata_link_printk(link, KERN_WARNING,
1724 "failed to reset engine (errno=%d)\n", rc);
1725
1726 ata_tf_init(link->device, &tf);
1727
1728 /* issue the first D2H Register FIS */
1729 msecs = 0;
1730 now = jiffies;
1731 if (time_after(now, deadline))
1732 msecs = jiffies_to_msecs(deadline - now);
1733
1734 tf.ctl |= ATA_SRST;
1735 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1736 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1737 rc = -EIO;
1738 reason = "1st FIS failed";
1739 goto fail;
1740 }
1741
1742 /* spec says at least 5us, but be generous and sleep for 1ms */
1743 msleep(1);
1744
1745 /* issue the second D2H Register FIS */
1746 tf.ctl &= ~ATA_SRST;
1747 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1748
1749 /* wait for link to become ready */
1750 rc = ata_wait_after_reset(link, deadline, check_ready);
1751 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1752 /*
1753 * Workaround for cases where link online status can't
1754 * be trusted. Treat device readiness timeout as link
1755 * offline.
1756 */
1757 ata_link_printk(link, KERN_INFO,
1758 "device not ready, treating as offline\n");
1759 *class = ATA_DEV_NONE;
1760 } else if (rc) {
1761 /* link occupied, -ENODEV too is an error */
1762 reason = "device not ready";
1763 goto fail;
1764 } else
1765 *class = ahci_dev_classify(ap);
1766
1767 DPRINTK("EXIT, class=%u\n", *class);
1768 return 0;
1769
1770 fail:
1771 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1772 return rc;
1773 }
1774
1775 static int ahci_check_ready(struct ata_link *link)
1776 {
1777 void __iomem *port_mmio = ahci_port_base(link->ap);
1778 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1779
1780 return ata_check_ready(status);
1781 }
1782
1783 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1784 unsigned long deadline)
1785 {
1786 int pmp = sata_srst_pmp(link);
1787
1788 DPRINTK("ENTER\n");
1789
1790 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1791 }
1792
1793 static int ahci_sb600_check_ready(struct ata_link *link)
1794 {
1795 void __iomem *port_mmio = ahci_port_base(link->ap);
1796 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1797 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1798
1799 /*
1800 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1801 * which can save timeout delay.
1802 */
1803 if (irq_status & PORT_IRQ_BAD_PMP)
1804 return -EIO;
1805
1806 return ata_check_ready(status);
1807 }
1808
1809 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1810 unsigned long deadline)
1811 {
1812 struct ata_port *ap = link->ap;
1813 void __iomem *port_mmio = ahci_port_base(ap);
1814 int pmp = sata_srst_pmp(link);
1815 int rc;
1816 u32 irq_sts;
1817
1818 DPRINTK("ENTER\n");
1819
1820 rc = ahci_do_softreset(link, class, pmp, deadline,
1821 ahci_sb600_check_ready);
1822
1823 /*
1824 * Soft reset fails on some ATI chips with IPMS set when PMP
1825 * is enabled but SATA HDD/ODD is connected to SATA port,
1826 * do soft reset again to port 0.
1827 */
1828 if (rc == -EIO) {
1829 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1830 if (irq_sts & PORT_IRQ_BAD_PMP) {
1831 ata_link_printk(link, KERN_WARNING,
1832 "applying SB600 PMP SRST workaround "
1833 "and retrying\n");
1834 rc = ahci_do_softreset(link, class, 0, deadline,
1835 ahci_check_ready);
1836 }
1837 }
1838
1839 return rc;
1840 }
1841
1842 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1843 unsigned long deadline)
1844 {
1845 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1846 struct ata_port *ap = link->ap;
1847 struct ahci_port_priv *pp = ap->private_data;
1848 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1849 struct ata_taskfile tf;
1850 bool online;
1851 int rc;
1852
1853 DPRINTK("ENTER\n");
1854
1855 ahci_stop_engine(ap);
1856
1857 /* clear D2H reception area to properly wait for D2H FIS */
1858 ata_tf_init(link->device, &tf);
1859 tf.command = 0x80;
1860 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1861
1862 rc = sata_link_hardreset(link, timing, deadline, &online,
1863 ahci_check_ready);
1864
1865 ahci_start_engine(ap);
1866
1867 if (online)
1868 *class = ahci_dev_classify(ap);
1869
1870 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1871 return rc;
1872 }
1873
1874 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1875 unsigned long deadline)
1876 {
1877 struct ata_port *ap = link->ap;
1878 bool online;
1879 int rc;
1880
1881 DPRINTK("ENTER\n");
1882
1883 ahci_stop_engine(ap);
1884
1885 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1886 deadline, &online, NULL);
1887
1888 ahci_start_engine(ap);
1889
1890 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1891
1892 /* vt8251 doesn't clear BSY on signature FIS reception,
1893 * request follow-up softreset.
1894 */
1895 return online ? -EAGAIN : rc;
1896 }
1897
1898 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1899 unsigned long deadline)
1900 {
1901 struct ata_port *ap = link->ap;
1902 struct ahci_port_priv *pp = ap->private_data;
1903 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1904 struct ata_taskfile tf;
1905 bool online;
1906 int rc;
1907
1908 ahci_stop_engine(ap);
1909
1910 /* clear D2H reception area to properly wait for D2H FIS */
1911 ata_tf_init(link->device, &tf);
1912 tf.command = 0x80;
1913 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1914
1915 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1916 deadline, &online, NULL);
1917
1918 ahci_start_engine(ap);
1919
1920 /* The pseudo configuration device on SIMG4726 attached to
1921 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1922 * hardreset if no device is attached to the first downstream
1923 * port && the pseudo device locks up on SRST w/ PMP==0. To
1924 * work around this, wait for !BSY only briefly. If BSY isn't
1925 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1926 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1927 *
1928 * Wait for two seconds. Devices attached to downstream port
1929 * which can't process the following IDENTIFY after this will
1930 * have to be reset again. For most cases, this should
1931 * suffice while making probing snappish enough.
1932 */
1933 if (online) {
1934 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1935 ahci_check_ready);
1936 if (rc)
1937 ahci_kick_engine(ap, 0);
1938 }
1939 return rc;
1940 }
1941
1942 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1943 {
1944 struct ata_port *ap = link->ap;
1945 void __iomem *port_mmio = ahci_port_base(ap);
1946 u32 new_tmp, tmp;
1947
1948 ata_std_postreset(link, class);
1949
1950 /* Make sure port's ATAPI bit is set appropriately */
1951 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1952 if (*class == ATA_DEV_ATAPI)
1953 new_tmp |= PORT_CMD_ATAPI;
1954 else
1955 new_tmp &= ~PORT_CMD_ATAPI;
1956 if (new_tmp != tmp) {
1957 writel(new_tmp, port_mmio + PORT_CMD);
1958 readl(port_mmio + PORT_CMD); /* flush */
1959 }
1960 }
1961
1962 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1963 {
1964 struct scatterlist *sg;
1965 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1966 unsigned int si;
1967
1968 VPRINTK("ENTER\n");
1969
1970 /*
1971 * Next, the S/G list.
1972 */
1973 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1974 dma_addr_t addr = sg_dma_address(sg);
1975 u32 sg_len = sg_dma_len(sg);
1976
1977 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1978 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1979 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1980 }
1981
1982 return si;
1983 }
1984
1985 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1986 {
1987 struct ata_port *ap = qc->ap;
1988 struct ahci_port_priv *pp = ap->private_data;
1989 int is_atapi = ata_is_atapi(qc->tf.protocol);
1990 void *cmd_tbl;
1991 u32 opts;
1992 const u32 cmd_fis_len = 5; /* five dwords */
1993 unsigned int n_elem;
1994
1995 /*
1996 * Fill in command table information. First, the header,
1997 * a SATA Register - Host to Device command FIS.
1998 */
1999 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2000
2001 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
2002 if (is_atapi) {
2003 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2004 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
2005 }
2006
2007 n_elem = 0;
2008 if (qc->flags & ATA_QCFLAG_DMAMAP)
2009 n_elem = ahci_fill_sg(qc, cmd_tbl);
2010
2011 /*
2012 * Fill in command slot information.
2013 */
2014 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
2015 if (qc->tf.flags & ATA_TFLAG_WRITE)
2016 opts |= AHCI_CMD_WRITE;
2017 if (is_atapi)
2018 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
2019
2020 ahci_fill_cmd_slot(pp, qc->tag, opts);
2021 }
2022
2023 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
2024 {
2025 struct ahci_host_priv *hpriv = ap->host->private_data;
2026 struct ahci_port_priv *pp = ap->private_data;
2027 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2028 struct ata_link *link = NULL;
2029 struct ata_queued_cmd *active_qc;
2030 struct ata_eh_info *active_ehi;
2031 u32 serror;
2032
2033 /* determine active link */
2034 ata_for_each_link(link, ap, EDGE)
2035 if (ata_link_active(link))
2036 break;
2037 if (!link)
2038 link = &ap->link;
2039
2040 active_qc = ata_qc_from_tag(ap, link->active_tag);
2041 active_ehi = &link->eh_info;
2042
2043 /* record irq stat */
2044 ata_ehi_clear_desc(host_ehi);
2045 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2046
2047 /* AHCI needs SError cleared; otherwise, it might lock up */
2048 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2049 ahci_scr_write(&ap->link, SCR_ERROR, serror);
2050 host_ehi->serror |= serror;
2051
2052 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2053 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2054 irq_stat &= ~PORT_IRQ_IF_ERR;
2055
2056 if (irq_stat & PORT_IRQ_TF_ERR) {
2057 /* If qc is active, charge it; otherwise, the active
2058 * link. There's no active qc on NCQ errors. It will
2059 * be determined by EH by reading log page 10h.
2060 */
2061 if (active_qc)
2062 active_qc->err_mask |= AC_ERR_DEV;
2063 else
2064 active_ehi->err_mask |= AC_ERR_DEV;
2065
2066 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2067 host_ehi->serror &= ~SERR_INTERNAL;
2068 }
2069
2070 if (irq_stat & PORT_IRQ_UNK_FIS) {
2071 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2072
2073 active_ehi->err_mask |= AC_ERR_HSM;
2074 active_ehi->action |= ATA_EH_RESET;
2075 ata_ehi_push_desc(active_ehi,
2076 "unknown FIS %08x %08x %08x %08x" ,
2077 unk[0], unk[1], unk[2], unk[3]);
2078 }
2079
2080 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2081 active_ehi->err_mask |= AC_ERR_HSM;
2082 active_ehi->action |= ATA_EH_RESET;
2083 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2084 }
2085
2086 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2087 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2088 host_ehi->action |= ATA_EH_RESET;
2089 ata_ehi_push_desc(host_ehi, "host bus error");
2090 }
2091
2092 if (irq_stat & PORT_IRQ_IF_ERR) {
2093 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2094 host_ehi->action |= ATA_EH_RESET;
2095 ata_ehi_push_desc(host_ehi, "interface fatal error");
2096 }
2097
2098 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2099 ata_ehi_hotplugged(host_ehi);
2100 ata_ehi_push_desc(host_ehi, "%s",
2101 irq_stat & PORT_IRQ_CONNECT ?
2102 "connection status changed" : "PHY RDY changed");
2103 }
2104
2105 /* okay, let's hand over to EH */
2106
2107 if (irq_stat & PORT_IRQ_FREEZE)
2108 ata_port_freeze(ap);
2109 else
2110 ata_port_abort(ap);
2111 }
2112
2113 static void ahci_port_intr(struct ata_port *ap)
2114 {
2115 void __iomem *port_mmio = ahci_port_base(ap);
2116 struct ata_eh_info *ehi = &ap->link.eh_info;
2117 struct ahci_port_priv *pp = ap->private_data;
2118 struct ahci_host_priv *hpriv = ap->host->private_data;
2119 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2120 u32 status, qc_active;
2121 int rc;
2122
2123 status = readl(port_mmio + PORT_IRQ_STAT);
2124 writel(status, port_mmio + PORT_IRQ_STAT);
2125
2126 /* ignore BAD_PMP while resetting */
2127 if (unlikely(resetting))
2128 status &= ~PORT_IRQ_BAD_PMP;
2129
2130 /* If we are getting PhyRdy, this is
2131 * just a power state change, we should
2132 * clear out this, plus the PhyRdy/Comm
2133 * Wake bits from Serror
2134 */
2135 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2136 (status & PORT_IRQ_PHYRDY)) {
2137 status &= ~PORT_IRQ_PHYRDY;
2138 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2139 }
2140
2141 if (unlikely(status & PORT_IRQ_ERROR)) {
2142 ahci_error_intr(ap, status);
2143 return;
2144 }
2145
2146 if (status & PORT_IRQ_SDB_FIS) {
2147 /* If SNotification is available, leave notification
2148 * handling to sata_async_notification(). If not,
2149 * emulate it by snooping SDB FIS RX area.
2150 *
2151 * Snooping FIS RX area is probably cheaper than
2152 * poking SNotification but some constrollers which
2153 * implement SNotification, ICH9 for example, don't
2154 * store AN SDB FIS into receive area.
2155 */
2156 if (hpriv->cap & HOST_CAP_SNTF)
2157 sata_async_notification(ap);
2158 else {
2159 /* If the 'N' bit in word 0 of the FIS is set,
2160 * we just received asynchronous notification.
2161 * Tell libata about it.
2162 */
2163 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2164 u32 f0 = le32_to_cpu(f[0]);
2165
2166 if (f0 & (1 << 15))
2167 sata_async_notification(ap);
2168 }
2169 }
2170
2171 /* pp->active_link is valid iff any command is in flight */
2172 if (ap->qc_active && pp->active_link->sactive)
2173 qc_active = readl(port_mmio + PORT_SCR_ACT);
2174 else
2175 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2176
2177 rc = ata_qc_complete_multiple(ap, qc_active);
2178
2179 /* while resetting, invalid completions are expected */
2180 if (unlikely(rc < 0 && !resetting)) {
2181 ehi->err_mask |= AC_ERR_HSM;
2182 ehi->action |= ATA_EH_RESET;
2183 ata_port_freeze(ap);
2184 }
2185 }
2186
2187 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2188 {
2189 struct ata_host *host = dev_instance;
2190 struct ahci_host_priv *hpriv;
2191 unsigned int i, handled = 0;
2192 void __iomem *mmio;
2193 u32 irq_stat, irq_masked;
2194
2195 VPRINTK("ENTER\n");
2196
2197 hpriv = host->private_data;
2198 mmio = host->iomap[AHCI_PCI_BAR];
2199
2200 /* sigh. 0xffffffff is a valid return from h/w */
2201 irq_stat = readl(mmio + HOST_IRQ_STAT);
2202 if (!irq_stat)
2203 return IRQ_NONE;
2204
2205 irq_masked = irq_stat & hpriv->port_map;
2206
2207 spin_lock(&host->lock);
2208
2209 for (i = 0; i < host->n_ports; i++) {
2210 struct ata_port *ap;
2211
2212 if (!(irq_masked & (1 << i)))
2213 continue;
2214
2215 ap = host->ports[i];
2216 if (ap) {
2217 ahci_port_intr(ap);
2218 VPRINTK("port %u\n", i);
2219 } else {
2220 VPRINTK("port %u (no irq)\n", i);
2221 if (ata_ratelimit())
2222 dev_printk(KERN_WARNING, host->dev,
2223 "interrupt on disabled port %u\n", i);
2224 }
2225
2226 handled = 1;
2227 }
2228
2229 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2230 * it should be cleared after all the port events are cleared;
2231 * otherwise, it will raise a spurious interrupt after each
2232 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2233 * information.
2234 *
2235 * Also, use the unmasked value to clear interrupt as spurious
2236 * pending event on a dummy port might cause screaming IRQ.
2237 */
2238 writel(irq_stat, mmio + HOST_IRQ_STAT);
2239
2240 spin_unlock(&host->lock);
2241
2242 VPRINTK("EXIT\n");
2243
2244 return IRQ_RETVAL(handled);
2245 }
2246
2247 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2248 {
2249 struct ata_port *ap = qc->ap;
2250 void __iomem *port_mmio = ahci_port_base(ap);
2251 struct ahci_port_priv *pp = ap->private_data;
2252
2253 /* Keep track of the currently active link. It will be used
2254 * in completion path to determine whether NCQ phase is in
2255 * progress.
2256 */
2257 pp->active_link = qc->dev->link;
2258
2259 if (qc->tf.protocol == ATA_PROT_NCQ)
2260 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2261 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2262
2263 ahci_sw_activity(qc->dev->link);
2264
2265 return 0;
2266 }
2267
2268 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2269 {
2270 struct ahci_port_priv *pp = qc->ap->private_data;
2271 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2272
2273 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2274 return true;
2275 }
2276
2277 static void ahci_freeze(struct ata_port *ap)
2278 {
2279 void __iomem *port_mmio = ahci_port_base(ap);
2280
2281 /* turn IRQ off */
2282 writel(0, port_mmio + PORT_IRQ_MASK);
2283 }
2284
2285 static void ahci_thaw(struct ata_port *ap)
2286 {
2287 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2288 void __iomem *port_mmio = ahci_port_base(ap);
2289 u32 tmp;
2290 struct ahci_port_priv *pp = ap->private_data;
2291
2292 /* clear IRQ */
2293 tmp = readl(port_mmio + PORT_IRQ_STAT);
2294 writel(tmp, port_mmio + PORT_IRQ_STAT);
2295 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2296
2297 /* turn IRQ back on */
2298 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2299 }
2300
2301 static void ahci_error_handler(struct ata_port *ap)
2302 {
2303 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2304 /* restart engine */
2305 ahci_stop_engine(ap);
2306 ahci_start_engine(ap);
2307 }
2308
2309 sata_pmp_error_handler(ap);
2310 }
2311
2312 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2313 {
2314 struct ata_port *ap = qc->ap;
2315
2316 /* make DMA engine forget about the failed command */
2317 if (qc->flags & ATA_QCFLAG_FAILED)
2318 ahci_kick_engine(ap, 1);
2319 }
2320
2321 static void ahci_pmp_attach(struct ata_port *ap)
2322 {
2323 void __iomem *port_mmio = ahci_port_base(ap);
2324 struct ahci_port_priv *pp = ap->private_data;
2325 u32 cmd;
2326
2327 cmd = readl(port_mmio + PORT_CMD);
2328 cmd |= PORT_CMD_PMP;
2329 writel(cmd, port_mmio + PORT_CMD);
2330
2331 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2332 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2333 }
2334
2335 static void ahci_pmp_detach(struct ata_port *ap)
2336 {
2337 void __iomem *port_mmio = ahci_port_base(ap);
2338 struct ahci_port_priv *pp = ap->private_data;
2339 u32 cmd;
2340
2341 cmd = readl(port_mmio + PORT_CMD);
2342 cmd &= ~PORT_CMD_PMP;
2343 writel(cmd, port_mmio + PORT_CMD);
2344
2345 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2346 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2347 }
2348
2349 static int ahci_port_resume(struct ata_port *ap)
2350 {
2351 ahci_power_up(ap);
2352 ahci_start_port(ap);
2353
2354 if (sata_pmp_attached(ap))
2355 ahci_pmp_attach(ap);
2356 else
2357 ahci_pmp_detach(ap);
2358
2359 return 0;
2360 }
2361
2362 #ifdef CONFIG_PM
2363 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2364 {
2365 const char *emsg = NULL;
2366 int rc;
2367
2368 rc = ahci_deinit_port(ap, &emsg);
2369 if (rc == 0)
2370 ahci_power_down(ap);
2371 else {
2372 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2373 ahci_start_port(ap);
2374 }
2375
2376 return rc;
2377 }
2378
2379 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2380 {
2381 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2382 struct ahci_host_priv *hpriv = host->private_data;
2383 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2384 u32 ctl;
2385
2386 if (mesg.event & PM_EVENT_SUSPEND &&
2387 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2388 dev_printk(KERN_ERR, &pdev->dev,
2389 "BIOS update required for suspend/resume\n");
2390 return -EIO;
2391 }
2392
2393 if (mesg.event & PM_EVENT_SLEEP) {
2394 /* AHCI spec rev1.1 section 8.3.3:
2395 * Software must disable interrupts prior to requesting a
2396 * transition of the HBA to D3 state.
2397 */
2398 ctl = readl(mmio + HOST_CTL);
2399 ctl &= ~HOST_IRQ_EN;
2400 writel(ctl, mmio + HOST_CTL);
2401 readl(mmio + HOST_CTL); /* flush */
2402 }
2403
2404 return ata_pci_device_suspend(pdev, mesg);
2405 }
2406
2407 static int ahci_pci_device_resume(struct pci_dev *pdev)
2408 {
2409 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2410 int rc;
2411
2412 rc = ata_pci_device_do_resume(pdev);
2413 if (rc)
2414 return rc;
2415
2416 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2417 rc = ahci_reset_controller(host);
2418 if (rc)
2419 return rc;
2420
2421 ahci_init_controller(host);
2422 }
2423
2424 ata_host_resume(host);
2425
2426 return 0;
2427 }
2428 #endif
2429
2430 static int ahci_port_start(struct ata_port *ap)
2431 {
2432 struct device *dev = ap->host->dev;
2433 struct ahci_port_priv *pp;
2434 void *mem;
2435 dma_addr_t mem_dma;
2436
2437 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2438 if (!pp)
2439 return -ENOMEM;
2440
2441 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2442 GFP_KERNEL);
2443 if (!mem)
2444 return -ENOMEM;
2445 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2446
2447 /*
2448 * First item in chunk of DMA memory: 32-slot command table,
2449 * 32 bytes each in size
2450 */
2451 pp->cmd_slot = mem;
2452 pp->cmd_slot_dma = mem_dma;
2453
2454 mem += AHCI_CMD_SLOT_SZ;
2455 mem_dma += AHCI_CMD_SLOT_SZ;
2456
2457 /*
2458 * Second item: Received-FIS area
2459 */
2460 pp->rx_fis = mem;
2461 pp->rx_fis_dma = mem_dma;
2462
2463 mem += AHCI_RX_FIS_SZ;
2464 mem_dma += AHCI_RX_FIS_SZ;
2465
2466 /*
2467 * Third item: data area for storing a single command
2468 * and its scatter-gather table
2469 */
2470 pp->cmd_tbl = mem;
2471 pp->cmd_tbl_dma = mem_dma;
2472
2473 /*
2474 * Save off initial list of interrupts to be enabled.
2475 * This could be changed later
2476 */
2477 pp->intr_mask = DEF_PORT_IRQ;
2478
2479 ap->private_data = pp;
2480
2481 /* engage engines, captain */
2482 return ahci_port_resume(ap);
2483 }
2484
2485 static void ahci_port_stop(struct ata_port *ap)
2486 {
2487 const char *emsg = NULL;
2488 int rc;
2489
2490 /* de-initialize port */
2491 rc = ahci_deinit_port(ap, &emsg);
2492 if (rc)
2493 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2494 }
2495
2496 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2497 {
2498 int rc;
2499
2500 if (using_dac &&
2501 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2502 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2503 if (rc) {
2504 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2505 if (rc) {
2506 dev_printk(KERN_ERR, &pdev->dev,
2507 "64-bit DMA enable failed\n");
2508 return rc;
2509 }
2510 }
2511 } else {
2512 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2513 if (rc) {
2514 dev_printk(KERN_ERR, &pdev->dev,
2515 "32-bit DMA enable failed\n");
2516 return rc;
2517 }
2518 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2519 if (rc) {
2520 dev_printk(KERN_ERR, &pdev->dev,
2521 "32-bit consistent DMA enable failed\n");
2522 return rc;
2523 }
2524 }
2525 return 0;
2526 }
2527
2528 static void ahci_print_info(struct ata_host *host)
2529 {
2530 struct ahci_host_priv *hpriv = host->private_data;
2531 struct pci_dev *pdev = to_pci_dev(host->dev);
2532 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2533 u32 vers, cap, impl, speed;
2534 const char *speed_s;
2535 u16 cc;
2536 const char *scc_s;
2537
2538 vers = readl(mmio + HOST_VERSION);
2539 cap = hpriv->cap;
2540 impl = hpriv->port_map;
2541
2542 speed = (cap >> 20) & 0xf;
2543 if (speed == 1)
2544 speed_s = "1.5";
2545 else if (speed == 2)
2546 speed_s = "3";
2547 else if (speed == 3)
2548 speed_s = "6";
2549 else
2550 speed_s = "?";
2551
2552 pci_read_config_word(pdev, 0x0a, &cc);
2553 if (cc == PCI_CLASS_STORAGE_IDE)
2554 scc_s = "IDE";
2555 else if (cc == PCI_CLASS_STORAGE_SATA)
2556 scc_s = "SATA";
2557 else if (cc == PCI_CLASS_STORAGE_RAID)
2558 scc_s = "RAID";
2559 else
2560 scc_s = "unknown";
2561
2562 dev_printk(KERN_INFO, &pdev->dev,
2563 "AHCI %02x%02x.%02x%02x "
2564 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2565 ,
2566
2567 (vers >> 24) & 0xff,
2568 (vers >> 16) & 0xff,
2569 (vers >> 8) & 0xff,
2570 vers & 0xff,
2571
2572 ((cap >> 8) & 0x1f) + 1,
2573 (cap & 0x1f) + 1,
2574 speed_s,
2575 impl,
2576 scc_s);
2577
2578 dev_printk(KERN_INFO, &pdev->dev,
2579 "flags: "
2580 "%s%s%s%s%s%s%s"
2581 "%s%s%s%s%s%s%s"
2582 "%s\n"
2583 ,
2584
2585 cap & (1 << 31) ? "64bit " : "",
2586 cap & (1 << 30) ? "ncq " : "",
2587 cap & (1 << 29) ? "sntf " : "",
2588 cap & (1 << 28) ? "ilck " : "",
2589 cap & (1 << 27) ? "stag " : "",
2590 cap & (1 << 26) ? "pm " : "",
2591 cap & (1 << 25) ? "led " : "",
2592
2593 cap & (1 << 24) ? "clo " : "",
2594 cap & (1 << 19) ? "nz " : "",
2595 cap & (1 << 18) ? "only " : "",
2596 cap & (1 << 17) ? "pmp " : "",
2597 cap & (1 << 15) ? "pio " : "",
2598 cap & (1 << 14) ? "slum " : "",
2599 cap & (1 << 13) ? "part " : "",
2600 cap & (1 << 6) ? "ems ": ""
2601 );
2602 }
2603
2604 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2605 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2606 * support PMP and the 4726 either directly exports the device
2607 * attached to the first downstream port or acts as a hardware storage
2608 * controller and emulate a single ATA device (can be RAID 0/1 or some
2609 * other configuration).
2610 *
2611 * When there's no device attached to the first downstream port of the
2612 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2613 * configure the 4726. However, ATA emulation of the device is very
2614 * lame. It doesn't send signature D2H Reg FIS after the initial
2615 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2616 *
2617 * The following function works around the problem by always using
2618 * hardreset on the port and not depending on receiving signature FIS
2619 * afterward. If signature FIS isn't received soon, ATA class is
2620 * assumed without follow-up softreset.
2621 */
2622 static void ahci_p5wdh_workaround(struct ata_host *host)
2623 {
2624 static struct dmi_system_id sysids[] = {
2625 {
2626 .ident = "P5W DH Deluxe",
2627 .matches = {
2628 DMI_MATCH(DMI_SYS_VENDOR,
2629 "ASUSTEK COMPUTER INC"),
2630 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2631 },
2632 },
2633 { }
2634 };
2635 struct pci_dev *pdev = to_pci_dev(host->dev);
2636
2637 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2638 dmi_check_system(sysids)) {
2639 struct ata_port *ap = host->ports[1];
2640
2641 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2642 "Deluxe on-board SIMG4726 workaround\n");
2643
2644 ap->ops = &ahci_p5wdh_ops;
2645 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2646 }
2647 }
2648
2649 /*
2650 * SB600 ahci controller on certain boards can't do 64bit DMA with
2651 * older BIOS.
2652 */
2653 static bool ahci_sb600_32bit_only(struct pci_dev *pdev)
2654 {
2655 static const struct dmi_system_id sysids[] = {
2656 /*
2657 * The oldest version known to be broken is 0901 and
2658 * working is 1501 which was released on 2007-10-26.
2659 * Force 32bit DMA on anything older than 1501.
2660 * Please read bko#9412 for more info.
2661 */
2662 {
2663 .ident = "ASUS M2A-VM",
2664 .matches = {
2665 DMI_MATCH(DMI_BOARD_VENDOR,
2666 "ASUSTeK Computer INC."),
2667 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2668 },
2669 .driver_data = "20071026", /* yyyymmdd */
2670 },
2671 /*
2672 * It's yet unknown whether more recent BIOS fixes the
2673 * problem. Blacklist the whole board for the time
2674 * being. Please read the following thread for more
2675 * info.
2676 *
2677 * http://thread.gmane.org/gmane.linux.ide/42326
2678 */
2679 {
2680 .ident = "Gigabyte GA-MA69VM-S2",
2681 .matches = {
2682 DMI_MATCH(DMI_BOARD_VENDOR,
2683 "Gigabyte Technology Co., Ltd."),
2684 DMI_MATCH(DMI_BOARD_NAME, "GA-MA69VM-S2"),
2685 },
2686 },
2687 { }
2688 };
2689 const struct dmi_system_id *match;
2690
2691 match = dmi_first_match(sysids);
2692 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
2693 !match)
2694 return false;
2695
2696 if (match->driver_data) {
2697 int year, month, date;
2698 char buf[9];
2699
2700 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2701 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2702
2703 if (strcmp(buf, match->driver_data) >= 0)
2704 return false;
2705
2706 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2707 "forcing 32bit DMA, update BIOS\n", match->ident);
2708 } else
2709 dev_printk(KERN_WARNING, &pdev->dev, "%s: this board can't "
2710 "do 64bit DMA, forcing 32bit\n", match->ident);
2711
2712 return true;
2713 }
2714
2715 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2716 {
2717 static const struct dmi_system_id broken_systems[] = {
2718 {
2719 .ident = "HP Compaq nx6310",
2720 .matches = {
2721 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2722 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2723 },
2724 /* PCI slot number of the controller */
2725 .driver_data = (void *)0x1FUL,
2726 },
2727 {
2728 .ident = "HP Compaq 6720s",
2729 .matches = {
2730 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2731 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2732 },
2733 /* PCI slot number of the controller */
2734 .driver_data = (void *)0x1FUL,
2735 },
2736
2737 { } /* terminate list */
2738 };
2739 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2740
2741 if (dmi) {
2742 unsigned long slot = (unsigned long)dmi->driver_data;
2743 /* apply the quirk only to on-board controllers */
2744 return slot == PCI_SLOT(pdev->devfn);
2745 }
2746
2747 return false;
2748 }
2749
2750 static bool ahci_broken_suspend(struct pci_dev *pdev)
2751 {
2752 static const struct dmi_system_id sysids[] = {
2753 /*
2754 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2755 * to the harddisk doesn't become online after
2756 * resuming from STR. Warn and fail suspend.
2757 */
2758 {
2759 .ident = "dv4",
2760 .matches = {
2761 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2762 DMI_MATCH(DMI_PRODUCT_NAME,
2763 "HP Pavilion dv4 Notebook PC"),
2764 },
2765 .driver_data = "F.30", /* cutoff BIOS version */
2766 },
2767 {
2768 .ident = "dv5",
2769 .matches = {
2770 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2771 DMI_MATCH(DMI_PRODUCT_NAME,
2772 "HP Pavilion dv5 Notebook PC"),
2773 },
2774 .driver_data = "F.16", /* cutoff BIOS version */
2775 },
2776 {
2777 .ident = "dv6",
2778 .matches = {
2779 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2780 DMI_MATCH(DMI_PRODUCT_NAME,
2781 "HP Pavilion dv6 Notebook PC"),
2782 },
2783 .driver_data = "F.21", /* cutoff BIOS version */
2784 },
2785 {
2786 .ident = "HDX18",
2787 .matches = {
2788 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2789 DMI_MATCH(DMI_PRODUCT_NAME,
2790 "HP HDX18 Notebook PC"),
2791 },
2792 .driver_data = "F.23", /* cutoff BIOS version */
2793 },
2794 { } /* terminate list */
2795 };
2796 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2797 const char *ver;
2798
2799 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2800 return false;
2801
2802 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2803
2804 return !ver || strcmp(ver, dmi->driver_data) < 0;
2805 }
2806
2807 static bool ahci_broken_online(struct pci_dev *pdev)
2808 {
2809 #define ENCODE_BUSDEVFN(bus, slot, func) \
2810 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2811 static const struct dmi_system_id sysids[] = {
2812 /*
2813 * There are several gigabyte boards which use
2814 * SIMG5723s configured as hardware RAID. Certain
2815 * 5723 firmware revisions shipped there keep the link
2816 * online but fail to answer properly to SRST or
2817 * IDENTIFY when no device is attached downstream
2818 * causing libata to retry quite a few times leading
2819 * to excessive detection delay.
2820 *
2821 * As these firmwares respond to the second reset try
2822 * with invalid device signature, considering unknown
2823 * sig as offline works around the problem acceptably.
2824 */
2825 {
2826 .ident = "EP45-DQ6",
2827 .matches = {
2828 DMI_MATCH(DMI_BOARD_VENDOR,
2829 "Gigabyte Technology Co., Ltd."),
2830 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2831 },
2832 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2833 },
2834 {
2835 .ident = "EP45-DS5",
2836 .matches = {
2837 DMI_MATCH(DMI_BOARD_VENDOR,
2838 "Gigabyte Technology Co., Ltd."),
2839 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2840 },
2841 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2842 },
2843 { } /* terminate list */
2844 };
2845 #undef ENCODE_BUSDEVFN
2846 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2847 unsigned int val;
2848
2849 if (!dmi)
2850 return false;
2851
2852 val = (unsigned long)dmi->driver_data;
2853
2854 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2855 }
2856
2857 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2858 {
2859 static int printed_version;
2860 unsigned int board_id = ent->driver_data;
2861 struct ata_port_info pi = ahci_port_info[board_id];
2862 const struct ata_port_info *ppi[] = { &pi, NULL };
2863 struct device *dev = &pdev->dev;
2864 struct ahci_host_priv *hpriv;
2865 struct ata_host *host;
2866 int n_ports, i, rc;
2867
2868 VPRINTK("ENTER\n");
2869
2870 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2871
2872 if (!printed_version++)
2873 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2874
2875 /* The AHCI driver can only drive the SATA ports, the PATA driver
2876 can drive them all so if both drivers are selected make sure
2877 AHCI stays out of the way */
2878 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2879 return -ENODEV;
2880
2881 /* acquire resources */
2882 rc = pcim_enable_device(pdev);
2883 if (rc)
2884 return rc;
2885
2886 /* AHCI controllers often implement SFF compatible interface.
2887 * Grab all PCI BARs just in case.
2888 */
2889 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2890 if (rc == -EBUSY)
2891 pcim_pin_device(pdev);
2892 if (rc)
2893 return rc;
2894
2895 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2896 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2897 u8 map;
2898
2899 /* ICH6s share the same PCI ID for both piix and ahci
2900 * modes. Enabling ahci mode while MAP indicates
2901 * combined mode is a bad idea. Yield to ata_piix.
2902 */
2903 pci_read_config_byte(pdev, ICH_MAP, &map);
2904 if (map & 0x3) {
2905 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2906 "combined mode, can't enable AHCI mode\n");
2907 return -ENODEV;
2908 }
2909 }
2910
2911 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2912 if (!hpriv)
2913 return -ENOMEM;
2914 hpriv->flags |= (unsigned long)pi.private_data;
2915
2916 /* MCP65 revision A1 and A2 can't do MSI */
2917 if (board_id == board_ahci_mcp65 &&
2918 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2919 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2920
2921 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2922 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2923 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2924
2925 /* apply sb600 32bit only quirk */
2926 if (ahci_sb600_32bit_only(pdev))
2927 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2928
2929 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2930 pci_enable_msi(pdev);
2931
2932 /* save initial config */
2933 ahci_save_initial_config(pdev, hpriv);
2934
2935 /* prepare host */
2936 if (hpriv->cap & HOST_CAP_NCQ)
2937 pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
2938
2939 if (hpriv->cap & HOST_CAP_PMP)
2940 pi.flags |= ATA_FLAG_PMP;
2941
2942 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2943 u8 messages;
2944 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2945 u32 em_loc = readl(mmio + HOST_EM_LOC);
2946 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2947
2948 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2949
2950 /* we only support LED message type right now */
2951 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2952 /* store em_loc */
2953 hpriv->em_loc = ((em_loc >> 16) * 4);
2954 pi.flags |= ATA_FLAG_EM;
2955 if (!(em_ctl & EM_CTL_ALHD))
2956 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2957 }
2958 }
2959
2960 if (ahci_broken_system_poweroff(pdev)) {
2961 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2962 dev_info(&pdev->dev,
2963 "quirky BIOS, skipping spindown on poweroff\n");
2964 }
2965
2966 if (ahci_broken_suspend(pdev)) {
2967 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2968 dev_printk(KERN_WARNING, &pdev->dev,
2969 "BIOS update required for suspend/resume\n");
2970 }
2971
2972 if (ahci_broken_online(pdev)) {
2973 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2974 dev_info(&pdev->dev,
2975 "online status unreliable, applying workaround\n");
2976 }
2977
2978 /* CAP.NP sometimes indicate the index of the last enabled
2979 * port, at other times, that of the last possible port, so
2980 * determining the maximum port number requires looking at
2981 * both CAP.NP and port_map.
2982 */
2983 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2984
2985 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2986 if (!host)
2987 return -ENOMEM;
2988 host->iomap = pcim_iomap_table(pdev);
2989 host->private_data = hpriv;
2990
2991 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
2992 host->flags |= ATA_HOST_PARALLEL_SCAN;
2993 else
2994 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
2995
2996 if (pi.flags & ATA_FLAG_EM)
2997 ahci_reset_em(host);
2998
2999 for (i = 0; i < host->n_ports; i++) {
3000 struct ata_port *ap = host->ports[i];
3001
3002 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3003 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3004 0x100 + ap->port_no * 0x80, "port");
3005
3006 /* set initial link pm policy */
3007 ap->pm_policy = NOT_AVAILABLE;
3008
3009 /* set enclosure management message type */
3010 if (ap->flags & ATA_FLAG_EM)
3011 ap->em_message_type = ahci_em_messages;
3012
3013
3014 /* disabled/not-implemented port */
3015 if (!(hpriv->port_map & (1 << i)))
3016 ap->ops = &ata_dummy_port_ops;
3017 }
3018
3019 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3020 ahci_p5wdh_workaround(host);
3021
3022 /* initialize adapter */
3023 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
3024 if (rc)
3025 return rc;
3026
3027 rc = ahci_reset_controller(host);
3028 if (rc)
3029 return rc;
3030
3031 ahci_init_controller(host);
3032 ahci_print_info(host);
3033
3034 pci_set_master(pdev);
3035 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3036 &ahci_sht);
3037 }
3038
3039 static int __init ahci_init(void)
3040 {
3041 return pci_register_driver(&ahci_pci_driver);
3042 }
3043
3044 static void __exit ahci_exit(void)
3045 {
3046 pci_unregister_driver(&ahci_pci_driver);
3047 }
3048
3049
3050 MODULE_AUTHOR("Jeff Garzik");
3051 MODULE_DESCRIPTION("AHCI SATA low-level driver");
3052 MODULE_LICENSE("GPL");
3053 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
3054 MODULE_VERSION(DRV_VERSION);
3055
3056 module_init(ahci_init);
3057 module_exit(ahci_exit);
Linux kernel - Deliverables
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