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[PATCH] ahci: kill AHCI_FLAG_RESET_NEEDS_CLO
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
82
83 /* global controller registers */
84 HOST_CAP = 0x00, /* host capabilities */
85 HOST_CTL = 0x04, /* global host control */
86 HOST_IRQ_STAT = 0x08, /* interrupt status */
87 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
88 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
89
90 /* HOST_CTL bits */
91 HOST_RESET = (1 << 0), /* reset controller; self-clear */
92 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
94
95 /* HOST_CAP bits */
96 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
97 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
99 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
100 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
101
102 /* registers for each SATA port */
103 PORT_LST_ADDR = 0x00, /* command list DMA addr */
104 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
105 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
106 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
107 PORT_IRQ_STAT = 0x10, /* interrupt status */
108 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
109 PORT_CMD = 0x18, /* port command */
110 PORT_TFDATA = 0x20, /* taskfile data */
111 PORT_SIG = 0x24, /* device TF signature */
112 PORT_CMD_ISSUE = 0x38, /* command issue */
113 PORT_SCR = 0x28, /* SATA phy register block */
114 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
115 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
116 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
117 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
118
119 /* PORT_IRQ_{STAT,MASK} bits */
120 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
121 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
122 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
123 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
124 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
125 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
126 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
127 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
128
129 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
130 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
131 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
132 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
133 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
134 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
135 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
136 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
137 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
138
139 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
140 PORT_IRQ_IF_ERR |
141 PORT_IRQ_CONNECT |
142 PORT_IRQ_PHYRDY |
143 PORT_IRQ_UNK_FIS,
144 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
145 PORT_IRQ_TF_ERR |
146 PORT_IRQ_HBUS_DATA_ERR,
147 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
148 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
149 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
150
151 /* PORT_CMD bits */
152 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
153 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
154 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
155 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
156 PORT_CMD_CLO = (1 << 3), /* Command list override */
157 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
158 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
159 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
160
161 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
162 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
163 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
164 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
165
166 /* hpriv->flags bits */
167 AHCI_FLAG_MSI = (1 << 0),
168
169 /* ap->flags bits */
170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
172 };
173
174 struct ahci_cmd_hdr {
175 u32 opts;
176 u32 status;
177 u32 tbl_addr;
178 u32 tbl_addr_hi;
179 u32 reserved[4];
180 };
181
182 struct ahci_sg {
183 u32 addr;
184 u32 addr_hi;
185 u32 reserved;
186 u32 flags_size;
187 };
188
189 struct ahci_host_priv {
190 unsigned long flags;
191 u32 cap; /* cache of HOST_CAP register */
192 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
193 };
194
195 struct ahci_port_priv {
196 struct ahci_cmd_hdr *cmd_slot;
197 dma_addr_t cmd_slot_dma;
198 void *cmd_tbl;
199 dma_addr_t cmd_tbl_dma;
200 void *rx_fis;
201 dma_addr_t rx_fis_dma;
202 };
203
204 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
205 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
206 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
207 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
208 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
209 static void ahci_irq_clear(struct ata_port *ap);
210 static int ahci_port_start(struct ata_port *ap);
211 static void ahci_port_stop(struct ata_port *ap);
212 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
213 static void ahci_qc_prep(struct ata_queued_cmd *qc);
214 static u8 ahci_check_status(struct ata_port *ap);
215 static void ahci_freeze(struct ata_port *ap);
216 static void ahci_thaw(struct ata_port *ap);
217 static void ahci_error_handler(struct ata_port *ap);
218 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
219 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
220 static int ahci_port_resume(struct ata_port *ap);
221 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
222 static int ahci_pci_device_resume(struct pci_dev *pdev);
223 static void ahci_remove_one (struct pci_dev *pdev);
224
225 static struct scsi_host_template ahci_sht = {
226 .module = THIS_MODULE,
227 .name = DRV_NAME,
228 .ioctl = ata_scsi_ioctl,
229 .queuecommand = ata_scsi_queuecmd,
230 .change_queue_depth = ata_scsi_change_queue_depth,
231 .can_queue = AHCI_MAX_CMDS - 1,
232 .this_id = ATA_SHT_THIS_ID,
233 .sg_tablesize = AHCI_MAX_SG,
234 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
235 .emulated = ATA_SHT_EMULATED,
236 .use_clustering = AHCI_USE_CLUSTERING,
237 .proc_name = DRV_NAME,
238 .dma_boundary = AHCI_DMA_BOUNDARY,
239 .slave_configure = ata_scsi_slave_config,
240 .slave_destroy = ata_scsi_slave_destroy,
241 .bios_param = ata_std_bios_param,
242 .suspend = ata_scsi_device_suspend,
243 .resume = ata_scsi_device_resume,
244 };
245
246 static const struct ata_port_operations ahci_ops = {
247 .port_disable = ata_port_disable,
248
249 .check_status = ahci_check_status,
250 .check_altstatus = ahci_check_status,
251 .dev_select = ata_noop_dev_select,
252
253 .tf_read = ahci_tf_read,
254
255 .qc_prep = ahci_qc_prep,
256 .qc_issue = ahci_qc_issue,
257
258 .irq_handler = ahci_interrupt,
259 .irq_clear = ahci_irq_clear,
260
261 .scr_read = ahci_scr_read,
262 .scr_write = ahci_scr_write,
263
264 .freeze = ahci_freeze,
265 .thaw = ahci_thaw,
266
267 .error_handler = ahci_error_handler,
268 .post_internal_cmd = ahci_post_internal_cmd,
269
270 .port_suspend = ahci_port_suspend,
271 .port_resume = ahci_port_resume,
272
273 .port_start = ahci_port_start,
274 .port_stop = ahci_port_stop,
275 };
276
277 static const struct ata_port_info ahci_port_info[] = {
278 /* board_ahci */
279 {
280 .sht = &ahci_sht,
281 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
282 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
283 ATA_FLAG_SKIP_D2H_BSY,
284 .pio_mask = 0x1f, /* pio0-4 */
285 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
286 .port_ops = &ahci_ops,
287 },
288 /* board_ahci_vt8251 */
289 {
290 .sht = &ahci_sht,
291 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
292 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
293 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_NO_NCQ,
294 .pio_mask = 0x1f, /* pio0-4 */
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &ahci_ops,
297 },
298 /* board_ahci_ign_iferr */
299 {
300 .sht = &ahci_sht,
301 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
302 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
303 ATA_FLAG_SKIP_D2H_BSY |
304 AHCI_FLAG_IGN_IRQ_IF_ERR,
305 .pio_mask = 0x1f, /* pio0-4 */
306 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
307 .port_ops = &ahci_ops,
308 },
309 };
310
311 static const struct pci_device_id ahci_pci_tbl[] = {
312 /* Intel */
313 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
314 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
315 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
316 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
317 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
318 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
319 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
320 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
321 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
322 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
323 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
324 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
325 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
326 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
327 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
328 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
329 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
330 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
331 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
332 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
333 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
334 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
335 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
336 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
337 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
338 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
339
340 /* JMicron */
341 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
342 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
343 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
344 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
345 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
346
347 /* ATI */
348 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
349 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
350
351 /* VIA */
352 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
353
354 /* NVIDIA */
355 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
356 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
357 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
358 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
359 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
366 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
367
368 /* SiS */
369 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
370 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
371 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
372
373 { } /* terminate list */
374 };
375
376
377 static struct pci_driver ahci_pci_driver = {
378 .name = DRV_NAME,
379 .id_table = ahci_pci_tbl,
380 .probe = ahci_init_one,
381 .suspend = ahci_pci_device_suspend,
382 .resume = ahci_pci_device_resume,
383 .remove = ahci_remove_one,
384 };
385
386
387 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
388 {
389 return base + 0x100 + (port * 0x80);
390 }
391
392 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
393 {
394 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
395 }
396
397 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
398 {
399 unsigned int sc_reg;
400
401 switch (sc_reg_in) {
402 case SCR_STATUS: sc_reg = 0; break;
403 case SCR_CONTROL: sc_reg = 1; break;
404 case SCR_ERROR: sc_reg = 2; break;
405 case SCR_ACTIVE: sc_reg = 3; break;
406 default:
407 return 0xffffffffU;
408 }
409
410 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
411 }
412
413
414 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
415 u32 val)
416 {
417 unsigned int sc_reg;
418
419 switch (sc_reg_in) {
420 case SCR_STATUS: sc_reg = 0; break;
421 case SCR_CONTROL: sc_reg = 1; break;
422 case SCR_ERROR: sc_reg = 2; break;
423 case SCR_ACTIVE: sc_reg = 3; break;
424 default:
425 return;
426 }
427
428 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
429 }
430
431 static void ahci_start_engine(void __iomem *port_mmio)
432 {
433 u32 tmp;
434
435 /* start DMA */
436 tmp = readl(port_mmio + PORT_CMD);
437 tmp |= PORT_CMD_START;
438 writel(tmp, port_mmio + PORT_CMD);
439 readl(port_mmio + PORT_CMD); /* flush */
440 }
441
442 static int ahci_stop_engine(void __iomem *port_mmio)
443 {
444 u32 tmp;
445
446 tmp = readl(port_mmio + PORT_CMD);
447
448 /* check if the HBA is idle */
449 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
450 return 0;
451
452 /* setting HBA to idle */
453 tmp &= ~PORT_CMD_START;
454 writel(tmp, port_mmio + PORT_CMD);
455
456 /* wait for engine to stop. This could be as long as 500 msec */
457 tmp = ata_wait_register(port_mmio + PORT_CMD,
458 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
459 if (tmp & PORT_CMD_LIST_ON)
460 return -EIO;
461
462 return 0;
463 }
464
465 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
466 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
467 {
468 u32 tmp;
469
470 /* set FIS registers */
471 if (cap & HOST_CAP_64)
472 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
473 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
474
475 if (cap & HOST_CAP_64)
476 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
477 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
478
479 /* enable FIS reception */
480 tmp = readl(port_mmio + PORT_CMD);
481 tmp |= PORT_CMD_FIS_RX;
482 writel(tmp, port_mmio + PORT_CMD);
483
484 /* flush */
485 readl(port_mmio + PORT_CMD);
486 }
487
488 static int ahci_stop_fis_rx(void __iomem *port_mmio)
489 {
490 u32 tmp;
491
492 /* disable FIS reception */
493 tmp = readl(port_mmio + PORT_CMD);
494 tmp &= ~PORT_CMD_FIS_RX;
495 writel(tmp, port_mmio + PORT_CMD);
496
497 /* wait for completion, spec says 500ms, give it 1000 */
498 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
499 PORT_CMD_FIS_ON, 10, 1000);
500 if (tmp & PORT_CMD_FIS_ON)
501 return -EBUSY;
502
503 return 0;
504 }
505
506 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
507 {
508 u32 cmd;
509
510 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
511
512 /* spin up device */
513 if (cap & HOST_CAP_SSS) {
514 cmd |= PORT_CMD_SPIN_UP;
515 writel(cmd, port_mmio + PORT_CMD);
516 }
517
518 /* wake up link */
519 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
520 }
521
522 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
523 {
524 u32 cmd, scontrol;
525
526 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
527
528 if (cap & HOST_CAP_SSC) {
529 /* enable transitions to slumber mode */
530 scontrol = readl(port_mmio + PORT_SCR_CTL);
531 if ((scontrol & 0x0f00) > 0x100) {
532 scontrol &= ~0xf00;
533 writel(scontrol, port_mmio + PORT_SCR_CTL);
534 }
535
536 /* put device into slumber mode */
537 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
538
539 /* wait for the transition to complete */
540 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
541 PORT_CMD_ICC_SLUMBER, 1, 50);
542 }
543
544 /* put device into listen mode */
545 if (cap & HOST_CAP_SSS) {
546 /* first set PxSCTL.DET to 0 */
547 scontrol = readl(port_mmio + PORT_SCR_CTL);
548 scontrol &= ~0xf;
549 writel(scontrol, port_mmio + PORT_SCR_CTL);
550
551 /* then set PxCMD.SUD to 0 */
552 cmd &= ~PORT_CMD_SPIN_UP;
553 writel(cmd, port_mmio + PORT_CMD);
554 }
555 }
556
557 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
558 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
559 {
560 /* power up */
561 ahci_power_up(port_mmio, cap);
562
563 /* enable FIS reception */
564 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
565
566 /* enable DMA */
567 ahci_start_engine(port_mmio);
568 }
569
570 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
571 {
572 int rc;
573
574 /* disable DMA */
575 rc = ahci_stop_engine(port_mmio);
576 if (rc) {
577 *emsg = "failed to stop engine";
578 return rc;
579 }
580
581 /* disable FIS reception */
582 rc = ahci_stop_fis_rx(port_mmio);
583 if (rc) {
584 *emsg = "failed stop FIS RX";
585 return rc;
586 }
587
588 /* put device into slumber mode */
589 ahci_power_down(port_mmio, cap);
590
591 return 0;
592 }
593
594 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
595 {
596 u32 cap_save, tmp;
597
598 cap_save = readl(mmio + HOST_CAP);
599 cap_save &= ( (1<<28) | (1<<17) );
600 cap_save |= (1 << 27);
601
602 /* global controller reset */
603 tmp = readl(mmio + HOST_CTL);
604 if ((tmp & HOST_RESET) == 0) {
605 writel(tmp | HOST_RESET, mmio + HOST_CTL);
606 readl(mmio + HOST_CTL); /* flush */
607 }
608
609 /* reset must complete within 1 second, or
610 * the hardware should be considered fried.
611 */
612 ssleep(1);
613
614 tmp = readl(mmio + HOST_CTL);
615 if (tmp & HOST_RESET) {
616 dev_printk(KERN_ERR, &pdev->dev,
617 "controller reset failed (0x%x)\n", tmp);
618 return -EIO;
619 }
620
621 writel(HOST_AHCI_EN, mmio + HOST_CTL);
622 (void) readl(mmio + HOST_CTL); /* flush */
623 writel(cap_save, mmio + HOST_CAP);
624 writel(0xf, mmio + HOST_PORTS_IMPL);
625 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
626
627 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
628 u16 tmp16;
629
630 /* configure PCS */
631 pci_read_config_word(pdev, 0x92, &tmp16);
632 tmp16 |= 0xf;
633 pci_write_config_word(pdev, 0x92, tmp16);
634 }
635
636 return 0;
637 }
638
639 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
640 int n_ports, u32 cap)
641 {
642 int i, rc;
643 u32 tmp;
644
645 for (i = 0; i < n_ports; i++) {
646 void __iomem *port_mmio = ahci_port_base(mmio, i);
647 const char *emsg = NULL;
648
649 #if 0 /* BIOSen initialize this incorrectly */
650 if (!(hpriv->port_map & (1 << i)))
651 continue;
652 #endif
653
654 /* make sure port is not active */
655 rc = ahci_deinit_port(port_mmio, cap, &emsg);
656 if (rc)
657 dev_printk(KERN_WARNING, &pdev->dev,
658 "%s (%d)\n", emsg, rc);
659
660 /* clear SError */
661 tmp = readl(port_mmio + PORT_SCR_ERR);
662 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
663 writel(tmp, port_mmio + PORT_SCR_ERR);
664
665 /* clear port IRQ */
666 tmp = readl(port_mmio + PORT_IRQ_STAT);
667 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
668 if (tmp)
669 writel(tmp, port_mmio + PORT_IRQ_STAT);
670
671 writel(1 << i, mmio + HOST_IRQ_STAT);
672 }
673
674 tmp = readl(mmio + HOST_CTL);
675 VPRINTK("HOST_CTL 0x%x\n", tmp);
676 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
677 tmp = readl(mmio + HOST_CTL);
678 VPRINTK("HOST_CTL 0x%x\n", tmp);
679 }
680
681 static unsigned int ahci_dev_classify(struct ata_port *ap)
682 {
683 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
684 struct ata_taskfile tf;
685 u32 tmp;
686
687 tmp = readl(port_mmio + PORT_SIG);
688 tf.lbah = (tmp >> 24) & 0xff;
689 tf.lbam = (tmp >> 16) & 0xff;
690 tf.lbal = (tmp >> 8) & 0xff;
691 tf.nsect = (tmp) & 0xff;
692
693 return ata_dev_classify(&tf);
694 }
695
696 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
697 u32 opts)
698 {
699 dma_addr_t cmd_tbl_dma;
700
701 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
702
703 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
704 pp->cmd_slot[tag].status = 0;
705 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
706 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
707 }
708
709 static int ahci_clo(struct ata_port *ap)
710 {
711 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
712 struct ahci_host_priv *hpriv = ap->host->private_data;
713 u32 tmp;
714
715 if (!(hpriv->cap & HOST_CAP_CLO))
716 return -EOPNOTSUPP;
717
718 tmp = readl(port_mmio + PORT_CMD);
719 tmp |= PORT_CMD_CLO;
720 writel(tmp, port_mmio + PORT_CMD);
721
722 tmp = ata_wait_register(port_mmio + PORT_CMD,
723 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
724 if (tmp & PORT_CMD_CLO)
725 return -EIO;
726
727 return 0;
728 }
729
730 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
731 {
732 struct ahci_port_priv *pp = ap->private_data;
733 void __iomem *mmio = ap->host->mmio_base;
734 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
735 const u32 cmd_fis_len = 5; /* five dwords */
736 const char *reason = NULL;
737 struct ata_taskfile tf;
738 u32 tmp;
739 u8 *fis;
740 int rc;
741
742 DPRINTK("ENTER\n");
743
744 if (ata_port_offline(ap)) {
745 DPRINTK("PHY reports no device\n");
746 *class = ATA_DEV_NONE;
747 return 0;
748 }
749
750 /* prepare for SRST (AHCI-1.1 10.4.1) */
751 rc = ahci_stop_engine(port_mmio);
752 if (rc) {
753 reason = "failed to stop engine";
754 goto fail_restart;
755 }
756
757 /* check BUSY/DRQ, perform Command List Override if necessary */
758 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
759 rc = ahci_clo(ap);
760
761 if (rc == -EOPNOTSUPP) {
762 reason = "port busy but CLO unavailable";
763 goto fail_restart;
764 } else if (rc) {
765 reason = "port busy but CLO failed";
766 goto fail_restart;
767 }
768 }
769
770 /* restart engine */
771 ahci_start_engine(port_mmio);
772
773 ata_tf_init(ap->device, &tf);
774 fis = pp->cmd_tbl;
775
776 /* issue the first D2H Register FIS */
777 ahci_fill_cmd_slot(pp, 0,
778 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
779
780 tf.ctl |= ATA_SRST;
781 ata_tf_to_fis(&tf, fis, 0);
782 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
783
784 writel(1, port_mmio + PORT_CMD_ISSUE);
785
786 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
787 if (tmp & 0x1) {
788 rc = -EIO;
789 reason = "1st FIS failed";
790 goto fail;
791 }
792
793 /* spec says at least 5us, but be generous and sleep for 1ms */
794 msleep(1);
795
796 /* issue the second D2H Register FIS */
797 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
798
799 tf.ctl &= ~ATA_SRST;
800 ata_tf_to_fis(&tf, fis, 0);
801 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
802
803 writel(1, port_mmio + PORT_CMD_ISSUE);
804 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
805
806 /* spec mandates ">= 2ms" before checking status.
807 * We wait 150ms, because that was the magic delay used for
808 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
809 * between when the ATA command register is written, and then
810 * status is checked. Because waiting for "a while" before
811 * checking status is fine, post SRST, we perform this magic
812 * delay here as well.
813 */
814 msleep(150);
815
816 *class = ATA_DEV_NONE;
817 if (ata_port_online(ap)) {
818 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
819 rc = -EIO;
820 reason = "device not ready";
821 goto fail;
822 }
823 *class = ahci_dev_classify(ap);
824 }
825
826 DPRINTK("EXIT, class=%u\n", *class);
827 return 0;
828
829 fail_restart:
830 ahci_start_engine(port_mmio);
831 fail:
832 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
833 return rc;
834 }
835
836 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
837 {
838 struct ahci_port_priv *pp = ap->private_data;
839 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
840 struct ata_taskfile tf;
841 void __iomem *mmio = ap->host->mmio_base;
842 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
843 int rc;
844
845 DPRINTK("ENTER\n");
846
847 ahci_stop_engine(port_mmio);
848
849 /* clear D2H reception area to properly wait for D2H FIS */
850 ata_tf_init(ap->device, &tf);
851 tf.command = 0xff;
852 ata_tf_to_fis(&tf, d2h_fis, 0);
853
854 rc = sata_std_hardreset(ap, class);
855
856 ahci_start_engine(port_mmio);
857
858 if (rc == 0 && ata_port_online(ap))
859 *class = ahci_dev_classify(ap);
860 if (*class == ATA_DEV_UNKNOWN)
861 *class = ATA_DEV_NONE;
862
863 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
864 return rc;
865 }
866
867 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
868 {
869 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
870 u32 new_tmp, tmp;
871
872 ata_std_postreset(ap, class);
873
874 /* Make sure port's ATAPI bit is set appropriately */
875 new_tmp = tmp = readl(port_mmio + PORT_CMD);
876 if (*class == ATA_DEV_ATAPI)
877 new_tmp |= PORT_CMD_ATAPI;
878 else
879 new_tmp &= ~PORT_CMD_ATAPI;
880 if (new_tmp != tmp) {
881 writel(new_tmp, port_mmio + PORT_CMD);
882 readl(port_mmio + PORT_CMD); /* flush */
883 }
884 }
885
886 static u8 ahci_check_status(struct ata_port *ap)
887 {
888 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
889
890 return readl(mmio + PORT_TFDATA) & 0xFF;
891 }
892
893 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
894 {
895 struct ahci_port_priv *pp = ap->private_data;
896 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
897
898 ata_tf_from_fis(d2h_fis, tf);
899 }
900
901 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
902 {
903 struct scatterlist *sg;
904 struct ahci_sg *ahci_sg;
905 unsigned int n_sg = 0;
906
907 VPRINTK("ENTER\n");
908
909 /*
910 * Next, the S/G list.
911 */
912 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
913 ata_for_each_sg(sg, qc) {
914 dma_addr_t addr = sg_dma_address(sg);
915 u32 sg_len = sg_dma_len(sg);
916
917 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
918 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
919 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
920
921 ahci_sg++;
922 n_sg++;
923 }
924
925 return n_sg;
926 }
927
928 static void ahci_qc_prep(struct ata_queued_cmd *qc)
929 {
930 struct ata_port *ap = qc->ap;
931 struct ahci_port_priv *pp = ap->private_data;
932 int is_atapi = is_atapi_taskfile(&qc->tf);
933 void *cmd_tbl;
934 u32 opts;
935 const u32 cmd_fis_len = 5; /* five dwords */
936 unsigned int n_elem;
937
938 /*
939 * Fill in command table information. First, the header,
940 * a SATA Register - Host to Device command FIS.
941 */
942 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
943
944 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
945 if (is_atapi) {
946 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
947 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
948 }
949
950 n_elem = 0;
951 if (qc->flags & ATA_QCFLAG_DMAMAP)
952 n_elem = ahci_fill_sg(qc, cmd_tbl);
953
954 /*
955 * Fill in command slot information.
956 */
957 opts = cmd_fis_len | n_elem << 16;
958 if (qc->tf.flags & ATA_TFLAG_WRITE)
959 opts |= AHCI_CMD_WRITE;
960 if (is_atapi)
961 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
962
963 ahci_fill_cmd_slot(pp, qc->tag, opts);
964 }
965
966 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
967 {
968 struct ahci_port_priv *pp = ap->private_data;
969 struct ata_eh_info *ehi = &ap->eh_info;
970 unsigned int err_mask = 0, action = 0;
971 struct ata_queued_cmd *qc;
972 u32 serror;
973
974 ata_ehi_clear_desc(ehi);
975
976 /* AHCI needs SError cleared; otherwise, it might lock up */
977 serror = ahci_scr_read(ap, SCR_ERROR);
978 ahci_scr_write(ap, SCR_ERROR, serror);
979
980 /* analyze @irq_stat */
981 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
982
983 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
984 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
985 irq_stat &= ~PORT_IRQ_IF_ERR;
986
987 if (irq_stat & PORT_IRQ_TF_ERR)
988 err_mask |= AC_ERR_DEV;
989
990 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
991 err_mask |= AC_ERR_HOST_BUS;
992 action |= ATA_EH_SOFTRESET;
993 }
994
995 if (irq_stat & PORT_IRQ_IF_ERR) {
996 err_mask |= AC_ERR_ATA_BUS;
997 action |= ATA_EH_SOFTRESET;
998 ata_ehi_push_desc(ehi, ", interface fatal error");
999 }
1000
1001 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1002 ata_ehi_hotplugged(ehi);
1003 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1004 "connection status changed" : "PHY RDY changed");
1005 }
1006
1007 if (irq_stat & PORT_IRQ_UNK_FIS) {
1008 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1009
1010 err_mask |= AC_ERR_HSM;
1011 action |= ATA_EH_SOFTRESET;
1012 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1013 unk[0], unk[1], unk[2], unk[3]);
1014 }
1015
1016 /* okay, let's hand over to EH */
1017 ehi->serror |= serror;
1018 ehi->action |= action;
1019
1020 qc = ata_qc_from_tag(ap, ap->active_tag);
1021 if (qc)
1022 qc->err_mask |= err_mask;
1023 else
1024 ehi->err_mask |= err_mask;
1025
1026 if (irq_stat & PORT_IRQ_FREEZE)
1027 ata_port_freeze(ap);
1028 else
1029 ata_port_abort(ap);
1030 }
1031
1032 static void ahci_host_intr(struct ata_port *ap)
1033 {
1034 void __iomem *mmio = ap->host->mmio_base;
1035 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1036 struct ata_eh_info *ehi = &ap->eh_info;
1037 u32 status, qc_active;
1038 int rc;
1039
1040 status = readl(port_mmio + PORT_IRQ_STAT);
1041 writel(status, port_mmio + PORT_IRQ_STAT);
1042
1043 if (unlikely(status & PORT_IRQ_ERROR)) {
1044 ahci_error_intr(ap, status);
1045 return;
1046 }
1047
1048 if (ap->sactive)
1049 qc_active = readl(port_mmio + PORT_SCR_ACT);
1050 else
1051 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1052
1053 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1054 if (rc > 0)
1055 return;
1056 if (rc < 0) {
1057 ehi->err_mask |= AC_ERR_HSM;
1058 ehi->action |= ATA_EH_SOFTRESET;
1059 ata_port_freeze(ap);
1060 return;
1061 }
1062
1063 /* hmmm... a spurious interupt */
1064
1065 /* some devices send D2H reg with I bit set during NCQ command phase */
1066 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1067 return;
1068
1069 /* ignore interim PIO setup fis interrupts */
1070 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1071 return;
1072
1073 if (ata_ratelimit())
1074 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1075 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1076 status, ap->active_tag, ap->sactive);
1077 }
1078
1079 static void ahci_irq_clear(struct ata_port *ap)
1080 {
1081 /* TODO */
1082 }
1083
1084 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1085 {
1086 struct ata_host *host = dev_instance;
1087 struct ahci_host_priv *hpriv;
1088 unsigned int i, handled = 0;
1089 void __iomem *mmio;
1090 u32 irq_stat, irq_ack = 0;
1091
1092 VPRINTK("ENTER\n");
1093
1094 hpriv = host->private_data;
1095 mmio = host->mmio_base;
1096
1097 /* sigh. 0xffffffff is a valid return from h/w */
1098 irq_stat = readl(mmio + HOST_IRQ_STAT);
1099 irq_stat &= hpriv->port_map;
1100 if (!irq_stat)
1101 return IRQ_NONE;
1102
1103 spin_lock(&host->lock);
1104
1105 for (i = 0; i < host->n_ports; i++) {
1106 struct ata_port *ap;
1107
1108 if (!(irq_stat & (1 << i)))
1109 continue;
1110
1111 ap = host->ports[i];
1112 if (ap) {
1113 ahci_host_intr(ap);
1114 VPRINTK("port %u\n", i);
1115 } else {
1116 VPRINTK("port %u (no irq)\n", i);
1117 if (ata_ratelimit())
1118 dev_printk(KERN_WARNING, host->dev,
1119 "interrupt on disabled port %u\n", i);
1120 }
1121
1122 irq_ack |= (1 << i);
1123 }
1124
1125 if (irq_ack) {
1126 writel(irq_ack, mmio + HOST_IRQ_STAT);
1127 handled = 1;
1128 }
1129
1130 spin_unlock(&host->lock);
1131
1132 VPRINTK("EXIT\n");
1133
1134 return IRQ_RETVAL(handled);
1135 }
1136
1137 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1138 {
1139 struct ata_port *ap = qc->ap;
1140 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1141
1142 if (qc->tf.protocol == ATA_PROT_NCQ)
1143 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1144 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1145 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1146
1147 return 0;
1148 }
1149
1150 static void ahci_freeze(struct ata_port *ap)
1151 {
1152 void __iomem *mmio = ap->host->mmio_base;
1153 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1154
1155 /* turn IRQ off */
1156 writel(0, port_mmio + PORT_IRQ_MASK);
1157 }
1158
1159 static void ahci_thaw(struct ata_port *ap)
1160 {
1161 void __iomem *mmio = ap->host->mmio_base;
1162 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1163 u32 tmp;
1164
1165 /* clear IRQ */
1166 tmp = readl(port_mmio + PORT_IRQ_STAT);
1167 writel(tmp, port_mmio + PORT_IRQ_STAT);
1168 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1169
1170 /* turn IRQ back on */
1171 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1172 }
1173
1174 static void ahci_error_handler(struct ata_port *ap)
1175 {
1176 void __iomem *mmio = ap->host->mmio_base;
1177 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1178
1179 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1180 /* restart engine */
1181 ahci_stop_engine(port_mmio);
1182 ahci_start_engine(port_mmio);
1183 }
1184
1185 /* perform recovery */
1186 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1187 ahci_postreset);
1188 }
1189
1190 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1191 {
1192 struct ata_port *ap = qc->ap;
1193 void __iomem *mmio = ap->host->mmio_base;
1194 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1195
1196 if (qc->flags & ATA_QCFLAG_FAILED)
1197 qc->err_mask |= AC_ERR_OTHER;
1198
1199 if (qc->err_mask) {
1200 /* make DMA engine forget about the failed command */
1201 ahci_stop_engine(port_mmio);
1202 ahci_start_engine(port_mmio);
1203 }
1204 }
1205
1206 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1207 {
1208 struct ahci_host_priv *hpriv = ap->host->private_data;
1209 struct ahci_port_priv *pp = ap->private_data;
1210 void __iomem *mmio = ap->host->mmio_base;
1211 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1212 const char *emsg = NULL;
1213 int rc;
1214
1215 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1216 if (rc) {
1217 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1218 ahci_init_port(port_mmio, hpriv->cap,
1219 pp->cmd_slot_dma, pp->rx_fis_dma);
1220 }
1221
1222 return rc;
1223 }
1224
1225 static int ahci_port_resume(struct ata_port *ap)
1226 {
1227 struct ahci_port_priv *pp = ap->private_data;
1228 struct ahci_host_priv *hpriv = ap->host->private_data;
1229 void __iomem *mmio = ap->host->mmio_base;
1230 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1231
1232 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1233
1234 return 0;
1235 }
1236
1237 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1238 {
1239 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1240 void __iomem *mmio = host->mmio_base;
1241 u32 ctl;
1242
1243 if (mesg.event == PM_EVENT_SUSPEND) {
1244 /* AHCI spec rev1.1 section 8.3.3:
1245 * Software must disable interrupts prior to requesting a
1246 * transition of the HBA to D3 state.
1247 */
1248 ctl = readl(mmio + HOST_CTL);
1249 ctl &= ~HOST_IRQ_EN;
1250 writel(ctl, mmio + HOST_CTL);
1251 readl(mmio + HOST_CTL); /* flush */
1252 }
1253
1254 return ata_pci_device_suspend(pdev, mesg);
1255 }
1256
1257 static int ahci_pci_device_resume(struct pci_dev *pdev)
1258 {
1259 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1260 struct ahci_host_priv *hpriv = host->private_data;
1261 void __iomem *mmio = host->mmio_base;
1262 int rc;
1263
1264 ata_pci_device_do_resume(pdev);
1265
1266 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1267 rc = ahci_reset_controller(mmio, pdev);
1268 if (rc)
1269 return rc;
1270
1271 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
1272 }
1273
1274 ata_host_resume(host);
1275
1276 return 0;
1277 }
1278
1279 static int ahci_port_start(struct ata_port *ap)
1280 {
1281 struct device *dev = ap->host->dev;
1282 struct ahci_host_priv *hpriv = ap->host->private_data;
1283 struct ahci_port_priv *pp;
1284 void __iomem *mmio = ap->host->mmio_base;
1285 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1286 void *mem;
1287 dma_addr_t mem_dma;
1288 int rc;
1289
1290 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1291 if (!pp)
1292 return -ENOMEM;
1293 memset(pp, 0, sizeof(*pp));
1294
1295 rc = ata_pad_alloc(ap, dev);
1296 if (rc) {
1297 kfree(pp);
1298 return rc;
1299 }
1300
1301 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1302 if (!mem) {
1303 ata_pad_free(ap, dev);
1304 kfree(pp);
1305 return -ENOMEM;
1306 }
1307 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1308
1309 /*
1310 * First item in chunk of DMA memory: 32-slot command table,
1311 * 32 bytes each in size
1312 */
1313 pp->cmd_slot = mem;
1314 pp->cmd_slot_dma = mem_dma;
1315
1316 mem += AHCI_CMD_SLOT_SZ;
1317 mem_dma += AHCI_CMD_SLOT_SZ;
1318
1319 /*
1320 * Second item: Received-FIS area
1321 */
1322 pp->rx_fis = mem;
1323 pp->rx_fis_dma = mem_dma;
1324
1325 mem += AHCI_RX_FIS_SZ;
1326 mem_dma += AHCI_RX_FIS_SZ;
1327
1328 /*
1329 * Third item: data area for storing a single command
1330 * and its scatter-gather table
1331 */
1332 pp->cmd_tbl = mem;
1333 pp->cmd_tbl_dma = mem_dma;
1334
1335 ap->private_data = pp;
1336
1337 /* initialize port */
1338 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1339
1340 return 0;
1341 }
1342
1343 static void ahci_port_stop(struct ata_port *ap)
1344 {
1345 struct device *dev = ap->host->dev;
1346 struct ahci_host_priv *hpriv = ap->host->private_data;
1347 struct ahci_port_priv *pp = ap->private_data;
1348 void __iomem *mmio = ap->host->mmio_base;
1349 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1350 const char *emsg = NULL;
1351 int rc;
1352
1353 /* de-initialize port */
1354 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1355 if (rc)
1356 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1357
1358 ap->private_data = NULL;
1359 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1360 pp->cmd_slot, pp->cmd_slot_dma);
1361 ata_pad_free(ap, dev);
1362 kfree(pp);
1363 }
1364
1365 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1366 unsigned int port_idx)
1367 {
1368 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1369 base = ahci_port_base_ul(base, port_idx);
1370 VPRINTK("base now==0x%lx\n", base);
1371
1372 port->cmd_addr = base;
1373 port->scr_addr = base + PORT_SCR;
1374
1375 VPRINTK("EXIT\n");
1376 }
1377
1378 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1379 {
1380 struct ahci_host_priv *hpriv = probe_ent->private_data;
1381 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1382 void __iomem *mmio = probe_ent->mmio_base;
1383 unsigned int i, using_dac;
1384 int rc;
1385
1386 rc = ahci_reset_controller(mmio, pdev);
1387 if (rc)
1388 return rc;
1389
1390 hpriv->cap = readl(mmio + HOST_CAP);
1391 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1392 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1393
1394 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1395 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1396
1397 using_dac = hpriv->cap & HOST_CAP_64;
1398 if (using_dac &&
1399 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1400 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1401 if (rc) {
1402 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1403 if (rc) {
1404 dev_printk(KERN_ERR, &pdev->dev,
1405 "64-bit DMA enable failed\n");
1406 return rc;
1407 }
1408 }
1409 } else {
1410 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1411 if (rc) {
1412 dev_printk(KERN_ERR, &pdev->dev,
1413 "32-bit DMA enable failed\n");
1414 return rc;
1415 }
1416 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1417 if (rc) {
1418 dev_printk(KERN_ERR, &pdev->dev,
1419 "32-bit consistent DMA enable failed\n");
1420 return rc;
1421 }
1422 }
1423
1424 for (i = 0; i < probe_ent->n_ports; i++)
1425 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1426
1427 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1428
1429 pci_set_master(pdev);
1430
1431 return 0;
1432 }
1433
1434 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1435 {
1436 struct ahci_host_priv *hpriv = probe_ent->private_data;
1437 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1438 void __iomem *mmio = probe_ent->mmio_base;
1439 u32 vers, cap, impl, speed;
1440 const char *speed_s;
1441 u16 cc;
1442 const char *scc_s;
1443
1444 vers = readl(mmio + HOST_VERSION);
1445 cap = hpriv->cap;
1446 impl = hpriv->port_map;
1447
1448 speed = (cap >> 20) & 0xf;
1449 if (speed == 1)
1450 speed_s = "1.5";
1451 else if (speed == 2)
1452 speed_s = "3";
1453 else
1454 speed_s = "?";
1455
1456 pci_read_config_word(pdev, 0x0a, &cc);
1457 if (cc == 0x0101)
1458 scc_s = "IDE";
1459 else if (cc == 0x0106)
1460 scc_s = "SATA";
1461 else if (cc == 0x0104)
1462 scc_s = "RAID";
1463 else
1464 scc_s = "unknown";
1465
1466 dev_printk(KERN_INFO, &pdev->dev,
1467 "AHCI %02x%02x.%02x%02x "
1468 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1469 ,
1470
1471 (vers >> 24) & 0xff,
1472 (vers >> 16) & 0xff,
1473 (vers >> 8) & 0xff,
1474 vers & 0xff,
1475
1476 ((cap >> 8) & 0x1f) + 1,
1477 (cap & 0x1f) + 1,
1478 speed_s,
1479 impl,
1480 scc_s);
1481
1482 dev_printk(KERN_INFO, &pdev->dev,
1483 "flags: "
1484 "%s%s%s%s%s%s"
1485 "%s%s%s%s%s%s%s\n"
1486 ,
1487
1488 cap & (1 << 31) ? "64bit " : "",
1489 cap & (1 << 30) ? "ncq " : "",
1490 cap & (1 << 28) ? "ilck " : "",
1491 cap & (1 << 27) ? "stag " : "",
1492 cap & (1 << 26) ? "pm " : "",
1493 cap & (1 << 25) ? "led " : "",
1494
1495 cap & (1 << 24) ? "clo " : "",
1496 cap & (1 << 19) ? "nz " : "",
1497 cap & (1 << 18) ? "only " : "",
1498 cap & (1 << 17) ? "pmp " : "",
1499 cap & (1 << 15) ? "pio " : "",
1500 cap & (1 << 14) ? "slum " : "",
1501 cap & (1 << 13) ? "part " : ""
1502 );
1503 }
1504
1505 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1506 {
1507 static int printed_version;
1508 struct ata_probe_ent *probe_ent = NULL;
1509 struct ahci_host_priv *hpriv;
1510 unsigned long base;
1511 void __iomem *mmio_base;
1512 unsigned int board_idx = (unsigned int) ent->driver_data;
1513 int have_msi, pci_dev_busy = 0;
1514 int rc;
1515
1516 VPRINTK("ENTER\n");
1517
1518 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1519
1520 if (!printed_version++)
1521 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1522
1523 /* JMicron-specific fixup: make sure we're in AHCI mode */
1524 /* This is protected from races with ata_jmicron by the pci probe
1525 locking */
1526 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1527 /* AHCI enable, AHCI on function 0 */
1528 pci_write_config_byte(pdev, 0x41, 0xa1);
1529 /* Function 1 is the PATA controller */
1530 if (PCI_FUNC(pdev->devfn))
1531 return -ENODEV;
1532 }
1533
1534 rc = pci_enable_device(pdev);
1535 if (rc)
1536 return rc;
1537
1538 rc = pci_request_regions(pdev, DRV_NAME);
1539 if (rc) {
1540 pci_dev_busy = 1;
1541 goto err_out;
1542 }
1543
1544 if (pci_enable_msi(pdev) == 0)
1545 have_msi = 1;
1546 else {
1547 pci_intx(pdev, 1);
1548 have_msi = 0;
1549 }
1550
1551 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1552 if (probe_ent == NULL) {
1553 rc = -ENOMEM;
1554 goto err_out_msi;
1555 }
1556
1557 memset(probe_ent, 0, sizeof(*probe_ent));
1558 probe_ent->dev = pci_dev_to_dev(pdev);
1559 INIT_LIST_HEAD(&probe_ent->node);
1560
1561 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1562 if (mmio_base == NULL) {
1563 rc = -ENOMEM;
1564 goto err_out_free_ent;
1565 }
1566 base = (unsigned long) mmio_base;
1567
1568 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1569 if (!hpriv) {
1570 rc = -ENOMEM;
1571 goto err_out_iounmap;
1572 }
1573 memset(hpriv, 0, sizeof(*hpriv));
1574
1575 probe_ent->sht = ahci_port_info[board_idx].sht;
1576 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1577 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1578 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1579 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1580
1581 probe_ent->irq = pdev->irq;
1582 probe_ent->irq_flags = IRQF_SHARED;
1583 probe_ent->mmio_base = mmio_base;
1584 probe_ent->private_data = hpriv;
1585
1586 if (have_msi)
1587 hpriv->flags |= AHCI_FLAG_MSI;
1588
1589 /* initialize adapter */
1590 rc = ahci_host_init(probe_ent);
1591 if (rc)
1592 goto err_out_hpriv;
1593
1594 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1595 (hpriv->cap & HOST_CAP_NCQ))
1596 probe_ent->port_flags |= ATA_FLAG_NCQ;
1597
1598 ahci_print_info(probe_ent);
1599
1600 /* FIXME: check ata_device_add return value */
1601 ata_device_add(probe_ent);
1602 kfree(probe_ent);
1603
1604 return 0;
1605
1606 err_out_hpriv:
1607 kfree(hpriv);
1608 err_out_iounmap:
1609 pci_iounmap(pdev, mmio_base);
1610 err_out_free_ent:
1611 kfree(probe_ent);
1612 err_out_msi:
1613 if (have_msi)
1614 pci_disable_msi(pdev);
1615 else
1616 pci_intx(pdev, 0);
1617 pci_release_regions(pdev);
1618 err_out:
1619 if (!pci_dev_busy)
1620 pci_disable_device(pdev);
1621 return rc;
1622 }
1623
1624 static void ahci_remove_one (struct pci_dev *pdev)
1625 {
1626 struct device *dev = pci_dev_to_dev(pdev);
1627 struct ata_host *host = dev_get_drvdata(dev);
1628 struct ahci_host_priv *hpriv = host->private_data;
1629 unsigned int i;
1630 int have_msi;
1631
1632 for (i = 0; i < host->n_ports; i++)
1633 ata_port_detach(host->ports[i]);
1634
1635 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1636 free_irq(host->irq, host);
1637
1638 for (i = 0; i < host->n_ports; i++) {
1639 struct ata_port *ap = host->ports[i];
1640
1641 ata_scsi_release(ap->scsi_host);
1642 scsi_host_put(ap->scsi_host);
1643 }
1644
1645 kfree(hpriv);
1646 pci_iounmap(pdev, host->mmio_base);
1647 kfree(host);
1648
1649 if (have_msi)
1650 pci_disable_msi(pdev);
1651 else
1652 pci_intx(pdev, 0);
1653 pci_release_regions(pdev);
1654 pci_disable_device(pdev);
1655 dev_set_drvdata(dev, NULL);
1656 }
1657
1658 static int __init ahci_init(void)
1659 {
1660 return pci_register_driver(&ahci_pci_driver);
1661 }
1662
1663 static void __exit ahci_exit(void)
1664 {
1665 pci_unregister_driver(&ahci_pci_driver);
1666 }
1667
1668
1669 MODULE_AUTHOR("Jeff Garzik");
1670 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1671 MODULE_LICENSE("GPL");
1672 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1673 MODULE_VERSION(DRV_VERSION);
1674
1675 module_init(ahci_init);
1676 module_exit(ahci_exit);
Linux kernel - Deliverables
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