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[libata] Add support for AHCI controllers of MCP67.
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48 #include <asm/io.h>
49
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
52
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_MAX_CMDS = 32,
60 AHCI_CMD_SZ = 32,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_RX_FIS_SZ = 256,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_vt8251 = 1,
81
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
95 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
96 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
97 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
98 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
99 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
100
101 /* registers for each SATA port */
102 PORT_LST_ADDR = 0x00, /* command list DMA addr */
103 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
104 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
105 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
106 PORT_IRQ_STAT = 0x10, /* interrupt status */
107 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
108 PORT_CMD = 0x18, /* port command */
109 PORT_TFDATA = 0x20, /* taskfile data */
110 PORT_SIG = 0x24, /* device TF signature */
111 PORT_CMD_ISSUE = 0x38, /* command issue */
112 PORT_SCR = 0x28, /* SATA phy register block */
113 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
114 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
115 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
116 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
117
118 /* PORT_IRQ_{STAT,MASK} bits */
119 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
120 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
121 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
122 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
123 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
124 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
125 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
126 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
127
128 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
129 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
130 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
131 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
132 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
133 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
134 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
135 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
136 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
137
138 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
139 PORT_IRQ_IF_ERR |
140 PORT_IRQ_CONNECT |
141 PORT_IRQ_PHYRDY |
142 PORT_IRQ_UNK_FIS,
143 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
144 PORT_IRQ_TF_ERR |
145 PORT_IRQ_HBUS_DATA_ERR,
146 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
147 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
148 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
149
150 /* PORT_CMD bits */
151 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
152 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
153 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
154 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
155 PORT_CMD_CLO = (1 << 3), /* Command list override */
156 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
157 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
158 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
159
160 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
161 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
162 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
163 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
164
165 /* hpriv->flags bits */
166 AHCI_FLAG_MSI = (1 << 0),
167
168 /* ap->flags bits */
169 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
170 AHCI_FLAG_NO_NCQ = (1 << 25),
171 };
172
173 struct ahci_cmd_hdr {
174 u32 opts;
175 u32 status;
176 u32 tbl_addr;
177 u32 tbl_addr_hi;
178 u32 reserved[4];
179 };
180
181 struct ahci_sg {
182 u32 addr;
183 u32 addr_hi;
184 u32 reserved;
185 u32 flags_size;
186 };
187
188 struct ahci_host_priv {
189 unsigned long flags;
190 u32 cap; /* cache of HOST_CAP register */
191 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
192 };
193
194 struct ahci_port_priv {
195 struct ahci_cmd_hdr *cmd_slot;
196 dma_addr_t cmd_slot_dma;
197 void *cmd_tbl;
198 dma_addr_t cmd_tbl_dma;
199 void *rx_fis;
200 dma_addr_t rx_fis_dma;
201 };
202
203 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
204 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
205 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
206 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
207 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
208 static void ahci_irq_clear(struct ata_port *ap);
209 static int ahci_port_start(struct ata_port *ap);
210 static void ahci_port_stop(struct ata_port *ap);
211 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
212 static void ahci_qc_prep(struct ata_queued_cmd *qc);
213 static u8 ahci_check_status(struct ata_port *ap);
214 static void ahci_freeze(struct ata_port *ap);
215 static void ahci_thaw(struct ata_port *ap);
216 static void ahci_error_handler(struct ata_port *ap);
217 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
218 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
219 static int ahci_port_resume(struct ata_port *ap);
220 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
221 static int ahci_pci_device_resume(struct pci_dev *pdev);
222 static void ahci_remove_one (struct pci_dev *pdev);
223
224 static struct scsi_host_template ahci_sht = {
225 .module = THIS_MODULE,
226 .name = DRV_NAME,
227 .ioctl = ata_scsi_ioctl,
228 .queuecommand = ata_scsi_queuecmd,
229 .change_queue_depth = ata_scsi_change_queue_depth,
230 .can_queue = AHCI_MAX_CMDS - 1,
231 .this_id = ATA_SHT_THIS_ID,
232 .sg_tablesize = AHCI_MAX_SG,
233 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
234 .emulated = ATA_SHT_EMULATED,
235 .use_clustering = AHCI_USE_CLUSTERING,
236 .proc_name = DRV_NAME,
237 .dma_boundary = AHCI_DMA_BOUNDARY,
238 .slave_configure = ata_scsi_slave_config,
239 .slave_destroy = ata_scsi_slave_destroy,
240 .bios_param = ata_std_bios_param,
241 .suspend = ata_scsi_device_suspend,
242 .resume = ata_scsi_device_resume,
243 };
244
245 static const struct ata_port_operations ahci_ops = {
246 .port_disable = ata_port_disable,
247
248 .check_status = ahci_check_status,
249 .check_altstatus = ahci_check_status,
250 .dev_select = ata_noop_dev_select,
251
252 .tf_read = ahci_tf_read,
253
254 .qc_prep = ahci_qc_prep,
255 .qc_issue = ahci_qc_issue,
256
257 .irq_handler = ahci_interrupt,
258 .irq_clear = ahci_irq_clear,
259
260 .scr_read = ahci_scr_read,
261 .scr_write = ahci_scr_write,
262
263 .freeze = ahci_freeze,
264 .thaw = ahci_thaw,
265
266 .error_handler = ahci_error_handler,
267 .post_internal_cmd = ahci_post_internal_cmd,
268
269 .port_suspend = ahci_port_suspend,
270 .port_resume = ahci_port_resume,
271
272 .port_start = ahci_port_start,
273 .port_stop = ahci_port_stop,
274 };
275
276 static const struct ata_port_info ahci_port_info[] = {
277 /* board_ahci */
278 {
279 .sht = &ahci_sht,
280 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
281 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
282 ATA_FLAG_SKIP_D2H_BSY,
283 .pio_mask = 0x1f, /* pio0-4 */
284 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
285 .port_ops = &ahci_ops,
286 },
287 /* board_ahci_vt8251 */
288 {
289 .sht = &ahci_sht,
290 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
291 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
292 ATA_FLAG_SKIP_D2H_BSY |
293 AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
294 .pio_mask = 0x1f, /* pio0-4 */
295 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
296 .port_ops = &ahci_ops,
297 },
298 };
299
300 static const struct pci_device_id ahci_pci_tbl[] = {
301 /* Intel */
302 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
303 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
304 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
305 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
306 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
307 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
308 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
309 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
310 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
311 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
312 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
313 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
314 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
315 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
316 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
317
318 /* JMicron */
319 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci }, /* JMicron JMB360 */
320 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci }, /* JMicron JMB361 */
321 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci }, /* JMicron JMB363 */
322 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci }, /* JMicron JMB365 */
323 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci }, /* JMicron JMB366 */
324
325 /* ATI */
326 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
327 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
328
329 /* VIA */
330 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
331
332 /* NVIDIA */
333 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
337 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
345
346 /* SiS */
347 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
348 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
349 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
350
351 { } /* terminate list */
352 };
353
354
355 static struct pci_driver ahci_pci_driver = {
356 .name = DRV_NAME,
357 .id_table = ahci_pci_tbl,
358 .probe = ahci_init_one,
359 .suspend = ahci_pci_device_suspend,
360 .resume = ahci_pci_device_resume,
361 .remove = ahci_remove_one,
362 };
363
364
365 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
366 {
367 return base + 0x100 + (port * 0x80);
368 }
369
370 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
371 {
372 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
373 }
374
375 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
376 {
377 unsigned int sc_reg;
378
379 switch (sc_reg_in) {
380 case SCR_STATUS: sc_reg = 0; break;
381 case SCR_CONTROL: sc_reg = 1; break;
382 case SCR_ERROR: sc_reg = 2; break;
383 case SCR_ACTIVE: sc_reg = 3; break;
384 default:
385 return 0xffffffffU;
386 }
387
388 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
389 }
390
391
392 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
393 u32 val)
394 {
395 unsigned int sc_reg;
396
397 switch (sc_reg_in) {
398 case SCR_STATUS: sc_reg = 0; break;
399 case SCR_CONTROL: sc_reg = 1; break;
400 case SCR_ERROR: sc_reg = 2; break;
401 case SCR_ACTIVE: sc_reg = 3; break;
402 default:
403 return;
404 }
405
406 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
407 }
408
409 static void ahci_start_engine(void __iomem *port_mmio)
410 {
411 u32 tmp;
412
413 /* start DMA */
414 tmp = readl(port_mmio + PORT_CMD);
415 tmp |= PORT_CMD_START;
416 writel(tmp, port_mmio + PORT_CMD);
417 readl(port_mmio + PORT_CMD); /* flush */
418 }
419
420 static int ahci_stop_engine(void __iomem *port_mmio)
421 {
422 u32 tmp;
423
424 tmp = readl(port_mmio + PORT_CMD);
425
426 /* check if the HBA is idle */
427 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
428 return 0;
429
430 /* setting HBA to idle */
431 tmp &= ~PORT_CMD_START;
432 writel(tmp, port_mmio + PORT_CMD);
433
434 /* wait for engine to stop. This could be as long as 500 msec */
435 tmp = ata_wait_register(port_mmio + PORT_CMD,
436 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
437 if (tmp & PORT_CMD_LIST_ON)
438 return -EIO;
439
440 return 0;
441 }
442
443 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
444 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
445 {
446 u32 tmp;
447
448 /* set FIS registers */
449 if (cap & HOST_CAP_64)
450 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
451 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
452
453 if (cap & HOST_CAP_64)
454 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
455 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
456
457 /* enable FIS reception */
458 tmp = readl(port_mmio + PORT_CMD);
459 tmp |= PORT_CMD_FIS_RX;
460 writel(tmp, port_mmio + PORT_CMD);
461
462 /* flush */
463 readl(port_mmio + PORT_CMD);
464 }
465
466 static int ahci_stop_fis_rx(void __iomem *port_mmio)
467 {
468 u32 tmp;
469
470 /* disable FIS reception */
471 tmp = readl(port_mmio + PORT_CMD);
472 tmp &= ~PORT_CMD_FIS_RX;
473 writel(tmp, port_mmio + PORT_CMD);
474
475 /* wait for completion, spec says 500ms, give it 1000 */
476 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
477 PORT_CMD_FIS_ON, 10, 1000);
478 if (tmp & PORT_CMD_FIS_ON)
479 return -EBUSY;
480
481 return 0;
482 }
483
484 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
485 {
486 u32 cmd;
487
488 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
489
490 /* spin up device */
491 if (cap & HOST_CAP_SSS) {
492 cmd |= PORT_CMD_SPIN_UP;
493 writel(cmd, port_mmio + PORT_CMD);
494 }
495
496 /* wake up link */
497 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
498 }
499
500 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
501 {
502 u32 cmd, scontrol;
503
504 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
505
506 if (cap & HOST_CAP_SSC) {
507 /* enable transitions to slumber mode */
508 scontrol = readl(port_mmio + PORT_SCR_CTL);
509 if ((scontrol & 0x0f00) > 0x100) {
510 scontrol &= ~0xf00;
511 writel(scontrol, port_mmio + PORT_SCR_CTL);
512 }
513
514 /* put device into slumber mode */
515 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
516
517 /* wait for the transition to complete */
518 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
519 PORT_CMD_ICC_SLUMBER, 1, 50);
520 }
521
522 /* put device into listen mode */
523 if (cap & HOST_CAP_SSS) {
524 /* first set PxSCTL.DET to 0 */
525 scontrol = readl(port_mmio + PORT_SCR_CTL);
526 scontrol &= ~0xf;
527 writel(scontrol, port_mmio + PORT_SCR_CTL);
528
529 /* then set PxCMD.SUD to 0 */
530 cmd &= ~PORT_CMD_SPIN_UP;
531 writel(cmd, port_mmio + PORT_CMD);
532 }
533 }
534
535 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
536 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
537 {
538 /* power up */
539 ahci_power_up(port_mmio, cap);
540
541 /* enable FIS reception */
542 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
543
544 /* enable DMA */
545 ahci_start_engine(port_mmio);
546 }
547
548 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
549 {
550 int rc;
551
552 /* disable DMA */
553 rc = ahci_stop_engine(port_mmio);
554 if (rc) {
555 *emsg = "failed to stop engine";
556 return rc;
557 }
558
559 /* disable FIS reception */
560 rc = ahci_stop_fis_rx(port_mmio);
561 if (rc) {
562 *emsg = "failed stop FIS RX";
563 return rc;
564 }
565
566 /* put device into slumber mode */
567 ahci_power_down(port_mmio, cap);
568
569 return 0;
570 }
571
572 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
573 {
574 u32 cap_save, tmp;
575
576 cap_save = readl(mmio + HOST_CAP);
577 cap_save &= ( (1<<28) | (1<<17) );
578 cap_save |= (1 << 27);
579
580 /* global controller reset */
581 tmp = readl(mmio + HOST_CTL);
582 if ((tmp & HOST_RESET) == 0) {
583 writel(tmp | HOST_RESET, mmio + HOST_CTL);
584 readl(mmio + HOST_CTL); /* flush */
585 }
586
587 /* reset must complete within 1 second, or
588 * the hardware should be considered fried.
589 */
590 ssleep(1);
591
592 tmp = readl(mmio + HOST_CTL);
593 if (tmp & HOST_RESET) {
594 dev_printk(KERN_ERR, &pdev->dev,
595 "controller reset failed (0x%x)\n", tmp);
596 return -EIO;
597 }
598
599 writel(HOST_AHCI_EN, mmio + HOST_CTL);
600 (void) readl(mmio + HOST_CTL); /* flush */
601 writel(cap_save, mmio + HOST_CAP);
602 writel(0xf, mmio + HOST_PORTS_IMPL);
603 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
604
605 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
606 u16 tmp16;
607
608 /* configure PCS */
609 pci_read_config_word(pdev, 0x92, &tmp16);
610 tmp16 |= 0xf;
611 pci_write_config_word(pdev, 0x92, tmp16);
612 }
613
614 return 0;
615 }
616
617 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
618 int n_ports, u32 cap)
619 {
620 int i, rc;
621 u32 tmp;
622
623 for (i = 0; i < n_ports; i++) {
624 void __iomem *port_mmio = ahci_port_base(mmio, i);
625 const char *emsg = NULL;
626
627 #if 0 /* BIOSen initialize this incorrectly */
628 if (!(hpriv->port_map & (1 << i)))
629 continue;
630 #endif
631
632 /* make sure port is not active */
633 rc = ahci_deinit_port(port_mmio, cap, &emsg);
634 if (rc)
635 dev_printk(KERN_WARNING, &pdev->dev,
636 "%s (%d)\n", emsg, rc);
637
638 /* clear SError */
639 tmp = readl(port_mmio + PORT_SCR_ERR);
640 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
641 writel(tmp, port_mmio + PORT_SCR_ERR);
642
643 /* clear port IRQ */
644 tmp = readl(port_mmio + PORT_IRQ_STAT);
645 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
646 if (tmp)
647 writel(tmp, port_mmio + PORT_IRQ_STAT);
648
649 writel(1 << i, mmio + HOST_IRQ_STAT);
650 }
651
652 tmp = readl(mmio + HOST_CTL);
653 VPRINTK("HOST_CTL 0x%x\n", tmp);
654 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
655 tmp = readl(mmio + HOST_CTL);
656 VPRINTK("HOST_CTL 0x%x\n", tmp);
657 }
658
659 static unsigned int ahci_dev_classify(struct ata_port *ap)
660 {
661 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
662 struct ata_taskfile tf;
663 u32 tmp;
664
665 tmp = readl(port_mmio + PORT_SIG);
666 tf.lbah = (tmp >> 24) & 0xff;
667 tf.lbam = (tmp >> 16) & 0xff;
668 tf.lbal = (tmp >> 8) & 0xff;
669 tf.nsect = (tmp) & 0xff;
670
671 return ata_dev_classify(&tf);
672 }
673
674 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
675 u32 opts)
676 {
677 dma_addr_t cmd_tbl_dma;
678
679 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
680
681 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
682 pp->cmd_slot[tag].status = 0;
683 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
684 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
685 }
686
687 static int ahci_clo(struct ata_port *ap)
688 {
689 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
690 struct ahci_host_priv *hpriv = ap->host->private_data;
691 u32 tmp;
692
693 if (!(hpriv->cap & HOST_CAP_CLO))
694 return -EOPNOTSUPP;
695
696 tmp = readl(port_mmio + PORT_CMD);
697 tmp |= PORT_CMD_CLO;
698 writel(tmp, port_mmio + PORT_CMD);
699
700 tmp = ata_wait_register(port_mmio + PORT_CMD,
701 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
702 if (tmp & PORT_CMD_CLO)
703 return -EIO;
704
705 return 0;
706 }
707
708 static int ahci_prereset(struct ata_port *ap)
709 {
710 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
711 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
712 /* ATA_BUSY hasn't cleared, so send a CLO */
713 ahci_clo(ap);
714 }
715
716 return ata_std_prereset(ap);
717 }
718
719 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
720 {
721 struct ahci_port_priv *pp = ap->private_data;
722 void __iomem *mmio = ap->host->mmio_base;
723 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
724 const u32 cmd_fis_len = 5; /* five dwords */
725 const char *reason = NULL;
726 struct ata_taskfile tf;
727 u32 tmp;
728 u8 *fis;
729 int rc;
730
731 DPRINTK("ENTER\n");
732
733 if (ata_port_offline(ap)) {
734 DPRINTK("PHY reports no device\n");
735 *class = ATA_DEV_NONE;
736 return 0;
737 }
738
739 /* prepare for SRST (AHCI-1.1 10.4.1) */
740 rc = ahci_stop_engine(port_mmio);
741 if (rc) {
742 reason = "failed to stop engine";
743 goto fail_restart;
744 }
745
746 /* check BUSY/DRQ, perform Command List Override if necessary */
747 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
748 rc = ahci_clo(ap);
749
750 if (rc == -EOPNOTSUPP) {
751 reason = "port busy but CLO unavailable";
752 goto fail_restart;
753 } else if (rc) {
754 reason = "port busy but CLO failed";
755 goto fail_restart;
756 }
757 }
758
759 /* restart engine */
760 ahci_start_engine(port_mmio);
761
762 ata_tf_init(ap->device, &tf);
763 fis = pp->cmd_tbl;
764
765 /* issue the first D2H Register FIS */
766 ahci_fill_cmd_slot(pp, 0,
767 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
768
769 tf.ctl |= ATA_SRST;
770 ata_tf_to_fis(&tf, fis, 0);
771 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
772
773 writel(1, port_mmio + PORT_CMD_ISSUE);
774
775 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
776 if (tmp & 0x1) {
777 rc = -EIO;
778 reason = "1st FIS failed";
779 goto fail;
780 }
781
782 /* spec says at least 5us, but be generous and sleep for 1ms */
783 msleep(1);
784
785 /* issue the second D2H Register FIS */
786 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
787
788 tf.ctl &= ~ATA_SRST;
789 ata_tf_to_fis(&tf, fis, 0);
790 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
791
792 writel(1, port_mmio + PORT_CMD_ISSUE);
793 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
794
795 /* spec mandates ">= 2ms" before checking status.
796 * We wait 150ms, because that was the magic delay used for
797 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
798 * between when the ATA command register is written, and then
799 * status is checked. Because waiting for "a while" before
800 * checking status is fine, post SRST, we perform this magic
801 * delay here as well.
802 */
803 msleep(150);
804
805 *class = ATA_DEV_NONE;
806 if (ata_port_online(ap)) {
807 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
808 rc = -EIO;
809 reason = "device not ready";
810 goto fail;
811 }
812 *class = ahci_dev_classify(ap);
813 }
814
815 DPRINTK("EXIT, class=%u\n", *class);
816 return 0;
817
818 fail_restart:
819 ahci_start_engine(port_mmio);
820 fail:
821 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
822 return rc;
823 }
824
825 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
826 {
827 struct ahci_port_priv *pp = ap->private_data;
828 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
829 struct ata_taskfile tf;
830 void __iomem *mmio = ap->host->mmio_base;
831 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
832 int rc;
833
834 DPRINTK("ENTER\n");
835
836 ahci_stop_engine(port_mmio);
837
838 /* clear D2H reception area to properly wait for D2H FIS */
839 ata_tf_init(ap->device, &tf);
840 tf.command = 0xff;
841 ata_tf_to_fis(&tf, d2h_fis, 0);
842
843 rc = sata_std_hardreset(ap, class);
844
845 ahci_start_engine(port_mmio);
846
847 if (rc == 0 && ata_port_online(ap))
848 *class = ahci_dev_classify(ap);
849 if (*class == ATA_DEV_UNKNOWN)
850 *class = ATA_DEV_NONE;
851
852 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
853 return rc;
854 }
855
856 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
857 {
858 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
859 u32 new_tmp, tmp;
860
861 ata_std_postreset(ap, class);
862
863 /* Make sure port's ATAPI bit is set appropriately */
864 new_tmp = tmp = readl(port_mmio + PORT_CMD);
865 if (*class == ATA_DEV_ATAPI)
866 new_tmp |= PORT_CMD_ATAPI;
867 else
868 new_tmp &= ~PORT_CMD_ATAPI;
869 if (new_tmp != tmp) {
870 writel(new_tmp, port_mmio + PORT_CMD);
871 readl(port_mmio + PORT_CMD); /* flush */
872 }
873 }
874
875 static u8 ahci_check_status(struct ata_port *ap)
876 {
877 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
878
879 return readl(mmio + PORT_TFDATA) & 0xFF;
880 }
881
882 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
883 {
884 struct ahci_port_priv *pp = ap->private_data;
885 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
886
887 ata_tf_from_fis(d2h_fis, tf);
888 }
889
890 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
891 {
892 struct scatterlist *sg;
893 struct ahci_sg *ahci_sg;
894 unsigned int n_sg = 0;
895
896 VPRINTK("ENTER\n");
897
898 /*
899 * Next, the S/G list.
900 */
901 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
902 ata_for_each_sg(sg, qc) {
903 dma_addr_t addr = sg_dma_address(sg);
904 u32 sg_len = sg_dma_len(sg);
905
906 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
907 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
908 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
909
910 ahci_sg++;
911 n_sg++;
912 }
913
914 return n_sg;
915 }
916
917 static void ahci_qc_prep(struct ata_queued_cmd *qc)
918 {
919 struct ata_port *ap = qc->ap;
920 struct ahci_port_priv *pp = ap->private_data;
921 int is_atapi = is_atapi_taskfile(&qc->tf);
922 void *cmd_tbl;
923 u32 opts;
924 const u32 cmd_fis_len = 5; /* five dwords */
925 unsigned int n_elem;
926
927 /*
928 * Fill in command table information. First, the header,
929 * a SATA Register - Host to Device command FIS.
930 */
931 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
932
933 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
934 if (is_atapi) {
935 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
936 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
937 }
938
939 n_elem = 0;
940 if (qc->flags & ATA_QCFLAG_DMAMAP)
941 n_elem = ahci_fill_sg(qc, cmd_tbl);
942
943 /*
944 * Fill in command slot information.
945 */
946 opts = cmd_fis_len | n_elem << 16;
947 if (qc->tf.flags & ATA_TFLAG_WRITE)
948 opts |= AHCI_CMD_WRITE;
949 if (is_atapi)
950 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
951
952 ahci_fill_cmd_slot(pp, qc->tag, opts);
953 }
954
955 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
956 {
957 struct ahci_port_priv *pp = ap->private_data;
958 struct ata_eh_info *ehi = &ap->eh_info;
959 unsigned int err_mask = 0, action = 0;
960 struct ata_queued_cmd *qc;
961 u32 serror;
962
963 ata_ehi_clear_desc(ehi);
964
965 /* AHCI needs SError cleared; otherwise, it might lock up */
966 serror = ahci_scr_read(ap, SCR_ERROR);
967 ahci_scr_write(ap, SCR_ERROR, serror);
968
969 /* analyze @irq_stat */
970 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
971
972 if (irq_stat & PORT_IRQ_TF_ERR)
973 err_mask |= AC_ERR_DEV;
974
975 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
976 err_mask |= AC_ERR_HOST_BUS;
977 action |= ATA_EH_SOFTRESET;
978 }
979
980 if (irq_stat & PORT_IRQ_IF_ERR) {
981 err_mask |= AC_ERR_ATA_BUS;
982 action |= ATA_EH_SOFTRESET;
983 ata_ehi_push_desc(ehi, ", interface fatal error");
984 }
985
986 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
987 ata_ehi_hotplugged(ehi);
988 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
989 "connection status changed" : "PHY RDY changed");
990 }
991
992 if (irq_stat & PORT_IRQ_UNK_FIS) {
993 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
994
995 err_mask |= AC_ERR_HSM;
996 action |= ATA_EH_SOFTRESET;
997 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
998 unk[0], unk[1], unk[2], unk[3]);
999 }
1000
1001 /* okay, let's hand over to EH */
1002 ehi->serror |= serror;
1003 ehi->action |= action;
1004
1005 qc = ata_qc_from_tag(ap, ap->active_tag);
1006 if (qc)
1007 qc->err_mask |= err_mask;
1008 else
1009 ehi->err_mask |= err_mask;
1010
1011 if (irq_stat & PORT_IRQ_FREEZE)
1012 ata_port_freeze(ap);
1013 else
1014 ata_port_abort(ap);
1015 }
1016
1017 static void ahci_host_intr(struct ata_port *ap)
1018 {
1019 void __iomem *mmio = ap->host->mmio_base;
1020 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1021 struct ata_eh_info *ehi = &ap->eh_info;
1022 u32 status, qc_active;
1023 int rc;
1024
1025 status = readl(port_mmio + PORT_IRQ_STAT);
1026 writel(status, port_mmio + PORT_IRQ_STAT);
1027
1028 if (unlikely(status & PORT_IRQ_ERROR)) {
1029 ahci_error_intr(ap, status);
1030 return;
1031 }
1032
1033 if (ap->sactive)
1034 qc_active = readl(port_mmio + PORT_SCR_ACT);
1035 else
1036 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1037
1038 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1039 if (rc > 0)
1040 return;
1041 if (rc < 0) {
1042 ehi->err_mask |= AC_ERR_HSM;
1043 ehi->action |= ATA_EH_SOFTRESET;
1044 ata_port_freeze(ap);
1045 return;
1046 }
1047
1048 /* hmmm... a spurious interupt */
1049
1050 /* some devices send D2H reg with I bit set during NCQ command phase */
1051 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
1052 return;
1053
1054 /* ignore interim PIO setup fis interrupts */
1055 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
1056 return;
1057
1058 if (ata_ratelimit())
1059 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1060 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1061 status, ap->active_tag, ap->sactive);
1062 }
1063
1064 static void ahci_irq_clear(struct ata_port *ap)
1065 {
1066 /* TODO */
1067 }
1068
1069 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1070 {
1071 struct ata_host *host = dev_instance;
1072 struct ahci_host_priv *hpriv;
1073 unsigned int i, handled = 0;
1074 void __iomem *mmio;
1075 u32 irq_stat, irq_ack = 0;
1076
1077 VPRINTK("ENTER\n");
1078
1079 hpriv = host->private_data;
1080 mmio = host->mmio_base;
1081
1082 /* sigh. 0xffffffff is a valid return from h/w */
1083 irq_stat = readl(mmio + HOST_IRQ_STAT);
1084 irq_stat &= hpriv->port_map;
1085 if (!irq_stat)
1086 return IRQ_NONE;
1087
1088 spin_lock(&host->lock);
1089
1090 for (i = 0; i < host->n_ports; i++) {
1091 struct ata_port *ap;
1092
1093 if (!(irq_stat & (1 << i)))
1094 continue;
1095
1096 ap = host->ports[i];
1097 if (ap) {
1098 ahci_host_intr(ap);
1099 VPRINTK("port %u\n", i);
1100 } else {
1101 VPRINTK("port %u (no irq)\n", i);
1102 if (ata_ratelimit())
1103 dev_printk(KERN_WARNING, host->dev,
1104 "interrupt on disabled port %u\n", i);
1105 }
1106
1107 irq_ack |= (1 << i);
1108 }
1109
1110 if (irq_ack) {
1111 writel(irq_ack, mmio + HOST_IRQ_STAT);
1112 handled = 1;
1113 }
1114
1115 spin_unlock(&host->lock);
1116
1117 VPRINTK("EXIT\n");
1118
1119 return IRQ_RETVAL(handled);
1120 }
1121
1122 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1123 {
1124 struct ata_port *ap = qc->ap;
1125 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1126
1127 if (qc->tf.protocol == ATA_PROT_NCQ)
1128 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1129 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1130 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1131
1132 return 0;
1133 }
1134
1135 static void ahci_freeze(struct ata_port *ap)
1136 {
1137 void __iomem *mmio = ap->host->mmio_base;
1138 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1139
1140 /* turn IRQ off */
1141 writel(0, port_mmio + PORT_IRQ_MASK);
1142 }
1143
1144 static void ahci_thaw(struct ata_port *ap)
1145 {
1146 void __iomem *mmio = ap->host->mmio_base;
1147 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1148 u32 tmp;
1149
1150 /* clear IRQ */
1151 tmp = readl(port_mmio + PORT_IRQ_STAT);
1152 writel(tmp, port_mmio + PORT_IRQ_STAT);
1153 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1154
1155 /* turn IRQ back on */
1156 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1157 }
1158
1159 static void ahci_error_handler(struct ata_port *ap)
1160 {
1161 void __iomem *mmio = ap->host->mmio_base;
1162 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1163
1164 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1165 /* restart engine */
1166 ahci_stop_engine(port_mmio);
1167 ahci_start_engine(port_mmio);
1168 }
1169
1170 /* perform recovery */
1171 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
1172 ahci_postreset);
1173 }
1174
1175 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1176 {
1177 struct ata_port *ap = qc->ap;
1178 void __iomem *mmio = ap->host->mmio_base;
1179 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1180
1181 if (qc->flags & ATA_QCFLAG_FAILED)
1182 qc->err_mask |= AC_ERR_OTHER;
1183
1184 if (qc->err_mask) {
1185 /* make DMA engine forget about the failed command */
1186 ahci_stop_engine(port_mmio);
1187 ahci_start_engine(port_mmio);
1188 }
1189 }
1190
1191 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1192 {
1193 struct ahci_host_priv *hpriv = ap->host->private_data;
1194 struct ahci_port_priv *pp = ap->private_data;
1195 void __iomem *mmio = ap->host->mmio_base;
1196 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1197 const char *emsg = NULL;
1198 int rc;
1199
1200 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1201 if (rc) {
1202 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1203 ahci_init_port(port_mmio, hpriv->cap,
1204 pp->cmd_slot_dma, pp->rx_fis_dma);
1205 }
1206
1207 return rc;
1208 }
1209
1210 static int ahci_port_resume(struct ata_port *ap)
1211 {
1212 struct ahci_port_priv *pp = ap->private_data;
1213 struct ahci_host_priv *hpriv = ap->host->private_data;
1214 void __iomem *mmio = ap->host->mmio_base;
1215 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1216
1217 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1218
1219 return 0;
1220 }
1221
1222 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1223 {
1224 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1225 void __iomem *mmio = host->mmio_base;
1226 u32 ctl;
1227
1228 if (mesg.event == PM_EVENT_SUSPEND) {
1229 /* AHCI spec rev1.1 section 8.3.3:
1230 * Software must disable interrupts prior to requesting a
1231 * transition of the HBA to D3 state.
1232 */
1233 ctl = readl(mmio + HOST_CTL);
1234 ctl &= ~HOST_IRQ_EN;
1235 writel(ctl, mmio + HOST_CTL);
1236 readl(mmio + HOST_CTL); /* flush */
1237 }
1238
1239 return ata_pci_device_suspend(pdev, mesg);
1240 }
1241
1242 static int ahci_pci_device_resume(struct pci_dev *pdev)
1243 {
1244 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1245 struct ahci_host_priv *hpriv = host->private_data;
1246 void __iomem *mmio = host->mmio_base;
1247 int rc;
1248
1249 ata_pci_device_do_resume(pdev);
1250
1251 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1252 rc = ahci_reset_controller(mmio, pdev);
1253 if (rc)
1254 return rc;
1255
1256 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
1257 }
1258
1259 ata_host_resume(host);
1260
1261 return 0;
1262 }
1263
1264 static int ahci_port_start(struct ata_port *ap)
1265 {
1266 struct device *dev = ap->host->dev;
1267 struct ahci_host_priv *hpriv = ap->host->private_data;
1268 struct ahci_port_priv *pp;
1269 void __iomem *mmio = ap->host->mmio_base;
1270 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1271 void *mem;
1272 dma_addr_t mem_dma;
1273 int rc;
1274
1275 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1276 if (!pp)
1277 return -ENOMEM;
1278 memset(pp, 0, sizeof(*pp));
1279
1280 rc = ata_pad_alloc(ap, dev);
1281 if (rc) {
1282 kfree(pp);
1283 return rc;
1284 }
1285
1286 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1287 if (!mem) {
1288 ata_pad_free(ap, dev);
1289 kfree(pp);
1290 return -ENOMEM;
1291 }
1292 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1293
1294 /*
1295 * First item in chunk of DMA memory: 32-slot command table,
1296 * 32 bytes each in size
1297 */
1298 pp->cmd_slot = mem;
1299 pp->cmd_slot_dma = mem_dma;
1300
1301 mem += AHCI_CMD_SLOT_SZ;
1302 mem_dma += AHCI_CMD_SLOT_SZ;
1303
1304 /*
1305 * Second item: Received-FIS area
1306 */
1307 pp->rx_fis = mem;
1308 pp->rx_fis_dma = mem_dma;
1309
1310 mem += AHCI_RX_FIS_SZ;
1311 mem_dma += AHCI_RX_FIS_SZ;
1312
1313 /*
1314 * Third item: data area for storing a single command
1315 * and its scatter-gather table
1316 */
1317 pp->cmd_tbl = mem;
1318 pp->cmd_tbl_dma = mem_dma;
1319
1320 ap->private_data = pp;
1321
1322 /* initialize port */
1323 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1324
1325 return 0;
1326 }
1327
1328 static void ahci_port_stop(struct ata_port *ap)
1329 {
1330 struct device *dev = ap->host->dev;
1331 struct ahci_host_priv *hpriv = ap->host->private_data;
1332 struct ahci_port_priv *pp = ap->private_data;
1333 void __iomem *mmio = ap->host->mmio_base;
1334 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1335 const char *emsg = NULL;
1336 int rc;
1337
1338 /* de-initialize port */
1339 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1340 if (rc)
1341 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1342
1343 ap->private_data = NULL;
1344 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1345 pp->cmd_slot, pp->cmd_slot_dma);
1346 ata_pad_free(ap, dev);
1347 kfree(pp);
1348 }
1349
1350 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1351 unsigned int port_idx)
1352 {
1353 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1354 base = ahci_port_base_ul(base, port_idx);
1355 VPRINTK("base now==0x%lx\n", base);
1356
1357 port->cmd_addr = base;
1358 port->scr_addr = base + PORT_SCR;
1359
1360 VPRINTK("EXIT\n");
1361 }
1362
1363 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1364 {
1365 struct ahci_host_priv *hpriv = probe_ent->private_data;
1366 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1367 void __iomem *mmio = probe_ent->mmio_base;
1368 unsigned int i, using_dac;
1369 int rc;
1370
1371 rc = ahci_reset_controller(mmio, pdev);
1372 if (rc)
1373 return rc;
1374
1375 hpriv->cap = readl(mmio + HOST_CAP);
1376 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1377 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1378
1379 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1380 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1381
1382 using_dac = hpriv->cap & HOST_CAP_64;
1383 if (using_dac &&
1384 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1385 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1386 if (rc) {
1387 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1388 if (rc) {
1389 dev_printk(KERN_ERR, &pdev->dev,
1390 "64-bit DMA enable failed\n");
1391 return rc;
1392 }
1393 }
1394 } else {
1395 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1396 if (rc) {
1397 dev_printk(KERN_ERR, &pdev->dev,
1398 "32-bit DMA enable failed\n");
1399 return rc;
1400 }
1401 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1402 if (rc) {
1403 dev_printk(KERN_ERR, &pdev->dev,
1404 "32-bit consistent DMA enable failed\n");
1405 return rc;
1406 }
1407 }
1408
1409 for (i = 0; i < probe_ent->n_ports; i++)
1410 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1411
1412 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1413
1414 pci_set_master(pdev);
1415
1416 return 0;
1417 }
1418
1419 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1420 {
1421 struct ahci_host_priv *hpriv = probe_ent->private_data;
1422 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1423 void __iomem *mmio = probe_ent->mmio_base;
1424 u32 vers, cap, impl, speed;
1425 const char *speed_s;
1426 u16 cc;
1427 const char *scc_s;
1428
1429 vers = readl(mmio + HOST_VERSION);
1430 cap = hpriv->cap;
1431 impl = hpriv->port_map;
1432
1433 speed = (cap >> 20) & 0xf;
1434 if (speed == 1)
1435 speed_s = "1.5";
1436 else if (speed == 2)
1437 speed_s = "3";
1438 else
1439 speed_s = "?";
1440
1441 pci_read_config_word(pdev, 0x0a, &cc);
1442 if (cc == 0x0101)
1443 scc_s = "IDE";
1444 else if (cc == 0x0106)
1445 scc_s = "SATA";
1446 else if (cc == 0x0104)
1447 scc_s = "RAID";
1448 else
1449 scc_s = "unknown";
1450
1451 dev_printk(KERN_INFO, &pdev->dev,
1452 "AHCI %02x%02x.%02x%02x "
1453 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1454 ,
1455
1456 (vers >> 24) & 0xff,
1457 (vers >> 16) & 0xff,
1458 (vers >> 8) & 0xff,
1459 vers & 0xff,
1460
1461 ((cap >> 8) & 0x1f) + 1,
1462 (cap & 0x1f) + 1,
1463 speed_s,
1464 impl,
1465 scc_s);
1466
1467 dev_printk(KERN_INFO, &pdev->dev,
1468 "flags: "
1469 "%s%s%s%s%s%s"
1470 "%s%s%s%s%s%s%s\n"
1471 ,
1472
1473 cap & (1 << 31) ? "64bit " : "",
1474 cap & (1 << 30) ? "ncq " : "",
1475 cap & (1 << 28) ? "ilck " : "",
1476 cap & (1 << 27) ? "stag " : "",
1477 cap & (1 << 26) ? "pm " : "",
1478 cap & (1 << 25) ? "led " : "",
1479
1480 cap & (1 << 24) ? "clo " : "",
1481 cap & (1 << 19) ? "nz " : "",
1482 cap & (1 << 18) ? "only " : "",
1483 cap & (1 << 17) ? "pmp " : "",
1484 cap & (1 << 15) ? "pio " : "",
1485 cap & (1 << 14) ? "slum " : "",
1486 cap & (1 << 13) ? "part " : ""
1487 );
1488 }
1489
1490 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1491 {
1492 static int printed_version;
1493 struct ata_probe_ent *probe_ent = NULL;
1494 struct ahci_host_priv *hpriv;
1495 unsigned long base;
1496 void __iomem *mmio_base;
1497 unsigned int board_idx = (unsigned int) ent->driver_data;
1498 int have_msi, pci_dev_busy = 0;
1499 int rc;
1500
1501 VPRINTK("ENTER\n");
1502
1503 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1504
1505 if (!printed_version++)
1506 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1507
1508 /* JMicron-specific fixup: make sure we're in AHCI mode */
1509 /* This is protected from races with ata_jmicron by the pci probe
1510 locking */
1511 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1512 /* AHCI enable, AHCI on function 0 */
1513 pci_write_config_byte(pdev, 0x41, 0xa1);
1514 /* Function 1 is the PATA controller */
1515 if (PCI_FUNC(pdev->devfn))
1516 return -ENODEV;
1517 }
1518
1519 rc = pci_enable_device(pdev);
1520 if (rc)
1521 return rc;
1522
1523 rc = pci_request_regions(pdev, DRV_NAME);
1524 if (rc) {
1525 pci_dev_busy = 1;
1526 goto err_out;
1527 }
1528
1529 if (pci_enable_msi(pdev) == 0)
1530 have_msi = 1;
1531 else {
1532 pci_intx(pdev, 1);
1533 have_msi = 0;
1534 }
1535
1536 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1537 if (probe_ent == NULL) {
1538 rc = -ENOMEM;
1539 goto err_out_msi;
1540 }
1541
1542 memset(probe_ent, 0, sizeof(*probe_ent));
1543 probe_ent->dev = pci_dev_to_dev(pdev);
1544 INIT_LIST_HEAD(&probe_ent->node);
1545
1546 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1547 if (mmio_base == NULL) {
1548 rc = -ENOMEM;
1549 goto err_out_free_ent;
1550 }
1551 base = (unsigned long) mmio_base;
1552
1553 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1554 if (!hpriv) {
1555 rc = -ENOMEM;
1556 goto err_out_iounmap;
1557 }
1558 memset(hpriv, 0, sizeof(*hpriv));
1559
1560 probe_ent->sht = ahci_port_info[board_idx].sht;
1561 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1562 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1563 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1564 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1565
1566 probe_ent->irq = pdev->irq;
1567 probe_ent->irq_flags = IRQF_SHARED;
1568 probe_ent->mmio_base = mmio_base;
1569 probe_ent->private_data = hpriv;
1570
1571 if (have_msi)
1572 hpriv->flags |= AHCI_FLAG_MSI;
1573
1574 /* initialize adapter */
1575 rc = ahci_host_init(probe_ent);
1576 if (rc)
1577 goto err_out_hpriv;
1578
1579 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1580 (hpriv->cap & HOST_CAP_NCQ))
1581 probe_ent->port_flags |= ATA_FLAG_NCQ;
1582
1583 ahci_print_info(probe_ent);
1584
1585 /* FIXME: check ata_device_add return value */
1586 ata_device_add(probe_ent);
1587 kfree(probe_ent);
1588
1589 return 0;
1590
1591 err_out_hpriv:
1592 kfree(hpriv);
1593 err_out_iounmap:
1594 pci_iounmap(pdev, mmio_base);
1595 err_out_free_ent:
1596 kfree(probe_ent);
1597 err_out_msi:
1598 if (have_msi)
1599 pci_disable_msi(pdev);
1600 else
1601 pci_intx(pdev, 0);
1602 pci_release_regions(pdev);
1603 err_out:
1604 if (!pci_dev_busy)
1605 pci_disable_device(pdev);
1606 return rc;
1607 }
1608
1609 static void ahci_remove_one (struct pci_dev *pdev)
1610 {
1611 struct device *dev = pci_dev_to_dev(pdev);
1612 struct ata_host *host = dev_get_drvdata(dev);
1613 struct ahci_host_priv *hpriv = host->private_data;
1614 unsigned int i;
1615 int have_msi;
1616
1617 for (i = 0; i < host->n_ports; i++)
1618 ata_port_detach(host->ports[i]);
1619
1620 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1621 free_irq(host->irq, host);
1622
1623 for (i = 0; i < host->n_ports; i++) {
1624 struct ata_port *ap = host->ports[i];
1625
1626 ata_scsi_release(ap->scsi_host);
1627 scsi_host_put(ap->scsi_host);
1628 }
1629
1630 kfree(hpriv);
1631 pci_iounmap(pdev, host->mmio_base);
1632 kfree(host);
1633
1634 if (have_msi)
1635 pci_disable_msi(pdev);
1636 else
1637 pci_intx(pdev, 0);
1638 pci_release_regions(pdev);
1639 pci_disable_device(pdev);
1640 dev_set_drvdata(dev, NULL);
1641 }
1642
1643 static int __init ahci_init(void)
1644 {
1645 return pci_register_driver(&ahci_pci_driver);
1646 }
1647
1648 static void __exit ahci_exit(void)
1649 {
1650 pci_unregister_driver(&ahci_pci_driver);
1651 }
1652
1653
1654 MODULE_AUTHOR("Jeff Garzik");
1655 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1656 MODULE_LICENSE("GPL");
1657 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1658 MODULE_VERSION(DRV_VERSION);
1659
1660 module_init(ahci_init);
1661 module_exit(ahci_exit);
Linux kernel - Deliverables
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