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libata: bump versions
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.2"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83 board_ahci_sb600 = 4,
84
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
91
92 /* HOST_CTL bits */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
96
97 /* HOST_CAP bits */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
142 PORT_IRQ_IF_ERR |
143 PORT_IRQ_CONNECT |
144 PORT_IRQ_PHYRDY |
145 PORT_IRQ_UNK_FIS,
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_TF_ERR |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
152
153 /* PORT_CMD bits */
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
167
168 /* ap->flags bits */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
174
175 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
176 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
177 ATA_FLAG_SKIP_D2H_BSY |
178 ATA_FLAG_ACPI_SATA,
179 };
180
181 struct ahci_cmd_hdr {
182 u32 opts;
183 u32 status;
184 u32 tbl_addr;
185 u32 tbl_addr_hi;
186 u32 reserved[4];
187 };
188
189 struct ahci_sg {
190 u32 addr;
191 u32 addr_hi;
192 u32 reserved;
193 u32 flags_size;
194 };
195
196 struct ahci_host_priv {
197 u32 cap; /* cap to use */
198 u32 port_map; /* port map to use */
199 u32 saved_cap; /* saved initial cap */
200 u32 saved_port_map; /* saved initial port_map */
201 };
202
203 struct ahci_port_priv {
204 struct ahci_cmd_hdr *cmd_slot;
205 dma_addr_t cmd_slot_dma;
206 void *cmd_tbl;
207 dma_addr_t cmd_tbl_dma;
208 void *rx_fis;
209 dma_addr_t rx_fis_dma;
210 /* for NCQ spurious interrupt analysis */
211 unsigned int ncq_saw_d2h:1;
212 unsigned int ncq_saw_dmas:1;
213 unsigned int ncq_saw_sdb:1;
214 };
215
216 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
217 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
218 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
219 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
220 static void ahci_irq_clear(struct ata_port *ap);
221 static int ahci_port_start(struct ata_port *ap);
222 static void ahci_port_stop(struct ata_port *ap);
223 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
224 static void ahci_qc_prep(struct ata_queued_cmd *qc);
225 static u8 ahci_check_status(struct ata_port *ap);
226 static void ahci_freeze(struct ata_port *ap);
227 static void ahci_thaw(struct ata_port *ap);
228 static void ahci_error_handler(struct ata_port *ap);
229 static void ahci_vt8251_error_handler(struct ata_port *ap);
230 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
231 #ifdef CONFIG_PM
232 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
233 static int ahci_port_resume(struct ata_port *ap);
234 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
235 static int ahci_pci_device_resume(struct pci_dev *pdev);
236 #endif
237
238 static struct scsi_host_template ahci_sht = {
239 .module = THIS_MODULE,
240 .name = DRV_NAME,
241 .ioctl = ata_scsi_ioctl,
242 .queuecommand = ata_scsi_queuecmd,
243 .change_queue_depth = ata_scsi_change_queue_depth,
244 .can_queue = AHCI_MAX_CMDS - 1,
245 .this_id = ATA_SHT_THIS_ID,
246 .sg_tablesize = AHCI_MAX_SG,
247 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
248 .emulated = ATA_SHT_EMULATED,
249 .use_clustering = AHCI_USE_CLUSTERING,
250 .proc_name = DRV_NAME,
251 .dma_boundary = AHCI_DMA_BOUNDARY,
252 .slave_configure = ata_scsi_slave_config,
253 .slave_destroy = ata_scsi_slave_destroy,
254 .bios_param = ata_std_bios_param,
255 };
256
257 static const struct ata_port_operations ahci_ops = {
258 .port_disable = ata_port_disable,
259
260 .check_status = ahci_check_status,
261 .check_altstatus = ahci_check_status,
262 .dev_select = ata_noop_dev_select,
263
264 .tf_read = ahci_tf_read,
265
266 .qc_prep = ahci_qc_prep,
267 .qc_issue = ahci_qc_issue,
268
269 .irq_clear = ahci_irq_clear,
270 .irq_on = ata_dummy_irq_on,
271 .irq_ack = ata_dummy_irq_ack,
272
273 .scr_read = ahci_scr_read,
274 .scr_write = ahci_scr_write,
275
276 .freeze = ahci_freeze,
277 .thaw = ahci_thaw,
278
279 .error_handler = ahci_error_handler,
280 .post_internal_cmd = ahci_post_internal_cmd,
281
282 #ifdef CONFIG_PM
283 .port_suspend = ahci_port_suspend,
284 .port_resume = ahci_port_resume,
285 #endif
286
287 .port_start = ahci_port_start,
288 .port_stop = ahci_port_stop,
289 };
290
291 static const struct ata_port_operations ahci_vt8251_ops = {
292 .port_disable = ata_port_disable,
293
294 .check_status = ahci_check_status,
295 .check_altstatus = ahci_check_status,
296 .dev_select = ata_noop_dev_select,
297
298 .tf_read = ahci_tf_read,
299
300 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue,
302
303 .irq_clear = ahci_irq_clear,
304 .irq_on = ata_dummy_irq_on,
305 .irq_ack = ata_dummy_irq_ack,
306
307 .scr_read = ahci_scr_read,
308 .scr_write = ahci_scr_write,
309
310 .freeze = ahci_freeze,
311 .thaw = ahci_thaw,
312
313 .error_handler = ahci_vt8251_error_handler,
314 .post_internal_cmd = ahci_post_internal_cmd,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320
321 .port_start = ahci_port_start,
322 .port_stop = ahci_port_stop,
323 };
324
325 static const struct ata_port_info ahci_port_info[] = {
326 /* board_ahci */
327 {
328 .flags = AHCI_FLAG_COMMON,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
332 },
333 /* board_ahci_pi */
334 {
335 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
336 .pio_mask = 0x1f, /* pio0-4 */
337 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
338 .port_ops = &ahci_ops,
339 },
340 /* board_ahci_vt8251 */
341 {
342 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
343 AHCI_FLAG_NO_NCQ,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
346 .port_ops = &ahci_vt8251_ops,
347 },
348 /* board_ahci_ign_iferr */
349 {
350 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
351 .pio_mask = 0x1f, /* pio0-4 */
352 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
353 .port_ops = &ahci_ops,
354 },
355 /* board_ahci_sb600 */
356 {
357 .flags = AHCI_FLAG_COMMON |
358 AHCI_FLAG_IGN_SERR_INTERNAL |
359 AHCI_FLAG_32BIT_ONLY,
360 .pio_mask = 0x1f, /* pio0-4 */
361 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
362 .port_ops = &ahci_ops,
363 },
364 };
365
366 static const struct pci_device_id ahci_pci_tbl[] = {
367 /* Intel */
368 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
369 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
370 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
371 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
372 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
373 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
374 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
375 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
376 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
377 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
378 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
380 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
381 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
382 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
383 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
384 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
385 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
386 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
388 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
389 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
390 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
391 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
392 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
393 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
395
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
399
400 /* ATI */
401 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
402 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
403
404 /* VIA */
405 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
406 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
407
408 /* NVIDIA */
409 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
429
430 /* SiS */
431 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
432 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
433 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
434
435 /* Generic, PCI class code for AHCI */
436 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
437 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
438
439 { } /* terminate list */
440 };
441
442
443 static struct pci_driver ahci_pci_driver = {
444 .name = DRV_NAME,
445 .id_table = ahci_pci_tbl,
446 .probe = ahci_init_one,
447 .remove = ata_pci_remove_one,
448 #ifdef CONFIG_PM
449 .suspend = ahci_pci_device_suspend,
450 .resume = ahci_pci_device_resume,
451 #endif
452 };
453
454
455 static inline int ahci_nr_ports(u32 cap)
456 {
457 return (cap & 0x1f) + 1;
458 }
459
460 static inline void __iomem *ahci_port_base(struct ata_port *ap)
461 {
462 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
463
464 return mmio + 0x100 + (ap->port_no * 0x80);
465 }
466
467 /**
468 * ahci_save_initial_config - Save and fixup initial config values
469 * @pdev: target PCI device
470 * @pi: associated ATA port info
471 * @hpriv: host private area to store config values
472 *
473 * Some registers containing configuration info might be setup by
474 * BIOS and might be cleared on reset. This function saves the
475 * initial values of those registers into @hpriv such that they
476 * can be restored after controller reset.
477 *
478 * If inconsistent, config values are fixed up by this function.
479 *
480 * LOCKING:
481 * None.
482 */
483 static void ahci_save_initial_config(struct pci_dev *pdev,
484 const struct ata_port_info *pi,
485 struct ahci_host_priv *hpriv)
486 {
487 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
488 u32 cap, port_map;
489 int i;
490
491 /* Values prefixed with saved_ are written back to host after
492 * reset. Values without are used for driver operation.
493 */
494 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
495 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
496
497 /* some chips lie about 64bit support */
498 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
499 dev_printk(KERN_INFO, &pdev->dev,
500 "controller can't do 64bit DMA, forcing 32bit\n");
501 cap &= ~HOST_CAP_64;
502 }
503
504 /* fixup zero port_map */
505 if (!port_map) {
506 port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1;
507 dev_printk(KERN_WARNING, &pdev->dev,
508 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
509
510 /* write the fixed up value to the PI register */
511 hpriv->saved_port_map = port_map;
512 }
513
514 /* cross check port_map and cap.n_ports */
515 if (pi->flags & AHCI_FLAG_HONOR_PI) {
516 u32 tmp_port_map = port_map;
517 int n_ports = ahci_nr_ports(cap);
518
519 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
520 if (tmp_port_map & (1 << i)) {
521 n_ports--;
522 tmp_port_map &= ~(1 << i);
523 }
524 }
525
526 /* Whine if inconsistent. No need to update cap.
527 * port_map is used to determine number of ports.
528 */
529 if (n_ports || tmp_port_map)
530 dev_printk(KERN_WARNING, &pdev->dev,
531 "nr_ports (%u) and implemented port map "
532 "(0x%x) don't match\n",
533 ahci_nr_ports(cap), port_map);
534 } else {
535 /* fabricate port_map from cap.nr_ports */
536 port_map = (1 << ahci_nr_ports(cap)) - 1;
537 }
538
539 /* record values to use during operation */
540 hpriv->cap = cap;
541 hpriv->port_map = port_map;
542 }
543
544 /**
545 * ahci_restore_initial_config - Restore initial config
546 * @host: target ATA host
547 *
548 * Restore initial config stored by ahci_save_initial_config().
549 *
550 * LOCKING:
551 * None.
552 */
553 static void ahci_restore_initial_config(struct ata_host *host)
554 {
555 struct ahci_host_priv *hpriv = host->private_data;
556 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
557
558 writel(hpriv->saved_cap, mmio + HOST_CAP);
559 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
560 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
561 }
562
563 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
564 {
565 unsigned int sc_reg;
566
567 switch (sc_reg_in) {
568 case SCR_STATUS: sc_reg = 0; break;
569 case SCR_CONTROL: sc_reg = 1; break;
570 case SCR_ERROR: sc_reg = 2; break;
571 case SCR_ACTIVE: sc_reg = 3; break;
572 default:
573 return 0xffffffffU;
574 }
575
576 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
577 }
578
579
580 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
581 u32 val)
582 {
583 unsigned int sc_reg;
584
585 switch (sc_reg_in) {
586 case SCR_STATUS: sc_reg = 0; break;
587 case SCR_CONTROL: sc_reg = 1; break;
588 case SCR_ERROR: sc_reg = 2; break;
589 case SCR_ACTIVE: sc_reg = 3; break;
590 default:
591 return;
592 }
593
594 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
595 }
596
597 static void ahci_start_engine(struct ata_port *ap)
598 {
599 void __iomem *port_mmio = ahci_port_base(ap);
600 u32 tmp;
601
602 /* start DMA */
603 tmp = readl(port_mmio + PORT_CMD);
604 tmp |= PORT_CMD_START;
605 writel(tmp, port_mmio + PORT_CMD);
606 readl(port_mmio + PORT_CMD); /* flush */
607 }
608
609 static int ahci_stop_engine(struct ata_port *ap)
610 {
611 void __iomem *port_mmio = ahci_port_base(ap);
612 u32 tmp;
613
614 tmp = readl(port_mmio + PORT_CMD);
615
616 /* check if the HBA is idle */
617 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
618 return 0;
619
620 /* setting HBA to idle */
621 tmp &= ~PORT_CMD_START;
622 writel(tmp, port_mmio + PORT_CMD);
623
624 /* wait for engine to stop. This could be as long as 500 msec */
625 tmp = ata_wait_register(port_mmio + PORT_CMD,
626 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
627 if (tmp & PORT_CMD_LIST_ON)
628 return -EIO;
629
630 return 0;
631 }
632
633 static void ahci_start_fis_rx(struct ata_port *ap)
634 {
635 void __iomem *port_mmio = ahci_port_base(ap);
636 struct ahci_host_priv *hpriv = ap->host->private_data;
637 struct ahci_port_priv *pp = ap->private_data;
638 u32 tmp;
639
640 /* set FIS registers */
641 if (hpriv->cap & HOST_CAP_64)
642 writel((pp->cmd_slot_dma >> 16) >> 16,
643 port_mmio + PORT_LST_ADDR_HI);
644 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
645
646 if (hpriv->cap & HOST_CAP_64)
647 writel((pp->rx_fis_dma >> 16) >> 16,
648 port_mmio + PORT_FIS_ADDR_HI);
649 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
650
651 /* enable FIS reception */
652 tmp = readl(port_mmio + PORT_CMD);
653 tmp |= PORT_CMD_FIS_RX;
654 writel(tmp, port_mmio + PORT_CMD);
655
656 /* flush */
657 readl(port_mmio + PORT_CMD);
658 }
659
660 static int ahci_stop_fis_rx(struct ata_port *ap)
661 {
662 void __iomem *port_mmio = ahci_port_base(ap);
663 u32 tmp;
664
665 /* disable FIS reception */
666 tmp = readl(port_mmio + PORT_CMD);
667 tmp &= ~PORT_CMD_FIS_RX;
668 writel(tmp, port_mmio + PORT_CMD);
669
670 /* wait for completion, spec says 500ms, give it 1000 */
671 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
672 PORT_CMD_FIS_ON, 10, 1000);
673 if (tmp & PORT_CMD_FIS_ON)
674 return -EBUSY;
675
676 return 0;
677 }
678
679 static void ahci_power_up(struct ata_port *ap)
680 {
681 struct ahci_host_priv *hpriv = ap->host->private_data;
682 void __iomem *port_mmio = ahci_port_base(ap);
683 u32 cmd;
684
685 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
686
687 /* spin up device */
688 if (hpriv->cap & HOST_CAP_SSS) {
689 cmd |= PORT_CMD_SPIN_UP;
690 writel(cmd, port_mmio + PORT_CMD);
691 }
692
693 /* wake up link */
694 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
695 }
696
697 #ifdef CONFIG_PM
698 static void ahci_power_down(struct ata_port *ap)
699 {
700 struct ahci_host_priv *hpriv = ap->host->private_data;
701 void __iomem *port_mmio = ahci_port_base(ap);
702 u32 cmd, scontrol;
703
704 if (!(hpriv->cap & HOST_CAP_SSS))
705 return;
706
707 /* put device into listen mode, first set PxSCTL.DET to 0 */
708 scontrol = readl(port_mmio + PORT_SCR_CTL);
709 scontrol &= ~0xf;
710 writel(scontrol, port_mmio + PORT_SCR_CTL);
711
712 /* then set PxCMD.SUD to 0 */
713 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
714 cmd &= ~PORT_CMD_SPIN_UP;
715 writel(cmd, port_mmio + PORT_CMD);
716 }
717 #endif
718
719 static void ahci_init_port(struct ata_port *ap)
720 {
721 /* enable FIS reception */
722 ahci_start_fis_rx(ap);
723
724 /* enable DMA */
725 ahci_start_engine(ap);
726 }
727
728 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
729 {
730 int rc;
731
732 /* disable DMA */
733 rc = ahci_stop_engine(ap);
734 if (rc) {
735 *emsg = "failed to stop engine";
736 return rc;
737 }
738
739 /* disable FIS reception */
740 rc = ahci_stop_fis_rx(ap);
741 if (rc) {
742 *emsg = "failed stop FIS RX";
743 return rc;
744 }
745
746 return 0;
747 }
748
749 static int ahci_reset_controller(struct ata_host *host)
750 {
751 struct pci_dev *pdev = to_pci_dev(host->dev);
752 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
753 u32 tmp;
754
755 /* global controller reset */
756 tmp = readl(mmio + HOST_CTL);
757 if ((tmp & HOST_RESET) == 0) {
758 writel(tmp | HOST_RESET, mmio + HOST_CTL);
759 readl(mmio + HOST_CTL); /* flush */
760 }
761
762 /* reset must complete within 1 second, or
763 * the hardware should be considered fried.
764 */
765 ssleep(1);
766
767 tmp = readl(mmio + HOST_CTL);
768 if (tmp & HOST_RESET) {
769 dev_printk(KERN_ERR, host->dev,
770 "controller reset failed (0x%x)\n", tmp);
771 return -EIO;
772 }
773
774 /* turn on AHCI mode */
775 writel(HOST_AHCI_EN, mmio + HOST_CTL);
776 (void) readl(mmio + HOST_CTL); /* flush */
777
778 /* some registers might be cleared on reset. restore initial values */
779 ahci_restore_initial_config(host);
780
781 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
782 u16 tmp16;
783
784 /* configure PCS */
785 pci_read_config_word(pdev, 0x92, &tmp16);
786 tmp16 |= 0xf;
787 pci_write_config_word(pdev, 0x92, tmp16);
788 }
789
790 return 0;
791 }
792
793 static void ahci_init_controller(struct ata_host *host)
794 {
795 struct pci_dev *pdev = to_pci_dev(host->dev);
796 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
797 int i, rc;
798 u32 tmp;
799
800 for (i = 0; i < host->n_ports; i++) {
801 struct ata_port *ap = host->ports[i];
802 void __iomem *port_mmio = ahci_port_base(ap);
803 const char *emsg = NULL;
804
805 if (ata_port_is_dummy(ap))
806 continue;
807
808 /* make sure port is not active */
809 rc = ahci_deinit_port(ap, &emsg);
810 if (rc)
811 dev_printk(KERN_WARNING, &pdev->dev,
812 "%s (%d)\n", emsg, rc);
813
814 /* clear SError */
815 tmp = readl(port_mmio + PORT_SCR_ERR);
816 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
817 writel(tmp, port_mmio + PORT_SCR_ERR);
818
819 /* clear port IRQ */
820 tmp = readl(port_mmio + PORT_IRQ_STAT);
821 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
822 if (tmp)
823 writel(tmp, port_mmio + PORT_IRQ_STAT);
824
825 writel(1 << i, mmio + HOST_IRQ_STAT);
826 }
827
828 tmp = readl(mmio + HOST_CTL);
829 VPRINTK("HOST_CTL 0x%x\n", tmp);
830 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
831 tmp = readl(mmio + HOST_CTL);
832 VPRINTK("HOST_CTL 0x%x\n", tmp);
833 }
834
835 static unsigned int ahci_dev_classify(struct ata_port *ap)
836 {
837 void __iomem *port_mmio = ahci_port_base(ap);
838 struct ata_taskfile tf;
839 u32 tmp;
840
841 tmp = readl(port_mmio + PORT_SIG);
842 tf.lbah = (tmp >> 24) & 0xff;
843 tf.lbam = (tmp >> 16) & 0xff;
844 tf.lbal = (tmp >> 8) & 0xff;
845 tf.nsect = (tmp) & 0xff;
846
847 return ata_dev_classify(&tf);
848 }
849
850 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
851 u32 opts)
852 {
853 dma_addr_t cmd_tbl_dma;
854
855 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
856
857 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
858 pp->cmd_slot[tag].status = 0;
859 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
860 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
861 }
862
863 static int ahci_clo(struct ata_port *ap)
864 {
865 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
866 struct ahci_host_priv *hpriv = ap->host->private_data;
867 u32 tmp;
868
869 if (!(hpriv->cap & HOST_CAP_CLO))
870 return -EOPNOTSUPP;
871
872 tmp = readl(port_mmio + PORT_CMD);
873 tmp |= PORT_CMD_CLO;
874 writel(tmp, port_mmio + PORT_CMD);
875
876 tmp = ata_wait_register(port_mmio + PORT_CMD,
877 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
878 if (tmp & PORT_CMD_CLO)
879 return -EIO;
880
881 return 0;
882 }
883
884 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
885 unsigned long deadline)
886 {
887 struct ahci_port_priv *pp = ap->private_data;
888 void __iomem *port_mmio = ahci_port_base(ap);
889 const u32 cmd_fis_len = 5; /* five dwords */
890 const char *reason = NULL;
891 struct ata_taskfile tf;
892 u32 tmp;
893 u8 *fis;
894 int rc;
895
896 DPRINTK("ENTER\n");
897
898 if (ata_port_offline(ap)) {
899 DPRINTK("PHY reports no device\n");
900 *class = ATA_DEV_NONE;
901 return 0;
902 }
903
904 /* prepare for SRST (AHCI-1.1 10.4.1) */
905 rc = ahci_stop_engine(ap);
906 if (rc) {
907 reason = "failed to stop engine";
908 goto fail_restart;
909 }
910
911 /* check BUSY/DRQ, perform Command List Override if necessary */
912 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
913 rc = ahci_clo(ap);
914
915 if (rc == -EOPNOTSUPP) {
916 reason = "port busy but CLO unavailable";
917 goto fail_restart;
918 } else if (rc) {
919 reason = "port busy but CLO failed";
920 goto fail_restart;
921 }
922 }
923
924 /* restart engine */
925 ahci_start_engine(ap);
926
927 ata_tf_init(ap->device, &tf);
928 fis = pp->cmd_tbl;
929
930 /* issue the first D2H Register FIS */
931 ahci_fill_cmd_slot(pp, 0,
932 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
933
934 tf.ctl |= ATA_SRST;
935 ata_tf_to_fis(&tf, fis, 0);
936 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
937
938 writel(1, port_mmio + PORT_CMD_ISSUE);
939
940 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
941 if (tmp & 0x1) {
942 rc = -EIO;
943 reason = "1st FIS failed";
944 goto fail;
945 }
946
947 /* spec says at least 5us, but be generous and sleep for 1ms */
948 msleep(1);
949
950 /* issue the second D2H Register FIS */
951 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
952
953 tf.ctl &= ~ATA_SRST;
954 ata_tf_to_fis(&tf, fis, 0);
955 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
956
957 writel(1, port_mmio + PORT_CMD_ISSUE);
958 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
959
960 /* spec mandates ">= 2ms" before checking status.
961 * We wait 150ms, because that was the magic delay used for
962 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
963 * between when the ATA command register is written, and then
964 * status is checked. Because waiting for "a while" before
965 * checking status is fine, post SRST, we perform this magic
966 * delay here as well.
967 */
968 msleep(150);
969
970 rc = ata_wait_ready(ap, deadline);
971 /* link occupied, -ENODEV too is an error */
972 if (rc) {
973 reason = "device not ready";
974 goto fail;
975 }
976 *class = ahci_dev_classify(ap);
977
978 DPRINTK("EXIT, class=%u\n", *class);
979 return 0;
980
981 fail_restart:
982 ahci_start_engine(ap);
983 fail:
984 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
985 return rc;
986 }
987
988 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
989 unsigned long deadline)
990 {
991 struct ahci_port_priv *pp = ap->private_data;
992 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
993 struct ata_taskfile tf;
994 int rc;
995
996 DPRINTK("ENTER\n");
997
998 ahci_stop_engine(ap);
999
1000 /* clear D2H reception area to properly wait for D2H FIS */
1001 ata_tf_init(ap->device, &tf);
1002 tf.command = 0x80;
1003 ata_tf_to_fis(&tf, d2h_fis, 0);
1004
1005 rc = sata_std_hardreset(ap, class, deadline);
1006
1007 ahci_start_engine(ap);
1008
1009 if (rc == 0 && ata_port_online(ap))
1010 *class = ahci_dev_classify(ap);
1011 if (*class == ATA_DEV_UNKNOWN)
1012 *class = ATA_DEV_NONE;
1013
1014 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1015 return rc;
1016 }
1017
1018 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1019 unsigned long deadline)
1020 {
1021 int rc;
1022
1023 DPRINTK("ENTER\n");
1024
1025 ahci_stop_engine(ap);
1026
1027 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1028 deadline);
1029
1030 /* vt8251 needs SError cleared for the port to operate */
1031 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1032
1033 ahci_start_engine(ap);
1034
1035 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1036
1037 /* vt8251 doesn't clear BSY on signature FIS reception,
1038 * request follow-up softreset.
1039 */
1040 return rc ?: -EAGAIN;
1041 }
1042
1043 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1044 {
1045 void __iomem *port_mmio = ahci_port_base(ap);
1046 u32 new_tmp, tmp;
1047
1048 ata_std_postreset(ap, class);
1049
1050 /* Make sure port's ATAPI bit is set appropriately */
1051 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1052 if (*class == ATA_DEV_ATAPI)
1053 new_tmp |= PORT_CMD_ATAPI;
1054 else
1055 new_tmp &= ~PORT_CMD_ATAPI;
1056 if (new_tmp != tmp) {
1057 writel(new_tmp, port_mmio + PORT_CMD);
1058 readl(port_mmio + PORT_CMD); /* flush */
1059 }
1060 }
1061
1062 static u8 ahci_check_status(struct ata_port *ap)
1063 {
1064 void __iomem *mmio = ap->ioaddr.cmd_addr;
1065
1066 return readl(mmio + PORT_TFDATA) & 0xFF;
1067 }
1068
1069 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1070 {
1071 struct ahci_port_priv *pp = ap->private_data;
1072 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1073
1074 ata_tf_from_fis(d2h_fis, tf);
1075 }
1076
1077 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1078 {
1079 struct scatterlist *sg;
1080 struct ahci_sg *ahci_sg;
1081 unsigned int n_sg = 0;
1082
1083 VPRINTK("ENTER\n");
1084
1085 /*
1086 * Next, the S/G list.
1087 */
1088 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1089 ata_for_each_sg(sg, qc) {
1090 dma_addr_t addr = sg_dma_address(sg);
1091 u32 sg_len = sg_dma_len(sg);
1092
1093 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1094 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1095 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1096
1097 ahci_sg++;
1098 n_sg++;
1099 }
1100
1101 return n_sg;
1102 }
1103
1104 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1105 {
1106 struct ata_port *ap = qc->ap;
1107 struct ahci_port_priv *pp = ap->private_data;
1108 int is_atapi = is_atapi_taskfile(&qc->tf);
1109 void *cmd_tbl;
1110 u32 opts;
1111 const u32 cmd_fis_len = 5; /* five dwords */
1112 unsigned int n_elem;
1113
1114 /*
1115 * Fill in command table information. First, the header,
1116 * a SATA Register - Host to Device command FIS.
1117 */
1118 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1119
1120 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1121 if (is_atapi) {
1122 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1123 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1124 }
1125
1126 n_elem = 0;
1127 if (qc->flags & ATA_QCFLAG_DMAMAP)
1128 n_elem = ahci_fill_sg(qc, cmd_tbl);
1129
1130 /*
1131 * Fill in command slot information.
1132 */
1133 opts = cmd_fis_len | n_elem << 16;
1134 if (qc->tf.flags & ATA_TFLAG_WRITE)
1135 opts |= AHCI_CMD_WRITE;
1136 if (is_atapi)
1137 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1138
1139 ahci_fill_cmd_slot(pp, qc->tag, opts);
1140 }
1141
1142 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1143 {
1144 struct ahci_port_priv *pp = ap->private_data;
1145 struct ata_eh_info *ehi = &ap->eh_info;
1146 unsigned int err_mask = 0, action = 0;
1147 struct ata_queued_cmd *qc;
1148 u32 serror;
1149
1150 ata_ehi_clear_desc(ehi);
1151
1152 /* AHCI needs SError cleared; otherwise, it might lock up */
1153 serror = ahci_scr_read(ap, SCR_ERROR);
1154 ahci_scr_write(ap, SCR_ERROR, serror);
1155
1156 /* analyze @irq_stat */
1157 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1158
1159 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1160 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1161 irq_stat &= ~PORT_IRQ_IF_ERR;
1162
1163 if (irq_stat & PORT_IRQ_TF_ERR) {
1164 err_mask |= AC_ERR_DEV;
1165 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1166 serror &= ~SERR_INTERNAL;
1167 }
1168
1169 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1170 err_mask |= AC_ERR_HOST_BUS;
1171 action |= ATA_EH_SOFTRESET;
1172 }
1173
1174 if (irq_stat & PORT_IRQ_IF_ERR) {
1175 err_mask |= AC_ERR_ATA_BUS;
1176 action |= ATA_EH_SOFTRESET;
1177 ata_ehi_push_desc(ehi, ", interface fatal error");
1178 }
1179
1180 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1181 ata_ehi_hotplugged(ehi);
1182 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1183 "connection status changed" : "PHY RDY changed");
1184 }
1185
1186 if (irq_stat & PORT_IRQ_UNK_FIS) {
1187 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1188
1189 err_mask |= AC_ERR_HSM;
1190 action |= ATA_EH_SOFTRESET;
1191 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1192 unk[0], unk[1], unk[2], unk[3]);
1193 }
1194
1195 /* okay, let's hand over to EH */
1196 ehi->serror |= serror;
1197 ehi->action |= action;
1198
1199 qc = ata_qc_from_tag(ap, ap->active_tag);
1200 if (qc)
1201 qc->err_mask |= err_mask;
1202 else
1203 ehi->err_mask |= err_mask;
1204
1205 if (irq_stat & PORT_IRQ_FREEZE)
1206 ata_port_freeze(ap);
1207 else
1208 ata_port_abort(ap);
1209 }
1210
1211 static void ahci_host_intr(struct ata_port *ap)
1212 {
1213 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1214 struct ata_eh_info *ehi = &ap->eh_info;
1215 struct ahci_port_priv *pp = ap->private_data;
1216 u32 status, qc_active;
1217 int rc, known_irq = 0;
1218
1219 status = readl(port_mmio + PORT_IRQ_STAT);
1220 writel(status, port_mmio + PORT_IRQ_STAT);
1221
1222 if (unlikely(status & PORT_IRQ_ERROR)) {
1223 ahci_error_intr(ap, status);
1224 return;
1225 }
1226
1227 if (ap->sactive)
1228 qc_active = readl(port_mmio + PORT_SCR_ACT);
1229 else
1230 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1231
1232 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1233 if (rc > 0)
1234 return;
1235 if (rc < 0) {
1236 ehi->err_mask |= AC_ERR_HSM;
1237 ehi->action |= ATA_EH_SOFTRESET;
1238 ata_port_freeze(ap);
1239 return;
1240 }
1241
1242 /* hmmm... a spurious interupt */
1243
1244 /* if !NCQ, ignore. No modern ATA device has broken HSM
1245 * implementation for non-NCQ commands.
1246 */
1247 if (!ap->sactive)
1248 return;
1249
1250 if (status & PORT_IRQ_D2H_REG_FIS) {
1251 if (!pp->ncq_saw_d2h)
1252 ata_port_printk(ap, KERN_INFO,
1253 "D2H reg with I during NCQ, "
1254 "this message won't be printed again\n");
1255 pp->ncq_saw_d2h = 1;
1256 known_irq = 1;
1257 }
1258
1259 if (status & PORT_IRQ_DMAS_FIS) {
1260 if (!pp->ncq_saw_dmas)
1261 ata_port_printk(ap, KERN_INFO,
1262 "DMAS FIS during NCQ, "
1263 "this message won't be printed again\n");
1264 pp->ncq_saw_dmas = 1;
1265 known_irq = 1;
1266 }
1267
1268 if (status & PORT_IRQ_SDB_FIS) {
1269 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1270
1271 if (le32_to_cpu(f[1])) {
1272 /* SDB FIS containing spurious completions
1273 * might be dangerous, whine and fail commands
1274 * with HSM violation. EH will turn off NCQ
1275 * after several such failures.
1276 */
1277 ata_ehi_push_desc(ehi,
1278 "spurious completions during NCQ "
1279 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1280 readl(port_mmio + PORT_CMD_ISSUE),
1281 readl(port_mmio + PORT_SCR_ACT),
1282 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1283 ehi->err_mask |= AC_ERR_HSM;
1284 ehi->action |= ATA_EH_SOFTRESET;
1285 ata_port_freeze(ap);
1286 } else {
1287 if (!pp->ncq_saw_sdb)
1288 ata_port_printk(ap, KERN_INFO,
1289 "spurious SDB FIS %08x:%08x during NCQ, "
1290 "this message won't be printed again\n",
1291 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1292 pp->ncq_saw_sdb = 1;
1293 }
1294 known_irq = 1;
1295 }
1296
1297 if (!known_irq)
1298 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1299 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1300 status, ap->active_tag, ap->sactive);
1301 }
1302
1303 static void ahci_irq_clear(struct ata_port *ap)
1304 {
1305 /* TODO */
1306 }
1307
1308 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1309 {
1310 struct ata_host *host = dev_instance;
1311 struct ahci_host_priv *hpriv;
1312 unsigned int i, handled = 0;
1313 void __iomem *mmio;
1314 u32 irq_stat, irq_ack = 0;
1315
1316 VPRINTK("ENTER\n");
1317
1318 hpriv = host->private_data;
1319 mmio = host->iomap[AHCI_PCI_BAR];
1320
1321 /* sigh. 0xffffffff is a valid return from h/w */
1322 irq_stat = readl(mmio + HOST_IRQ_STAT);
1323 irq_stat &= hpriv->port_map;
1324 if (!irq_stat)
1325 return IRQ_NONE;
1326
1327 spin_lock(&host->lock);
1328
1329 for (i = 0; i < host->n_ports; i++) {
1330 struct ata_port *ap;
1331
1332 if (!(irq_stat & (1 << i)))
1333 continue;
1334
1335 ap = host->ports[i];
1336 if (ap) {
1337 ahci_host_intr(ap);
1338 VPRINTK("port %u\n", i);
1339 } else {
1340 VPRINTK("port %u (no irq)\n", i);
1341 if (ata_ratelimit())
1342 dev_printk(KERN_WARNING, host->dev,
1343 "interrupt on disabled port %u\n", i);
1344 }
1345
1346 irq_ack |= (1 << i);
1347 }
1348
1349 if (irq_ack) {
1350 writel(irq_ack, mmio + HOST_IRQ_STAT);
1351 handled = 1;
1352 }
1353
1354 spin_unlock(&host->lock);
1355
1356 VPRINTK("EXIT\n");
1357
1358 return IRQ_RETVAL(handled);
1359 }
1360
1361 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1362 {
1363 struct ata_port *ap = qc->ap;
1364 void __iomem *port_mmio = ahci_port_base(ap);
1365
1366 if (qc->tf.protocol == ATA_PROT_NCQ)
1367 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1368 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1369 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1370
1371 return 0;
1372 }
1373
1374 static void ahci_freeze(struct ata_port *ap)
1375 {
1376 void __iomem *port_mmio = ahci_port_base(ap);
1377
1378 /* turn IRQ off */
1379 writel(0, port_mmio + PORT_IRQ_MASK);
1380 }
1381
1382 static void ahci_thaw(struct ata_port *ap)
1383 {
1384 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1385 void __iomem *port_mmio = ahci_port_base(ap);
1386 u32 tmp;
1387
1388 /* clear IRQ */
1389 tmp = readl(port_mmio + PORT_IRQ_STAT);
1390 writel(tmp, port_mmio + PORT_IRQ_STAT);
1391 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1392
1393 /* turn IRQ back on */
1394 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1395 }
1396
1397 static void ahci_error_handler(struct ata_port *ap)
1398 {
1399 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1400 /* restart engine */
1401 ahci_stop_engine(ap);
1402 ahci_start_engine(ap);
1403 }
1404
1405 /* perform recovery */
1406 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1407 ahci_postreset);
1408 }
1409
1410 static void ahci_vt8251_error_handler(struct ata_port *ap)
1411 {
1412 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1413 /* restart engine */
1414 ahci_stop_engine(ap);
1415 ahci_start_engine(ap);
1416 }
1417
1418 /* perform recovery */
1419 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1420 ahci_postreset);
1421 }
1422
1423 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1424 {
1425 struct ata_port *ap = qc->ap;
1426
1427 if (qc->flags & ATA_QCFLAG_FAILED) {
1428 /* make DMA engine forget about the failed command */
1429 ahci_stop_engine(ap);
1430 ahci_start_engine(ap);
1431 }
1432 }
1433
1434 #ifdef CONFIG_PM
1435 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1436 {
1437 const char *emsg = NULL;
1438 int rc;
1439
1440 rc = ahci_deinit_port(ap, &emsg);
1441 if (rc == 0)
1442 ahci_power_down(ap);
1443 else {
1444 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1445 ahci_init_port(ap);
1446 }
1447
1448 return rc;
1449 }
1450
1451 static int ahci_port_resume(struct ata_port *ap)
1452 {
1453 ahci_power_up(ap);
1454 ahci_init_port(ap);
1455
1456 return 0;
1457 }
1458
1459 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1460 {
1461 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1462 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1463 u32 ctl;
1464
1465 if (mesg.event == PM_EVENT_SUSPEND) {
1466 /* AHCI spec rev1.1 section 8.3.3:
1467 * Software must disable interrupts prior to requesting a
1468 * transition of the HBA to D3 state.
1469 */
1470 ctl = readl(mmio + HOST_CTL);
1471 ctl &= ~HOST_IRQ_EN;
1472 writel(ctl, mmio + HOST_CTL);
1473 readl(mmio + HOST_CTL); /* flush */
1474 }
1475
1476 return ata_pci_device_suspend(pdev, mesg);
1477 }
1478
1479 static int ahci_pci_device_resume(struct pci_dev *pdev)
1480 {
1481 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1482 int rc;
1483
1484 rc = ata_pci_device_do_resume(pdev);
1485 if (rc)
1486 return rc;
1487
1488 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1489 rc = ahci_reset_controller(host);
1490 if (rc)
1491 return rc;
1492
1493 ahci_init_controller(host);
1494 }
1495
1496 ata_host_resume(host);
1497
1498 return 0;
1499 }
1500 #endif
1501
1502 static int ahci_port_start(struct ata_port *ap)
1503 {
1504 struct device *dev = ap->host->dev;
1505 struct ahci_port_priv *pp;
1506 void *mem;
1507 dma_addr_t mem_dma;
1508 int rc;
1509
1510 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1511 if (!pp)
1512 return -ENOMEM;
1513
1514 rc = ata_pad_alloc(ap, dev);
1515 if (rc)
1516 return rc;
1517
1518 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1519 GFP_KERNEL);
1520 if (!mem)
1521 return -ENOMEM;
1522 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1523
1524 /*
1525 * First item in chunk of DMA memory: 32-slot command table,
1526 * 32 bytes each in size
1527 */
1528 pp->cmd_slot = mem;
1529 pp->cmd_slot_dma = mem_dma;
1530
1531 mem += AHCI_CMD_SLOT_SZ;
1532 mem_dma += AHCI_CMD_SLOT_SZ;
1533
1534 /*
1535 * Second item: Received-FIS area
1536 */
1537 pp->rx_fis = mem;
1538 pp->rx_fis_dma = mem_dma;
1539
1540 mem += AHCI_RX_FIS_SZ;
1541 mem_dma += AHCI_RX_FIS_SZ;
1542
1543 /*
1544 * Third item: data area for storing a single command
1545 * and its scatter-gather table
1546 */
1547 pp->cmd_tbl = mem;
1548 pp->cmd_tbl_dma = mem_dma;
1549
1550 ap->private_data = pp;
1551
1552 /* power up port */
1553 ahci_power_up(ap);
1554
1555 /* initialize port */
1556 ahci_init_port(ap);
1557
1558 return 0;
1559 }
1560
1561 static void ahci_port_stop(struct ata_port *ap)
1562 {
1563 const char *emsg = NULL;
1564 int rc;
1565
1566 /* de-initialize port */
1567 rc = ahci_deinit_port(ap, &emsg);
1568 if (rc)
1569 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1570 }
1571
1572 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1573 {
1574 int rc;
1575
1576 if (using_dac &&
1577 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1578 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1579 if (rc) {
1580 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1581 if (rc) {
1582 dev_printk(KERN_ERR, &pdev->dev,
1583 "64-bit DMA enable failed\n");
1584 return rc;
1585 }
1586 }
1587 } else {
1588 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1589 if (rc) {
1590 dev_printk(KERN_ERR, &pdev->dev,
1591 "32-bit DMA enable failed\n");
1592 return rc;
1593 }
1594 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1595 if (rc) {
1596 dev_printk(KERN_ERR, &pdev->dev,
1597 "32-bit consistent DMA enable failed\n");
1598 return rc;
1599 }
1600 }
1601 return 0;
1602 }
1603
1604 static void ahci_print_info(struct ata_host *host)
1605 {
1606 struct ahci_host_priv *hpriv = host->private_data;
1607 struct pci_dev *pdev = to_pci_dev(host->dev);
1608 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1609 u32 vers, cap, impl, speed;
1610 const char *speed_s;
1611 u16 cc;
1612 const char *scc_s;
1613
1614 vers = readl(mmio + HOST_VERSION);
1615 cap = hpriv->cap;
1616 impl = hpriv->port_map;
1617
1618 speed = (cap >> 20) & 0xf;
1619 if (speed == 1)
1620 speed_s = "1.5";
1621 else if (speed == 2)
1622 speed_s = "3";
1623 else
1624 speed_s = "?";
1625
1626 pci_read_config_word(pdev, 0x0a, &cc);
1627 if (cc == PCI_CLASS_STORAGE_IDE)
1628 scc_s = "IDE";
1629 else if (cc == PCI_CLASS_STORAGE_SATA)
1630 scc_s = "SATA";
1631 else if (cc == PCI_CLASS_STORAGE_RAID)
1632 scc_s = "RAID";
1633 else
1634 scc_s = "unknown";
1635
1636 dev_printk(KERN_INFO, &pdev->dev,
1637 "AHCI %02x%02x.%02x%02x "
1638 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1639 ,
1640
1641 (vers >> 24) & 0xff,
1642 (vers >> 16) & 0xff,
1643 (vers >> 8) & 0xff,
1644 vers & 0xff,
1645
1646 ((cap >> 8) & 0x1f) + 1,
1647 (cap & 0x1f) + 1,
1648 speed_s,
1649 impl,
1650 scc_s);
1651
1652 dev_printk(KERN_INFO, &pdev->dev,
1653 "flags: "
1654 "%s%s%s%s%s%s"
1655 "%s%s%s%s%s%s%s\n"
1656 ,
1657
1658 cap & (1 << 31) ? "64bit " : "",
1659 cap & (1 << 30) ? "ncq " : "",
1660 cap & (1 << 28) ? "ilck " : "",
1661 cap & (1 << 27) ? "stag " : "",
1662 cap & (1 << 26) ? "pm " : "",
1663 cap & (1 << 25) ? "led " : "",
1664
1665 cap & (1 << 24) ? "clo " : "",
1666 cap & (1 << 19) ? "nz " : "",
1667 cap & (1 << 18) ? "only " : "",
1668 cap & (1 << 17) ? "pmp " : "",
1669 cap & (1 << 15) ? "pio " : "",
1670 cap & (1 << 14) ? "slum " : "",
1671 cap & (1 << 13) ? "part " : ""
1672 );
1673 }
1674
1675 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1676 {
1677 static int printed_version;
1678 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1679 const struct ata_port_info *ppi[] = { &pi, NULL };
1680 struct device *dev = &pdev->dev;
1681 struct ahci_host_priv *hpriv;
1682 struct ata_host *host;
1683 int i, rc;
1684
1685 VPRINTK("ENTER\n");
1686
1687 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1688
1689 if (!printed_version++)
1690 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1691
1692 /* acquire resources */
1693 rc = pcim_enable_device(pdev);
1694 if (rc)
1695 return rc;
1696
1697 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1698 if (rc == -EBUSY)
1699 pcim_pin_device(pdev);
1700 if (rc)
1701 return rc;
1702
1703 if (pci_enable_msi(pdev))
1704 pci_intx(pdev, 1);
1705
1706 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1707 if (!hpriv)
1708 return -ENOMEM;
1709
1710 /* save initial config */
1711 ahci_save_initial_config(pdev, &pi, hpriv);
1712
1713 /* prepare host */
1714 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1715 pi.flags |= ATA_FLAG_NCQ;
1716
1717 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1718 if (!host)
1719 return -ENOMEM;
1720 host->iomap = pcim_iomap_table(pdev);
1721 host->private_data = hpriv;
1722
1723 for (i = 0; i < host->n_ports; i++) {
1724 if (hpriv->port_map & (1 << i)) {
1725 struct ata_port *ap = host->ports[i];
1726 void __iomem *port_mmio = ahci_port_base(ap);
1727
1728 ap->ioaddr.cmd_addr = port_mmio;
1729 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1730 } else
1731 host->ports[i]->ops = &ata_dummy_port_ops;
1732 }
1733
1734 /* initialize adapter */
1735 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1736 if (rc)
1737 return rc;
1738
1739 rc = ahci_reset_controller(host);
1740 if (rc)
1741 return rc;
1742
1743 ahci_init_controller(host);
1744 ahci_print_info(host);
1745
1746 pci_set_master(pdev);
1747 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1748 &ahci_sht);
1749 }
1750
1751 static int __init ahci_init(void)
1752 {
1753 return pci_register_driver(&ahci_pci_driver);
1754 }
1755
1756 static void __exit ahci_exit(void)
1757 {
1758 pci_unregister_driver(&ahci_pci_driver);
1759 }
1760
1761
1762 MODULE_AUTHOR("Jeff Garzik");
1763 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1764 MODULE_LICENSE("GPL");
1765 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1766 MODULE_VERSION(DRV_VERSION);
1767
1768 module_init(ahci_init);
1769 module_exit(ahci_exit);
Linux kernel - Deliverables
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