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ahci/pata_jmicron: match class not function number
[deliverable/linux.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.1"
50
51
52 enum {
53 AHCI_PCI_BAR = 5,
54 AHCI_MAX_PORTS = 32,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_MAX_CMDS = 32,
59 AHCI_CMD_SZ = 32,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
61 AHCI_RX_FIS_SZ = 256,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
67 AHCI_RX_FIS_SZ,
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 board_ahci = 0,
80 board_ahci_pi = 1,
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
83
84 /* global controller registers */
85 HOST_CAP = 0x00, /* host capabilities */
86 HOST_CTL = 0x04, /* global host control */
87 HOST_IRQ_STAT = 0x08, /* interrupt status */
88 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
89 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
90
91 /* HOST_CTL bits */
92 HOST_RESET = (1 << 0), /* reset controller; self-clear */
93 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
94 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
95
96 /* HOST_CAP bits */
97 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
98 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
99 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
100 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
101 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
102
103 /* registers for each SATA port */
104 PORT_LST_ADDR = 0x00, /* command list DMA addr */
105 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
106 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
107 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
108 PORT_IRQ_STAT = 0x10, /* interrupt status */
109 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
110 PORT_CMD = 0x18, /* port command */
111 PORT_TFDATA = 0x20, /* taskfile data */
112 PORT_SIG = 0x24, /* device TF signature */
113 PORT_CMD_ISSUE = 0x38, /* command issue */
114 PORT_SCR = 0x28, /* SATA phy register block */
115 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
116 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
117 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
118 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
119
120 /* PORT_IRQ_{STAT,MASK} bits */
121 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
122 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
123 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
124 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
125 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
126 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
127 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
128 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
129
130 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
131 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
132 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
133 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
134 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
135 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
136 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
137 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
138 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
139
140 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
141 PORT_IRQ_IF_ERR |
142 PORT_IRQ_CONNECT |
143 PORT_IRQ_PHYRDY |
144 PORT_IRQ_UNK_FIS,
145 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
146 PORT_IRQ_TF_ERR |
147 PORT_IRQ_HBUS_DATA_ERR,
148 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
149 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
150 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
151
152 /* PORT_CMD bits */
153 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
154 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
155 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
156 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
157 PORT_CMD_CLO = (1 << 3), /* Command list override */
158 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
159 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
160 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
161
162 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
163 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
164 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
165 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
166
167 /* ap->flags bits */
168 AHCI_FLAG_NO_NCQ = (1 << 24),
169 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
170 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
171 };
172
173 struct ahci_cmd_hdr {
174 u32 opts;
175 u32 status;
176 u32 tbl_addr;
177 u32 tbl_addr_hi;
178 u32 reserved[4];
179 };
180
181 struct ahci_sg {
182 u32 addr;
183 u32 addr_hi;
184 u32 reserved;
185 u32 flags_size;
186 };
187
188 struct ahci_host_priv {
189 u32 cap; /* cache of HOST_CAP register */
190 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
191 };
192
193 struct ahci_port_priv {
194 struct ahci_cmd_hdr *cmd_slot;
195 dma_addr_t cmd_slot_dma;
196 void *cmd_tbl;
197 dma_addr_t cmd_tbl_dma;
198 void *rx_fis;
199 dma_addr_t rx_fis_dma;
200 /* for NCQ spurious interrupt analysis */
201 unsigned int ncq_saw_d2h:1;
202 unsigned int ncq_saw_dmas:1;
203 };
204
205 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
206 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
207 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
208 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
209 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
210 static void ahci_irq_clear(struct ata_port *ap);
211 static int ahci_port_start(struct ata_port *ap);
212 static void ahci_port_stop(struct ata_port *ap);
213 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
214 static void ahci_qc_prep(struct ata_queued_cmd *qc);
215 static u8 ahci_check_status(struct ata_port *ap);
216 static void ahci_freeze(struct ata_port *ap);
217 static void ahci_thaw(struct ata_port *ap);
218 static void ahci_error_handler(struct ata_port *ap);
219 static void ahci_vt8251_error_handler(struct ata_port *ap);
220 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
221 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
222 static int ahci_port_resume(struct ata_port *ap);
223 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
224 static int ahci_pci_device_resume(struct pci_dev *pdev);
225
226 static struct scsi_host_template ahci_sht = {
227 .module = THIS_MODULE,
228 .name = DRV_NAME,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
231 .change_queue_depth = ata_scsi_change_queue_depth,
232 .can_queue = AHCI_MAX_CMDS - 1,
233 .this_id = ATA_SHT_THIS_ID,
234 .sg_tablesize = AHCI_MAX_SG,
235 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
236 .emulated = ATA_SHT_EMULATED,
237 .use_clustering = AHCI_USE_CLUSTERING,
238 .proc_name = DRV_NAME,
239 .dma_boundary = AHCI_DMA_BOUNDARY,
240 .slave_configure = ata_scsi_slave_config,
241 .slave_destroy = ata_scsi_slave_destroy,
242 .bios_param = ata_std_bios_param,
243 .suspend = ata_scsi_device_suspend,
244 .resume = ata_scsi_device_resume,
245 };
246
247 static const struct ata_port_operations ahci_ops = {
248 .port_disable = ata_port_disable,
249
250 .check_status = ahci_check_status,
251 .check_altstatus = ahci_check_status,
252 .dev_select = ata_noop_dev_select,
253
254 .tf_read = ahci_tf_read,
255
256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
258
259 .irq_handler = ahci_interrupt,
260 .irq_clear = ahci_irq_clear,
261 .irq_on = ata_dummy_irq_on,
262 .irq_ack = ata_dummy_irq_ack,
263
264 .scr_read = ahci_scr_read,
265 .scr_write = ahci_scr_write,
266
267 .freeze = ahci_freeze,
268 .thaw = ahci_thaw,
269
270 .error_handler = ahci_error_handler,
271 .post_internal_cmd = ahci_post_internal_cmd,
272
273 .port_suspend = ahci_port_suspend,
274 .port_resume = ahci_port_resume,
275
276 .port_start = ahci_port_start,
277 .port_stop = ahci_port_stop,
278 };
279
280 static const struct ata_port_operations ahci_vt8251_ops = {
281 .port_disable = ata_port_disable,
282
283 .check_status = ahci_check_status,
284 .check_altstatus = ahci_check_status,
285 .dev_select = ata_noop_dev_select,
286
287 .tf_read = ahci_tf_read,
288
289 .qc_prep = ahci_qc_prep,
290 .qc_issue = ahci_qc_issue,
291
292 .irq_handler = ahci_interrupt,
293 .irq_clear = ahci_irq_clear,
294 .irq_on = ata_dummy_irq_on,
295 .irq_ack = ata_dummy_irq_ack,
296
297 .scr_read = ahci_scr_read,
298 .scr_write = ahci_scr_write,
299
300 .freeze = ahci_freeze,
301 .thaw = ahci_thaw,
302
303 .error_handler = ahci_vt8251_error_handler,
304 .post_internal_cmd = ahci_post_internal_cmd,
305
306 .port_suspend = ahci_port_suspend,
307 .port_resume = ahci_port_resume,
308
309 .port_start = ahci_port_start,
310 .port_stop = ahci_port_stop,
311 };
312
313 static const struct ata_port_info ahci_port_info[] = {
314 /* board_ahci */
315 {
316 .sht = &ahci_sht,
317 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
318 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
319 ATA_FLAG_SKIP_D2H_BSY,
320 .pio_mask = 0x1f, /* pio0-4 */
321 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
322 .port_ops = &ahci_ops,
323 },
324 /* board_ahci_pi */
325 {
326 .sht = &ahci_sht,
327 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
328 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
329 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
330 .pio_mask = 0x1f, /* pio0-4 */
331 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
332 .port_ops = &ahci_ops,
333 },
334 /* board_ahci_vt8251 */
335 {
336 .sht = &ahci_sht,
337 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
338 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
339 ATA_FLAG_SKIP_D2H_BSY |
340 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
341 .pio_mask = 0x1f, /* pio0-4 */
342 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
343 .port_ops = &ahci_vt8251_ops,
344 },
345 /* board_ahci_ign_iferr */
346 {
347 .sht = &ahci_sht,
348 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
349 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
350 ATA_FLAG_SKIP_D2H_BSY |
351 AHCI_FLAG_IGN_IRQ_IF_ERR,
352 .pio_mask = 0x1f, /* pio0-4 */
353 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
354 .port_ops = &ahci_ops,
355 },
356 };
357
358 static const struct pci_device_id ahci_pci_tbl[] = {
359 /* Intel */
360 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
361 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
362 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
363 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
364 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
365 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
366 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
367 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
368 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
369 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
370 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
371 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
372 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
373 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
374 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
375 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
376 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
377 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
378 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
379 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
380 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
381 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
382 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
383 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
384 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
385 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
386
387 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
388 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
389 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
390
391 /* ATI */
392 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
393 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
394
395 /* VIA */
396 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
397
398 /* NVIDIA */
399 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
400 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
401 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
402 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
403 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
404 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
405 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
406 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
407 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
408 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
409 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
410 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
411 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
412 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
413 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
414 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
415 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
416 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
419
420 /* SiS */
421 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
422 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
423 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
424
425 /* Generic, PCI class code for AHCI */
426 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
427 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
428
429 { } /* terminate list */
430 };
431
432
433 static struct pci_driver ahci_pci_driver = {
434 .name = DRV_NAME,
435 .id_table = ahci_pci_tbl,
436 .probe = ahci_init_one,
437 .remove = ata_pci_remove_one,
438 .suspend = ahci_pci_device_suspend,
439 .resume = ahci_pci_device_resume,
440 };
441
442
443 static inline int ahci_nr_ports(u32 cap)
444 {
445 return (cap & 0x1f) + 1;
446 }
447
448 static inline void __iomem *ahci_port_base(void __iomem *base,
449 unsigned int port)
450 {
451 return base + 0x100 + (port * 0x80);
452 }
453
454 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
455 {
456 unsigned int sc_reg;
457
458 switch (sc_reg_in) {
459 case SCR_STATUS: sc_reg = 0; break;
460 case SCR_CONTROL: sc_reg = 1; break;
461 case SCR_ERROR: sc_reg = 2; break;
462 case SCR_ACTIVE: sc_reg = 3; break;
463 default:
464 return 0xffffffffU;
465 }
466
467 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
468 }
469
470
471 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
472 u32 val)
473 {
474 unsigned int sc_reg;
475
476 switch (sc_reg_in) {
477 case SCR_STATUS: sc_reg = 0; break;
478 case SCR_CONTROL: sc_reg = 1; break;
479 case SCR_ERROR: sc_reg = 2; break;
480 case SCR_ACTIVE: sc_reg = 3; break;
481 default:
482 return;
483 }
484
485 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
486 }
487
488 static void ahci_start_engine(void __iomem *port_mmio)
489 {
490 u32 tmp;
491
492 /* start DMA */
493 tmp = readl(port_mmio + PORT_CMD);
494 tmp |= PORT_CMD_START;
495 writel(tmp, port_mmio + PORT_CMD);
496 readl(port_mmio + PORT_CMD); /* flush */
497 }
498
499 static int ahci_stop_engine(void __iomem *port_mmio)
500 {
501 u32 tmp;
502
503 tmp = readl(port_mmio + PORT_CMD);
504
505 /* check if the HBA is idle */
506 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
507 return 0;
508
509 /* setting HBA to idle */
510 tmp &= ~PORT_CMD_START;
511 writel(tmp, port_mmio + PORT_CMD);
512
513 /* wait for engine to stop. This could be as long as 500 msec */
514 tmp = ata_wait_register(port_mmio + PORT_CMD,
515 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
516 if (tmp & PORT_CMD_LIST_ON)
517 return -EIO;
518
519 return 0;
520 }
521
522 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
523 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
524 {
525 u32 tmp;
526
527 /* set FIS registers */
528 if (cap & HOST_CAP_64)
529 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
530 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
531
532 if (cap & HOST_CAP_64)
533 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
534 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
535
536 /* enable FIS reception */
537 tmp = readl(port_mmio + PORT_CMD);
538 tmp |= PORT_CMD_FIS_RX;
539 writel(tmp, port_mmio + PORT_CMD);
540
541 /* flush */
542 readl(port_mmio + PORT_CMD);
543 }
544
545 static int ahci_stop_fis_rx(void __iomem *port_mmio)
546 {
547 u32 tmp;
548
549 /* disable FIS reception */
550 tmp = readl(port_mmio + PORT_CMD);
551 tmp &= ~PORT_CMD_FIS_RX;
552 writel(tmp, port_mmio + PORT_CMD);
553
554 /* wait for completion, spec says 500ms, give it 1000 */
555 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
556 PORT_CMD_FIS_ON, 10, 1000);
557 if (tmp & PORT_CMD_FIS_ON)
558 return -EBUSY;
559
560 return 0;
561 }
562
563 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
564 {
565 u32 cmd;
566
567 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
568
569 /* spin up device */
570 if (cap & HOST_CAP_SSS) {
571 cmd |= PORT_CMD_SPIN_UP;
572 writel(cmd, port_mmio + PORT_CMD);
573 }
574
575 /* wake up link */
576 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
577 }
578
579 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
580 {
581 u32 cmd, scontrol;
582
583 if (!(cap & HOST_CAP_SSS))
584 return;
585
586 /* put device into listen mode, first set PxSCTL.DET to 0 */
587 scontrol = readl(port_mmio + PORT_SCR_CTL);
588 scontrol &= ~0xf;
589 writel(scontrol, port_mmio + PORT_SCR_CTL);
590
591 /* then set PxCMD.SUD to 0 */
592 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
593 cmd &= ~PORT_CMD_SPIN_UP;
594 writel(cmd, port_mmio + PORT_CMD);
595 }
596
597 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
598 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
599 {
600 /* enable FIS reception */
601 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
602
603 /* enable DMA */
604 ahci_start_engine(port_mmio);
605 }
606
607 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
608 {
609 int rc;
610
611 /* disable DMA */
612 rc = ahci_stop_engine(port_mmio);
613 if (rc) {
614 *emsg = "failed to stop engine";
615 return rc;
616 }
617
618 /* disable FIS reception */
619 rc = ahci_stop_fis_rx(port_mmio);
620 if (rc) {
621 *emsg = "failed stop FIS RX";
622 return rc;
623 }
624
625 return 0;
626 }
627
628 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
629 {
630 u32 cap_save, impl_save, tmp;
631
632 cap_save = readl(mmio + HOST_CAP);
633 impl_save = readl(mmio + HOST_PORTS_IMPL);
634
635 /* global controller reset */
636 tmp = readl(mmio + HOST_CTL);
637 if ((tmp & HOST_RESET) == 0) {
638 writel(tmp | HOST_RESET, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
640 }
641
642 /* reset must complete within 1 second, or
643 * the hardware should be considered fried.
644 */
645 ssleep(1);
646
647 tmp = readl(mmio + HOST_CTL);
648 if (tmp & HOST_RESET) {
649 dev_printk(KERN_ERR, &pdev->dev,
650 "controller reset failed (0x%x)\n", tmp);
651 return -EIO;
652 }
653
654 /* turn on AHCI mode */
655 writel(HOST_AHCI_EN, mmio + HOST_CTL);
656 (void) readl(mmio + HOST_CTL); /* flush */
657
658 /* These write-once registers are normally cleared on reset.
659 * Restore BIOS values... which we HOPE were present before
660 * reset.
661 */
662 if (!impl_save) {
663 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
664 dev_printk(KERN_WARNING, &pdev->dev,
665 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
666 }
667 writel(cap_save, mmio + HOST_CAP);
668 writel(impl_save, mmio + HOST_PORTS_IMPL);
669 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
670
671 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
672 u16 tmp16;
673
674 /* configure PCS */
675 pci_read_config_word(pdev, 0x92, &tmp16);
676 tmp16 |= 0xf;
677 pci_write_config_word(pdev, 0x92, tmp16);
678 }
679
680 return 0;
681 }
682
683 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
684 int n_ports, unsigned int port_flags,
685 struct ahci_host_priv *hpriv)
686 {
687 int i, rc;
688 u32 tmp;
689
690 for (i = 0; i < n_ports; i++) {
691 void __iomem *port_mmio = ahci_port_base(mmio, i);
692 const char *emsg = NULL;
693
694 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
695 !(hpriv->port_map & (1 << i)))
696 continue;
697
698 /* make sure port is not active */
699 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
700 if (rc)
701 dev_printk(KERN_WARNING, &pdev->dev,
702 "%s (%d)\n", emsg, rc);
703
704 /* clear SError */
705 tmp = readl(port_mmio + PORT_SCR_ERR);
706 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
707 writel(tmp, port_mmio + PORT_SCR_ERR);
708
709 /* clear port IRQ */
710 tmp = readl(port_mmio + PORT_IRQ_STAT);
711 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
712 if (tmp)
713 writel(tmp, port_mmio + PORT_IRQ_STAT);
714
715 writel(1 << i, mmio + HOST_IRQ_STAT);
716 }
717
718 tmp = readl(mmio + HOST_CTL);
719 VPRINTK("HOST_CTL 0x%x\n", tmp);
720 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
721 tmp = readl(mmio + HOST_CTL);
722 VPRINTK("HOST_CTL 0x%x\n", tmp);
723 }
724
725 static unsigned int ahci_dev_classify(struct ata_port *ap)
726 {
727 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
728 struct ata_taskfile tf;
729 u32 tmp;
730
731 tmp = readl(port_mmio + PORT_SIG);
732 tf.lbah = (tmp >> 24) & 0xff;
733 tf.lbam = (tmp >> 16) & 0xff;
734 tf.lbal = (tmp >> 8) & 0xff;
735 tf.nsect = (tmp) & 0xff;
736
737 return ata_dev_classify(&tf);
738 }
739
740 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
741 u32 opts)
742 {
743 dma_addr_t cmd_tbl_dma;
744
745 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
746
747 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
748 pp->cmd_slot[tag].status = 0;
749 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
750 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
751 }
752
753 static int ahci_clo(struct ata_port *ap)
754 {
755 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 u32 tmp;
758
759 if (!(hpriv->cap & HOST_CAP_CLO))
760 return -EOPNOTSUPP;
761
762 tmp = readl(port_mmio + PORT_CMD);
763 tmp |= PORT_CMD_CLO;
764 writel(tmp, port_mmio + PORT_CMD);
765
766 tmp = ata_wait_register(port_mmio + PORT_CMD,
767 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
768 if (tmp & PORT_CMD_CLO)
769 return -EIO;
770
771 return 0;
772 }
773
774 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
775 {
776 struct ahci_port_priv *pp = ap->private_data;
777 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
778 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
779 const u32 cmd_fis_len = 5; /* five dwords */
780 const char *reason = NULL;
781 struct ata_taskfile tf;
782 u32 tmp;
783 u8 *fis;
784 int rc;
785
786 DPRINTK("ENTER\n");
787
788 if (ata_port_offline(ap)) {
789 DPRINTK("PHY reports no device\n");
790 *class = ATA_DEV_NONE;
791 return 0;
792 }
793
794 /* prepare for SRST (AHCI-1.1 10.4.1) */
795 rc = ahci_stop_engine(port_mmio);
796 if (rc) {
797 reason = "failed to stop engine";
798 goto fail_restart;
799 }
800
801 /* check BUSY/DRQ, perform Command List Override if necessary */
802 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
803 rc = ahci_clo(ap);
804
805 if (rc == -EOPNOTSUPP) {
806 reason = "port busy but CLO unavailable";
807 goto fail_restart;
808 } else if (rc) {
809 reason = "port busy but CLO failed";
810 goto fail_restart;
811 }
812 }
813
814 /* restart engine */
815 ahci_start_engine(port_mmio);
816
817 ata_tf_init(ap->device, &tf);
818 fis = pp->cmd_tbl;
819
820 /* issue the first D2H Register FIS */
821 ahci_fill_cmd_slot(pp, 0,
822 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
823
824 tf.ctl |= ATA_SRST;
825 ata_tf_to_fis(&tf, fis, 0);
826 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
827
828 writel(1, port_mmio + PORT_CMD_ISSUE);
829
830 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
831 if (tmp & 0x1) {
832 rc = -EIO;
833 reason = "1st FIS failed";
834 goto fail;
835 }
836
837 /* spec says at least 5us, but be generous and sleep for 1ms */
838 msleep(1);
839
840 /* issue the second D2H Register FIS */
841 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
842
843 tf.ctl &= ~ATA_SRST;
844 ata_tf_to_fis(&tf, fis, 0);
845 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
846
847 writel(1, port_mmio + PORT_CMD_ISSUE);
848 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
849
850 /* spec mandates ">= 2ms" before checking status.
851 * We wait 150ms, because that was the magic delay used for
852 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
853 * between when the ATA command register is written, and then
854 * status is checked. Because waiting for "a while" before
855 * checking status is fine, post SRST, we perform this magic
856 * delay here as well.
857 */
858 msleep(150);
859
860 *class = ATA_DEV_NONE;
861 if (ata_port_online(ap)) {
862 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
863 rc = -EIO;
864 reason = "device not ready";
865 goto fail;
866 }
867 *class = ahci_dev_classify(ap);
868 }
869
870 DPRINTK("EXIT, class=%u\n", *class);
871 return 0;
872
873 fail_restart:
874 ahci_start_engine(port_mmio);
875 fail:
876 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
877 return rc;
878 }
879
880 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
881 {
882 struct ahci_port_priv *pp = ap->private_data;
883 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
884 struct ata_taskfile tf;
885 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
886 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
887 int rc;
888
889 DPRINTK("ENTER\n");
890
891 ahci_stop_engine(port_mmio);
892
893 /* clear D2H reception area to properly wait for D2H FIS */
894 ata_tf_init(ap->device, &tf);
895 tf.command = 0x80;
896 ata_tf_to_fis(&tf, d2h_fis, 0);
897
898 rc = sata_std_hardreset(ap, class);
899
900 ahci_start_engine(port_mmio);
901
902 if (rc == 0 && ata_port_online(ap))
903 *class = ahci_dev_classify(ap);
904 if (*class == ATA_DEV_UNKNOWN)
905 *class = ATA_DEV_NONE;
906
907 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
908 return rc;
909 }
910
911 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
912 {
913 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
914 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
915 int rc;
916
917 DPRINTK("ENTER\n");
918
919 ahci_stop_engine(port_mmio);
920
921 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
922
923 /* vt8251 needs SError cleared for the port to operate */
924 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
925
926 ahci_start_engine(port_mmio);
927
928 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
929
930 /* vt8251 doesn't clear BSY on signature FIS reception,
931 * request follow-up softreset.
932 */
933 return rc ?: -EAGAIN;
934 }
935
936 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
937 {
938 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
939 u32 new_tmp, tmp;
940
941 ata_std_postreset(ap, class);
942
943 /* Make sure port's ATAPI bit is set appropriately */
944 new_tmp = tmp = readl(port_mmio + PORT_CMD);
945 if (*class == ATA_DEV_ATAPI)
946 new_tmp |= PORT_CMD_ATAPI;
947 else
948 new_tmp &= ~PORT_CMD_ATAPI;
949 if (new_tmp != tmp) {
950 writel(new_tmp, port_mmio + PORT_CMD);
951 readl(port_mmio + PORT_CMD); /* flush */
952 }
953 }
954
955 static u8 ahci_check_status(struct ata_port *ap)
956 {
957 void __iomem *mmio = ap->ioaddr.cmd_addr;
958
959 return readl(mmio + PORT_TFDATA) & 0xFF;
960 }
961
962 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
963 {
964 struct ahci_port_priv *pp = ap->private_data;
965 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
966
967 ata_tf_from_fis(d2h_fis, tf);
968 }
969
970 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
971 {
972 struct scatterlist *sg;
973 struct ahci_sg *ahci_sg;
974 unsigned int n_sg = 0;
975
976 VPRINTK("ENTER\n");
977
978 /*
979 * Next, the S/G list.
980 */
981 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
982 ata_for_each_sg(sg, qc) {
983 dma_addr_t addr = sg_dma_address(sg);
984 u32 sg_len = sg_dma_len(sg);
985
986 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
987 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
988 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
989
990 ahci_sg++;
991 n_sg++;
992 }
993
994 return n_sg;
995 }
996
997 static void ahci_qc_prep(struct ata_queued_cmd *qc)
998 {
999 struct ata_port *ap = qc->ap;
1000 struct ahci_port_priv *pp = ap->private_data;
1001 int is_atapi = is_atapi_taskfile(&qc->tf);
1002 void *cmd_tbl;
1003 u32 opts;
1004 const u32 cmd_fis_len = 5; /* five dwords */
1005 unsigned int n_elem;
1006
1007 /*
1008 * Fill in command table information. First, the header,
1009 * a SATA Register - Host to Device command FIS.
1010 */
1011 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1012
1013 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1014 if (is_atapi) {
1015 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1016 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1017 }
1018
1019 n_elem = 0;
1020 if (qc->flags & ATA_QCFLAG_DMAMAP)
1021 n_elem = ahci_fill_sg(qc, cmd_tbl);
1022
1023 /*
1024 * Fill in command slot information.
1025 */
1026 opts = cmd_fis_len | n_elem << 16;
1027 if (qc->tf.flags & ATA_TFLAG_WRITE)
1028 opts |= AHCI_CMD_WRITE;
1029 if (is_atapi)
1030 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1031
1032 ahci_fill_cmd_slot(pp, qc->tag, opts);
1033 }
1034
1035 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1036 {
1037 struct ahci_port_priv *pp = ap->private_data;
1038 struct ata_eh_info *ehi = &ap->eh_info;
1039 unsigned int err_mask = 0, action = 0;
1040 struct ata_queued_cmd *qc;
1041 u32 serror;
1042
1043 ata_ehi_clear_desc(ehi);
1044
1045 /* AHCI needs SError cleared; otherwise, it might lock up */
1046 serror = ahci_scr_read(ap, SCR_ERROR);
1047 ahci_scr_write(ap, SCR_ERROR, serror);
1048
1049 /* analyze @irq_stat */
1050 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1051
1052 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1053 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1054 irq_stat &= ~PORT_IRQ_IF_ERR;
1055
1056 if (irq_stat & PORT_IRQ_TF_ERR)
1057 err_mask |= AC_ERR_DEV;
1058
1059 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1060 err_mask |= AC_ERR_HOST_BUS;
1061 action |= ATA_EH_SOFTRESET;
1062 }
1063
1064 if (irq_stat & PORT_IRQ_IF_ERR) {
1065 err_mask |= AC_ERR_ATA_BUS;
1066 action |= ATA_EH_SOFTRESET;
1067 ata_ehi_push_desc(ehi, ", interface fatal error");
1068 }
1069
1070 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1071 ata_ehi_hotplugged(ehi);
1072 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1073 "connection status changed" : "PHY RDY changed");
1074 }
1075
1076 if (irq_stat & PORT_IRQ_UNK_FIS) {
1077 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1078
1079 err_mask |= AC_ERR_HSM;
1080 action |= ATA_EH_SOFTRESET;
1081 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1082 unk[0], unk[1], unk[2], unk[3]);
1083 }
1084
1085 /* okay, let's hand over to EH */
1086 ehi->serror |= serror;
1087 ehi->action |= action;
1088
1089 qc = ata_qc_from_tag(ap, ap->active_tag);
1090 if (qc)
1091 qc->err_mask |= err_mask;
1092 else
1093 ehi->err_mask |= err_mask;
1094
1095 if (irq_stat & PORT_IRQ_FREEZE)
1096 ata_port_freeze(ap);
1097 else
1098 ata_port_abort(ap);
1099 }
1100
1101 static void ahci_host_intr(struct ata_port *ap)
1102 {
1103 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1104 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1105 struct ata_eh_info *ehi = &ap->eh_info;
1106 struct ahci_port_priv *pp = ap->private_data;
1107 u32 status, qc_active;
1108 int rc, known_irq = 0;
1109
1110 status = readl(port_mmio + PORT_IRQ_STAT);
1111 writel(status, port_mmio + PORT_IRQ_STAT);
1112
1113 if (unlikely(status & PORT_IRQ_ERROR)) {
1114 ahci_error_intr(ap, status);
1115 return;
1116 }
1117
1118 if (ap->sactive)
1119 qc_active = readl(port_mmio + PORT_SCR_ACT);
1120 else
1121 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1122
1123 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1124 if (rc > 0)
1125 return;
1126 if (rc < 0) {
1127 ehi->err_mask |= AC_ERR_HSM;
1128 ehi->action |= ATA_EH_SOFTRESET;
1129 ata_port_freeze(ap);
1130 return;
1131 }
1132
1133 /* hmmm... a spurious interupt */
1134
1135 /* if !NCQ, ignore. No modern ATA device has broken HSM
1136 * implementation for non-NCQ commands.
1137 */
1138 if (!ap->sactive)
1139 return;
1140
1141 if (status & PORT_IRQ_D2H_REG_FIS) {
1142 if (!pp->ncq_saw_d2h)
1143 ata_port_printk(ap, KERN_INFO,
1144 "D2H reg with I during NCQ, "
1145 "this message won't be printed again\n");
1146 pp->ncq_saw_d2h = 1;
1147 known_irq = 1;
1148 }
1149
1150 if (status & PORT_IRQ_DMAS_FIS) {
1151 if (!pp->ncq_saw_dmas)
1152 ata_port_printk(ap, KERN_INFO,
1153 "DMAS FIS during NCQ, "
1154 "this message won't be printed again\n");
1155 pp->ncq_saw_dmas = 1;
1156 known_irq = 1;
1157 }
1158
1159 if (status & PORT_IRQ_SDB_FIS) {
1160 /* SDB FIS containing spurious completions might be
1161 * dangerous, whine and fail commands with HSM
1162 * violation. EH will turn off NCQ after several such
1163 * failures.
1164 */
1165 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1166
1167 ata_ehi_push_desc(ehi, "spurious completion during NCQ "
1168 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1169 readl(port_mmio + PORT_CMD_ISSUE),
1170 readl(port_mmio + PORT_SCR_ACT),
1171 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1172
1173 ehi->err_mask |= AC_ERR_HSM;
1174 ehi->action |= ATA_EH_SOFTRESET;
1175 ata_port_freeze(ap);
1176
1177 known_irq = 1;
1178 }
1179
1180 if (!known_irq)
1181 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1182 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1183 status, ap->active_tag, ap->sactive);
1184 }
1185
1186 static void ahci_irq_clear(struct ata_port *ap)
1187 {
1188 /* TODO */
1189 }
1190
1191 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1192 {
1193 struct ata_host *host = dev_instance;
1194 struct ahci_host_priv *hpriv;
1195 unsigned int i, handled = 0;
1196 void __iomem *mmio;
1197 u32 irq_stat, irq_ack = 0;
1198
1199 VPRINTK("ENTER\n");
1200
1201 hpriv = host->private_data;
1202 mmio = host->iomap[AHCI_PCI_BAR];
1203
1204 /* sigh. 0xffffffff is a valid return from h/w */
1205 irq_stat = readl(mmio + HOST_IRQ_STAT);
1206 irq_stat &= hpriv->port_map;
1207 if (!irq_stat)
1208 return IRQ_NONE;
1209
1210 spin_lock(&host->lock);
1211
1212 for (i = 0; i < host->n_ports; i++) {
1213 struct ata_port *ap;
1214
1215 if (!(irq_stat & (1 << i)))
1216 continue;
1217
1218 ap = host->ports[i];
1219 if (ap) {
1220 ahci_host_intr(ap);
1221 VPRINTK("port %u\n", i);
1222 } else {
1223 VPRINTK("port %u (no irq)\n", i);
1224 if (ata_ratelimit())
1225 dev_printk(KERN_WARNING, host->dev,
1226 "interrupt on disabled port %u\n", i);
1227 }
1228
1229 irq_ack |= (1 << i);
1230 }
1231
1232 if (irq_ack) {
1233 writel(irq_ack, mmio + HOST_IRQ_STAT);
1234 handled = 1;
1235 }
1236
1237 spin_unlock(&host->lock);
1238
1239 VPRINTK("EXIT\n");
1240
1241 return IRQ_RETVAL(handled);
1242 }
1243
1244 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1245 {
1246 struct ata_port *ap = qc->ap;
1247 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1248
1249 if (qc->tf.protocol == ATA_PROT_NCQ)
1250 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1251 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1252 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1253
1254 return 0;
1255 }
1256
1257 static void ahci_freeze(struct ata_port *ap)
1258 {
1259 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1260 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1261
1262 /* turn IRQ off */
1263 writel(0, port_mmio + PORT_IRQ_MASK);
1264 }
1265
1266 static void ahci_thaw(struct ata_port *ap)
1267 {
1268 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1269 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1270 u32 tmp;
1271
1272 /* clear IRQ */
1273 tmp = readl(port_mmio + PORT_IRQ_STAT);
1274 writel(tmp, port_mmio + PORT_IRQ_STAT);
1275 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1276
1277 /* turn IRQ back on */
1278 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1279 }
1280
1281 static void ahci_error_handler(struct ata_port *ap)
1282 {
1283 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1284 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1285
1286 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1287 /* restart engine */
1288 ahci_stop_engine(port_mmio);
1289 ahci_start_engine(port_mmio);
1290 }
1291
1292 /* perform recovery */
1293 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1294 ahci_postreset);
1295 }
1296
1297 static void ahci_vt8251_error_handler(struct ata_port *ap)
1298 {
1299 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1300 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1301
1302 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1303 /* restart engine */
1304 ahci_stop_engine(port_mmio);
1305 ahci_start_engine(port_mmio);
1306 }
1307
1308 /* perform recovery */
1309 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1310 ahci_postreset);
1311 }
1312
1313 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1314 {
1315 struct ata_port *ap = qc->ap;
1316 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1317 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1318
1319 if (qc->flags & ATA_QCFLAG_FAILED)
1320 qc->err_mask |= AC_ERR_OTHER;
1321
1322 if (qc->err_mask) {
1323 /* make DMA engine forget about the failed command */
1324 ahci_stop_engine(port_mmio);
1325 ahci_start_engine(port_mmio);
1326 }
1327 }
1328
1329 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1330 {
1331 struct ahci_host_priv *hpriv = ap->host->private_data;
1332 struct ahci_port_priv *pp = ap->private_data;
1333 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1334 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1335 const char *emsg = NULL;
1336 int rc;
1337
1338 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1339 if (rc == 0)
1340 ahci_power_down(port_mmio, hpriv->cap);
1341 else {
1342 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1343 ahci_init_port(port_mmio, hpriv->cap,
1344 pp->cmd_slot_dma, pp->rx_fis_dma);
1345 }
1346
1347 return rc;
1348 }
1349
1350 static int ahci_port_resume(struct ata_port *ap)
1351 {
1352 struct ahci_port_priv *pp = ap->private_data;
1353 struct ahci_host_priv *hpriv = ap->host->private_data;
1354 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1355 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1356
1357 ahci_power_up(port_mmio, hpriv->cap);
1358 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1359
1360 return 0;
1361 }
1362
1363 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1364 {
1365 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1366 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1367 u32 ctl;
1368
1369 if (mesg.event == PM_EVENT_SUSPEND) {
1370 /* AHCI spec rev1.1 section 8.3.3:
1371 * Software must disable interrupts prior to requesting a
1372 * transition of the HBA to D3 state.
1373 */
1374 ctl = readl(mmio + HOST_CTL);
1375 ctl &= ~HOST_IRQ_EN;
1376 writel(ctl, mmio + HOST_CTL);
1377 readl(mmio + HOST_CTL); /* flush */
1378 }
1379
1380 return ata_pci_device_suspend(pdev, mesg);
1381 }
1382
1383 static int ahci_pci_device_resume(struct pci_dev *pdev)
1384 {
1385 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1386 struct ahci_host_priv *hpriv = host->private_data;
1387 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1388 int rc;
1389
1390 rc = ata_pci_device_do_resume(pdev);
1391 if (rc)
1392 return rc;
1393
1394 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1395 rc = ahci_reset_controller(mmio, pdev);
1396 if (rc)
1397 return rc;
1398
1399 ahci_init_controller(mmio, pdev, host->n_ports,
1400 host->ports[0]->flags, hpriv);
1401 }
1402
1403 ata_host_resume(host);
1404
1405 return 0;
1406 }
1407
1408 static int ahci_port_start(struct ata_port *ap)
1409 {
1410 struct device *dev = ap->host->dev;
1411 struct ahci_host_priv *hpriv = ap->host->private_data;
1412 struct ahci_port_priv *pp;
1413 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1414 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1415 void *mem;
1416 dma_addr_t mem_dma;
1417 int rc;
1418
1419 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1420 if (!pp)
1421 return -ENOMEM;
1422
1423 rc = ata_pad_alloc(ap, dev);
1424 if (rc)
1425 return rc;
1426
1427 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1428 GFP_KERNEL);
1429 if (!mem)
1430 return -ENOMEM;
1431 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1432
1433 /*
1434 * First item in chunk of DMA memory: 32-slot command table,
1435 * 32 bytes each in size
1436 */
1437 pp->cmd_slot = mem;
1438 pp->cmd_slot_dma = mem_dma;
1439
1440 mem += AHCI_CMD_SLOT_SZ;
1441 mem_dma += AHCI_CMD_SLOT_SZ;
1442
1443 /*
1444 * Second item: Received-FIS area
1445 */
1446 pp->rx_fis = mem;
1447 pp->rx_fis_dma = mem_dma;
1448
1449 mem += AHCI_RX_FIS_SZ;
1450 mem_dma += AHCI_RX_FIS_SZ;
1451
1452 /*
1453 * Third item: data area for storing a single command
1454 * and its scatter-gather table
1455 */
1456 pp->cmd_tbl = mem;
1457 pp->cmd_tbl_dma = mem_dma;
1458
1459 ap->private_data = pp;
1460
1461 /* power up port */
1462 ahci_power_up(port_mmio, hpriv->cap);
1463
1464 /* initialize port */
1465 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1466
1467 return 0;
1468 }
1469
1470 static void ahci_port_stop(struct ata_port *ap)
1471 {
1472 struct ahci_host_priv *hpriv = ap->host->private_data;
1473 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1474 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1475 const char *emsg = NULL;
1476 int rc;
1477
1478 /* de-initialize port */
1479 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1480 if (rc)
1481 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1482 }
1483
1484 static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1485 unsigned int port_idx)
1486 {
1487 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1488 base = ahci_port_base(base, port_idx);
1489 VPRINTK("base now==0x%lx\n", base);
1490
1491 port->cmd_addr = base;
1492 port->scr_addr = base + PORT_SCR;
1493
1494 VPRINTK("EXIT\n");
1495 }
1496
1497 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1498 {
1499 struct ahci_host_priv *hpriv = probe_ent->private_data;
1500 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1501 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1502 unsigned int i, cap_n_ports, using_dac;
1503 int rc;
1504
1505 rc = ahci_reset_controller(mmio, pdev);
1506 if (rc)
1507 return rc;
1508
1509 hpriv->cap = readl(mmio + HOST_CAP);
1510 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1511 cap_n_ports = ahci_nr_ports(hpriv->cap);
1512
1513 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1514 hpriv->cap, hpriv->port_map, cap_n_ports);
1515
1516 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1517 unsigned int n_ports = cap_n_ports;
1518 u32 port_map = hpriv->port_map;
1519 int max_port = 0;
1520
1521 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1522 if (port_map & (1 << i)) {
1523 n_ports--;
1524 port_map &= ~(1 << i);
1525 max_port = i;
1526 } else
1527 probe_ent->dummy_port_mask |= 1 << i;
1528 }
1529
1530 if (n_ports || port_map)
1531 dev_printk(KERN_WARNING, &pdev->dev,
1532 "nr_ports (%u) and implemented port map "
1533 "(0x%x) don't match\n",
1534 cap_n_ports, hpriv->port_map);
1535
1536 probe_ent->n_ports = max_port + 1;
1537 } else
1538 probe_ent->n_ports = cap_n_ports;
1539
1540 using_dac = hpriv->cap & HOST_CAP_64;
1541 if (using_dac &&
1542 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1543 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1544 if (rc) {
1545 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1546 if (rc) {
1547 dev_printk(KERN_ERR, &pdev->dev,
1548 "64-bit DMA enable failed\n");
1549 return rc;
1550 }
1551 }
1552 } else {
1553 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1554 if (rc) {
1555 dev_printk(KERN_ERR, &pdev->dev,
1556 "32-bit DMA enable failed\n");
1557 return rc;
1558 }
1559 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1560 if (rc) {
1561 dev_printk(KERN_ERR, &pdev->dev,
1562 "32-bit consistent DMA enable failed\n");
1563 return rc;
1564 }
1565 }
1566
1567 for (i = 0; i < probe_ent->n_ports; i++)
1568 ahci_setup_port(&probe_ent->port[i], mmio, i);
1569
1570 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1571 probe_ent->port_flags, hpriv);
1572
1573 pci_set_master(pdev);
1574
1575 return 0;
1576 }
1577
1578 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1579 {
1580 struct ahci_host_priv *hpriv = probe_ent->private_data;
1581 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1582 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1583 u32 vers, cap, impl, speed;
1584 const char *speed_s;
1585 u16 cc;
1586 const char *scc_s;
1587
1588 vers = readl(mmio + HOST_VERSION);
1589 cap = hpriv->cap;
1590 impl = hpriv->port_map;
1591
1592 speed = (cap >> 20) & 0xf;
1593 if (speed == 1)
1594 speed_s = "1.5";
1595 else if (speed == 2)
1596 speed_s = "3";
1597 else
1598 speed_s = "?";
1599
1600 pci_read_config_word(pdev, 0x0a, &cc);
1601 if (cc == PCI_CLASS_STORAGE_IDE)
1602 scc_s = "IDE";
1603 else if (cc == PCI_CLASS_STORAGE_SATA)
1604 scc_s = "SATA";
1605 else if (cc == PCI_CLASS_STORAGE_RAID)
1606 scc_s = "RAID";
1607 else
1608 scc_s = "unknown";
1609
1610 dev_printk(KERN_INFO, &pdev->dev,
1611 "AHCI %02x%02x.%02x%02x "
1612 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1613 ,
1614
1615 (vers >> 24) & 0xff,
1616 (vers >> 16) & 0xff,
1617 (vers >> 8) & 0xff,
1618 vers & 0xff,
1619
1620 ((cap >> 8) & 0x1f) + 1,
1621 (cap & 0x1f) + 1,
1622 speed_s,
1623 impl,
1624 scc_s);
1625
1626 dev_printk(KERN_INFO, &pdev->dev,
1627 "flags: "
1628 "%s%s%s%s%s%s"
1629 "%s%s%s%s%s%s%s\n"
1630 ,
1631
1632 cap & (1 << 31) ? "64bit " : "",
1633 cap & (1 << 30) ? "ncq " : "",
1634 cap & (1 << 28) ? "ilck " : "",
1635 cap & (1 << 27) ? "stag " : "",
1636 cap & (1 << 26) ? "pm " : "",
1637 cap & (1 << 25) ? "led " : "",
1638
1639 cap & (1 << 24) ? "clo " : "",
1640 cap & (1 << 19) ? "nz " : "",
1641 cap & (1 << 18) ? "only " : "",
1642 cap & (1 << 17) ? "pmp " : "",
1643 cap & (1 << 15) ? "pio " : "",
1644 cap & (1 << 14) ? "slum " : "",
1645 cap & (1 << 13) ? "part " : ""
1646 );
1647 }
1648
1649 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1650 {
1651 static int printed_version;
1652 unsigned int board_idx = (unsigned int) ent->driver_data;
1653 struct device *dev = &pdev->dev;
1654 struct ata_probe_ent *probe_ent;
1655 struct ahci_host_priv *hpriv;
1656 int rc;
1657
1658 VPRINTK("ENTER\n");
1659
1660 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1661
1662 if (!printed_version++)
1663 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1664
1665 rc = pcim_enable_device(pdev);
1666 if (rc)
1667 return rc;
1668
1669 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1670 if (rc == -EBUSY)
1671 pcim_pin_device(pdev);
1672 if (rc)
1673 return rc;
1674
1675 if (pci_enable_msi(pdev))
1676 pci_intx(pdev, 1);
1677
1678 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1679 if (probe_ent == NULL)
1680 return -ENOMEM;
1681
1682 probe_ent->dev = pci_dev_to_dev(pdev);
1683 INIT_LIST_HEAD(&probe_ent->node);
1684
1685 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1686 if (!hpriv)
1687 return -ENOMEM;
1688
1689 probe_ent->sht = ahci_port_info[board_idx].sht;
1690 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1691 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1692 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1693 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1694
1695 probe_ent->irq = pdev->irq;
1696 probe_ent->irq_flags = IRQF_SHARED;
1697 probe_ent->iomap = pcim_iomap_table(pdev);
1698 probe_ent->private_data = hpriv;
1699
1700 /* initialize adapter */
1701 rc = ahci_host_init(probe_ent);
1702 if (rc)
1703 return rc;
1704
1705 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1706 (hpriv->cap & HOST_CAP_NCQ))
1707 probe_ent->port_flags |= ATA_FLAG_NCQ;
1708
1709 ahci_print_info(probe_ent);
1710
1711 if (!ata_device_add(probe_ent))
1712 return -ENODEV;
1713
1714 devm_kfree(dev, probe_ent);
1715 return 0;
1716 }
1717
1718 static int __init ahci_init(void)
1719 {
1720 return pci_register_driver(&ahci_pci_driver);
1721 }
1722
1723 static void __exit ahci_exit(void)
1724 {
1725 pci_unregister_driver(&ahci_pci_driver);
1726 }
1727
1728
1729 MODULE_AUTHOR("Jeff Garzik");
1730 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1731 MODULE_LICENSE("GPL");
1732 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1733 MODULE_VERSION(DRV_VERSION);
1734
1735 module_init(ahci_init);
1736 module_exit(ahci_exit);
Linux kernel - Deliverables
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