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libata: reimplement suspend/resume support using sdev->manage_start_stop
[deliverable/linux.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.11"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
107
108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
110
111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
120 /* controller IDs */
121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
132
133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
142 PIIX_AHCI_DEVICE = 6,
143 };
144
145 struct piix_map_db {
146 const u32 mask;
147 const u16 port_enable;
148 const int map[][4];
149 };
150
151 struct piix_host_priv {
152 const int *map;
153 };
154
155 static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
157 static void piix_pata_error_handler(struct ata_port *ap);
158 static void piix_sata_error_handler(struct ata_port *ap);
159 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
160 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
161 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
162 static int ich_pata_cable_detect(struct ata_port *ap);
163
164 static unsigned int in_module_init = 1;
165
166 static const struct pci_device_id piix_pci_tbl[] = {
167 /* Intel PIIX3 for the 430HX etc */
168 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
169 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
170 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
171 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
172 /* Intel PIIX4 */
173 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
174 /* Intel PIIX4 */
175 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
176 /* Intel PIIX */
177 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
178 /* Intel ICH (i810, i815, i840) UDMA 66*/
179 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
180 /* Intel ICH0 : UDMA 33*/
181 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
182 /* Intel ICH2M */
183 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
184 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
185 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
186 /* Intel ICH3M */
187 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH3 (E7500/1) UDMA 100 */
189 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
190 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
191 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH5 */
194 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
195 /* C-ICH (i810E2) */
196 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
198 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 /* ICH6 (and 6) (i915) UDMA 100 */
200 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ICH7/7-R (i945, i975) UDMA 100*/
202 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
203 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204
205 /* NOTE: The following PCI ids must be kept in sync with the
206 * list in drivers/pci/quirks.c.
207 */
208
209 /* 82801EB (ICH5) */
210 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
211 /* 82801EB (ICH5) */
212 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
213 /* 6300ESB (ICH5 variant with broken PCS present bits) */
214 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
215 /* 6300ESB pretending RAID */
216 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
217 /* 82801FB/FW (ICH6/ICH6W) */
218 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
219 /* 82801FR/FRW (ICH6R/ICH6RW) */
220 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
221 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
222 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
223 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
224 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
225 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
226 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
227 /* Enterprise Southbridge 2 (631xESB/632xESB) */
228 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
229 /* SATA Controller 1 IDE (ICH8) */
230 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
231 /* SATA Controller 2 IDE (ICH8) */
232 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
233 /* Mobile SATA Controller IDE (ICH8M) */
234 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
235 /* SATA Controller IDE (ICH9) */
236 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
237 /* SATA Controller IDE (ICH9) */
238 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
239 /* SATA Controller IDE (ICH9) */
240 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 /* SATA Controller IDE (ICH9M) */
242 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
243 /* SATA Controller IDE (ICH9M) */
244 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
245 /* SATA Controller IDE (ICH9M) */
246 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247
248 { } /* terminate list */
249 };
250
251 static struct pci_driver piix_pci_driver = {
252 .name = DRV_NAME,
253 .id_table = piix_pci_tbl,
254 .probe = piix_init_one,
255 .remove = ata_pci_remove_one,
256 #ifdef CONFIG_PM
257 .suspend = ata_pci_device_suspend,
258 .resume = ata_pci_device_resume,
259 #endif
260 };
261
262 static struct scsi_host_template piix_sht = {
263 .module = THIS_MODULE,
264 .name = DRV_NAME,
265 .ioctl = ata_scsi_ioctl,
266 .queuecommand = ata_scsi_queuecmd,
267 .can_queue = ATA_DEF_QUEUE,
268 .this_id = ATA_SHT_THIS_ID,
269 .sg_tablesize = LIBATA_MAX_PRD,
270 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
271 .emulated = ATA_SHT_EMULATED,
272 .use_clustering = ATA_SHT_USE_CLUSTERING,
273 .proc_name = DRV_NAME,
274 .dma_boundary = ATA_DMA_BOUNDARY,
275 .slave_configure = ata_scsi_slave_config,
276 .slave_destroy = ata_scsi_slave_destroy,
277 .bios_param = ata_std_bios_param,
278 };
279
280 static const struct ata_port_operations piix_pata_ops = {
281 .port_disable = ata_port_disable,
282 .set_piomode = piix_set_piomode,
283 .set_dmamode = piix_set_dmamode,
284 .mode_filter = ata_pci_default_filter,
285
286 .tf_load = ata_tf_load,
287 .tf_read = ata_tf_read,
288 .check_status = ata_check_status,
289 .exec_command = ata_exec_command,
290 .dev_select = ata_std_dev_select,
291
292 .bmdma_setup = ata_bmdma_setup,
293 .bmdma_start = ata_bmdma_start,
294 .bmdma_stop = ata_bmdma_stop,
295 .bmdma_status = ata_bmdma_status,
296 .qc_prep = ata_qc_prep,
297 .qc_issue = ata_qc_issue_prot,
298 .data_xfer = ata_data_xfer,
299
300 .freeze = ata_bmdma_freeze,
301 .thaw = ata_bmdma_thaw,
302 .error_handler = piix_pata_error_handler,
303 .post_internal_cmd = ata_bmdma_post_internal_cmd,
304 .cable_detect = ata_cable_40wire,
305
306 .irq_handler = ata_interrupt,
307 .irq_clear = ata_bmdma_irq_clear,
308 .irq_on = ata_irq_on,
309 .irq_ack = ata_irq_ack,
310
311 .port_start = ata_port_start,
312 };
313
314 static const struct ata_port_operations ich_pata_ops = {
315 .port_disable = ata_port_disable,
316 .set_piomode = piix_set_piomode,
317 .set_dmamode = ich_set_dmamode,
318 .mode_filter = ata_pci_default_filter,
319
320 .tf_load = ata_tf_load,
321 .tf_read = ata_tf_read,
322 .check_status = ata_check_status,
323 .exec_command = ata_exec_command,
324 .dev_select = ata_std_dev_select,
325
326 .bmdma_setup = ata_bmdma_setup,
327 .bmdma_start = ata_bmdma_start,
328 .bmdma_stop = ata_bmdma_stop,
329 .bmdma_status = ata_bmdma_status,
330 .qc_prep = ata_qc_prep,
331 .qc_issue = ata_qc_issue_prot,
332 .data_xfer = ata_data_xfer,
333
334 .freeze = ata_bmdma_freeze,
335 .thaw = ata_bmdma_thaw,
336 .error_handler = piix_pata_error_handler,
337 .post_internal_cmd = ata_bmdma_post_internal_cmd,
338 .cable_detect = ich_pata_cable_detect,
339
340 .irq_handler = ata_interrupt,
341 .irq_clear = ata_bmdma_irq_clear,
342 .irq_on = ata_irq_on,
343 .irq_ack = ata_irq_ack,
344
345 .port_start = ata_port_start,
346 };
347
348 static const struct ata_port_operations piix_sata_ops = {
349 .port_disable = ata_port_disable,
350
351 .tf_load = ata_tf_load,
352 .tf_read = ata_tf_read,
353 .check_status = ata_check_status,
354 .exec_command = ata_exec_command,
355 .dev_select = ata_std_dev_select,
356
357 .bmdma_setup = ata_bmdma_setup,
358 .bmdma_start = ata_bmdma_start,
359 .bmdma_stop = ata_bmdma_stop,
360 .bmdma_status = ata_bmdma_status,
361 .qc_prep = ata_qc_prep,
362 .qc_issue = ata_qc_issue_prot,
363 .data_xfer = ata_data_xfer,
364
365 .freeze = ata_bmdma_freeze,
366 .thaw = ata_bmdma_thaw,
367 .error_handler = piix_sata_error_handler,
368 .post_internal_cmd = ata_bmdma_post_internal_cmd,
369
370 .irq_handler = ata_interrupt,
371 .irq_clear = ata_bmdma_irq_clear,
372 .irq_on = ata_irq_on,
373 .irq_ack = ata_irq_ack,
374
375 .port_start = ata_port_start,
376 };
377
378 static const struct piix_map_db ich5_map_db = {
379 .mask = 0x7,
380 .port_enable = 0x3,
381 .map = {
382 /* PM PS SM SS MAP */
383 { P0, NA, P1, NA }, /* 000b */
384 { P1, NA, P0, NA }, /* 001b */
385 { RV, RV, RV, RV },
386 { RV, RV, RV, RV },
387 { P0, P1, IDE, IDE }, /* 100b */
388 { P1, P0, IDE, IDE }, /* 101b */
389 { IDE, IDE, P0, P1 }, /* 110b */
390 { IDE, IDE, P1, P0 }, /* 111b */
391 },
392 };
393
394 static const struct piix_map_db ich6_map_db = {
395 .mask = 0x3,
396 .port_enable = 0xf,
397 .map = {
398 /* PM PS SM SS MAP */
399 { P0, P2, P1, P3 }, /* 00b */
400 { IDE, IDE, P1, P3 }, /* 01b */
401 { P0, P2, IDE, IDE }, /* 10b */
402 { RV, RV, RV, RV },
403 },
404 };
405
406 static const struct piix_map_db ich6m_map_db = {
407 .mask = 0x3,
408 .port_enable = 0x5,
409
410 /* Map 01b isn't specified in the doc but some notebooks use
411 * it anyway. MAP 01b have been spotted on both ICH6M and
412 * ICH7M.
413 */
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, P2, RV, RV }, /* 00b */
417 { IDE, IDE, P1, P3 }, /* 01b */
418 { P0, P2, IDE, IDE }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421 };
422
423 static const struct piix_map_db ich8_map_db = {
424 .mask = 0x3,
425 .port_enable = 0x3,
426 .map = {
427 /* PM PS SM SS MAP */
428 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
429 { RV, RV, RV, RV },
430 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
431 { RV, RV, RV, RV },
432 },
433 };
434
435 static const struct piix_map_db *piix_map_db_table[] = {
436 [ich5_sata] = &ich5_map_db,
437 [ich6_sata] = &ich6_map_db,
438 [ich6_sata_ahci] = &ich6_map_db,
439 [ich6m_sata_ahci] = &ich6m_map_db,
440 [ich8_sata_ahci] = &ich8_map_db,
441 };
442
443 static struct ata_port_info piix_port_info[] = {
444 /* piix_pata_33: 0: PIIX4 at 33MHz */
445 {
446 .sht = &piix_sht,
447 .flags = PIIX_PATA_FLAGS,
448 .pio_mask = 0x1f, /* pio0-4 */
449 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
450 .udma_mask = ATA_UDMA_MASK_40C,
451 .port_ops = &piix_pata_ops,
452 },
453
454 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
455 {
456 .sht = &piix_sht,
457 .flags = PIIX_PATA_FLAGS,
458 .pio_mask = 0x1f, /* pio 0-4 */
459 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
460 .udma_mask = ATA_UDMA2, /* UDMA33 */
461 .port_ops = &ich_pata_ops,
462 },
463 /* ich_pata_66: 2 ICH controllers up to 66MHz */
464 {
465 .sht = &piix_sht,
466 .flags = PIIX_PATA_FLAGS,
467 .pio_mask = 0x1f, /* pio 0-4 */
468 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
469 .udma_mask = ATA_UDMA4,
470 .port_ops = &ich_pata_ops,
471 },
472
473 /* ich_pata_100: 3 */
474 {
475 .sht = &piix_sht,
476 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
477 .pio_mask = 0x1f, /* pio0-4 */
478 .mwdma_mask = 0x06, /* mwdma1-2 */
479 .udma_mask = ATA_UDMA5, /* udma0-5 */
480 .port_ops = &ich_pata_ops,
481 },
482
483 /* ich_pata_133: 4 ICH with full UDMA6 */
484 {
485 .sht = &piix_sht,
486 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
487 .pio_mask = 0x1f, /* pio 0-4 */
488 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
489 .udma_mask = ATA_UDMA6, /* UDMA133 */
490 .port_ops = &ich_pata_ops,
491 },
492
493 /* ich5_sata: 5 */
494 {
495 .sht = &piix_sht,
496 .flags = PIIX_SATA_FLAGS,
497 .pio_mask = 0x1f, /* pio0-4 */
498 .mwdma_mask = 0x07, /* mwdma0-2 */
499 .udma_mask = 0x7f, /* udma0-6 */
500 .port_ops = &piix_sata_ops,
501 },
502
503 /* ich6_sata: 6 */
504 {
505 .sht = &piix_sht,
506 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
507 .pio_mask = 0x1f, /* pio0-4 */
508 .mwdma_mask = 0x07, /* mwdma0-2 */
509 .udma_mask = 0x7f, /* udma0-6 */
510 .port_ops = &piix_sata_ops,
511 },
512
513 /* ich6_sata_ahci: 7 */
514 {
515 .sht = &piix_sht,
516 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
517 PIIX_FLAG_AHCI,
518 .pio_mask = 0x1f, /* pio0-4 */
519 .mwdma_mask = 0x07, /* mwdma0-2 */
520 .udma_mask = 0x7f, /* udma0-6 */
521 .port_ops = &piix_sata_ops,
522 },
523
524 /* ich6m_sata_ahci: 8 */
525 {
526 .sht = &piix_sht,
527 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
528 PIIX_FLAG_AHCI,
529 .pio_mask = 0x1f, /* pio0-4 */
530 .mwdma_mask = 0x07, /* mwdma0-2 */
531 .udma_mask = 0x7f, /* udma0-6 */
532 .port_ops = &piix_sata_ops,
533 },
534
535 /* ich8_sata_ahci: 9 */
536 {
537 .sht = &piix_sht,
538 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
539 PIIX_FLAG_AHCI,
540 .pio_mask = 0x1f, /* pio0-4 */
541 .mwdma_mask = 0x07, /* mwdma0-2 */
542 .udma_mask = 0x7f, /* udma0-6 */
543 .port_ops = &piix_sata_ops,
544 },
545
546 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
547 {
548 .sht = &piix_sht,
549 .flags = PIIX_PATA_FLAGS,
550 .pio_mask = 0x1f, /* pio0-4 */
551 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
552 .port_ops = &piix_pata_ops,
553 },
554 };
555
556 static struct pci_bits piix_enable_bits[] = {
557 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
558 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
559 };
560
561 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
562 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
563 MODULE_LICENSE("GPL");
564 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
565 MODULE_VERSION(DRV_VERSION);
566
567 struct ich_laptop {
568 u16 device;
569 u16 subvendor;
570 u16 subdevice;
571 };
572
573 /*
574 * List of laptops that use short cables rather than 80 wire
575 */
576
577 static const struct ich_laptop ich_laptop[] = {
578 /* devid, subvendor, subdev */
579 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
580 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
581 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
582 /* end marker */
583 { 0, }
584 };
585
586 /**
587 * ich_pata_cable_detect - Probe host controller cable detect info
588 * @ap: Port for which cable detect info is desired
589 *
590 * Read 80c cable indicator from ATA PCI device's PCI config
591 * register. This register is normally set by firmware (BIOS).
592 *
593 * LOCKING:
594 * None (inherited from caller).
595 */
596
597 static int ich_pata_cable_detect(struct ata_port *ap)
598 {
599 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
600 const struct ich_laptop *lap = &ich_laptop[0];
601 u8 tmp, mask;
602
603 /* Check for specials - Acer Aspire 5602WLMi */
604 while (lap->device) {
605 if (lap->device == pdev->device &&
606 lap->subvendor == pdev->subsystem_vendor &&
607 lap->subdevice == pdev->subsystem_device) {
608 return ATA_CBL_PATA40_SHORT;
609 }
610 lap++;
611 }
612
613 /* check BIOS cable detect results */
614 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
615 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
616 if ((tmp & mask) == 0)
617 return ATA_CBL_PATA40;
618 return ATA_CBL_PATA80;
619 }
620
621 /**
622 * piix_pata_prereset - prereset for PATA host controller
623 * @ap: Target port
624 * @deadline: deadline jiffies for the operation
625 *
626 * LOCKING:
627 * None (inherited from caller).
628 */
629 static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
630 {
631 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
632
633 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
634 return -ENOENT;
635 return ata_std_prereset(ap, deadline);
636 }
637
638 static void piix_pata_error_handler(struct ata_port *ap)
639 {
640 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
641 ata_std_postreset);
642 }
643
644 static void piix_sata_error_handler(struct ata_port *ap)
645 {
646 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
647 ata_std_postreset);
648 }
649
650 /**
651 * piix_set_piomode - Initialize host controller PATA PIO timings
652 * @ap: Port whose timings we are configuring
653 * @adev: um
654 *
655 * Set PIO mode for device, in host controller PCI config space.
656 *
657 * LOCKING:
658 * None (inherited from caller).
659 */
660
661 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
662 {
663 unsigned int pio = adev->pio_mode - XFER_PIO_0;
664 struct pci_dev *dev = to_pci_dev(ap->host->dev);
665 unsigned int is_slave = (adev->devno != 0);
666 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
667 unsigned int slave_port = 0x44;
668 u16 master_data;
669 u8 slave_data;
670 u8 udma_enable;
671 int control = 0;
672
673 /*
674 * See Intel Document 298600-004 for the timing programing rules
675 * for ICH controllers.
676 */
677
678 static const /* ISP RTC */
679 u8 timings[][2] = { { 0, 0 },
680 { 0, 0 },
681 { 1, 0 },
682 { 2, 1 },
683 { 2, 3 }, };
684
685 if (pio >= 2)
686 control |= 1; /* TIME1 enable */
687 if (ata_pio_need_iordy(adev))
688 control |= 2; /* IE enable */
689
690 /* Intel specifies that the PPE functionality is for disk only */
691 if (adev->class == ATA_DEV_ATA)
692 control |= 4; /* PPE enable */
693
694 pci_read_config_word(dev, master_port, &master_data);
695 if (is_slave) {
696 /* Enable SITRE (seperate slave timing register) */
697 master_data |= 0x4000;
698 /* enable PPE1, IE1 and TIME1 as needed */
699 master_data |= (control << 4);
700 pci_read_config_byte(dev, slave_port, &slave_data);
701 slave_data &= (ap->port_no ? 0x0f : 0xf0);
702 /* Load the timing nibble for this slave */
703 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
704 } else {
705 /* Master keeps the bits in a different format */
706 master_data &= 0xccf8;
707 /* Enable PPE, IE and TIME as appropriate */
708 master_data |= control;
709 master_data |=
710 (timings[pio][0] << 12) |
711 (timings[pio][1] << 8);
712 }
713 pci_write_config_word(dev, master_port, master_data);
714 if (is_slave)
715 pci_write_config_byte(dev, slave_port, slave_data);
716
717 /* Ensure the UDMA bit is off - it will be turned back on if
718 UDMA is selected */
719
720 if (ap->udma_mask) {
721 pci_read_config_byte(dev, 0x48, &udma_enable);
722 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
723 pci_write_config_byte(dev, 0x48, udma_enable);
724 }
725 }
726
727 /**
728 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
729 * @ap: Port whose timings we are configuring
730 * @adev: Drive in question
731 * @udma: udma mode, 0 - 6
732 * @isich: set if the chip is an ICH device
733 *
734 * Set UDMA mode for device, in host controller PCI config space.
735 *
736 * LOCKING:
737 * None (inherited from caller).
738 */
739
740 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
741 {
742 struct pci_dev *dev = to_pci_dev(ap->host->dev);
743 u8 master_port = ap->port_no ? 0x42 : 0x40;
744 u16 master_data;
745 u8 speed = adev->dma_mode;
746 int devid = adev->devno + 2 * ap->port_no;
747 u8 udma_enable = 0;
748
749 static const /* ISP RTC */
750 u8 timings[][2] = { { 0, 0 },
751 { 0, 0 },
752 { 1, 0 },
753 { 2, 1 },
754 { 2, 3 }, };
755
756 pci_read_config_word(dev, master_port, &master_data);
757 if (ap->udma_mask)
758 pci_read_config_byte(dev, 0x48, &udma_enable);
759
760 if (speed >= XFER_UDMA_0) {
761 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
762 u16 udma_timing;
763 u16 ideconf;
764 int u_clock, u_speed;
765
766 /*
767 * UDMA is handled by a combination of clock switching and
768 * selection of dividers
769 *
770 * Handy rule: Odd modes are UDMATIMx 01, even are 02
771 * except UDMA0 which is 00
772 */
773 u_speed = min(2 - (udma & 1), udma);
774 if (udma == 5)
775 u_clock = 0x1000; /* 100Mhz */
776 else if (udma > 2)
777 u_clock = 1; /* 66Mhz */
778 else
779 u_clock = 0; /* 33Mhz */
780
781 udma_enable |= (1 << devid);
782
783 /* Load the CT/RP selection */
784 pci_read_config_word(dev, 0x4A, &udma_timing);
785 udma_timing &= ~(3 << (4 * devid));
786 udma_timing |= u_speed << (4 * devid);
787 pci_write_config_word(dev, 0x4A, udma_timing);
788
789 if (isich) {
790 /* Select a 33/66/100Mhz clock */
791 pci_read_config_word(dev, 0x54, &ideconf);
792 ideconf &= ~(0x1001 << devid);
793 ideconf |= u_clock << devid;
794 /* For ICH or later we should set bit 10 for better
795 performance (WR_PingPong_En) */
796 pci_write_config_word(dev, 0x54, ideconf);
797 }
798 } else {
799 /*
800 * MWDMA is driven by the PIO timings. We must also enable
801 * IORDY unconditionally along with TIME1. PPE has already
802 * been set when the PIO timing was set.
803 */
804 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
805 unsigned int control;
806 u8 slave_data;
807 const unsigned int needed_pio[3] = {
808 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
809 };
810 int pio = needed_pio[mwdma] - XFER_PIO_0;
811
812 control = 3; /* IORDY|TIME1 */
813
814 /* If the drive MWDMA is faster than it can do PIO then
815 we must force PIO into PIO0 */
816
817 if (adev->pio_mode < needed_pio[mwdma])
818 /* Enable DMA timing only */
819 control |= 8; /* PIO cycles in PIO0 */
820
821 if (adev->devno) { /* Slave */
822 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
823 master_data |= control << 4;
824 pci_read_config_byte(dev, 0x44, &slave_data);
825 slave_data &= (0x0F + 0xE1 * ap->port_no);
826 /* Load the matching timing */
827 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
828 pci_write_config_byte(dev, 0x44, slave_data);
829 } else { /* Master */
830 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
831 and master timing bits */
832 master_data |= control;
833 master_data |=
834 (timings[pio][0] << 12) |
835 (timings[pio][1] << 8);
836 }
837 udma_enable &= ~(1 << devid);
838 pci_write_config_word(dev, master_port, master_data);
839 }
840 /* Don't scribble on 0x48 if the controller does not support UDMA */
841 if (ap->udma_mask)
842 pci_write_config_byte(dev, 0x48, udma_enable);
843 }
844
845 /**
846 * piix_set_dmamode - Initialize host controller PATA DMA timings
847 * @ap: Port whose timings we are configuring
848 * @adev: um
849 *
850 * Set MW/UDMA mode for device, in host controller PCI config space.
851 *
852 * LOCKING:
853 * None (inherited from caller).
854 */
855
856 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
857 {
858 do_pata_set_dmamode(ap, adev, 0);
859 }
860
861 /**
862 * ich_set_dmamode - Initialize host controller PATA DMA timings
863 * @ap: Port whose timings we are configuring
864 * @adev: um
865 *
866 * Set MW/UDMA mode for device, in host controller PCI config space.
867 *
868 * LOCKING:
869 * None (inherited from caller).
870 */
871
872 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
873 {
874 do_pata_set_dmamode(ap, adev, 1);
875 }
876
877 #define AHCI_PCI_BAR 5
878 #define AHCI_GLOBAL_CTL 0x04
879 #define AHCI_ENABLE (1 << 31)
880 static int piix_disable_ahci(struct pci_dev *pdev)
881 {
882 void __iomem *mmio;
883 u32 tmp;
884 int rc = 0;
885
886 /* BUG: pci_enable_device has not yet been called. This
887 * works because this device is usually set up by BIOS.
888 */
889
890 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
891 !pci_resource_len(pdev, AHCI_PCI_BAR))
892 return 0;
893
894 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
895 if (!mmio)
896 return -ENOMEM;
897
898 tmp = readl(mmio + AHCI_GLOBAL_CTL);
899 if (tmp & AHCI_ENABLE) {
900 tmp &= ~AHCI_ENABLE;
901 writel(tmp, mmio + AHCI_GLOBAL_CTL);
902
903 tmp = readl(mmio + AHCI_GLOBAL_CTL);
904 if (tmp & AHCI_ENABLE)
905 rc = -EIO;
906 }
907
908 pci_iounmap(pdev, mmio);
909 return rc;
910 }
911
912 /**
913 * piix_check_450nx_errata - Check for problem 450NX setup
914 * @ata_dev: the PCI device to check
915 *
916 * Check for the present of 450NX errata #19 and errata #25. If
917 * they are found return an error code so we can turn off DMA
918 */
919
920 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
921 {
922 struct pci_dev *pdev = NULL;
923 u16 cfg;
924 u8 rev;
925 int no_piix_dma = 0;
926
927 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
928 {
929 /* Look for 450NX PXB. Check for problem configurations
930 A PCI quirk checks bit 6 already */
931 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
932 pci_read_config_word(pdev, 0x41, &cfg);
933 /* Only on the original revision: IDE DMA can hang */
934 if (rev == 0x00)
935 no_piix_dma = 1;
936 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
937 else if (cfg & (1<<14) && rev < 5)
938 no_piix_dma = 2;
939 }
940 if (no_piix_dma)
941 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
942 if (no_piix_dma == 2)
943 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
944 return no_piix_dma;
945 }
946
947 static void __devinit piix_init_pcs(struct pci_dev *pdev,
948 struct ata_port_info *pinfo,
949 const struct piix_map_db *map_db)
950 {
951 u16 pcs, new_pcs;
952
953 pci_read_config_word(pdev, ICH5_PCS, &pcs);
954
955 new_pcs = pcs | map_db->port_enable;
956
957 if (new_pcs != pcs) {
958 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
959 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
960 msleep(150);
961 }
962 }
963
964 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
965 struct ata_port_info *pinfo,
966 const struct piix_map_db *map_db)
967 {
968 struct piix_host_priv *hpriv = pinfo[0].private_data;
969 const unsigned int *map;
970 int i, invalid_map = 0;
971 u8 map_value;
972
973 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
974
975 map = map_db->map[map_value & map_db->mask];
976
977 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
978 for (i = 0; i < 4; i++) {
979 switch (map[i]) {
980 case RV:
981 invalid_map = 1;
982 printk(" XX");
983 break;
984
985 case NA:
986 printk(" --");
987 break;
988
989 case IDE:
990 WARN_ON((i & 1) || map[i + 1] != IDE);
991 pinfo[i / 2] = piix_port_info[ich_pata_100];
992 pinfo[i / 2].private_data = hpriv;
993 i++;
994 printk(" IDE IDE");
995 break;
996
997 default:
998 printk(" P%d", map[i]);
999 if (i & 1)
1000 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1001 break;
1002 }
1003 }
1004 printk(" ]\n");
1005
1006 if (invalid_map)
1007 dev_printk(KERN_ERR, &pdev->dev,
1008 "invalid MAP value %u\n", map_value);
1009
1010 hpriv->map = map;
1011 }
1012
1013 /**
1014 * piix_init_one - Register PIIX ATA PCI device with kernel services
1015 * @pdev: PCI device to register
1016 * @ent: Entry in piix_pci_tbl matching with @pdev
1017 *
1018 * Called from kernel PCI layer. We probe for combined mode (sigh),
1019 * and then hand over control to libata, for it to do the rest.
1020 *
1021 * LOCKING:
1022 * Inherited from PCI layer (may sleep).
1023 *
1024 * RETURNS:
1025 * Zero on success, or -ERRNO value.
1026 */
1027
1028 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1029 {
1030 static int printed_version;
1031 struct device *dev = &pdev->dev;
1032 struct ata_port_info port_info[2];
1033 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1034 struct piix_host_priv *hpriv;
1035 unsigned long port_flags;
1036
1037 if (!printed_version++)
1038 dev_printk(KERN_DEBUG, &pdev->dev,
1039 "version " DRV_VERSION "\n");
1040
1041 /* no hotplugging support (FIXME) */
1042 if (!in_module_init)
1043 return -ENODEV;
1044
1045 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1046 if (!hpriv)
1047 return -ENOMEM;
1048
1049 port_info[0] = piix_port_info[ent->driver_data];
1050 port_info[1] = piix_port_info[ent->driver_data];
1051 port_info[0].private_data = hpriv;
1052 port_info[1].private_data = hpriv;
1053
1054 port_flags = port_info[0].flags;
1055
1056 if (port_flags & PIIX_FLAG_AHCI) {
1057 u8 tmp;
1058 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1059 if (tmp == PIIX_AHCI_DEVICE) {
1060 int rc = piix_disable_ahci(pdev);
1061 if (rc)
1062 return rc;
1063 }
1064 }
1065
1066 /* Initialize SATA map */
1067 if (port_flags & ATA_FLAG_SATA) {
1068 piix_init_sata_map(pdev, port_info,
1069 piix_map_db_table[ent->driver_data]);
1070 piix_init_pcs(pdev, port_info,
1071 piix_map_db_table[ent->driver_data]);
1072 }
1073
1074 /* On ICH5, some BIOSen disable the interrupt using the
1075 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1076 * On ICH6, this bit has the same effect, but only when
1077 * MSI is disabled (and it is disabled, as we don't use
1078 * message-signalled interrupts currently).
1079 */
1080 if (port_flags & PIIX_FLAG_CHECKINTR)
1081 pci_intx(pdev, 1);
1082
1083 if (piix_check_450nx_errata(pdev)) {
1084 /* This writes into the master table but it does not
1085 really matter for this errata as we will apply it to
1086 all the PIIX devices on the board */
1087 port_info[0].mwdma_mask = 0;
1088 port_info[0].udma_mask = 0;
1089 port_info[1].mwdma_mask = 0;
1090 port_info[1].udma_mask = 0;
1091 }
1092 return ata_pci_init_one(pdev, ppinfo, 2);
1093 }
1094
1095 static int __init piix_init(void)
1096 {
1097 int rc;
1098
1099 DPRINTK("pci_register_driver\n");
1100 rc = pci_register_driver(&piix_pci_driver);
1101 if (rc)
1102 return rc;
1103
1104 in_module_init = 0;
1105
1106 DPRINTK("done\n");
1107 return 0;
1108 }
1109
1110 static void __exit piix_exit(void)
1111 {
1112 pci_unregister_driver(&piix_pci_driver);
1113 }
1114
1115 module_init(piix_init);
1116 module_exit(piix_exit);
Linux kernel - Deliverables
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