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[PATCH] libata: refuse to register IRQless ports
[deliverable/linux.git] / drivers / ata / pata_hpt37x.c
1 /*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 * TODO
13 * PLL mode
14 * Look into engine reset on timeout errors. Should not be
15 * required.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <scsi/scsi_host.h>
25 #include <linux/libata.h>
26
27 #define DRV_NAME "pata_hpt37x"
28 #define DRV_VERSION "0.5"
29
30 struct hpt_clock {
31 u8 xfer_speed;
32 u32 timing;
33 };
34
35 struct hpt_chip {
36 const char *name;
37 unsigned int base;
38 struct hpt_clock const *clocks[4];
39 };
40
41 /* key for bus clock timings
42 * bit
43 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
44 * DMA. cycles = value + 1
45 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
46 * DMA. cycles = value + 1
47 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * register access.
49 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * register access.
51 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
52 * during task file register access.
53 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * xfer.
55 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
56 * register access.
57 * 28 UDMA enable
58 * 29 DMA enable
59 * 30 PIO_MST enable. if set, the chip is in bus master mode during
60 * PIO.
61 * 31 FIFO enable.
62 */
63
64 /* from highpoint documentation. these are old values */
65 static const struct hpt_clock hpt370_timings_33[] = {
66 /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
67 { XFER_UDMA_5, 0x16454e31 },
68 { XFER_UDMA_4, 0x16454e31 },
69 { XFER_UDMA_3, 0x166d4e31 },
70 { XFER_UDMA_2, 0x16494e31 },
71 { XFER_UDMA_1, 0x164d4e31 },
72 { XFER_UDMA_0, 0x16514e31 },
73
74 { XFER_MW_DMA_2, 0x26514e21 },
75 { XFER_MW_DMA_1, 0x26514e33 },
76 { XFER_MW_DMA_0, 0x26514e97 },
77
78 { XFER_PIO_4, 0x06514e21 },
79 { XFER_PIO_3, 0x06514e22 },
80 { XFER_PIO_2, 0x06514e33 },
81 { XFER_PIO_1, 0x06914e43 },
82 { XFER_PIO_0, 0x06914e57 },
83 { 0, 0x06514e57 }
84 };
85
86 static const struct hpt_clock hpt370_timings_66[] = {
87 { XFER_UDMA_5, 0x14846231 },
88 { XFER_UDMA_4, 0x14886231 },
89 { XFER_UDMA_3, 0x148c6231 },
90 { XFER_UDMA_2, 0x148c6231 },
91 { XFER_UDMA_1, 0x14906231 },
92 { XFER_UDMA_0, 0x14986231 },
93
94 { XFER_MW_DMA_2, 0x26514e21 },
95 { XFER_MW_DMA_1, 0x26514e33 },
96 { XFER_MW_DMA_0, 0x26514e97 },
97
98 { XFER_PIO_4, 0x06514e21 },
99 { XFER_PIO_3, 0x06514e22 },
100 { XFER_PIO_2, 0x06514e33 },
101 { XFER_PIO_1, 0x06914e43 },
102 { XFER_PIO_0, 0x06914e57 },
103 { 0, 0x06514e57 }
104 };
105
106 /* these are the current (4 sep 2001) timings from highpoint */
107 static const struct hpt_clock hpt370a_timings_33[] = {
108 { XFER_UDMA_5, 0x12446231 },
109 { XFER_UDMA_4, 0x12446231 },
110 { XFER_UDMA_3, 0x126c6231 },
111 { XFER_UDMA_2, 0x12486231 },
112 { XFER_UDMA_1, 0x124c6233 },
113 { XFER_UDMA_0, 0x12506297 },
114
115 { XFER_MW_DMA_2, 0x22406c31 },
116 { XFER_MW_DMA_1, 0x22406c33 },
117 { XFER_MW_DMA_0, 0x22406c97 },
118
119 { XFER_PIO_4, 0x06414e31 },
120 { XFER_PIO_3, 0x06414e42 },
121 { XFER_PIO_2, 0x06414e53 },
122 { XFER_PIO_1, 0x06814e93 },
123 { XFER_PIO_0, 0x06814ea7 },
124 { 0, 0x06814ea7 }
125 };
126
127 /* 2x 33MHz timings */
128 static const struct hpt_clock hpt370a_timings_66[] = {
129 { XFER_UDMA_5, 0x1488e673 },
130 { XFER_UDMA_4, 0x1488e673 },
131 { XFER_UDMA_3, 0x1498e673 },
132 { XFER_UDMA_2, 0x1490e673 },
133 { XFER_UDMA_1, 0x1498e677 },
134 { XFER_UDMA_0, 0x14a0e73f },
135
136 { XFER_MW_DMA_2, 0x2480fa73 },
137 { XFER_MW_DMA_1, 0x2480fa77 },
138 { XFER_MW_DMA_0, 0x2480fb3f },
139
140 { XFER_PIO_4, 0x0c82be73 },
141 { XFER_PIO_3, 0x0c82be95 },
142 { XFER_PIO_2, 0x0c82beb7 },
143 { XFER_PIO_1, 0x0d02bf37 },
144 { XFER_PIO_0, 0x0d02bf5f },
145 { 0, 0x0d02bf5f }
146 };
147
148 static const struct hpt_clock hpt370a_timings_50[] = {
149 { XFER_UDMA_5, 0x12848242 },
150 { XFER_UDMA_4, 0x12ac8242 },
151 { XFER_UDMA_3, 0x128c8242 },
152 { XFER_UDMA_2, 0x120c8242 },
153 { XFER_UDMA_1, 0x12148254 },
154 { XFER_UDMA_0, 0x121882ea },
155
156 { XFER_MW_DMA_2, 0x22808242 },
157 { XFER_MW_DMA_1, 0x22808254 },
158 { XFER_MW_DMA_0, 0x228082ea },
159
160 { XFER_PIO_4, 0x0a81f442 },
161 { XFER_PIO_3, 0x0a81f443 },
162 { XFER_PIO_2, 0x0a81f454 },
163 { XFER_PIO_1, 0x0ac1f465 },
164 { XFER_PIO_0, 0x0ac1f48a },
165 { 0, 0x0ac1f48a }
166 };
167
168 static const struct hpt_clock hpt372_timings_33[] = {
169 { XFER_UDMA_6, 0x1c81dc62 },
170 { XFER_UDMA_5, 0x1c6ddc62 },
171 { XFER_UDMA_4, 0x1c8ddc62 },
172 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
173 { XFER_UDMA_2, 0x1c91dc62 },
174 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
175 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
176
177 { XFER_MW_DMA_2, 0x2c829262 },
178 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
179 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
180
181 { XFER_PIO_4, 0x0c829c62 },
182 { XFER_PIO_3, 0x0c829c84 },
183 { XFER_PIO_2, 0x0c829ca6 },
184 { XFER_PIO_1, 0x0d029d26 },
185 { XFER_PIO_0, 0x0d029d5e },
186 { 0, 0x0d029d5e }
187 };
188
189 static const struct hpt_clock hpt372_timings_50[] = {
190 { XFER_UDMA_5, 0x12848242 },
191 { XFER_UDMA_4, 0x12ac8242 },
192 { XFER_UDMA_3, 0x128c8242 },
193 { XFER_UDMA_2, 0x120c8242 },
194 { XFER_UDMA_1, 0x12148254 },
195 { XFER_UDMA_0, 0x121882ea },
196
197 { XFER_MW_DMA_2, 0x22808242 },
198 { XFER_MW_DMA_1, 0x22808254 },
199 { XFER_MW_DMA_0, 0x228082ea },
200
201 { XFER_PIO_4, 0x0a81f442 },
202 { XFER_PIO_3, 0x0a81f443 },
203 { XFER_PIO_2, 0x0a81f454 },
204 { XFER_PIO_1, 0x0ac1f465 },
205 { XFER_PIO_0, 0x0ac1f48a },
206 { 0, 0x0a81f443 }
207 };
208
209 static const struct hpt_clock hpt372_timings_66[] = {
210 { XFER_UDMA_6, 0x1c869c62 },
211 { XFER_UDMA_5, 0x1cae9c62 },
212 { XFER_UDMA_4, 0x1c8a9c62 },
213 { XFER_UDMA_3, 0x1c8e9c62 },
214 { XFER_UDMA_2, 0x1c929c62 },
215 { XFER_UDMA_1, 0x1c9a9c62 },
216 { XFER_UDMA_0, 0x1c829c62 },
217
218 { XFER_MW_DMA_2, 0x2c829c62 },
219 { XFER_MW_DMA_1, 0x2c829c66 },
220 { XFER_MW_DMA_0, 0x2c829d2e },
221
222 { XFER_PIO_4, 0x0c829c62 },
223 { XFER_PIO_3, 0x0c829c84 },
224 { XFER_PIO_2, 0x0c829ca6 },
225 { XFER_PIO_1, 0x0d029d26 },
226 { XFER_PIO_0, 0x0d029d5e },
227 { 0, 0x0d029d26 }
228 };
229
230 static const struct hpt_clock hpt374_timings_33[] = {
231 { XFER_UDMA_6, 0x12808242 },
232 { XFER_UDMA_5, 0x12848242 },
233 { XFER_UDMA_4, 0x12ac8242 },
234 { XFER_UDMA_3, 0x128c8242 },
235 { XFER_UDMA_2, 0x120c8242 },
236 { XFER_UDMA_1, 0x12148254 },
237 { XFER_UDMA_0, 0x121882ea },
238
239 { XFER_MW_DMA_2, 0x22808242 },
240 { XFER_MW_DMA_1, 0x22808254 },
241 { XFER_MW_DMA_0, 0x228082ea },
242
243 { XFER_PIO_4, 0x0a81f442 },
244 { XFER_PIO_3, 0x0a81f443 },
245 { XFER_PIO_2, 0x0a81f454 },
246 { XFER_PIO_1, 0x0ac1f465 },
247 { XFER_PIO_0, 0x0ac1f48a },
248 { 0, 0x06814e93 }
249 };
250
251 static const struct hpt_chip hpt370 = {
252 "HPT370",
253 48,
254 {
255 hpt370_timings_33,
256 NULL,
257 NULL,
258 hpt370_timings_66
259 }
260 };
261
262 static const struct hpt_chip hpt370a = {
263 "HPT370A",
264 48,
265 {
266 hpt370a_timings_33,
267 NULL,
268 hpt370a_timings_50,
269 hpt370a_timings_66
270 }
271 };
272
273 static const struct hpt_chip hpt372 = {
274 "HPT372",
275 55,
276 {
277 hpt372_timings_33,
278 NULL,
279 hpt372_timings_50,
280 hpt372_timings_66
281 }
282 };
283
284 static const struct hpt_chip hpt302 = {
285 "HPT302",
286 66,
287 {
288 hpt372_timings_33,
289 NULL,
290 hpt372_timings_50,
291 hpt372_timings_66
292 }
293 };
294
295 static const struct hpt_chip hpt371 = {
296 "HPT371",
297 66,
298 {
299 hpt372_timings_33,
300 NULL,
301 hpt372_timings_50,
302 hpt372_timings_66
303 }
304 };
305
306 static const struct hpt_chip hpt372a = {
307 "HPT372A",
308 66,
309 {
310 hpt372_timings_33,
311 NULL,
312 hpt372_timings_50,
313 hpt372_timings_66
314 }
315 };
316
317 static const struct hpt_chip hpt374 = {
318 "HPT374",
319 48,
320 {
321 hpt374_timings_33,
322 NULL,
323 NULL,
324 NULL
325 }
326 };
327
328 /**
329 * hpt37x_find_mode - reset the hpt37x bus
330 * @ap: ATA port
331 * @speed: transfer mode
332 *
333 * Return the 32bit register programming information for this channel
334 * that matches the speed provided.
335 */
336
337 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
338 {
339 struct hpt_clock *clocks = ap->host->private_data;
340
341 while(clocks->xfer_speed) {
342 if (clocks->xfer_speed == speed)
343 return clocks->timing;
344 clocks++;
345 }
346 BUG();
347 return 0xffffffffU; /* silence compiler warning */
348 }
349
350 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
351 {
352 unsigned char model_num[40];
353 char *s;
354 unsigned int len;
355 int i = 0;
356
357 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
358 sizeof(model_num));
359 s = &model_num[0];
360 len = strnlen(s, sizeof(model_num));
361
362 /* ATAPI specifies that empty space is blank-filled; remove blanks */
363 while ((len > 0) && (s[len - 1] == ' ')) {
364 len--;
365 s[len] = 0;
366 }
367
368 while(list[i] != NULL) {
369 if (!strncmp(list[i], s, len)) {
370 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
371 modestr, list[i]);
372 return 1;
373 }
374 i++;
375 }
376 return 0;
377 }
378
379 static const char *bad_ata33[] = {
380 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
381 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
382 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
383 "Maxtor 90510D4",
384 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
385 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
386 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
387 NULL
388 };
389
390 static const char *bad_ata100_5[] = {
391 "IBM-DTLA-307075",
392 "IBM-DTLA-307060",
393 "IBM-DTLA-307045",
394 "IBM-DTLA-307030",
395 "IBM-DTLA-307020",
396 "IBM-DTLA-307015",
397 "IBM-DTLA-305040",
398 "IBM-DTLA-305030",
399 "IBM-DTLA-305020",
400 "IC35L010AVER07-0",
401 "IC35L020AVER07-0",
402 "IC35L030AVER07-0",
403 "IC35L040AVER07-0",
404 "IC35L060AVER07-0",
405 "WDC AC310200R",
406 NULL
407 };
408
409 /**
410 * hpt370_filter - mode selection filter
411 * @ap: ATA interface
412 * @adev: ATA device
413 *
414 * Block UDMA on devices that cause trouble with this controller.
415 */
416
417 static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
418 {
419 if (adev->class != ATA_DEV_ATA) {
420 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
421 mask &= ~ATA_MASK_UDMA;
422 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
423 mask &= ~(0x1F << ATA_SHIFT_UDMA);
424 }
425 return ata_pci_default_filter(ap, adev, mask);
426 }
427
428 /**
429 * hpt370a_filter - mode selection filter
430 * @ap: ATA interface
431 * @adev: ATA device
432 *
433 * Block UDMA on devices that cause trouble with this controller.
434 */
435
436 static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
437 {
438 if (adev->class != ATA_DEV_ATA) {
439 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
440 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
441 }
442 return ata_pci_default_filter(ap, adev, mask);
443 }
444
445 /**
446 * hpt37x_pre_reset - reset the hpt37x bus
447 * @ap: ATA port to reset
448 *
449 * Perform the initial reset handling for the 370/372 and 374 func 0
450 */
451
452 static int hpt37x_pre_reset(struct ata_port *ap)
453 {
454 u8 scr2, ata66;
455 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
456
457 pci_read_config_byte(pdev, 0x5B, &scr2);
458 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
459 /* Cable register now active */
460 pci_read_config_byte(pdev, 0x5A, &ata66);
461 /* Restore state */
462 pci_write_config_byte(pdev, 0x5B, scr2);
463
464 if (ata66 & (1 << ap->port_no))
465 ap->cbl = ATA_CBL_PATA40;
466 else
467 ap->cbl = ATA_CBL_PATA80;
468
469 /* Reset the state machine */
470 pci_write_config_byte(pdev, 0x50, 0x37);
471 pci_write_config_byte(pdev, 0x54, 0x37);
472 udelay(100);
473
474 return ata_std_prereset(ap);
475 }
476
477 /**
478 * hpt37x_error_handler - reset the hpt374
479 * @ap: ATA port to reset
480 *
481 * Perform probe for HPT37x, except for HPT374 channel 2
482 */
483
484 static void hpt37x_error_handler(struct ata_port *ap)
485 {
486 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
487 }
488
489 static int hpt374_pre_reset(struct ata_port *ap)
490 {
491 u16 mcr3, mcr6;
492 u8 ata66;
493
494 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
495 /* Do the extra channel work */
496 pci_read_config_word(pdev, 0x52, &mcr3);
497 pci_read_config_word(pdev, 0x56, &mcr6);
498 /* Set bit 15 of 0x52 to enable TCBLID as input
499 Set bit 15 of 0x56 to enable FCBLID as input
500 */
501 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
502 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
503 pci_read_config_byte(pdev, 0x5A, &ata66);
504 /* Reset TCBLID/FCBLID to output */
505 pci_write_config_word(pdev, 0x52, mcr3);
506 pci_write_config_word(pdev, 0x56, mcr6);
507
508 if (ata66 & (1 << ap->port_no))
509 ap->cbl = ATA_CBL_PATA40;
510 else
511 ap->cbl = ATA_CBL_PATA80;
512
513 /* Reset the state machine */
514 pci_write_config_byte(pdev, 0x50, 0x37);
515 pci_write_config_byte(pdev, 0x54, 0x37);
516 udelay(100);
517
518 return ata_std_prereset(ap);
519 }
520
521 /**
522 * hpt374_error_handler - reset the hpt374
523 * @classes:
524 *
525 * The 374 cable detect is a little different due to the extra
526 * channels. The function 0 channels work like usual but function 1
527 * is special
528 */
529
530 static void hpt374_error_handler(struct ata_port *ap)
531 {
532 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
533
534 if (!(PCI_FUNC(pdev->devfn) & 1))
535 hpt37x_error_handler(ap);
536 else
537 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
538 }
539
540 /**
541 * hpt370_set_piomode - PIO setup
542 * @ap: ATA interface
543 * @adev: device on the interface
544 *
545 * Perform PIO mode setup.
546 */
547
548 static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
549 {
550 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
551 u32 addr1, addr2;
552 u32 reg;
553 u32 mode;
554 u8 fast;
555
556 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
557 addr2 = 0x51 + 4 * ap->port_no;
558
559 /* Fast interrupt prediction disable, hold off interrupt disable */
560 pci_read_config_byte(pdev, addr2, &fast);
561 fast &= ~0x02;
562 fast |= 0x01;
563 pci_write_config_byte(pdev, addr2, fast);
564
565 pci_read_config_dword(pdev, addr1, &reg);
566 mode = hpt37x_find_mode(ap, adev->pio_mode);
567 mode &= ~0x8000000; /* No FIFO in PIO */
568 mode &= ~0x30070000; /* Leave config bits alone */
569 reg &= 0x30070000; /* Strip timing bits */
570 pci_write_config_dword(pdev, addr1, reg | mode);
571 }
572
573 /**
574 * hpt370_set_dmamode - DMA timing setup
575 * @ap: ATA interface
576 * @adev: Device being configured
577 *
578 * Set up the channel for MWDMA or UDMA modes. Much the same as with
579 * PIO, load the mode number and then set MWDMA or UDMA flag.
580 */
581
582 static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
583 {
584 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
585 u32 addr1, addr2;
586 u32 reg;
587 u32 mode;
588 u8 fast;
589
590 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
591 addr2 = 0x51 + 4 * ap->port_no;
592
593 /* Fast interrupt prediction disable, hold off interrupt disable */
594 pci_read_config_byte(pdev, addr2, &fast);
595 fast &= ~0x02;
596 fast |= 0x01;
597 pci_write_config_byte(pdev, addr2, fast);
598
599 pci_read_config_dword(pdev, addr1, &reg);
600 mode = hpt37x_find_mode(ap, adev->dma_mode);
601 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
602 mode &= ~0xC0000000; /* Leave config bits alone */
603 reg &= 0xC0000000; /* Strip timing bits */
604 pci_write_config_dword(pdev, addr1, reg | mode);
605 }
606
607 /**
608 * hpt370_bmdma_start - DMA engine begin
609 * @qc: ATA command
610 *
611 * The 370 and 370A want us to reset the DMA engine each time we
612 * use it. The 372 and later are fine.
613 */
614
615 static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
616 {
617 struct ata_port *ap = qc->ap;
618 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
619 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
620 udelay(10);
621 ata_bmdma_start(qc);
622 }
623
624 /**
625 * hpt370_bmdma_end - DMA engine stop
626 * @qc: ATA command
627 *
628 * Work around the HPT370 DMA engine.
629 */
630
631 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
632 {
633 struct ata_port *ap = qc->ap;
634 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
635 u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2);
636 u8 dma_cmd;
637 unsigned long bmdma = ap->ioaddr.bmdma_addr;
638
639 if (dma_stat & 0x01) {
640 udelay(20);
641 dma_stat = inb(bmdma + 2);
642 }
643 if (dma_stat & 0x01) {
644 /* Clear the engine */
645 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
646 udelay(10);
647 /* Stop DMA */
648 dma_cmd = inb(bmdma );
649 outb(dma_cmd & 0xFE, bmdma);
650 /* Clear Error */
651 dma_stat = inb(bmdma + 2);
652 outb(dma_stat | 0x06 , bmdma + 2);
653 /* Clear the engine */
654 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
655 udelay(10);
656 }
657 ata_bmdma_stop(qc);
658 }
659
660 /**
661 * hpt372_set_piomode - PIO setup
662 * @ap: ATA interface
663 * @adev: device on the interface
664 *
665 * Perform PIO mode setup.
666 */
667
668 static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
669 {
670 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
671 u32 addr1, addr2;
672 u32 reg;
673 u32 mode;
674 u8 fast;
675
676 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
677 addr2 = 0x51 + 4 * ap->port_no;
678
679 /* Fast interrupt prediction disable, hold off interrupt disable */
680 pci_read_config_byte(pdev, addr2, &fast);
681 fast &= ~0x07;
682 pci_write_config_byte(pdev, addr2, fast);
683
684 pci_read_config_dword(pdev, addr1, &reg);
685 mode = hpt37x_find_mode(ap, adev->pio_mode);
686
687 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
688 mode &= ~0x80000000; /* No FIFO in PIO */
689 mode &= ~0x30070000; /* Leave config bits alone */
690 reg &= 0x30070000; /* Strip timing bits */
691 pci_write_config_dword(pdev, addr1, reg | mode);
692 }
693
694 /**
695 * hpt372_set_dmamode - DMA timing setup
696 * @ap: ATA interface
697 * @adev: Device being configured
698 *
699 * Set up the channel for MWDMA or UDMA modes. Much the same as with
700 * PIO, load the mode number and then set MWDMA or UDMA flag.
701 */
702
703 static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
704 {
705 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
706 u32 addr1, addr2;
707 u32 reg;
708 u32 mode;
709 u8 fast;
710
711 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
712 addr2 = 0x51 + 4 * ap->port_no;
713
714 /* Fast interrupt prediction disable, hold off interrupt disable */
715 pci_read_config_byte(pdev, addr2, &fast);
716 fast &= ~0x07;
717 pci_write_config_byte(pdev, addr2, fast);
718
719 pci_read_config_dword(pdev, addr1, &reg);
720 mode = hpt37x_find_mode(ap, adev->dma_mode);
721 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
722 mode &= ~0xC0000000; /* Leave config bits alone */
723 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
724 reg &= 0xC0000000; /* Strip timing bits */
725 pci_write_config_dword(pdev, addr1, reg | mode);
726 }
727
728 /**
729 * hpt37x_bmdma_end - DMA engine stop
730 * @qc: ATA command
731 *
732 * Clean up after the HPT372 and later DMA engine
733 */
734
735 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
736 {
737 struct ata_port *ap = qc->ap;
738 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
739 int mscreg = 0x50 + 2 * ap->port_no;
740 u8 bwsr_stat, msc_stat;
741
742 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
743 pci_read_config_byte(pdev, mscreg, &msc_stat);
744 if (bwsr_stat & (1 << ap->port_no))
745 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
746 ata_bmdma_stop(qc);
747 }
748
749
750 static struct scsi_host_template hpt37x_sht = {
751 .module = THIS_MODULE,
752 .name = DRV_NAME,
753 .ioctl = ata_scsi_ioctl,
754 .queuecommand = ata_scsi_queuecmd,
755 .can_queue = ATA_DEF_QUEUE,
756 .this_id = ATA_SHT_THIS_ID,
757 .sg_tablesize = LIBATA_MAX_PRD,
758 .max_sectors = ATA_MAX_SECTORS,
759 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
760 .emulated = ATA_SHT_EMULATED,
761 .use_clustering = ATA_SHT_USE_CLUSTERING,
762 .proc_name = DRV_NAME,
763 .dma_boundary = ATA_DMA_BOUNDARY,
764 .slave_configure = ata_scsi_slave_config,
765 .bios_param = ata_std_bios_param,
766 };
767
768 /*
769 * Configuration for HPT370
770 */
771
772 static struct ata_port_operations hpt370_port_ops = {
773 .port_disable = ata_port_disable,
774 .set_piomode = hpt370_set_piomode,
775 .set_dmamode = hpt370_set_dmamode,
776 .mode_filter = hpt370_filter,
777
778 .tf_load = ata_tf_load,
779 .tf_read = ata_tf_read,
780 .check_status = ata_check_status,
781 .exec_command = ata_exec_command,
782 .dev_select = ata_std_dev_select,
783
784 .freeze = ata_bmdma_freeze,
785 .thaw = ata_bmdma_thaw,
786 .error_handler = hpt37x_error_handler,
787 .post_internal_cmd = ata_bmdma_post_internal_cmd,
788
789 .bmdma_setup = ata_bmdma_setup,
790 .bmdma_start = hpt370_bmdma_start,
791 .bmdma_stop = hpt370_bmdma_stop,
792 .bmdma_status = ata_bmdma_status,
793
794 .qc_prep = ata_qc_prep,
795 .qc_issue = ata_qc_issue_prot,
796 .eng_timeout = ata_eng_timeout,
797 .data_xfer = ata_pio_data_xfer,
798
799 .irq_handler = ata_interrupt,
800 .irq_clear = ata_bmdma_irq_clear,
801
802 .port_start = ata_port_start,
803 .port_stop = ata_port_stop,
804 .host_stop = ata_host_stop
805 };
806
807 /*
808 * Configuration for HPT370A. Close to 370 but less filters
809 */
810
811 static struct ata_port_operations hpt370a_port_ops = {
812 .port_disable = ata_port_disable,
813 .set_piomode = hpt370_set_piomode,
814 .set_dmamode = hpt370_set_dmamode,
815 .mode_filter = hpt370a_filter,
816
817 .tf_load = ata_tf_load,
818 .tf_read = ata_tf_read,
819 .check_status = ata_check_status,
820 .exec_command = ata_exec_command,
821 .dev_select = ata_std_dev_select,
822
823 .freeze = ata_bmdma_freeze,
824 .thaw = ata_bmdma_thaw,
825 .error_handler = hpt37x_error_handler,
826 .post_internal_cmd = ata_bmdma_post_internal_cmd,
827
828 .bmdma_setup = ata_bmdma_setup,
829 .bmdma_start = hpt370_bmdma_start,
830 .bmdma_stop = hpt370_bmdma_stop,
831 .bmdma_status = ata_bmdma_status,
832
833 .qc_prep = ata_qc_prep,
834 .qc_issue = ata_qc_issue_prot,
835 .eng_timeout = ata_eng_timeout,
836 .data_xfer = ata_pio_data_xfer,
837
838 .irq_handler = ata_interrupt,
839 .irq_clear = ata_bmdma_irq_clear,
840
841 .port_start = ata_port_start,
842 .port_stop = ata_port_stop,
843 .host_stop = ata_host_stop
844 };
845
846 /*
847 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
848 * and DMA mode setting functionality.
849 */
850
851 static struct ata_port_operations hpt372_port_ops = {
852 .port_disable = ata_port_disable,
853 .set_piomode = hpt372_set_piomode,
854 .set_dmamode = hpt372_set_dmamode,
855 .mode_filter = ata_pci_default_filter,
856
857 .tf_load = ata_tf_load,
858 .tf_read = ata_tf_read,
859 .check_status = ata_check_status,
860 .exec_command = ata_exec_command,
861 .dev_select = ata_std_dev_select,
862
863 .freeze = ata_bmdma_freeze,
864 .thaw = ata_bmdma_thaw,
865 .error_handler = hpt37x_error_handler,
866 .post_internal_cmd = ata_bmdma_post_internal_cmd,
867
868 .bmdma_setup = ata_bmdma_setup,
869 .bmdma_start = ata_bmdma_start,
870 .bmdma_stop = hpt37x_bmdma_stop,
871 .bmdma_status = ata_bmdma_status,
872
873 .qc_prep = ata_qc_prep,
874 .qc_issue = ata_qc_issue_prot,
875 .eng_timeout = ata_eng_timeout,
876 .data_xfer = ata_pio_data_xfer,
877
878 .irq_handler = ata_interrupt,
879 .irq_clear = ata_bmdma_irq_clear,
880
881 .port_start = ata_port_start,
882 .port_stop = ata_port_stop,
883 .host_stop = ata_host_stop
884 };
885
886 /*
887 * Configuration for HPT374. Mode setting works like 372 and friends
888 * but we have a different cable detection procedure.
889 */
890
891 static struct ata_port_operations hpt374_port_ops = {
892 .port_disable = ata_port_disable,
893 .set_piomode = hpt372_set_piomode,
894 .set_dmamode = hpt372_set_dmamode,
895 .mode_filter = ata_pci_default_filter,
896
897 .tf_load = ata_tf_load,
898 .tf_read = ata_tf_read,
899 .check_status = ata_check_status,
900 .exec_command = ata_exec_command,
901 .dev_select = ata_std_dev_select,
902
903 .freeze = ata_bmdma_freeze,
904 .thaw = ata_bmdma_thaw,
905 .error_handler = hpt374_error_handler,
906 .post_internal_cmd = ata_bmdma_post_internal_cmd,
907
908 .bmdma_setup = ata_bmdma_setup,
909 .bmdma_start = ata_bmdma_start,
910 .bmdma_stop = hpt37x_bmdma_stop,
911 .bmdma_status = ata_bmdma_status,
912
913 .qc_prep = ata_qc_prep,
914 .qc_issue = ata_qc_issue_prot,
915 .eng_timeout = ata_eng_timeout,
916 .data_xfer = ata_pio_data_xfer,
917
918 .irq_handler = ata_interrupt,
919 .irq_clear = ata_bmdma_irq_clear,
920
921 .port_start = ata_port_start,
922 .port_stop = ata_port_stop,
923 .host_stop = ata_host_stop
924 };
925
926 /**
927 * htp37x_clock_slot - Turn timing to PC clock entry
928 * @freq: Reported frequency timing
929 * @base: Base timing
930 *
931 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
932 * and 3 for 66Mhz)
933 */
934
935 static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
936 {
937 unsigned int f = (base * freq) / 192; /* Mhz */
938 if (f < 40)
939 return 0; /* 33Mhz slot */
940 if (f < 45)
941 return 1; /* 40Mhz slot */
942 if (f < 55)
943 return 2; /* 50Mhz slot */
944 return 3; /* 60Mhz slot */
945 }
946
947 /**
948 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
949 * @dev: PCI device
950 *
951 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
952 * succeeds
953 */
954
955 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
956 {
957 u8 reg5b;
958 u32 reg5c;
959 int tries;
960
961 for(tries = 0; tries < 0x5000; tries++) {
962 udelay(50);
963 pci_read_config_byte(dev, 0x5b, &reg5b);
964 if (reg5b & 0x80) {
965 /* See if it stays set */
966 for(tries = 0; tries < 0x1000; tries ++) {
967 pci_read_config_byte(dev, 0x5b, &reg5b);
968 /* Failed ? */
969 if ((reg5b & 0x80) == 0)
970 return 0;
971 }
972 /* Turn off tuning, we have the DPLL set */
973 pci_read_config_dword(dev, 0x5c, &reg5c);
974 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
975 return 1;
976 }
977 }
978 /* Never went stable */
979 return 0;
980 }
981 /**
982 * hpt37x_init_one - Initialise an HPT37X/302
983 * @dev: PCI device
984 * @id: Entry in match table
985 *
986 * Initialise an HPT37x device. There are some interesting complications
987 * here. Firstly the chip may report 366 and be one of several variants.
988 * Secondly all the timings depend on the clock for the chip which we must
989 * detect and look up
990 *
991 * This is the known chip mappings. It may be missing a couple of later
992 * releases.
993 *
994 * Chip version PCI Rev Notes
995 * HPT366 4 (HPT366) 0 Other driver
996 * HPT366 4 (HPT366) 1 Other driver
997 * HPT368 4 (HPT366) 2 Other driver
998 * HPT370 4 (HPT366) 3 UDMA100
999 * HPT370A 4 (HPT366) 4 UDMA100
1000 * HPT372 4 (HPT366) 5 UDMA133 (1)
1001 * HPT372N 4 (HPT366) 6 Other driver
1002 * HPT372A 5 (HPT372) 1 UDMA133 (1)
1003 * HPT372N 5 (HPT372) 2 Other driver
1004 * HPT302 6 (HPT302) 1 UDMA133
1005 * HPT302N 6 (HPT302) 2 Other driver
1006 * HPT371 7 (HPT371) * UDMA133
1007 * HPT374 8 (HPT374) * UDMA133 4 channel
1008 * HPT372N 9 (HPT372N) * Other driver
1009 *
1010 * (1) UDMA133 support depends on the bus clock
1011 */
1012
1013 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1014 {
1015 /* HPT370 - UDMA100 */
1016 static struct ata_port_info info_hpt370 = {
1017 .sht = &hpt37x_sht,
1018 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1019 .pio_mask = 0x1f,
1020 .mwdma_mask = 0x07,
1021 .udma_mask = 0x3f,
1022 .port_ops = &hpt370_port_ops
1023 };
1024 /* HPT370A - UDMA100 */
1025 static struct ata_port_info info_hpt370a = {
1026 .sht = &hpt37x_sht,
1027 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1028 .pio_mask = 0x1f,
1029 .mwdma_mask = 0x07,
1030 .udma_mask = 0x3f,
1031 .port_ops = &hpt370a_port_ops
1032 };
1033 /* HPT371, 372 and friends - UDMA133 */
1034 static struct ata_port_info info_hpt372 = {
1035 .sht = &hpt37x_sht,
1036 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1037 .pio_mask = 0x1f,
1038 .mwdma_mask = 0x07,
1039 .udma_mask = 0x7f,
1040 .port_ops = &hpt372_port_ops
1041 };
1042 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
1043 static struct ata_port_info info_hpt372_50 = {
1044 .sht = &hpt37x_sht,
1045 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1046 .pio_mask = 0x1f,
1047 .mwdma_mask = 0x07,
1048 .udma_mask = 0x3f,
1049 .port_ops = &hpt372_port_ops
1050 };
1051 /* HPT374 - UDMA133 */
1052 static struct ata_port_info info_hpt374 = {
1053 .sht = &hpt37x_sht,
1054 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1055 .pio_mask = 0x1f,
1056 .mwdma_mask = 0x07,
1057 .udma_mask = 0x7f,
1058 .port_ops = &hpt374_port_ops
1059 };
1060
1061 static const int MHz[4] = { 33, 40, 50, 66 };
1062
1063 struct ata_port_info *port_info[2];
1064 struct ata_port_info *port;
1065
1066 u8 irqmask;
1067 u32 class_rev;
1068 u32 freq;
1069
1070 const struct hpt_chip *chip_table;
1071 int clock_slot;
1072
1073 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1074 class_rev &= 0xFF;
1075
1076 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
1077 /* May be a later chip in disguise. Check */
1078 /* Older chips are in the HPT366 driver. Ignore them */
1079 if (class_rev < 3)
1080 return -ENODEV;
1081 /* N series chips have their own driver. Ignore */
1082 if (class_rev == 6)
1083 return -ENODEV;
1084
1085 switch(class_rev) {
1086 case 3:
1087 port = &info_hpt370;
1088 chip_table = &hpt370;
1089 break;
1090 case 4:
1091 port = &info_hpt370a;
1092 chip_table = &hpt370a;
1093 break;
1094 case 5:
1095 port = &info_hpt372;
1096 chip_table = &hpt372;
1097 break;
1098 default:
1099 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
1100 return -ENODEV;
1101 }
1102 } else {
1103 switch(dev->device) {
1104 case PCI_DEVICE_ID_TTI_HPT372:
1105 /* 372N if rev >= 2*/
1106 if (class_rev >= 2)
1107 return -ENODEV;
1108 port = &info_hpt372;
1109 chip_table = &hpt372a;
1110 break;
1111 case PCI_DEVICE_ID_TTI_HPT302:
1112 /* 302N if rev > 1 */
1113 if (class_rev > 1)
1114 return -ENODEV;
1115 port = &info_hpt372;
1116 /* Check this */
1117 chip_table = &hpt302;
1118 break;
1119 case PCI_DEVICE_ID_TTI_HPT371:
1120 port = &info_hpt372;
1121 chip_table = &hpt371;
1122 break;
1123 case PCI_DEVICE_ID_TTI_HPT374:
1124 chip_table = &hpt374;
1125 port = &info_hpt374;
1126 break;
1127 default:
1128 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1129 return -ENODEV;
1130 }
1131 }
1132 /* Ok so this is a chip we support */
1133
1134 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1135 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1136 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1137 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1138
1139 pci_read_config_byte(dev, 0x5A, &irqmask);
1140 irqmask &= ~0x10;
1141 pci_write_config_byte(dev, 0x5a, irqmask);
1142
1143 /*
1144 * default to pci clock. make sure MA15/16 are set to output
1145 * to prevent drives having problems with 40-pin cables. Needed
1146 * for some drives such as IBM-DTLA which will not enter ready
1147 * state on reset when PDIAG is a input.
1148 */
1149
1150 pci_write_config_byte(dev, 0x5b, 0x23);
1151
1152 pci_read_config_dword(dev, 0x70, &freq);
1153 if ((freq >> 12) != 0xABCDE) {
1154 int i;
1155 u8 sr;
1156 u32 total = 0;
1157
1158 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
1159
1160 /* This is the process the HPT371 BIOS is reported to use */
1161 for(i = 0; i < 128; i++) {
1162 pci_read_config_byte(dev, 0x78, &sr);
1163 total += sr;
1164 udelay(15);
1165 }
1166 freq = total / 128;
1167 }
1168 freq &= 0x1FF;
1169
1170 /*
1171 * Turn the frequency check into a band and then find a timing
1172 * table to match it.
1173 */
1174
1175 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1176 if (chip_table->clocks[clock_slot] == NULL) {
1177 /*
1178 * We need to try PLL mode instead
1179 */
1180 unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192;
1181 unsigned int f_high = f_low + 2;
1182 int adjust;
1183
1184 for(adjust = 0; adjust < 8; adjust++) {
1185 if (hpt37x_calibrate_dpll(dev))
1186 break;
1187 /* See if it'll settle at a fractionally different clock */
1188 if ((adjust & 3) == 3) {
1189 f_low --;
1190 f_high ++;
1191 }
1192 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1193 }
1194 if (adjust == 8) {
1195 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1196 return -ENODEV;
1197 }
1198 /* Check if this works for all cases */
1199 port->private_data = (void *)hpt370_timings_66;
1200
1201 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1202 } else {
1203 port->private_data = (void *)chip_table->clocks[clock_slot];
1204 /*
1205 * Perform a final fixup. The 371 and 372 clock determines
1206 * if UDMA133 is available.
1207 */
1208
1209 if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
1210 printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
1211 if (port == &info_hpt372)
1212 port = &info_hpt372_50;
1213 else BUG();
1214 }
1215 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
1216 }
1217 port_info[0] = port_info[1] = port;
1218 /* Now kick off ATA set up */
1219 return ata_pci_init_one(dev, port_info, 2);
1220 }
1221
1222 static struct pci_device_id hpt37x[] = {
1223 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
1224 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371), },
1225 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372), },
1226 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374), },
1227 { PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302), },
1228 { 0, },
1229 };
1230
1231 static struct pci_driver hpt37x_pci_driver = {
1232 .name = DRV_NAME,
1233 .id_table = hpt37x,
1234 .probe = hpt37x_init_one,
1235 .remove = ata_pci_remove_one
1236 };
1237
1238 static int __init hpt37x_init(void)
1239 {
1240 return pci_register_driver(&hpt37x_pci_driver);
1241 }
1242
1243
1244 static void __exit hpt37x_exit(void)
1245 {
1246 pci_unregister_driver(&hpt37x_pci_driver);
1247 }
1248
1249
1250 MODULE_AUTHOR("Alan Cox");
1251 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1252 MODULE_LICENSE("GPL");
1253 MODULE_DEVICE_TABLE(pci, hpt37x);
1254 MODULE_VERSION(DRV_VERSION);
1255
1256 module_init(hpt37x_init);
1257 module_exit(hpt37x_exit);
Linux kernel - Deliverables
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