drivers/ata/pata_hpt3x2n.c

   1 /*
   2  * Libata driver for the highpoint 372N and 302N UDMA66 ATA controllers.
   3  *
   4  * This driver is heavily based upon:
   5  *
   6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7  *
   8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10  * Portions Copyright (C) 2003          Red Hat Inc
  11  * Portions Copyright (C) 2005-2007     MontaVista Software, Inc.
  12  *
  13  *
  14  * TODO
  15  *      Work out best PLL policy
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/delay.h>
  24 #include <scsi/scsi_host.h>
  25 #include <linux/libata.h>
  26
  27 #define DRV_NAME        "pata_hpt3x2n"
  28 #define DRV_VERSION     "0.3.4"
  29
  30 enum {
  31         HPT_PCI_FAST    =       (1 << 31),
  32         PCI66           =       (1 << 1),
  33         USE_DPLL        =       (1 << 0)
  34 };
  35
  36 struct hpt_clock {
  37         u8      xfer_speed;
  38         u32     timing;
  39 };
  40
  41 struct hpt_chip {
  42         const char *name;
  43         struct hpt_clock *clocks[3];
  44 };
  45
  46 /* key for bus clock timings
  47  * bit
  48  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  49  *        DMA. cycles = value + 1
  50  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  51  *        DMA. cycles = value + 1
  52  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  53  *        register access.
  54  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  55  *        register access.
  56  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  57  *        during task file register access.
  58  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  59  *        xfer.
  60  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  61  *        register access.
  62  * 28     UDMA enable
  63  * 29     DMA enable
  64  * 30     PIO_MST enable. if set, the chip is in bus master mode during
  65  *        PIO.
  66  * 31     FIFO enable.
  67  */
  68
  69 /* 66MHz DPLL clocks */
  70
  71 static struct hpt_clock hpt3x2n_clocks[] = {
  72         {       XFER_UDMA_7,    0x1c869c62      },
  73         {       XFER_UDMA_6,    0x1c869c62      },
  74         {       XFER_UDMA_5,    0x1c8a9c62      },
  75         {       XFER_UDMA_4,    0x1c8a9c62      },
  76         {       XFER_UDMA_3,    0x1c8e9c62      },
  77         {       XFER_UDMA_2,    0x1c929c62      },
  78         {       XFER_UDMA_1,    0x1c9a9c62      },
  79         {       XFER_UDMA_0,    0x1c829c62      },
  80
  81         {       XFER_MW_DMA_2,  0x2c829c62      },
  82         {       XFER_MW_DMA_1,  0x2c829c66      },
  83         {       XFER_MW_DMA_0,  0x2c829d2c      },
  84
  85         {       XFER_PIO_4,     0x0c829c62      },
  86         {       XFER_PIO_3,     0x0c829c84      },
  87         {       XFER_PIO_2,     0x0c829ca6      },
  88         {       XFER_PIO_1,     0x0d029d26      },
  89         {       XFER_PIO_0,     0x0d029d5e      },
  90         {       0,              0x0d029d5e      }
  91 };
  92
  93 /**
  94  *      hpt3x2n_find_mode       -       reset the hpt3x2n bus
  95  *      @ap: ATA port
  96  *      @speed: transfer mode
  97  *
  98  *      Return the 32bit register programming information for this channel
  99  *      that matches the speed provided. For the moment the clocks table
 100  *      is hard coded but easy to change. This will be needed if we use
 101  *      different DPLLs
 102  */
 103
 104 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
 105 {
 106         struct hpt_clock *clocks = hpt3x2n_clocks;
 107
 108         while(clocks->xfer_speed) {
 109                 if (clocks->xfer_speed == speed)
 110                         return clocks->timing;
 111                 clocks++;
 112         }
 113         BUG();
 114         return 0xffffffffU;     /* silence compiler warning */
 115 }
 116
 117 /**
 118  *      hpt3x2n_cable_detect    -       Detect the cable type
 119  *      @ap: ATA port to detect on
 120  *
 121  *      Return the cable type attached to this port
 122  */
 123
 124 static int hpt3x2n_cable_detect(struct ata_port *ap)
 125 {
 126         u8 scr2, ata66;
 127         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 128
 129         pci_read_config_byte(pdev, 0x5B, &scr2);
 130         pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
 131         /* Cable register now active */
 132         pci_read_config_byte(pdev, 0x5A, &ata66);
 133         /* Restore state */
 134         pci_write_config_byte(pdev, 0x5B, scr2);
 135
 136         if (ata66 & (1 << ap->port_no))
 137                 return ATA_CBL_PATA40;
 138         else
 139                 return ATA_CBL_PATA80;
 140 }
 141
 142 /**
 143  *      hpt3x2n_pre_reset       -       reset the hpt3x2n bus
 144  *      @link: ATA link to reset
 145  *      @deadline: deadline jiffies for the operation
 146  *
 147  *      Perform the initial reset handling for the 3x2n series controllers.
 148  *      Reset the hardware and state machine,
 149  */
 150
 151 static int hpt3xn_pre_reset(struct ata_link *link, unsigned long deadline)
 152 {
 153         struct ata_port *ap = link->ap;
 154         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 155         /* Reset the state machine */
 156         pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
 157         udelay(100);
 158
 159         return ata_std_prereset(link, deadline);
 160 }
 161
 162 /**
 163  *      hpt3x2n_error_handler   -       probe the hpt3x2n bus
 164  *      @ap: ATA port to reset
 165  *
 166  *      Perform the probe reset handling for the 3x2N
 167  */
 168
 169 static void hpt3x2n_error_handler(struct ata_port *ap)
 170 {
 171         ata_bmdma_drive_eh(ap, hpt3xn_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
 172 }
 173
 174 /**
 175  *      hpt3x2n_set_piomode             -       PIO setup
 176  *      @ap: ATA interface
 177  *      @adev: device on the interface
 178  *
 179  *      Perform PIO mode setup.
 180  */
 181
 182 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
 183 {
 184         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 185         u32 addr1, addr2;
 186         u32 reg;
 187         u32 mode;
 188         u8 fast;
 189
 190         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 191         addr2 = 0x51 + 4 * ap->port_no;
 192
 193         /* Fast interrupt prediction disable, hold off interrupt disable */
 194         pci_read_config_byte(pdev, addr2, &fast);
 195         fast &= ~0x07;
 196         pci_write_config_byte(pdev, addr2, fast);
 197
 198         pci_read_config_dword(pdev, addr1, &reg);
 199         mode = hpt3x2n_find_mode(ap, adev->pio_mode);
 200         mode &= ~0x8000000;     /* No FIFO in PIO */
 201         mode &= ~0x30070000;    /* Leave config bits alone */
 202         reg &= 0x30070000;      /* Strip timing bits */
 203         pci_write_config_dword(pdev, addr1, reg | mode);
 204 }
 205
 206 /**
 207  *      hpt3x2n_set_dmamode             -       DMA timing setup
 208  *      @ap: ATA interface
 209  *      @adev: Device being configured
 210  *
 211  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 212  *      PIO, load the mode number and then set MWDMA or UDMA flag.
 213  */
 214
 215 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 216 {
 217         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 218         u32 addr1, addr2;
 219         u32 reg;
 220         u32 mode;
 221         u8 fast;
 222
 223         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 224         addr2 = 0x51 + 4 * ap->port_no;
 225
 226         /* Fast interrupt prediction disable, hold off interrupt disable */
 227         pci_read_config_byte(pdev, addr2, &fast);
 228         fast &= ~0x07;
 229         pci_write_config_byte(pdev, addr2, fast);
 230
 231         pci_read_config_dword(pdev, addr1, &reg);
 232         mode = hpt3x2n_find_mode(ap, adev->dma_mode);
 233         mode |= 0x8000000;      /* FIFO in MWDMA or UDMA */
 234         mode &= ~0xC0000000;    /* Leave config bits alone */
 235         reg &= 0xC0000000;      /* Strip timing bits */
 236         pci_write_config_dword(pdev, addr1, reg | mode);
 237 }
 238
 239 /**
 240  *      hpt3x2n_bmdma_end               -       DMA engine stop
 241  *      @qc: ATA command
 242  *
 243  *      Clean up after the HPT3x2n and later DMA engine
 244  */
 245
 246 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
 247 {
 248         struct ata_port *ap = qc->ap;
 249         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 250         int mscreg = 0x50 + 2 * ap->port_no;
 251         u8 bwsr_stat, msc_stat;
 252
 253         pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
 254         pci_read_config_byte(pdev, mscreg, &msc_stat);
 255         if (bwsr_stat & (1 << ap->port_no))
 256                 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
 257         ata_bmdma_stop(qc);
 258 }
 259
 260 /**
 261  *      hpt3x2n_set_clock       -       clock control
 262  *      @ap: ATA port
 263  *      @source: 0x21 or 0x23 for PLL or PCI sourced clock
 264  *
 265  *      Switch the ATA bus clock between the PLL and PCI clock sources
 266  *      while correctly isolating the bus and resetting internal logic
 267  *
 268  *      We must use the DPLL for
 269  *      -       writing
 270  *      -       second channel UDMA7 (SATA ports) or higher
 271  *      -       66MHz PCI
 272  *
 273  *      or we will underclock the device and get reduced performance.
 274  */
 275
 276 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
 277 {
 278         void __iomem *bmdma = ap->ioaddr.bmdma_addr;
 279
 280         /* Tristate the bus */
 281         iowrite8(0x80, bmdma+0x73);
 282         iowrite8(0x80, bmdma+0x77);
 283
 284         /* Switch clock and reset channels */
 285         iowrite8(source, bmdma+0x7B);
 286         iowrite8(0xC0, bmdma+0x79);
 287
 288         /* Reset state machines */
 289         iowrite8(0x37, bmdma+0x70);
 290         iowrite8(0x37, bmdma+0x74);
 291
 292         /* Complete reset */
 293         iowrite8(0x00, bmdma+0x79);
 294
 295         /* Reconnect channels to bus */
 296         iowrite8(0x00, bmdma+0x73);
 297         iowrite8(0x00, bmdma+0x77);
 298 }
 299
 300 /* Check if our partner interface is busy */
 301
 302 static int hpt3x2n_pair_idle(struct ata_port *ap)
 303 {
 304         struct ata_host *host = ap->host;
 305         struct ata_port *pair = host->ports[ap->port_no ^ 1];
 306
 307         if (pair->hsm_task_state == HSM_ST_IDLE)
 308                 return 1;
 309         return 0;
 310 }
 311
 312 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
 313 {
 314         long flags = (long)ap->host->private_data;
 315         /* See if we should use the DPLL */
 316         if (writing)
 317                 return USE_DPLL;        /* Needed for write */
 318         if (flags & PCI66)
 319                 return USE_DPLL;        /* Needed at 66Mhz */
 320         return 0;
 321 }
 322
 323 static unsigned int hpt3x2n_qc_issue_prot(struct ata_queued_cmd *qc)
 324 {
 325         struct ata_taskfile *tf = &qc->tf;
 326         struct ata_port *ap = qc->ap;
 327         int flags = (long)ap->host->private_data;
 328
 329         if (hpt3x2n_pair_idle(ap)) {
 330                 int dpll = hpt3x2n_use_dpll(ap, (tf->flags & ATA_TFLAG_WRITE));
 331                 if ((flags & USE_DPLL) != dpll) {
 332                         if (dpll == 1)
 333                                 hpt3x2n_set_clock(ap, 0x21);
 334                         else
 335                                 hpt3x2n_set_clock(ap, 0x23);
 336                 }
 337         }
 338         return ata_qc_issue_prot(qc);
 339 }
 340
 341 static struct scsi_host_template hpt3x2n_sht = {
 342         ATA_BMDMA_SHT(DRV_NAME),
 343 };
 344
 345 /*
 346  *      Configuration for HPT3x2n.
 347  */
 348
 349 static struct ata_port_operations hpt3x2n_port_ops = {
 350         .set_piomode    = hpt3x2n_set_piomode,
 351         .set_dmamode    = hpt3x2n_set_dmamode,
 352         .mode_filter    = ata_pci_default_filter,
 353
 354         .tf_load        = ata_tf_load,
 355         .tf_read        = ata_tf_read,
 356         .check_status   = ata_check_status,
 357         .exec_command   = ata_exec_command,
 358         .dev_select     = ata_std_dev_select,
 359
 360         .freeze         = ata_bmdma_freeze,
 361         .thaw           = ata_bmdma_thaw,
 362         .error_handler  = hpt3x2n_error_handler,
 363         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 364         .cable_detect   = hpt3x2n_cable_detect,
 365
 366         .bmdma_setup    = ata_bmdma_setup,
 367         .bmdma_start    = ata_bmdma_start,
 368         .bmdma_stop     = hpt3x2n_bmdma_stop,
 369         .bmdma_status   = ata_bmdma_status,
 370
 371         .qc_prep        = ata_qc_prep,
 372         .qc_issue       = hpt3x2n_qc_issue_prot,
 373
 374         .data_xfer      = ata_data_xfer,
 375
 376         .irq_handler    = ata_interrupt,
 377         .irq_clear      = ata_bmdma_irq_clear,
 378         .irq_on         = ata_irq_on,
 379
 380         .port_start     = ata_sff_port_start,
 381 };
 382
 383 /**
 384  *      hpt3xn_calibrate_dpll           -       Calibrate the DPLL loop
 385  *      @dev: PCI device
 386  *
 387  *      Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
 388  *      succeeds
 389  */
 390
 391 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
 392 {
 393         u8 reg5b;
 394         u32 reg5c;
 395         int tries;
 396
 397         for(tries = 0; tries < 0x5000; tries++) {
 398                 udelay(50);
 399                 pci_read_config_byte(dev, 0x5b, &reg5b);
 400                 if (reg5b & 0x80) {
 401                         /* See if it stays set */
 402                         for(tries = 0; tries < 0x1000; tries ++) {
 403                                 pci_read_config_byte(dev, 0x5b, &reg5b);
 404                                 /* Failed ? */
 405                                 if ((reg5b & 0x80) == 0)
 406                                         return 0;
 407                         }
 408                         /* Turn off tuning, we have the DPLL set */
 409                         pci_read_config_dword(dev, 0x5c, &reg5c);
 410                         pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
 411                         return 1;
 412                 }
 413         }
 414         /* Never went stable */
 415         return 0;
 416 }
 417
 418 static int hpt3x2n_pci_clock(struct pci_dev *pdev)
 419 {
 420         unsigned long freq;
 421         u32 fcnt;
 422         unsigned long iobase = pci_resource_start(pdev, 4);
 423
 424         fcnt = inl(iobase + 0x90);      /* Not PCI readable for some chips */
 425         if ((fcnt >> 12) != 0xABCDE) {
 426                 printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n");
 427                 return 33;      /* Not BIOS set */
 428         }
 429         fcnt &= 0x1FF;
 430
 431         freq = (fcnt * 77) / 192;
 432
 433         /* Clamp to bands */
 434         if (freq < 40)
 435                 return 33;
 436         if (freq < 45)
 437                 return 40;
 438         if (freq < 55)
 439                 return 50;
 440         return 66;
 441 }
 442
 443 /**
 444  *      hpt3x2n_init_one                -       Initialise an HPT37X/302
 445  *      @dev: PCI device
 446  *      @id: Entry in match table
 447  *
 448  *      Initialise an HPT3x2n device. There are some interesting complications
 449  *      here. Firstly the chip may report 366 and be one of several variants.
 450  *      Secondly all the timings depend on the clock for the chip which we must
 451  *      detect and look up
 452  *
 453  *      This is the known chip mappings. It may be missing a couple of later
 454  *      releases.
 455  *
 456  *      Chip version            PCI             Rev     Notes
 457  *      HPT372                  4 (HPT366)      5       Other driver
 458  *      HPT372N                 4 (HPT366)      6       UDMA133
 459  *      HPT372                  5 (HPT372)      1       Other driver
 460  *      HPT372N                 5 (HPT372)      2       UDMA133
 461  *      HPT302                  6 (HPT302)      *       Other driver
 462  *      HPT302N                 6 (HPT302)      > 1     UDMA133
 463  *      HPT371                  7 (HPT371)      *       Other driver
 464  *      HPT371N                 7 (HPT371)      > 1     UDMA133
 465  *      HPT374                  8 (HPT374)      *       Other driver
 466  *      HPT372N                 9 (HPT372N)     *       UDMA133
 467  *
 468  *      (1) UDMA133 support depends on the bus clock
 469  *
 470  *      To pin down             HPT371N
 471  */
 472
 473 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 474 {
 475         /* HPT372N and friends - UDMA133 */
 476         static const struct ata_port_info info = {
 477                 .sht = &hpt3x2n_sht,
 478                 .flags = ATA_FLAG_SLAVE_POSS,
 479                 .pio_mask = 0x1f,
 480                 .mwdma_mask = 0x07,
 481                 .udma_mask = ATA_UDMA6,
 482                 .port_ops = &hpt3x2n_port_ops
 483         };
 484         struct ata_port_info port = info;
 485         const struct ata_port_info *ppi[] = { &port, NULL };
 486
 487         u8 irqmask;
 488         u32 class_rev;
 489
 490         unsigned int pci_mhz;
 491         unsigned int f_low, f_high;
 492         int adjust;
 493         unsigned long iobase = pci_resource_start(dev, 4);
 494         int rc;
 495
 496         rc = pcim_enable_device(dev);
 497         if (rc)
 498                 return rc;
 499
 500         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 501         class_rev &= 0xFF;
 502
 503         switch(dev->device) {
 504                 case PCI_DEVICE_ID_TTI_HPT366:
 505                         if (class_rev < 6)
 506                                 return -ENODEV;
 507                         break;
 508                 case PCI_DEVICE_ID_TTI_HPT371:
 509                         if (class_rev < 2)
 510                                 return -ENODEV;
 511                         /* 371N if rev > 1 */
 512                         break;
 513                 case PCI_DEVICE_ID_TTI_HPT372:
 514                         /* 372N if rev >= 2*/
 515                         if (class_rev < 2)
 516                                 return -ENODEV;
 517                         break;
 518                 case PCI_DEVICE_ID_TTI_HPT302:
 519                         if (class_rev < 2)
 520                                 return -ENODEV;
 521                         break;
 522                 case PCI_DEVICE_ID_TTI_HPT372N:
 523                         break;
 524                 default:
 525                         printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device);
 526                         return -ENODEV;
 527         }
 528
 529         /* Ok so this is a chip we support */
 530
 531         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 532         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 533         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 534         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 535
 536         pci_read_config_byte(dev, 0x5A, &irqmask);
 537         irqmask &= ~0x10;
 538         pci_write_config_byte(dev, 0x5a, irqmask);
 539
 540         /*
 541          * HPT371 chips physically have only one channel, the secondary one,
 542          * but the primary channel registers do exist!  Go figure...
 543          * So,  we manually disable the non-existing channel here
 544          * (if the BIOS hasn't done this already).
 545          */
 546         if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
 547                 u8 mcr1;
 548                 pci_read_config_byte(dev, 0x50, &mcr1);
 549                 mcr1 &= ~0x04;
 550                 pci_write_config_byte(dev, 0x50, mcr1);
 551         }
 552
 553         /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
 554            50 for UDMA100. Right now we always use 66 */
 555
 556         pci_mhz = hpt3x2n_pci_clock(dev);
 557
 558         f_low = (pci_mhz * 48) / 66;    /* PCI Mhz for 66Mhz DPLL */
 559         f_high = f_low + 2;             /* Tolerance */
 560
 561         pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
 562         /* PLL clock */
 563         pci_write_config_byte(dev, 0x5B, 0x21);
 564
 565         /* Unlike the 37x we don't try jiggling the frequency */
 566         for(adjust = 0; adjust < 8; adjust++) {
 567                 if (hpt3xn_calibrate_dpll(dev))
 568                         break;
 569                 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
 570         }
 571         if (adjust == 8) {
 572                 printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n");
 573                 return -ENODEV;
 574         }
 575
 576         printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n",
 577                pci_mhz);
 578         /* Set our private data up. We only need a few flags so we use
 579            it directly */
 580         port.private_data = NULL;
 581         if (pci_mhz > 60) {
 582                 port.private_data = (void *)PCI66;
 583                 /*
 584                  * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
 585                  * the MISC. register to stretch the UltraDMA Tss timing.
 586                  * NOTE: This register is only writeable via I/O space.
 587                  */
 588                 if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
 589                         outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
 590         }
 591
 592         /* Now kick off ATA set up */
 593         return ata_pci_init_one(dev, ppi);
 594 }
 595
 596 static const struct pci_device_id hpt3x2n[] = {
 597         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 598         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
 599         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
 600         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
 601         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
 602
 603         { },
 604 };
 605
 606 static struct pci_driver hpt3x2n_pci_driver = {
 607         .name           = DRV_NAME,
 608         .id_table       = hpt3x2n,
 609         .probe          = hpt3x2n_init_one,
 610         .remove         = ata_pci_remove_one
 611 };
 612
 613 static int __init hpt3x2n_init(void)
 614 {
 615         return pci_register_driver(&hpt3x2n_pci_driver);
 616 }
 617
 618 static void __exit hpt3x2n_exit(void)
 619 {
 620         pci_unregister_driver(&hpt3x2n_pci_driver);
 621 }
 622
 623 MODULE_AUTHOR("Alan Cox");
 624 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3x2n/30x");
 625 MODULE_LICENSE("GPL");
 626 MODULE_DEVICE_TABLE(pci, hpt3x2n);
 627 MODULE_VERSION(DRV_VERSION);
 628
 629 module_init(hpt3x2n_init);
 630 module_exit(hpt3x2n_exit);