drivers/ata/pata_mpiix.c

   1 /*
   2  * pata_mpiix.c         - Intel MPIIX PATA for new ATA layer
   3  *                        (C) 2005-2006 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *
   6  * The MPIIX is different enough to the PIIX4 and friends that we give it
   7  * a separate driver. The old ide/pci code handles this by just not tuning
   8  * MPIIX at all.
   9  *
  10  * The MPIIX also differs in another important way from the majority of PIIX
  11  * devices. The chip is a bridge (pardon the pun) between the old world of
  12  * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
  13  * IDE controller is not decoded in PCI space and the chip does not claim to
  14  * be IDE class PCI. This requires slightly non-standard probe logic compared
  15  * with PCI IDE and also that we do not disable the device when our driver is
  16  * unloaded (as it has many other functions).
  17  *
  18  * The driver conciously keeps this logic internally to avoid pushing quirky
  19  * PATA history into the clean libata layer.
  20  *
  21  * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
  22  * hard disk present this driver will not detect it. This is not a bug. In this
  23  * configuration the secondary port of the MPIIX is disabled and the addresses
  24  * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
  25  * to operate.
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <scsi/scsi_host.h>
  35 #include <linux/libata.h>
  36
  37 #define DRV_NAME "pata_mpiix"
  38 #define DRV_VERSION "0.7.6"
  39
  40 enum {
  41         IDETIM = 0x6C,          /* IDE control register */
  42         IORDY = (1 << 1),
  43         PPE = (1 << 2),
  44         FTIM = (1 << 0),
  45         ENABLED = (1 << 15),
  46         SECONDARY = (1 << 14)
  47 };
  48
  49 static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
  50 {
  51         struct ata_port *ap = link->ap;
  52         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  53         static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
  54
  55         if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
  56                 return -ENOENT;
  57
  58         return ata_std_prereset(link, deadline);
  59 }
  60
  61 /**
  62  *      mpiix_error_handler             -       probe reset
  63  *      @ap: ATA port
  64  *
  65  *      Perform the ATA probe and bus reset sequence plus specific handling
  66  *      for this hardware. The MPIIX has the enable bits in a different place
  67  *      to PIIX4 and friends. As a pure PIO device it has no cable detect
  68  */
  69
  70 static void mpiix_error_handler(struct ata_port *ap)
  71 {
  72         ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  73 }
  74
  75 /**
  76  *      mpiix_set_piomode       -       set initial PIO mode data
  77  *      @ap: ATA interface
  78  *      @adev: ATA device
  79  *
  80  *      Called to do the PIO mode setup. The MPIIX allows us to program the
  81  *      IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
  82  *      prefetching or IORDY are used.
  83  *
  84  *      This would get very ugly because we can only program timing for one
  85  *      device at a time, the other gets PIO0. Fortunately libata calls
  86  *      our qc_issue_prot command before a command is issued so we can
  87  *      flip the timings back and forth to reduce the pain.
  88  */
  89
  90 static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
  91 {
  92         int control = 0;
  93         int pio = adev->pio_mode - XFER_PIO_0;
  94         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  95         u16 idetim;
  96         static const     /* ISP  RTC */
  97         u8 timings[][2] = { { 0, 0 },
  98                             { 0, 0 },
  99                             { 1, 0 },
 100                             { 2, 1 },
 101                             { 2, 3 }, };
 102
 103         pci_read_config_word(pdev, IDETIM, &idetim);
 104
 105         /* Mask the IORDY/TIME/PPE for this device */
 106         if (adev->class == ATA_DEV_ATA)
 107                 control |= PPE;         /* Enable prefetch/posting for disk */
 108         if (ata_pio_need_iordy(adev))
 109                 control |= IORDY;
 110         if (pio > 1)
 111                 control |= FTIM;        /* This drive is on the fast timing bank */
 112
 113         /* Mask out timing and clear both TIME bank selects */
 114         idetim &= 0xCCEE;
 115         idetim &= ~(0x07  << (4 * adev->devno));
 116         idetim |= control << (4 * adev->devno);
 117
 118         idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 119         pci_write_config_word(pdev, IDETIM, idetim);
 120
 121         /* We use ap->private_data as a pointer to the device currently
 122            loaded for timing */
 123         ap->private_data = adev;
 124 }
 125
 126 /**
 127  *      mpiix_qc_issue_prot     -       command issue
 128  *      @qc: command pending
 129  *
 130  *      Called when the libata layer is about to issue a command. We wrap
 131  *      this interface so that we can load the correct ATA timings if
 132  *      necessary. Our logic also clears TIME0/TIME1 for the other device so
 133  *      that, even if we get this wrong, cycles to the other device will
 134  *      be made PIO0.
 135  */
 136
 137 static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
 138 {
 139         struct ata_port *ap = qc->ap;
 140         struct ata_device *adev = qc->dev;
 141
 142         /* If modes have been configured and the channel data is not loaded
 143            then load it. We have to check if pio_mode is set as the core code
 144            does not set adev->pio_mode to XFER_PIO_0 while probing as would be
 145            logical */
 146
 147         if (adev->pio_mode && adev != ap->private_data)
 148                 mpiix_set_piomode(ap, adev);
 149
 150         return ata_qc_issue_prot(qc);
 151 }
 152
 153 static struct scsi_host_template mpiix_sht = {
 154         ATA_PIO_SHT(DRV_NAME),
 155 };
 156
 157 static struct ata_port_operations mpiix_port_ops = {
 158         .inherits       = &ata_sff_port_ops,
 159         .qc_issue       = mpiix_qc_issue_prot,
 160         .cable_detect   = ata_cable_40wire,
 161         .set_piomode    = mpiix_set_piomode,
 162         .error_handler  = mpiix_error_handler,
 163 };
 164
 165 static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 166 {
 167         /* Single threaded by the PCI probe logic */
 168         static int printed_version;
 169         struct ata_host *host;
 170         struct ata_port *ap;
 171         void __iomem *cmd_addr, *ctl_addr;
 172         u16 idetim;
 173         int cmd, ctl, irq;
 174
 175         if (!printed_version++)
 176                 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
 177
 178         host = ata_host_alloc(&dev->dev, 1);
 179         if (!host)
 180                 return -ENOMEM;
 181         ap = host->ports[0];
 182
 183         /* MPIIX has many functions which can be turned on or off according
 184            to other devices present. Make sure IDE is enabled before we try
 185            and use it */
 186
 187         pci_read_config_word(dev, IDETIM, &idetim);
 188         if (!(idetim & ENABLED))
 189                 return -ENODEV;
 190
 191         /* See if it's primary or secondary channel... */
 192         if (!(idetim & SECONDARY)) {
 193                 cmd = 0x1F0;
 194                 ctl = 0x3F6;
 195                 irq = 14;
 196         } else {
 197                 cmd = 0x170;
 198                 ctl = 0x376;
 199                 irq = 15;
 200         }
 201
 202         cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
 203         ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
 204         if (!cmd_addr || !ctl_addr)
 205                 return -ENOMEM;
 206
 207         ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
 208
 209         /* We do our own plumbing to avoid leaking special cases for whacko
 210            ancient hardware into the core code. There are two issues to
 211            worry about.  #1 The chip is a bridge so if in legacy mode and
 212            without BARs set fools the setup.  #2 If you pci_disable_device
 213            the MPIIX your box goes castors up */
 214
 215         ap->ops = &mpiix_port_ops;
 216         ap->pio_mask = 0x1F;
 217         ap->flags |= ATA_FLAG_SLAVE_POSS;
 218
 219         ap->ioaddr.cmd_addr = cmd_addr;
 220         ap->ioaddr.ctl_addr = ctl_addr;
 221         ap->ioaddr.altstatus_addr = ctl_addr;
 222
 223         /* Let libata fill in the port details */
 224         ata_std_ports(&ap->ioaddr);
 225
 226         /* activate host */
 227         return ata_host_activate(host, irq, ata_interrupt, IRQF_SHARED,
 228                                  &mpiix_sht);
 229 }
 230
 231 static const struct pci_device_id mpiix[] = {
 232         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
 233
 234         { },
 235 };
 236
 237 static struct pci_driver mpiix_pci_driver = {
 238         .name           = DRV_NAME,
 239         .id_table       = mpiix,
 240         .probe          = mpiix_init_one,
 241         .remove         = ata_pci_remove_one,
 242 #ifdef CONFIG_PM
 243         .suspend        = ata_pci_device_suspend,
 244         .resume         = ata_pci_device_resume,
 245 #endif
 246 };
 247
 248 static int __init mpiix_init(void)
 249 {
 250         return pci_register_driver(&mpiix_pci_driver);
 251 }
 252
 253 static void __exit mpiix_exit(void)
 254 {
 255         pci_unregister_driver(&mpiix_pci_driver);
 256 }
 257
 258 MODULE_AUTHOR("Alan Cox");
 259 MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
 260 MODULE_LICENSE("GPL");
 261 MODULE_DEVICE_TABLE(pci, mpiix);
 262 MODULE_VERSION(DRV_VERSION);
 263
 264 module_init(mpiix_init);
 265 module_exit(mpiix_exit);