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libata: implement and use SHT initializers
[deliverable/linux.git] / drivers / ata / pata_pdc2027x.c
1 /*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0"
39 #undef PDC_DEBUG
40
41 #ifdef PDC_DEBUG
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
43 #else
44 #define PDPRINTK(fmt, args...)
45 #endif
46
47 enum {
48 PDC_MMIO_BAR = 5,
49
50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63 };
64
65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
66 static void pdc2027x_error_handler(struct ata_port *ap);
67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
70 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71 static int pdc2027x_cable_detect(struct ata_port *ap);
72 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
73
74 /*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82 static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84 } pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90 };
91
92 static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94 } pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98 };
99
100 static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102 } pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110 };
111
112 static const struct pci_device_id pdc2027x_pci_tbl[] = {
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
121 { } /* terminate list */
122 };
123
124 static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
128 .remove = ata_pci_remove_one,
129 };
130
131 static struct scsi_host_template pdc2027x_sht = {
132 ATA_BMDMA_SHT(DRV_NAME),
133 };
134
135 static struct ata_port_operations pdc2027x_pata100_ops = {
136 .mode_filter = ata_pci_default_filter,
137
138 .tf_load = ata_tf_load,
139 .tf_read = ata_tf_read,
140 .check_status = ata_check_status,
141 .exec_command = ata_exec_command,
142 .dev_select = ata_std_dev_select,
143
144 .check_atapi_dma = pdc2027x_check_atapi_dma,
145 .bmdma_setup = ata_bmdma_setup,
146 .bmdma_start = ata_bmdma_start,
147 .bmdma_stop = ata_bmdma_stop,
148 .bmdma_status = ata_bmdma_status,
149 .qc_prep = ata_qc_prep,
150 .qc_issue = ata_qc_issue_prot,
151 .data_xfer = ata_data_xfer,
152
153 .freeze = ata_bmdma_freeze,
154 .thaw = ata_bmdma_thaw,
155 .error_handler = pdc2027x_error_handler,
156 .post_internal_cmd = ata_bmdma_post_internal_cmd,
157 .cable_detect = pdc2027x_cable_detect,
158
159 .irq_clear = ata_bmdma_irq_clear,
160 .irq_on = ata_irq_on,
161
162 .port_start = ata_sff_port_start,
163 };
164
165 static struct ata_port_operations pdc2027x_pata133_ops = {
166 .set_piomode = pdc2027x_set_piomode,
167 .set_dmamode = pdc2027x_set_dmamode,
168 .set_mode = pdc2027x_set_mode,
169 .mode_filter = pdc2027x_mode_filter,
170
171 .tf_load = ata_tf_load,
172 .tf_read = ata_tf_read,
173 .check_status = ata_check_status,
174 .exec_command = ata_exec_command,
175 .dev_select = ata_std_dev_select,
176
177 .check_atapi_dma = pdc2027x_check_atapi_dma,
178 .bmdma_setup = ata_bmdma_setup,
179 .bmdma_start = ata_bmdma_start,
180 .bmdma_stop = ata_bmdma_stop,
181 .bmdma_status = ata_bmdma_status,
182 .qc_prep = ata_qc_prep,
183 .qc_issue = ata_qc_issue_prot,
184 .data_xfer = ata_data_xfer,
185
186 .freeze = ata_bmdma_freeze,
187 .thaw = ata_bmdma_thaw,
188 .error_handler = pdc2027x_error_handler,
189 .post_internal_cmd = ata_bmdma_post_internal_cmd,
190 .cable_detect = pdc2027x_cable_detect,
191
192 .irq_clear = ata_bmdma_irq_clear,
193 .irq_on = ata_irq_on,
194
195 .port_start = ata_sff_port_start,
196 };
197
198 static struct ata_port_info pdc2027x_port_info[] = {
199 /* PDC_UDMA_100 */
200 {
201 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
202 ATA_FLAG_MMIO,
203 .pio_mask = 0x1f, /* pio0-4 */
204 .mwdma_mask = 0x07, /* mwdma0-2 */
205 .udma_mask = ATA_UDMA5, /* udma0-5 */
206 .port_ops = &pdc2027x_pata100_ops,
207 },
208 /* PDC_UDMA_133 */
209 {
210 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
211 ATA_FLAG_MMIO,
212 .pio_mask = 0x1f, /* pio0-4 */
213 .mwdma_mask = 0x07, /* mwdma0-2 */
214 .udma_mask = ATA_UDMA6, /* udma0-6 */
215 .port_ops = &pdc2027x_pata133_ops,
216 },
217 };
218
219 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
220 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
221 MODULE_LICENSE("GPL");
222 MODULE_VERSION(DRV_VERSION);
223 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
224
225 /**
226 * port_mmio - Get the MMIO address of PDC2027x extended registers
227 * @ap: Port
228 * @offset: offset from mmio base
229 */
230 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
231 {
232 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
233 }
234
235 /**
236 * dev_mmio - Get the MMIO address of PDC2027x extended registers
237 * @ap: Port
238 * @adev: device
239 * @offset: offset from mmio base
240 */
241 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
242 {
243 u8 adj = (adev->devno) ? 0x08 : 0x00;
244 return port_mmio(ap, offset) + adj;
245 }
246
247 /**
248 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
249 * @ap: Port for which cable detect info is desired
250 *
251 * Read 80c cable indicator from Promise extended register.
252 * This register is latched when the system is reset.
253 *
254 * LOCKING:
255 * None (inherited from caller).
256 */
257 static int pdc2027x_cable_detect(struct ata_port *ap)
258 {
259 u32 cgcr;
260
261 /* check cable detect results */
262 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
263 if (cgcr & (1 << 26))
264 goto cbl40;
265
266 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
267
268 return ATA_CBL_PATA80;
269 cbl40:
270 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
271 return ATA_CBL_PATA40;
272 }
273
274 /**
275 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
276 * @ap: Port to check
277 */
278 static inline int pdc2027x_port_enabled(struct ata_port *ap)
279 {
280 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
281 }
282
283 /**
284 * pdc2027x_prereset - prereset for PATA host controller
285 * @link: Target link
286 * @deadline: deadline jiffies for the operation
287 *
288 * Probeinit including cable detection.
289 *
290 * LOCKING:
291 * None (inherited from caller).
292 */
293
294 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
295 {
296 /* Check whether port enabled */
297 if (!pdc2027x_port_enabled(link->ap))
298 return -ENOENT;
299 return ata_std_prereset(link, deadline);
300 }
301
302 /**
303 * pdc2027x_error_handler - Perform reset on PATA port and classify
304 * @ap: Port to reset
305 *
306 * Reset PATA phy and classify attached devices.
307 *
308 * LOCKING:
309 * None (inherited from caller).
310 */
311
312 static void pdc2027x_error_handler(struct ata_port *ap)
313 {
314 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
315 }
316
317 /**
318 * pdc2720x_mode_filter - mode selection filter
319 * @adev: ATA device
320 * @mask: list of modes proposed
321 *
322 * Block UDMA on devices that cause trouble with this controller.
323 */
324
325 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
326 {
327 unsigned char model_num[ATA_ID_PROD_LEN + 1];
328 struct ata_device *pair = ata_dev_pair(adev);
329
330 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
331 return ata_pci_default_filter(adev, mask);
332
333 /* Check for slave of a Maxtor at UDMA6 */
334 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
335 ATA_ID_PROD_LEN + 1);
336 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
337 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
338 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
339
340 return ata_pci_default_filter(adev, mask);
341 }
342
343 /**
344 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
345 * @ap: Port to configure
346 * @adev: um
347 * @pio: PIO mode, 0 - 4
348 *
349 * Set PIO mode for device.
350 *
351 * LOCKING:
352 * None (inherited from caller).
353 */
354
355 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
356 {
357 unsigned int pio = adev->pio_mode - XFER_PIO_0;
358 u32 ctcr0, ctcr1;
359
360 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
361
362 /* Sanity check */
363 if (pio > 4) {
364 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
365 return;
366
367 }
368
369 /* Set the PIO timing registers using value table for 133MHz */
370 PDPRINTK("Set pio regs... \n");
371
372 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
373 ctcr0 &= 0xffff0000;
374 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
375 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
376 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
377
378 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
379 ctcr1 &= 0x00ffffff;
380 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
381 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
382
383 PDPRINTK("Set pio regs done\n");
384
385 PDPRINTK("Set to pio mode[%u] \n", pio);
386 }
387
388 /**
389 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
390 * @ap: Port to configure
391 * @adev: um
392 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
393 *
394 * Set UDMA mode for device.
395 *
396 * LOCKING:
397 * None (inherited from caller).
398 */
399 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
400 {
401 unsigned int dma_mode = adev->dma_mode;
402 u32 ctcr0, ctcr1;
403
404 if ((dma_mode >= XFER_UDMA_0) &&
405 (dma_mode <= XFER_UDMA_6)) {
406 /* Set the UDMA timing registers with value table for 133MHz */
407 unsigned int udma_mode = dma_mode & 0x07;
408
409 if (dma_mode == XFER_UDMA_2) {
410 /*
411 * Turn off tHOLD.
412 * If tHOLD is '1', the hardware will add half clock for data hold time.
413 * This code segment seems to be no effect. tHOLD will be overwritten below.
414 */
415 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
416 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
417 }
418
419 PDPRINTK("Set udma regs... \n");
420
421 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
422 ctcr1 &= 0xff000000;
423 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
424 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
425 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
426 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
427
428 PDPRINTK("Set udma regs done\n");
429
430 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
431
432 } else if ((dma_mode >= XFER_MW_DMA_0) &&
433 (dma_mode <= XFER_MW_DMA_2)) {
434 /* Set the MDMA timing registers with value table for 133MHz */
435 unsigned int mdma_mode = dma_mode & 0x07;
436
437 PDPRINTK("Set mdma regs... \n");
438 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
439
440 ctcr0 &= 0x0000ffff;
441 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
442 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
443
444 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
445 PDPRINTK("Set mdma regs done\n");
446
447 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
448 } else {
449 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
450 }
451 }
452
453 /**
454 * pdc2027x_set_mode - Set the timing registers back to correct values.
455 * @link: link to configure
456 * @r_failed: Returned device for failure
457 *
458 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
459 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
460 * This function overwrites the possibly incorrect values set by the hardware to be correct.
461 */
462 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
463 {
464 struct ata_port *ap = link->ap;
465 struct ata_device *dev;
466 int rc;
467
468 rc = ata_do_set_mode(link, r_failed);
469 if (rc < 0)
470 return rc;
471
472 ata_link_for_each_dev(dev, link) {
473 if (ata_dev_enabled(dev)) {
474
475 pdc2027x_set_piomode(ap, dev);
476
477 /*
478 * Enable prefetch if the device support PIO only.
479 */
480 if (dev->xfer_shift == ATA_SHIFT_PIO) {
481 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
482 ctcr1 |= (1 << 25);
483 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
484
485 PDPRINTK("Turn on prefetch\n");
486 } else {
487 pdc2027x_set_dmamode(ap, dev);
488 }
489 }
490 }
491 return 0;
492 }
493
494 /**
495 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
496 * @qc: Metadata associated with taskfile to check
497 *
498 * LOCKING:
499 * None (inherited from caller).
500 *
501 * RETURNS: 0 when ATAPI DMA can be used
502 * 1 otherwise
503 */
504 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
505 {
506 struct scsi_cmnd *cmd = qc->scsicmd;
507 u8 *scsicmd = cmd->cmnd;
508 int rc = 1; /* atapi dma off by default */
509
510 /*
511 * This workaround is from Promise's GPL driver.
512 * If ATAPI DMA is used for commands not in the
513 * following white list, say MODE_SENSE and REQUEST_SENSE,
514 * pdc2027x might hit the irq lost problem.
515 */
516 switch (scsicmd[0]) {
517 case READ_10:
518 case WRITE_10:
519 case READ_12:
520 case WRITE_12:
521 case READ_6:
522 case WRITE_6:
523 case 0xad: /* READ_DVD_STRUCTURE */
524 case 0xbe: /* READ_CD */
525 /* ATAPI DMA is ok */
526 rc = 0;
527 break;
528 default:
529 ;
530 }
531
532 return rc;
533 }
534
535 /**
536 * pdc_read_counter - Read the ctr counter
537 * @host: target ATA host
538 */
539
540 static long pdc_read_counter(struct ata_host *host)
541 {
542 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
543 long counter;
544 int retry = 1;
545 u32 bccrl, bccrh, bccrlv, bccrhv;
546
547 retry:
548 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
549 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
550
551 /* Read the counter values again for verification */
552 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
553 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
554
555 counter = (bccrh << 15) | bccrl;
556
557 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
558 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
559
560 /*
561 * The 30-bit decreasing counter are read by 2 pieces.
562 * Incorrect value may be read when both bccrh and bccrl are changing.
563 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
564 */
565 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
566 retry--;
567 PDPRINTK("rereading counter\n");
568 goto retry;
569 }
570
571 return counter;
572 }
573
574 /**
575 * adjust_pll - Adjust the PLL input clock in Hz.
576 *
577 * @pdc_controller: controller specific information
578 * @host: target ATA host
579 * @pll_clock: The input of PLL in HZ
580 */
581 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
582 {
583 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
584 u16 pll_ctl;
585 long pll_clock_khz = pll_clock / 1000;
586 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
587 long ratio = pout_required / pll_clock_khz;
588 int F, R;
589
590 /* Sanity check */
591 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
592 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
593 return;
594 }
595
596 #ifdef PDC_DEBUG
597 PDPRINTK("pout_required is %ld\n", pout_required);
598
599 /* Show the current clock value of PLL control register
600 * (maybe already configured by the firmware)
601 */
602 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
603
604 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
605 #endif
606
607 /*
608 * Calculate the ratio of F, R and OD
609 * POUT = (F + 2) / (( R + 2) * NO)
610 */
611 if (ratio < 8600L) { /* 8.6x */
612 /* Using NO = 0x01, R = 0x0D */
613 R = 0x0d;
614 } else if (ratio < 12900L) { /* 12.9x */
615 /* Using NO = 0x01, R = 0x08 */
616 R = 0x08;
617 } else if (ratio < 16100L) { /* 16.1x */
618 /* Using NO = 0x01, R = 0x06 */
619 R = 0x06;
620 } else if (ratio < 64000L) { /* 64x */
621 R = 0x00;
622 } else {
623 /* Invalid ratio */
624 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
625 return;
626 }
627
628 F = (ratio * (R+2)) / 1000 - 2;
629
630 if (unlikely(F < 0 || F > 127)) {
631 /* Invalid F */
632 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
633 return;
634 }
635
636 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
637
638 pll_ctl = (R << 8) | F;
639
640 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
641
642 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
643 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
644
645 /* Wait the PLL circuit to be stable */
646 mdelay(30);
647
648 #ifdef PDC_DEBUG
649 /*
650 * Show the current clock value of PLL control register
651 * (maybe configured by the firmware)
652 */
653 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
654
655 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
656 #endif
657
658 return;
659 }
660
661 /**
662 * detect_pll_input_clock - Detect the PLL input clock in Hz.
663 * @host: target ATA host
664 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
665 * Half of the PCI clock.
666 */
667 static long pdc_detect_pll_input_clock(struct ata_host *host)
668 {
669 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
670 u32 scr;
671 long start_count, end_count;
672 struct timeval start_time, end_time;
673 long pll_clock, usec_elapsed;
674
675 /* Start the test mode */
676 scr = ioread32(mmio_base + PDC_SYS_CTL);
677 PDPRINTK("scr[%X]\n", scr);
678 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
679 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
680
681 /* Read current counter value */
682 start_count = pdc_read_counter(host);
683 do_gettimeofday(&start_time);
684
685 /* Let the counter run for 100 ms. */
686 mdelay(100);
687
688 /* Read the counter values again */
689 end_count = pdc_read_counter(host);
690 do_gettimeofday(&end_time);
691
692 /* Stop the test mode */
693 scr = ioread32(mmio_base + PDC_SYS_CTL);
694 PDPRINTK("scr[%X]\n", scr);
695 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
696 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
697
698 /* calculate the input clock in Hz */
699 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
700 (end_time.tv_usec - start_time.tv_usec);
701
702 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
703 (100000000 / usec_elapsed);
704
705 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
706 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
707
708 return pll_clock;
709 }
710
711 /**
712 * pdc_hardware_init - Initialize the hardware.
713 * @host: target ATA host
714 * @board_idx: board identifier
715 */
716 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
717 {
718 long pll_clock;
719
720 /*
721 * Detect PLL input clock rate.
722 * On some system, where PCI bus is running at non-standard clock rate.
723 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
724 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
725 */
726 pll_clock = pdc_detect_pll_input_clock(host);
727
728 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
729
730 /* Adjust PLL control register */
731 pdc_adjust_pll(host, pll_clock, board_idx);
732
733 return 0;
734 }
735
736 /**
737 * pdc_ata_setup_port - setup the mmio address
738 * @port: ata ioports to setup
739 * @base: base address
740 */
741 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
742 {
743 port->cmd_addr =
744 port->data_addr = base;
745 port->feature_addr =
746 port->error_addr = base + 0x05;
747 port->nsect_addr = base + 0x0a;
748 port->lbal_addr = base + 0x0f;
749 port->lbam_addr = base + 0x10;
750 port->lbah_addr = base + 0x15;
751 port->device_addr = base + 0x1a;
752 port->command_addr =
753 port->status_addr = base + 0x1f;
754 port->altstatus_addr =
755 port->ctl_addr = base + 0x81a;
756 }
757
758 /**
759 * pdc2027x_init_one - PCI probe function
760 * Called when an instance of PCI adapter is inserted.
761 * This function checks whether the hardware is supported,
762 * initialize hardware and register an instance of ata_host to
763 * libata. (implements struct pci_driver.probe() )
764 *
765 * @pdev: instance of pci_dev found
766 * @ent: matching entry in the id_tbl[]
767 */
768 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
769 {
770 static int printed_version;
771 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
772 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
773 unsigned int board_idx = (unsigned int) ent->driver_data;
774 const struct ata_port_info *ppi[] =
775 { &pdc2027x_port_info[board_idx], NULL };
776 struct ata_host *host;
777 void __iomem *mmio_base;
778 int i, rc;
779
780 if (!printed_version++)
781 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
782
783 /* alloc host */
784 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
785 if (!host)
786 return -ENOMEM;
787
788 /* acquire resources and fill host */
789 rc = pcim_enable_device(pdev);
790 if (rc)
791 return rc;
792
793 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
794 if (rc)
795 return rc;
796 host->iomap = pcim_iomap_table(pdev);
797
798 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
799 if (rc)
800 return rc;
801
802 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
803 if (rc)
804 return rc;
805
806 mmio_base = host->iomap[PDC_MMIO_BAR];
807
808 for (i = 0; i < 2; i++) {
809 struct ata_port *ap = host->ports[i];
810
811 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
812 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
813
814 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
815 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
816 }
817
818 //pci_enable_intx(pdev);
819
820 /* initialize adapter */
821 if (pdc_hardware_init(host, board_idx) != 0)
822 return -EIO;
823
824 pci_set_master(pdev);
825 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
826 &pdc2027x_sht);
827 }
828
829 /**
830 * pdc2027x_init - Called after this module is loaded into the kernel.
831 */
832 static int __init pdc2027x_init(void)
833 {
834 return pci_register_driver(&pdc2027x_pci_driver);
835 }
836
837 /**
838 * pdc2027x_exit - Called before this module unloaded from the kernel
839 */
840 static void __exit pdc2027x_exit(void)
841 {
842 pci_unregister_driver(&pdc2027x_pci_driver);
843 }
844
845 module_init(pdc2027x_init);
846 module_exit(pdc2027x_exit);
Linux kernel - Deliverables
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