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[PATCH] libata-eh: Remove layering violation and duplication when handling absent...
[deliverable/linux.git] / drivers / ata / pata_pdc2027x.c
1 /*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36 #include <asm/io.h>
37
38 #define DRV_NAME "pata_pdc2027x"
39 #define DRV_VERSION "0.74-ac5"
40 #undef PDC_DEBUG
41
42 #ifdef PDC_DEBUG
43 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44 #else
45 #define PDPRINTK(fmt, args...)
46 #endif
47
48 enum {
49 PDC_UDMA_100 = 0,
50 PDC_UDMA_133 = 1,
51
52 PDC_100_MHZ = 100000000,
53 PDC_133_MHZ = 133333333,
54
55 PDC_SYS_CTL = 0x1100,
56 PDC_ATA_CTL = 0x1104,
57 PDC_GLOBAL_CTL = 0x1108,
58 PDC_CTCR0 = 0x110C,
59 PDC_CTCR1 = 0x1110,
60 PDC_BYTE_COUNT = 0x1120,
61 PDC_PLL_CTL = 0x1202,
62 };
63
64 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
65 static void pdc2027x_remove_one(struct pci_dev *pdev);
66 static void pdc2027x_error_handler(struct ata_port *ap);
67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69 static void pdc2027x_post_set_mode(struct ata_port *ap);
70 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
71
72 /*
73 * ATA Timing Tables based on 133MHz controller clock.
74 * These tables are only used when the controller is in 133MHz clock.
75 * If the controller is in 100MHz clock, the ASIC hardware will
76 * set the timing registers automatically when "set feature" command
77 * is issued to the device. However, if the controller clock is 133MHz,
78 * the following tables must be used.
79 */
80 static struct pdc2027x_pio_timing {
81 u8 value0, value1, value2;
82 } pdc2027x_pio_timing_tbl [] = {
83 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
84 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
85 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
86 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
87 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
88 };
89
90 static struct pdc2027x_mdma_timing {
91 u8 value0, value1;
92 } pdc2027x_mdma_timing_tbl [] = {
93 { 0xdf, 0x5f }, /* MDMA mode 0 */
94 { 0x6b, 0x27 }, /* MDMA mode 1 */
95 { 0x69, 0x25 }, /* MDMA mode 2 */
96 };
97
98 static struct pdc2027x_udma_timing {
99 u8 value0, value1, value2;
100 } pdc2027x_udma_timing_tbl [] = {
101 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
102 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
103 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
104 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
105 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
106 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
107 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
108 };
109
110 static const struct pci_device_id pdc2027x_pci_tbl[] = {
111 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
112 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
113 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_100 },
114 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
115 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
116 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
117 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PDC_UDMA_133 },
118 { } /* terminate list */
119 };
120
121 static struct pci_driver pdc2027x_pci_driver = {
122 .name = DRV_NAME,
123 .id_table = pdc2027x_pci_tbl,
124 .probe = pdc2027x_init_one,
125 .remove = __devexit_p(pdc2027x_remove_one),
126 };
127
128 static struct scsi_host_template pdc2027x_sht = {
129 .module = THIS_MODULE,
130 .name = DRV_NAME,
131 .ioctl = ata_scsi_ioctl,
132 .queuecommand = ata_scsi_queuecmd,
133 .can_queue = ATA_DEF_QUEUE,
134 .this_id = ATA_SHT_THIS_ID,
135 .sg_tablesize = LIBATA_MAX_PRD,
136 .max_sectors = ATA_MAX_SECTORS,
137 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
138 .emulated = ATA_SHT_EMULATED,
139 .use_clustering = ATA_SHT_USE_CLUSTERING,
140 .proc_name = DRV_NAME,
141 .dma_boundary = ATA_DMA_BOUNDARY,
142 .slave_configure = ata_scsi_slave_config,
143 .bios_param = ata_std_bios_param,
144 };
145
146 static struct ata_port_operations pdc2027x_pata100_ops = {
147 .port_disable = ata_port_disable,
148
149 .tf_load = ata_tf_load,
150 .tf_read = ata_tf_read,
151 .check_status = ata_check_status,
152 .exec_command = ata_exec_command,
153 .dev_select = ata_std_dev_select,
154
155 .check_atapi_dma = pdc2027x_check_atapi_dma,
156 .bmdma_setup = ata_bmdma_setup,
157 .bmdma_start = ata_bmdma_start,
158 .bmdma_stop = ata_bmdma_stop,
159 .bmdma_status = ata_bmdma_status,
160 .qc_prep = ata_qc_prep,
161 .qc_issue = ata_qc_issue_prot,
162 .data_xfer = ata_mmio_data_xfer,
163
164 .freeze = ata_bmdma_freeze,
165 .thaw = ata_bmdma_thaw,
166 .error_handler = pdc2027x_error_handler,
167 .post_internal_cmd = ata_bmdma_post_internal_cmd,
168
169 .irq_handler = ata_interrupt,
170 .irq_clear = ata_bmdma_irq_clear,
171
172 .port_start = ata_port_start,
173 .port_stop = ata_port_stop,
174 .host_stop = ata_pci_host_stop,
175 };
176
177 static struct ata_port_operations pdc2027x_pata133_ops = {
178 .port_disable = ata_port_disable,
179 .set_piomode = pdc2027x_set_piomode,
180 .set_dmamode = pdc2027x_set_dmamode,
181 .post_set_mode = pdc2027x_post_set_mode,
182
183 .tf_load = ata_tf_load,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = ata_exec_command,
187 .dev_select = ata_std_dev_select,
188
189 .check_atapi_dma = pdc2027x_check_atapi_dma,
190 .bmdma_setup = ata_bmdma_setup,
191 .bmdma_start = ata_bmdma_start,
192 .bmdma_stop = ata_bmdma_stop,
193 .bmdma_status = ata_bmdma_status,
194 .qc_prep = ata_qc_prep,
195 .qc_issue = ata_qc_issue_prot,
196 .data_xfer = ata_mmio_data_xfer,
197
198 .freeze = ata_bmdma_freeze,
199 .thaw = ata_bmdma_thaw,
200 .error_handler = pdc2027x_error_handler,
201 .post_internal_cmd = ata_bmdma_post_internal_cmd,
202
203 .irq_handler = ata_interrupt,
204 .irq_clear = ata_bmdma_irq_clear,
205
206 .port_start = ata_port_start,
207 .port_stop = ata_port_stop,
208 .host_stop = ata_pci_host_stop,
209 };
210
211 static struct ata_port_info pdc2027x_port_info[] = {
212 /* PDC_UDMA_100 */
213 {
214 .sht = &pdc2027x_sht,
215 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
216 ATA_FLAG_MMIO,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = ATA_UDMA5, /* udma0-5 */
220 .port_ops = &pdc2027x_pata100_ops,
221 },
222 /* PDC_UDMA_133 */
223 {
224 .sht = &pdc2027x_sht,
225 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
226 ATA_FLAG_MMIO,
227 .pio_mask = 0x1f, /* pio0-4 */
228 .mwdma_mask = 0x07, /* mwdma0-2 */
229 .udma_mask = ATA_UDMA6, /* udma0-6 */
230 .port_ops = &pdc2027x_pata133_ops,
231 },
232 };
233
234 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
235 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
236 MODULE_LICENSE("GPL");
237 MODULE_VERSION(DRV_VERSION);
238 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
239
240 /**
241 * port_mmio - Get the MMIO address of PDC2027x extended registers
242 * @ap: Port
243 * @offset: offset from mmio base
244 */
245 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
246 {
247 return ap->host->mmio_base + ap->port_no * 0x100 + offset;
248 }
249
250 /**
251 * dev_mmio - Get the MMIO address of PDC2027x extended registers
252 * @ap: Port
253 * @adev: device
254 * @offset: offset from mmio base
255 */
256 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
257 {
258 u8 adj = (adev->devno) ? 0x08 : 0x00;
259 return port_mmio(ap, offset) + adj;
260 }
261
262 /**
263 * pdc2027x_pata_cbl_detect - Probe host controller cable detect info
264 * @ap: Port for which cable detect info is desired
265 *
266 * Read 80c cable indicator from Promise extended register.
267 * This register is latched when the system is reset.
268 *
269 * LOCKING:
270 * None (inherited from caller).
271 */
272 static void pdc2027x_cbl_detect(struct ata_port *ap)
273 {
274 u32 cgcr;
275
276 /* check cable detect results */
277 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
278 if (cgcr & (1 << 26))
279 goto cbl40;
280
281 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
282
283 ap->cbl = ATA_CBL_PATA80;
284 return;
285
286 cbl40:
287 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
288 ap->cbl = ATA_CBL_PATA40;
289 ap->udma_mask &= ATA_UDMA_MASK_40C;
290 }
291
292 /**
293 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
294 * @ap: Port to check
295 */
296 static inline int pdc2027x_port_enabled(struct ata_port *ap)
297 {
298 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
299 }
300
301 /**
302 * pdc2027x_prereset - prereset for PATA host controller
303 * @ap: Target port
304 *
305 * Probeinit including cable detection.
306 *
307 * LOCKING:
308 * None (inherited from caller).
309 */
310
311 static int pdc2027x_prereset(struct ata_port *ap)
312 {
313 /* Check whether port enabled */
314 if (!pdc2027x_port_enabled(ap))
315 return -ENOENT;
316 pdc2027x_cbl_detect(ap);
317 return ata_std_prereset(ap);
318 }
319
320 /**
321 * pdc2027x_error_handler - Perform reset on PATA port and classify
322 * @ap: Port to reset
323 *
324 * Reset PATA phy and classify attached devices.
325 *
326 * LOCKING:
327 * None (inherited from caller).
328 */
329
330 static void pdc2027x_error_handler(struct ata_port *ap)
331 {
332 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
333 }
334
335 /**
336 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
337 * @ap: Port to configure
338 * @adev: um
339 * @pio: PIO mode, 0 - 4
340 *
341 * Set PIO mode for device.
342 *
343 * LOCKING:
344 * None (inherited from caller).
345 */
346
347 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
348 {
349 unsigned int pio = adev->pio_mode - XFER_PIO_0;
350 u32 ctcr0, ctcr1;
351
352 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
353
354 /* Sanity check */
355 if (pio > 4) {
356 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
357 return;
358
359 }
360
361 /* Set the PIO timing registers using value table for 133MHz */
362 PDPRINTK("Set pio regs... \n");
363
364 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
365 ctcr0 &= 0xffff0000;
366 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
367 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
368 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
369
370 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
371 ctcr1 &= 0x00ffffff;
372 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
373 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
374
375 PDPRINTK("Set pio regs done\n");
376
377 PDPRINTK("Set to pio mode[%u] \n", pio);
378 }
379
380 /**
381 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
382 * @ap: Port to configure
383 * @adev: um
384 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
385 *
386 * Set UDMA mode for device.
387 *
388 * LOCKING:
389 * None (inherited from caller).
390 */
391 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
392 {
393 unsigned int dma_mode = adev->dma_mode;
394 u32 ctcr0, ctcr1;
395
396 if ((dma_mode >= XFER_UDMA_0) &&
397 (dma_mode <= XFER_UDMA_6)) {
398 /* Set the UDMA timing registers with value table for 133MHz */
399 unsigned int udma_mode = dma_mode & 0x07;
400
401 if (dma_mode == XFER_UDMA_2) {
402 /*
403 * Turn off tHOLD.
404 * If tHOLD is '1', the hardware will add half clock for data hold time.
405 * This code segment seems to be no effect. tHOLD will be overwritten below.
406 */
407 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
408 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
409 }
410
411 PDPRINTK("Set udma regs... \n");
412
413 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
414 ctcr1 &= 0xff000000;
415 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
416 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
417 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
418 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
419
420 PDPRINTK("Set udma regs done\n");
421
422 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
423
424 } else if ((dma_mode >= XFER_MW_DMA_0) &&
425 (dma_mode <= XFER_MW_DMA_2)) {
426 /* Set the MDMA timing registers with value table for 133MHz */
427 unsigned int mdma_mode = dma_mode & 0x07;
428
429 PDPRINTK("Set mdma regs... \n");
430 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
431
432 ctcr0 &= 0x0000ffff;
433 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
434 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
435
436 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
437 PDPRINTK("Set mdma regs done\n");
438
439 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
440 } else {
441 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
442 }
443 }
444
445 /**
446 * pdc2027x_post_set_mode - Set the timing registers back to correct values.
447 * @ap: Port to configure
448 *
449 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
450 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
451 * This function overwrites the possibly incorrect values set by the hardware to be correct.
452 */
453 static void pdc2027x_post_set_mode(struct ata_port *ap)
454 {
455 int i;
456
457 for (i = 0; i < ATA_MAX_DEVICES; i++) {
458 struct ata_device *dev = &ap->device[i];
459
460 if (ata_dev_enabled(dev)) {
461
462 pdc2027x_set_piomode(ap, dev);
463
464 /*
465 * Enable prefetch if the device support PIO only.
466 */
467 if (dev->xfer_shift == ATA_SHIFT_PIO) {
468 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
469 ctcr1 |= (1 << 25);
470 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
471
472 PDPRINTK("Turn on prefetch\n");
473 } else {
474 pdc2027x_set_dmamode(ap, dev);
475 }
476 }
477 }
478 }
479
480 /**
481 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
482 * @qc: Metadata associated with taskfile to check
483 *
484 * LOCKING:
485 * None (inherited from caller).
486 *
487 * RETURNS: 0 when ATAPI DMA can be used
488 * 1 otherwise
489 */
490 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
491 {
492 struct scsi_cmnd *cmd = qc->scsicmd;
493 u8 *scsicmd = cmd->cmnd;
494 int rc = 1; /* atapi dma off by default */
495
496 /*
497 * This workaround is from Promise's GPL driver.
498 * If ATAPI DMA is used for commands not in the
499 * following white list, say MODE_SENSE and REQUEST_SENSE,
500 * pdc2027x might hit the irq lost problem.
501 */
502 switch (scsicmd[0]) {
503 case READ_10:
504 case WRITE_10:
505 case READ_12:
506 case WRITE_12:
507 case READ_6:
508 case WRITE_6:
509 case 0xad: /* READ_DVD_STRUCTURE */
510 case 0xbe: /* READ_CD */
511 /* ATAPI DMA is ok */
512 rc = 0;
513 break;
514 default:
515 ;
516 }
517
518 return rc;
519 }
520
521 /**
522 * pdc_read_counter - Read the ctr counter
523 * @probe_ent: for the port address
524 */
525
526 static long pdc_read_counter(struct ata_probe_ent *probe_ent)
527 {
528 long counter;
529 int retry = 1;
530 u32 bccrl, bccrh, bccrlv, bccrhv;
531
532 retry:
533 bccrl = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
534 bccrh = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
535 rmb();
536
537 /* Read the counter values again for verification */
538 bccrlv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT) & 0xffff;
539 bccrhv = readl(probe_ent->mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
540 rmb();
541
542 counter = (bccrh << 15) | bccrl;
543
544 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
545 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
546
547 /*
548 * The 30-bit decreasing counter are read by 2 pieces.
549 * Incorrect value may be read when both bccrh and bccrl are changing.
550 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
551 */
552 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
553 retry--;
554 PDPRINTK("rereading counter\n");
555 goto retry;
556 }
557
558 return counter;
559 }
560
561 /**
562 * adjust_pll - Adjust the PLL input clock in Hz.
563 *
564 * @pdc_controller: controller specific information
565 * @probe_ent: For the port address
566 * @pll_clock: The input of PLL in HZ
567 */
568 static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
569 {
570
571 u16 pll_ctl;
572 long pll_clock_khz = pll_clock / 1000;
573 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
574 long ratio = pout_required / pll_clock_khz;
575 int F, R;
576
577 /* Sanity check */
578 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
579 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
580 return;
581 }
582
583 #ifdef PDC_DEBUG
584 PDPRINTK("pout_required is %ld\n", pout_required);
585
586 /* Show the current clock value of PLL control register
587 * (maybe already configured by the firmware)
588 */
589 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
590
591 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
592 #endif
593
594 /*
595 * Calculate the ratio of F, R and OD
596 * POUT = (F + 2) / (( R + 2) * NO)
597 */
598 if (ratio < 8600L) { /* 8.6x */
599 /* Using NO = 0x01, R = 0x0D */
600 R = 0x0d;
601 } else if (ratio < 12900L) { /* 12.9x */
602 /* Using NO = 0x01, R = 0x08 */
603 R = 0x08;
604 } else if (ratio < 16100L) { /* 16.1x */
605 /* Using NO = 0x01, R = 0x06 */
606 R = 0x06;
607 } else if (ratio < 64000L) { /* 64x */
608 R = 0x00;
609 } else {
610 /* Invalid ratio */
611 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
612 return;
613 }
614
615 F = (ratio * (R+2)) / 1000 - 2;
616
617 if (unlikely(F < 0 || F > 127)) {
618 /* Invalid F */
619 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
620 return;
621 }
622
623 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
624
625 pll_ctl = (R << 8) | F;
626
627 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
628
629 writew(pll_ctl, probe_ent->mmio_base + PDC_PLL_CTL);
630 readw(probe_ent->mmio_base + PDC_PLL_CTL); /* flush */
631
632 /* Wait the PLL circuit to be stable */
633 mdelay(30);
634
635 #ifdef PDC_DEBUG
636 /*
637 * Show the current clock value of PLL control register
638 * (maybe configured by the firmware)
639 */
640 pll_ctl = readw(probe_ent->mmio_base + PDC_PLL_CTL);
641
642 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
643 #endif
644
645 return;
646 }
647
648 /**
649 * detect_pll_input_clock - Detect the PLL input clock in Hz.
650 * @probe_ent: for the port address
651 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
652 * Half of the PCI clock.
653 */
654 static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
655 {
656 u32 scr;
657 long start_count, end_count;
658 long pll_clock;
659
660 /* Read current counter value */
661 start_count = pdc_read_counter(probe_ent);
662
663 /* Start the test mode */
664 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
665 PDPRINTK("scr[%X]\n", scr);
666 writel(scr | (0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
667 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
668
669 /* Let the counter run for 100 ms. */
670 mdelay(100);
671
672 /* Read the counter values again */
673 end_count = pdc_read_counter(probe_ent);
674
675 /* Stop the test mode */
676 scr = readl(probe_ent->mmio_base + PDC_SYS_CTL);
677 PDPRINTK("scr[%X]\n", scr);
678 writel(scr & ~(0x01 << 14), probe_ent->mmio_base + PDC_SYS_CTL);
679 readl(probe_ent->mmio_base + PDC_SYS_CTL); /* flush */
680
681 /* calculate the input clock in Hz */
682 pll_clock = (start_count - end_count) * 10;
683
684 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
685 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
686
687 return pll_clock;
688 }
689
690 /**
691 * pdc_hardware_init - Initialize the hardware.
692 * @pdev: instance of pci_dev found
693 * @pdc_controller: controller specific information
694 * @pe: for the port address
695 */
696 static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
697 {
698 long pll_clock;
699
700 /*
701 * Detect PLL input clock rate.
702 * On some system, where PCI bus is running at non-standard clock rate.
703 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
704 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
705 */
706 pll_clock = pdc_detect_pll_input_clock(pe);
707
708 if (pll_clock < 0) /* counter overflow? Try again. */
709 pll_clock = pdc_detect_pll_input_clock(pe);
710
711 dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
712
713 /* Adjust PLL control register */
714 pdc_adjust_pll(pe, pll_clock, board_idx);
715
716 return 0;
717 }
718
719 /**
720 * pdc_ata_setup_port - setup the mmio address
721 * @port: ata ioports to setup
722 * @base: base address
723 */
724 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
725 {
726 port->cmd_addr =
727 port->data_addr = base;
728 port->feature_addr =
729 port->error_addr = base + 0x05;
730 port->nsect_addr = base + 0x0a;
731 port->lbal_addr = base + 0x0f;
732 port->lbam_addr = base + 0x10;
733 port->lbah_addr = base + 0x15;
734 port->device_addr = base + 0x1a;
735 port->command_addr =
736 port->status_addr = base + 0x1f;
737 port->altstatus_addr =
738 port->ctl_addr = base + 0x81a;
739 }
740
741 /**
742 * pdc2027x_init_one - PCI probe function
743 * Called when an instance of PCI adapter is inserted.
744 * This function checks whether the hardware is supported,
745 * initialize hardware and register an instance of ata_host to
746 * libata by providing struct ata_probe_ent and ata_device_add().
747 * (implements struct pci_driver.probe() )
748 *
749 * @pdev: instance of pci_dev found
750 * @ent: matching entry in the id_tbl[]
751 */
752 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
753 {
754 static int printed_version;
755 unsigned int board_idx = (unsigned int) ent->driver_data;
756
757 struct ata_probe_ent *probe_ent = NULL;
758 unsigned long base;
759 void __iomem *mmio_base;
760 int rc;
761
762 if (!printed_version++)
763 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
764
765 rc = pci_enable_device(pdev);
766 if (rc)
767 return rc;
768
769 rc = pci_request_regions(pdev, DRV_NAME);
770 if (rc)
771 goto err_out;
772
773 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
774 if (rc)
775 goto err_out_regions;
776
777 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
778 if (rc)
779 goto err_out_regions;
780
781 /* Prepare the probe entry */
782 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
783 if (probe_ent == NULL) {
784 rc = -ENOMEM;
785 goto err_out_regions;
786 }
787
788 probe_ent->dev = pci_dev_to_dev(pdev);
789 INIT_LIST_HEAD(&probe_ent->node);
790
791 mmio_base = pci_iomap(pdev, 5, 0);
792 if (!mmio_base) {
793 rc = -ENOMEM;
794 goto err_out_free_ent;
795 }
796
797 base = (unsigned long) mmio_base;
798
799 probe_ent->sht = pdc2027x_port_info[board_idx].sht;
800 probe_ent->port_flags = pdc2027x_port_info[board_idx].flags;
801 probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
802 probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask;
803 probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
804 probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
805
806 probe_ent->irq = pdev->irq;
807 probe_ent->irq_flags = SA_SHIRQ;
808 probe_ent->mmio_base = mmio_base;
809
810 pdc_ata_setup_port(&probe_ent->port[0], base + 0x17c0);
811 probe_ent->port[0].bmdma_addr = base + 0x1000;
812 pdc_ata_setup_port(&probe_ent->port[1], base + 0x15c0);
813 probe_ent->port[1].bmdma_addr = base + 0x1008;
814
815 probe_ent->n_ports = 2;
816
817 pci_set_master(pdev);
818 //pci_enable_intx(pdev);
819
820 /* initialize adapter */
821 if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
822 goto err_out_free_ent;
823
824 ata_device_add(probe_ent);
825 kfree(probe_ent);
826
827 return 0;
828
829 err_out_free_ent:
830 kfree(probe_ent);
831 err_out_regions:
832 pci_release_regions(pdev);
833 err_out:
834 pci_disable_device(pdev);
835 return rc;
836 }
837
838 /**
839 * pdc2027x_remove_one - Called to remove a single instance of the
840 * adapter.
841 *
842 * @dev: The PCI device to remove.
843 * FIXME: module load/unload not working yet
844 */
845 static void __devexit pdc2027x_remove_one(struct pci_dev *pdev)
846 {
847 ata_pci_remove_one(pdev);
848 }
849
850 /**
851 * pdc2027x_init - Called after this module is loaded into the kernel.
852 */
853 static int __init pdc2027x_init(void)
854 {
855 return pci_module_init(&pdc2027x_pci_driver);
856 }
857
858 /**
859 * pdc2027x_exit - Called before this module unloaded from the kernel
860 */
861 static void __exit pdc2027x_exit(void)
862 {
863 pci_unregister_driver(&pdc2027x_pci_driver);
864 }
865
866 module_init(pdc2027x_init);
867 module_exit(pdc2027x_exit);
Linux kernel - Deliverables
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