drivers/ata/pata_pdc202xx_old.c

   1 /*
   2  * pata_pdc202xx_old.c  - Promise PDC202xx PATA for new ATA layer
   3  *                        (C) 2005 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *                        (C) 2007 Bartlomiej Zolnierkiewicz
   6  *
   7  * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
   8  *
   9  * First cut with LBA48/ATAPI
  10  *
  11  * TODO:
  12  *      Channel interlock/reset on both required ?
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/blkdev.h>
  20 #include <linux/delay.h>
  21 #include <scsi/scsi_host.h>
  22 #include <linux/libata.h>
  23
  24 #define DRV_NAME "pata_pdc202xx_old"
  25 #define DRV_VERSION "0.4.3"
  26
  27 static int pdc2026x_cable_detect(struct ata_port *ap)
  28 {
  29         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  30         u16 cis;
  31
  32         pci_read_config_word(pdev, 0x50, &cis);
  33         if (cis & (1 << (10 + ap->port_no)))
  34                 return ATA_CBL_PATA40;
  35         return ATA_CBL_PATA80;
  36 }
  37
  38 /**
  39  *      pdc202xx_configure_piomode      -       set chip PIO timing
  40  *      @ap: ATA interface
  41  *      @adev: ATA device
  42  *      @pio: PIO mode
  43  *
  44  *      Called to do the PIO mode setup. Our timing registers are shared
  45  *      so a configure_dmamode call will undo any work we do here and vice
  46  *      versa
  47  */
  48
  49 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
  50 {
  51         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  52         int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
  53         static u16 pio_timing[5] = {
  54                 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
  55         };
  56         u8 r_ap, r_bp;
  57
  58         pci_read_config_byte(pdev, port, &r_ap);
  59         pci_read_config_byte(pdev, port + 1, &r_bp);
  60         r_ap &= ~0x3F;  /* Preserve ERRDY_EN, SYNC_IN */
  61         r_bp &= ~0x1F;
  62         r_ap |= (pio_timing[pio] >> 8);
  63         r_bp |= (pio_timing[pio] & 0xFF);
  64
  65         if (ata_pio_need_iordy(adev))
  66                 r_ap |= 0x20;   /* IORDY enable */
  67         if (adev->class == ATA_DEV_ATA)
  68                 r_ap |= 0x10;   /* FIFO enable */
  69         pci_write_config_byte(pdev, port, r_ap);
  70         pci_write_config_byte(pdev, port + 1, r_bp);
  71 }
  72
  73 /**
  74  *      pdc202xx_set_piomode    -       set initial PIO mode data
  75  *      @ap: ATA interface
  76  *      @adev: ATA device
  77  *
  78  *      Called to do the PIO mode setup. Our timing registers are shared
  79  *      but we want to set the PIO timing by default.
  80  */
  81
  82 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
  83 {
  84         pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
  85 }
  86
  87 /**
  88  *      pdc202xx_configure_dmamode      -       set DMA mode in chip
  89  *      @ap: ATA interface
  90  *      @adev: ATA device
  91  *
  92  *      Load DMA cycle times into the chip ready for a DMA transfer
  93  *      to occur.
  94  */
  95
  96 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  97 {
  98         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  99         int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
 100         static u8 udma_timing[6][2] = {
 101                 { 0x60, 0x03 }, /* 33 Mhz Clock */
 102                 { 0x40, 0x02 },
 103                 { 0x20, 0x01 },
 104                 { 0x40, 0x02 }, /* 66 Mhz Clock */
 105                 { 0x20, 0x01 },
 106                 { 0x20, 0x01 }
 107         };
 108         static u8 mdma_timing[3][2] = {
 109                 { 0xe0, 0x0f },
 110                 { 0x60, 0x04 },
 111                 { 0x60, 0x03 },
 112         };
 113         u8 r_bp, r_cp;
 114
 115         pci_read_config_byte(pdev, port + 1, &r_bp);
 116         pci_read_config_byte(pdev, port + 2, &r_cp);
 117
 118         r_bp &= ~0xE0;
 119         r_cp &= ~0x0F;
 120
 121         if (adev->dma_mode >= XFER_UDMA_0) {
 122                 int speed = adev->dma_mode - XFER_UDMA_0;
 123                 r_bp |= udma_timing[speed][0];
 124                 r_cp |= udma_timing[speed][1];
 125
 126         } else {
 127                 int speed = adev->dma_mode - XFER_MW_DMA_0;
 128                 r_bp |= mdma_timing[speed][0];
 129                 r_cp |= mdma_timing[speed][1];
 130         }
 131         pci_write_config_byte(pdev, port + 1, r_bp);
 132         pci_write_config_byte(pdev, port + 2, r_cp);
 133
 134 }
 135
 136 /**
 137  *      pdc2026x_bmdma_start            -       DMA engine begin
 138  *      @qc: ATA command
 139  *
 140  *      In UDMA3 or higher we have to clock switch for the duration of the
 141  *      DMA transfer sequence.
 142  *
 143  *      Note: The host lock held by the libata layer protects
 144  *      us from two channels both trying to set DMA bits at once
 145  */
 146
 147 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
 148 {
 149         struct ata_port *ap = qc->ap;
 150         struct ata_device *adev = qc->dev;
 151         struct ata_taskfile *tf = &qc->tf;
 152         int sel66 = ap->port_no ? 0x08: 0x02;
 153
 154         void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
 155         void __iomem *clock = master + 0x11;
 156         void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
 157
 158         u32 len;
 159
 160         /* Check we keep host level locking here */
 161         if (adev->dma_mode >= XFER_UDMA_2)
 162                 iowrite8(ioread8(clock) | sel66, clock);
 163         else
 164                 iowrite8(ioread8(clock) & ~sel66, clock);
 165
 166         /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
 167            and move to qc_issue ? */
 168         pdc202xx_set_dmamode(ap, qc->dev);
 169
 170         /* Cases the state machine will not complete correctly without help */
 171         if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATA_PROT_ATAPI_DMA)
 172         {
 173                 len = qc->nbytes / 2;
 174
 175                 if (tf->flags & ATA_TFLAG_WRITE)
 176                         len |= 0x06000000;
 177                 else
 178                         len |= 0x05000000;
 179
 180                 iowrite32(len, atapi_reg);
 181         }
 182
 183         /* Activate DMA */
 184         ata_bmdma_start(qc);
 185 }
 186
 187 /**
 188  *      pdc2026x_bmdma_end              -       DMA engine stop
 189  *      @qc: ATA command
 190  *
 191  *      After a DMA completes we need to put the clock back to 33MHz for
 192  *      PIO timings.
 193  *
 194  *      Note: The host lock held by the libata layer protects
 195  *      us from two channels both trying to set DMA bits at once
 196  */
 197
 198 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
 199 {
 200         struct ata_port *ap = qc->ap;
 201         struct ata_device *adev = qc->dev;
 202         struct ata_taskfile *tf = &qc->tf;
 203
 204         int sel66 = ap->port_no ? 0x08: 0x02;
 205         /* The clock bits are in the same register for both channels */
 206         void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
 207         void __iomem *clock = master + 0x11;
 208         void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
 209
 210         /* Cases the state machine will not complete correctly */
 211         if (tf->protocol == ATA_PROT_ATAPI_DMA || ( tf->flags & ATA_TFLAG_LBA48)) {
 212                 iowrite32(0, atapi_reg);
 213                 iowrite8(ioread8(clock) & ~sel66, clock);
 214         }
 215         /* Flip back to 33Mhz for PIO */
 216         if (adev->dma_mode >= XFER_UDMA_2)
 217                 iowrite8(ioread8(clock) & ~sel66, clock);
 218         ata_bmdma_stop(qc);
 219         pdc202xx_set_piomode(ap, adev);
 220 }
 221
 222 /**
 223  *      pdc2026x_dev_config     -       device setup hook
 224  *      @adev: newly found device
 225  *
 226  *      Perform chip specific early setup. We need to lock the transfer
 227  *      sizes to 8bit to avoid making the state engine on the 2026x cards
 228  *      barf.
 229  */
 230
 231 static void pdc2026x_dev_config(struct ata_device *adev)
 232 {
 233         adev->max_sectors = 256;
 234 }
 235
 236 static int pdc2026x_port_start(struct ata_port *ap)
 237 {
 238         void __iomem *bmdma = ap->ioaddr.bmdma_addr;
 239         if (bmdma) {
 240                 /* Enable burst mode */
 241                 u8 burst = ioread8(bmdma + 0x1f);
 242                 iowrite8(burst | 0x01, bmdma + 0x1f);
 243         }
 244         return ata_sff_port_start(ap);
 245 }
 246
 247 static struct scsi_host_template pdc202xx_sht = {
 248         .module                 = THIS_MODULE,
 249         .name                   = DRV_NAME,
 250         .ioctl                  = ata_scsi_ioctl,
 251         .queuecommand           = ata_scsi_queuecmd,
 252         .can_queue              = ATA_DEF_QUEUE,
 253         .this_id                = ATA_SHT_THIS_ID,
 254         .sg_tablesize           = LIBATA_MAX_PRD,
 255         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 256         .emulated               = ATA_SHT_EMULATED,
 257         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 258         .proc_name              = DRV_NAME,
 259         .dma_boundary           = ATA_DMA_BOUNDARY,
 260         .slave_configure        = ata_scsi_slave_config,
 261         .slave_destroy          = ata_scsi_slave_destroy,
 262         .bios_param             = ata_std_bios_param,
 263 };
 264
 265 static struct ata_port_operations pdc2024x_port_ops = {
 266         .set_piomode    = pdc202xx_set_piomode,
 267         .set_dmamode    = pdc202xx_set_dmamode,
 268         .mode_filter    = ata_pci_default_filter,
 269         .tf_load        = ata_tf_load,
 270         .tf_read        = ata_tf_read,
 271         .check_status   = ata_check_status,
 272         .exec_command   = ata_exec_command,
 273         .dev_select     = ata_std_dev_select,
 274
 275         .freeze         = ata_bmdma_freeze,
 276         .thaw           = ata_bmdma_thaw,
 277         .error_handler  = ata_bmdma_error_handler,
 278         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 279         .cable_detect   = ata_cable_40wire,
 280
 281         .bmdma_setup    = ata_bmdma_setup,
 282         .bmdma_start    = ata_bmdma_start,
 283         .bmdma_stop     = ata_bmdma_stop,
 284         .bmdma_status   = ata_bmdma_status,
 285
 286         .qc_prep        = ata_qc_prep,
 287         .qc_issue       = ata_qc_issue_prot,
 288         .data_xfer      = ata_data_xfer,
 289
 290         .irq_handler    = ata_interrupt,
 291         .irq_clear      = ata_bmdma_irq_clear,
 292         .irq_on         = ata_irq_on,
 293
 294         .port_start     = ata_sff_port_start,
 295 };
 296
 297 static struct ata_port_operations pdc2026x_port_ops = {
 298         .set_piomode    = pdc202xx_set_piomode,
 299         .set_dmamode    = pdc202xx_set_dmamode,
 300         .mode_filter    = ata_pci_default_filter,
 301         .tf_load        = ata_tf_load,
 302         .tf_read        = ata_tf_read,
 303         .check_status   = ata_check_status,
 304         .exec_command   = ata_exec_command,
 305         .dev_select     = ata_std_dev_select,
 306         .dev_config     = pdc2026x_dev_config,
 307
 308         .freeze         = ata_bmdma_freeze,
 309         .thaw           = ata_bmdma_thaw,
 310         .error_handler  = ata_bmdma_error_handler,
 311         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 312         .cable_detect   = pdc2026x_cable_detect,
 313
 314         .bmdma_setup    = ata_bmdma_setup,
 315         .bmdma_start    = pdc2026x_bmdma_start,
 316         .bmdma_stop     = pdc2026x_bmdma_stop,
 317         .bmdma_status   = ata_bmdma_status,
 318
 319         .qc_prep        = ata_qc_prep,
 320         .qc_issue       = ata_qc_issue_prot,
 321         .data_xfer      = ata_data_xfer,
 322
 323         .irq_handler    = ata_interrupt,
 324         .irq_clear      = ata_bmdma_irq_clear,
 325         .irq_on         = ata_irq_on,
 326
 327         .port_start     = pdc2026x_port_start,
 328 };
 329
 330 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 331 {
 332         static const struct ata_port_info info[3] = {
 333                 {
 334                         .sht = &pdc202xx_sht,
 335                         .flags = ATA_FLAG_SLAVE_POSS,
 336                         .pio_mask = 0x1f,
 337                         .mwdma_mask = 0x07,
 338                         .udma_mask = ATA_UDMA2,
 339                         .port_ops = &pdc2024x_port_ops
 340                 },
 341                 {
 342                         .sht = &pdc202xx_sht,
 343                         .flags = ATA_FLAG_SLAVE_POSS,
 344                         .pio_mask = 0x1f,
 345                         .mwdma_mask = 0x07,
 346                         .udma_mask = ATA_UDMA4,
 347                         .port_ops = &pdc2026x_port_ops
 348                 },
 349                 {
 350                         .sht = &pdc202xx_sht,
 351                         .flags = ATA_FLAG_SLAVE_POSS,
 352                         .pio_mask = 0x1f,
 353                         .mwdma_mask = 0x07,
 354                         .udma_mask = ATA_UDMA5,
 355                         .port_ops = &pdc2026x_port_ops
 356                 }
 357
 358         };
 359         const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
 360
 361         if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
 362                 struct pci_dev *bridge = dev->bus->self;
 363                 /* Don't grab anything behind a Promise I2O RAID */
 364                 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
 365                         if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
 366                                 return -ENODEV;
 367                         if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
 368                                 return -ENODEV;
 369                 }
 370         }
 371         return ata_pci_init_one(dev, ppi);
 372 }
 373
 374 static const struct pci_device_id pdc202xx[] = {
 375         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
 376         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
 377         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
 378         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
 379         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
 380
 381         { },
 382 };
 383
 384 static struct pci_driver pdc202xx_pci_driver = {
 385         .name           = DRV_NAME,
 386         .id_table       = pdc202xx,
 387         .probe          = pdc202xx_init_one,
 388         .remove         = ata_pci_remove_one,
 389 #ifdef CONFIG_PM
 390         .suspend        = ata_pci_device_suspend,
 391         .resume         = ata_pci_device_resume,
 392 #endif
 393 };
 394
 395 static int __init pdc202xx_init(void)
 396 {
 397         return pci_register_driver(&pdc202xx_pci_driver);
 398 }
 399
 400 static void __exit pdc202xx_exit(void)
 401 {
 402         pci_unregister_driver(&pdc202xx_pci_driver);
 403 }
 404
 405 MODULE_AUTHOR("Alan Cox");
 406 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
 407 MODULE_LICENSE("GPL");
 408 MODULE_DEVICE_TABLE(pci, pdc202xx);
 409 MODULE_VERSION(DRV_VERSION);
 410
 411 module_init(pdc202xx_init);
 412 module_exit(pdc202xx_exit);