2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
9 * First cut with LBA48/ATAPI
12 * Channel interlock/reset on both required
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
24 #define DRV_NAME "pata_pdc202xx_old"
25 #define DRV_VERSION "0.4.2"
27 static int pdc2026x_cable_detect(struct ata_port
*ap
)
29 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
32 pci_read_config_word(pdev
, 0x50, &cis
);
33 if (cis
& (1 << (10 + ap
->port_no
)))
34 return ATA_CBL_PATA40
;
35 return ATA_CBL_PATA80
;
39 * pdc202xx_configure_piomode - set chip PIO timing
44 * Called to do the PIO mode setup. Our timing registers are shared
45 * so a configure_dmamode call will undo any work we do here and vice
49 static void pdc202xx_configure_piomode(struct ata_port
*ap
, struct ata_device
*adev
, int pio
)
51 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
52 int port
= 0x60 + 8 * ap
->port_no
+ 4 * adev
->devno
;
53 static u16 pio_timing
[5] = {
54 0x0913, 0x050C , 0x0308, 0x0206, 0x0104
58 pci_read_config_byte(pdev
, port
, &r_ap
);
59 pci_read_config_byte(pdev
, port
+ 1, &r_bp
);
60 r_ap
&= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
62 r_ap
|= (pio_timing
[pio
] >> 8);
63 r_bp
|= (pio_timing
[pio
] & 0xFF);
65 if (ata_pio_need_iordy(adev
))
66 r_ap
|= 0x20; /* IORDY enable */
67 if (adev
->class == ATA_DEV_ATA
)
68 r_ap
|= 0x10; /* FIFO enable */
69 pci_write_config_byte(pdev
, port
, r_ap
);
70 pci_write_config_byte(pdev
, port
+ 1, r_bp
);
74 * pdc202xx_set_piomode - set initial PIO mode data
78 * Called to do the PIO mode setup. Our timing registers are shared
79 * but we want to set the PIO timing by default.
82 static void pdc202xx_set_piomode(struct ata_port
*ap
, struct ata_device
*adev
)
84 pdc202xx_configure_piomode(ap
, adev
, adev
->pio_mode
- XFER_PIO_0
);
88 * pdc202xx_configure_dmamode - set DMA mode in chip
92 * Load DMA cycle times into the chip ready for a DMA transfer
96 static void pdc202xx_set_dmamode(struct ata_port
*ap
, struct ata_device
*adev
)
98 struct pci_dev
*pdev
= to_pci_dev(ap
->host
->dev
);
99 int port
= 0x60 + 8 * ap
->port_no
+ 4 * adev
->devno
;
100 static u8 udma_timing
[6][2] = {
101 { 0x60, 0x03 }, /* 33 Mhz Clock */
104 { 0x40, 0x02 }, /* 66 Mhz Clock */
108 static u8 mdma_timing
[3][2] = {
115 pci_read_config_byte(pdev
, port
+ 1, &r_bp
);
116 pci_read_config_byte(pdev
, port
+ 2, &r_cp
);
121 if (adev
->dma_mode
>= XFER_UDMA_0
) {
122 int speed
= adev
->dma_mode
- XFER_UDMA_0
;
123 r_bp
|= udma_timing
[speed
][0];
124 r_cp
|= udma_timing
[speed
][1];
127 int speed
= adev
->dma_mode
- XFER_MW_DMA_0
;
128 r_bp
|= mdma_timing
[speed
][0];
129 r_cp
|= mdma_timing
[speed
][1];
131 pci_write_config_byte(pdev
, port
+ 1, r_bp
);
132 pci_write_config_byte(pdev
, port
+ 2, r_cp
);
137 * pdc2026x_bmdma_start - DMA engine begin
140 * In UDMA3 or higher we have to clock switch for the duration of the
141 * DMA transfer sequence.
144 static void pdc2026x_bmdma_start(struct ata_queued_cmd
*qc
)
146 struct ata_port
*ap
= qc
->ap
;
147 struct ata_device
*adev
= qc
->dev
;
148 struct ata_taskfile
*tf
= &qc
->tf
;
149 int sel66
= ap
->port_no
? 0x08: 0x02;
151 void __iomem
*master
= ap
->host
->ports
[0]->ioaddr
.bmdma_addr
;
152 void __iomem
*clock
= master
+ 0x11;
153 void __iomem
*atapi_reg
= master
+ 0x20 + (4 * ap
->port_no
);
157 /* Check we keep host level locking here */
158 if (adev
->dma_mode
>= XFER_UDMA_2
)
159 iowrite8(ioread8(clock
) | sel66
, clock
);
161 iowrite8(ioread8(clock
) & ~sel66
, clock
);
163 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
164 and move to qc_issue ? */
165 pdc202xx_set_dmamode(ap
, qc
->dev
);
167 /* Cases the state machine will not complete correctly without help */
168 if ((tf
->flags
& ATA_TFLAG_LBA48
) || tf
->protocol
== ATA_PROT_ATAPI_DMA
)
170 len
= qc
->nbytes
/ 2;
172 if (tf
->flags
& ATA_TFLAG_WRITE
)
177 iowrite32(len
, atapi_reg
);
185 * pdc2026x_bmdma_end - DMA engine stop
188 * After a DMA completes we need to put the clock back to 33MHz for
192 static void pdc2026x_bmdma_stop(struct ata_queued_cmd
*qc
)
194 struct ata_port
*ap
= qc
->ap
;
195 struct ata_device
*adev
= qc
->dev
;
196 struct ata_taskfile
*tf
= &qc
->tf
;
198 int sel66
= ap
->port_no
? 0x08: 0x02;
199 /* The clock bits are in the same register for both channels */
200 void __iomem
*master
= ap
->host
->ports
[0]->ioaddr
.bmdma_addr
;
201 void __iomem
*clock
= master
+ 0x11;
202 void __iomem
*atapi_reg
= master
+ 0x20 + (4 * ap
->port_no
);
204 /* Cases the state machine will not complete correctly */
205 if (tf
->protocol
== ATA_PROT_ATAPI_DMA
|| ( tf
->flags
& ATA_TFLAG_LBA48
)) {
206 iowrite32(0, atapi_reg
);
207 iowrite8(ioread8(clock
) & ~sel66
, clock
);
209 /* Check we keep host level locking here */
210 /* Flip back to 33Mhz for PIO */
211 if (adev
->dma_mode
>= XFER_UDMA_2
)
212 iowrite8(ioread8(clock
) & ~sel66
, clock
);
218 * pdc2026x_dev_config - device setup hook
219 * @adev: newly found device
221 * Perform chip specific early setup. We need to lock the transfer
222 * sizes to 8bit to avoid making the state engine on the 2026x cards
226 static void pdc2026x_dev_config(struct ata_device
*adev
)
228 adev
->max_sectors
= 256;
231 static struct scsi_host_template pdc202xx_sht
= {
232 .module
= THIS_MODULE
,
234 .ioctl
= ata_scsi_ioctl
,
235 .queuecommand
= ata_scsi_queuecmd
,
236 .can_queue
= ATA_DEF_QUEUE
,
237 .this_id
= ATA_SHT_THIS_ID
,
238 .sg_tablesize
= LIBATA_MAX_PRD
,
239 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
240 .emulated
= ATA_SHT_EMULATED
,
241 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
242 .proc_name
= DRV_NAME
,
243 .dma_boundary
= ATA_DMA_BOUNDARY
,
244 .slave_configure
= ata_scsi_slave_config
,
245 .slave_destroy
= ata_scsi_slave_destroy
,
246 .bios_param
= ata_std_bios_param
,
249 static struct ata_port_operations pdc2024x_port_ops
= {
250 .set_piomode
= pdc202xx_set_piomode
,
251 .set_dmamode
= pdc202xx_set_dmamode
,
252 .mode_filter
= ata_pci_default_filter
,
253 .tf_load
= ata_tf_load
,
254 .tf_read
= ata_tf_read
,
255 .check_status
= ata_check_status
,
256 .exec_command
= ata_exec_command
,
257 .dev_select
= ata_std_dev_select
,
259 .freeze
= ata_bmdma_freeze
,
260 .thaw
= ata_bmdma_thaw
,
261 .error_handler
= ata_bmdma_error_handler
,
262 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
263 .cable_detect
= ata_cable_40wire
,
265 .bmdma_setup
= ata_bmdma_setup
,
266 .bmdma_start
= ata_bmdma_start
,
267 .bmdma_stop
= ata_bmdma_stop
,
268 .bmdma_status
= ata_bmdma_status
,
270 .qc_prep
= ata_qc_prep
,
271 .qc_issue
= ata_qc_issue_prot
,
272 .data_xfer
= ata_data_xfer
,
274 .irq_handler
= ata_interrupt
,
275 .irq_clear
= ata_bmdma_irq_clear
,
276 .irq_on
= ata_irq_on
,
278 .port_start
= ata_port_start
,
281 static struct ata_port_operations pdc2026x_port_ops
= {
282 .set_piomode
= pdc202xx_set_piomode
,
283 .set_dmamode
= pdc202xx_set_dmamode
,
284 .mode_filter
= ata_pci_default_filter
,
285 .tf_load
= ata_tf_load
,
286 .tf_read
= ata_tf_read
,
287 .check_status
= ata_check_status
,
288 .exec_command
= ata_exec_command
,
289 .dev_select
= ata_std_dev_select
,
290 .dev_config
= pdc2026x_dev_config
,
292 .freeze
= ata_bmdma_freeze
,
293 .thaw
= ata_bmdma_thaw
,
294 .error_handler
= ata_bmdma_error_handler
,
295 .post_internal_cmd
= ata_bmdma_post_internal_cmd
,
296 .cable_detect
= pdc2026x_cable_detect
,
298 .bmdma_setup
= ata_bmdma_setup
,
299 .bmdma_start
= pdc2026x_bmdma_start
,
300 .bmdma_stop
= pdc2026x_bmdma_stop
,
301 .bmdma_status
= ata_bmdma_status
,
303 .qc_prep
= ata_qc_prep
,
304 .qc_issue
= ata_qc_issue_prot
,
305 .data_xfer
= ata_data_xfer
,
307 .irq_handler
= ata_interrupt
,
308 .irq_clear
= ata_bmdma_irq_clear
,
309 .irq_on
= ata_irq_on
,
311 .port_start
= ata_port_start
,
314 static int pdc202xx_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
316 static const struct ata_port_info info
[3] = {
318 .sht
= &pdc202xx_sht
,
319 .flags
= ATA_FLAG_SLAVE_POSS
,
322 .udma_mask
= ATA_UDMA2
,
323 .port_ops
= &pdc2024x_port_ops
326 .sht
= &pdc202xx_sht
,
327 .flags
= ATA_FLAG_SLAVE_POSS
,
330 .udma_mask
= ATA_UDMA4
,
331 .port_ops
= &pdc2026x_port_ops
334 .sht
= &pdc202xx_sht
,
335 .flags
= ATA_FLAG_SLAVE_POSS
,
338 .udma_mask
= ATA_UDMA5
,
339 .port_ops
= &pdc2026x_port_ops
343 const struct ata_port_info
*ppi
[] = { &info
[id
->driver_data
], NULL
};
345 if (dev
->device
== PCI_DEVICE_ID_PROMISE_20265
) {
346 struct pci_dev
*bridge
= dev
->bus
->self
;
347 /* Don't grab anything behind a Promise I2O RAID */
348 if (bridge
&& bridge
->vendor
== PCI_VENDOR_ID_INTEL
) {
349 if( bridge
->device
== PCI_DEVICE_ID_INTEL_I960
)
351 if( bridge
->device
== PCI_DEVICE_ID_INTEL_I960RM
)
355 return ata_pci_init_one(dev
, ppi
);
358 static const struct pci_device_id pdc202xx
[] = {
359 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20246
), 0 },
360 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20262
), 1 },
361 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20263
), 1 },
362 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20265
), 2 },
363 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20267
), 2 },
368 static struct pci_driver pdc202xx_pci_driver
= {
370 .id_table
= pdc202xx
,
371 .probe
= pdc202xx_init_one
,
372 .remove
= ata_pci_remove_one
,
374 .suspend
= ata_pci_device_suspend
,
375 .resume
= ata_pci_device_resume
,
379 static int __init
pdc202xx_init(void)
381 return pci_register_driver(&pdc202xx_pci_driver
);
384 static void __exit
pdc202xx_exit(void)
386 pci_unregister_driver(&pdc202xx_pci_driver
);
389 MODULE_AUTHOR("Alan Cox");
390 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
391 MODULE_LICENSE("GPL");
392 MODULE_DEVICE_TABLE(pci
, pdc202xx
);
393 MODULE_VERSION(DRV_VERSION
);
395 module_init(pdc202xx_init
);
396 module_exit(pdc202xx_exit
);