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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[deliverable/linux.git] / drivers / ata / pata_scc.c
1 /*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "pata_scc"
46 #define DRV_VERSION "0.3"
47
48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50 /* PCI BARs */
51 #define SCC_CTRL_BAR 0
52 #define SCC_BMID_BAR 1
53
54 /* offset of CTRL registers */
55 #define SCC_CTL_PIOSHT 0x000
56 #define SCC_CTL_PIOCT 0x004
57 #define SCC_CTL_MDMACT 0x008
58 #define SCC_CTL_MCRCST 0x00C
59 #define SCC_CTL_SDMACT 0x010
60 #define SCC_CTL_SCRCST 0x014
61 #define SCC_CTL_UDENVT 0x018
62 #define SCC_CTL_TDVHSEL 0x020
63 #define SCC_CTL_MODEREG 0x024
64 #define SCC_CTL_ECMODE 0xF00
65 #define SCC_CTL_MAEA0 0xF50
66 #define SCC_CTL_MAEC0 0xF54
67 #define SCC_CTL_CCKCTRL 0xFF0
68
69 /* offset of BMID registers */
70 #define SCC_DMA_CMD 0x000
71 #define SCC_DMA_STATUS 0x004
72 #define SCC_DMA_TABLE_OFS 0x008
73 #define SCC_DMA_INTMASK 0x010
74 #define SCC_DMA_INTST 0x014
75 #define SCC_DMA_PTERADD 0x018
76 #define SCC_REG_CMD_ADDR 0x020
77 #define SCC_REG_DATA 0x000
78 #define SCC_REG_ERR 0x004
79 #define SCC_REG_FEATURE 0x004
80 #define SCC_REG_NSECT 0x008
81 #define SCC_REG_LBAL 0x00C
82 #define SCC_REG_LBAM 0x010
83 #define SCC_REG_LBAH 0x014
84 #define SCC_REG_DEVICE 0x018
85 #define SCC_REG_STATUS 0x01C
86 #define SCC_REG_CMD 0x01C
87 #define SCC_REG_ALTSTATUS 0x020
88
89 /* register value */
90 #define TDVHSEL_MASTER 0x00000001
91 #define TDVHSEL_SLAVE 0x00000004
92
93 #define MODE_JCUSFEN 0x00000080
94
95 #define ECMODE_VALUE 0x01
96
97 #define CCKCTRL_ATARESET 0x00040000
98 #define CCKCTRL_BUFCNT 0x00020000
99 #define CCKCTRL_CRST 0x00010000
100 #define CCKCTRL_OCLKEN 0x00000100
101 #define CCKCTRL_ATACLKOEN 0x00000002
102 #define CCKCTRL_LCLKEN 0x00000001
103
104 #define QCHCD_IOS_SS 0x00000001
105
106 #define QCHSD_STPDIAG 0x00020000
107
108 #define INTMASK_MSK 0xD1000012
109 #define INTSTS_SERROR 0x80000000
110 #define INTSTS_PRERR 0x40000000
111 #define INTSTS_RERR 0x10000000
112 #define INTSTS_ICERR 0x01000000
113 #define INTSTS_BMSINT 0x00000010
114 #define INTSTS_BMHE 0x00000008
115 #define INTSTS_IOIRQS 0x00000004
116 #define INTSTS_INTRQ 0x00000002
117 #define INTSTS_ACTEINT 0x00000001
118
119
120 /* PIO transfer mode table */
121 /* JCHST */
122 static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125 };
126
127 /* JCHHT */
128 static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131 };
132
133 /* JCHCT */
134 static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137 };
138
139 /* DMA transfer mode table */
140 /* JCHDCTM/JCHDCTS */
141 static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144 };
145
146 /* JCSTWTM/JCSTWTS */
147 static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150 };
151
152 /* JCTSS */
153 static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156 };
157
158 /* JCENVT */
159 static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162 };
163
164 /* JCACTSELS/JCACTSELM */
165 static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168 };
169
170 static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174 };
175
176 /**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187 static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188 {
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207 }
208
209 /**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221 static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222 {
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259 }
260
261 unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
262 {
263 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
264 if (adev->class == ATA_DEV_ATAPI &&
265 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
266 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
267 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
268 }
269 return ata_pci_default_filter(adev, mask);
270 }
271
272 /**
273 * scc_tf_load - send taskfile registers to host controller
274 * @ap: Port to which output is sent
275 * @tf: ATA taskfile register set
276 *
277 * Note: Original code is ata_tf_load().
278 */
279
280 static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
281 {
282 struct ata_ioports *ioaddr = &ap->ioaddr;
283 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
284
285 if (tf->ctl != ap->last_ctl) {
286 out_be32(ioaddr->ctl_addr, tf->ctl);
287 ap->last_ctl = tf->ctl;
288 ata_wait_idle(ap);
289 }
290
291 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
292 out_be32(ioaddr->feature_addr, tf->hob_feature);
293 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
294 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
295 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
296 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
297 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
298 tf->hob_feature,
299 tf->hob_nsect,
300 tf->hob_lbal,
301 tf->hob_lbam,
302 tf->hob_lbah);
303 }
304
305 if (is_addr) {
306 out_be32(ioaddr->feature_addr, tf->feature);
307 out_be32(ioaddr->nsect_addr, tf->nsect);
308 out_be32(ioaddr->lbal_addr, tf->lbal);
309 out_be32(ioaddr->lbam_addr, tf->lbam);
310 out_be32(ioaddr->lbah_addr, tf->lbah);
311 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
312 tf->feature,
313 tf->nsect,
314 tf->lbal,
315 tf->lbam,
316 tf->lbah);
317 }
318
319 if (tf->flags & ATA_TFLAG_DEVICE) {
320 out_be32(ioaddr->device_addr, tf->device);
321 VPRINTK("device 0x%X\n", tf->device);
322 }
323
324 ata_wait_idle(ap);
325 }
326
327 /**
328 * scc_check_status - Read device status reg & clear interrupt
329 * @ap: port where the device is
330 *
331 * Note: Original code is ata_check_status().
332 */
333
334 static u8 scc_check_status (struct ata_port *ap)
335 {
336 return in_be32(ap->ioaddr.status_addr);
337 }
338
339 /**
340 * scc_tf_read - input device's ATA taskfile shadow registers
341 * @ap: Port from which input is read
342 * @tf: ATA taskfile register set for storing input
343 *
344 * Note: Original code is ata_tf_read().
345 */
346
347 static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
348 {
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350
351 tf->command = scc_check_status(ap);
352 tf->feature = in_be32(ioaddr->error_addr);
353 tf->nsect = in_be32(ioaddr->nsect_addr);
354 tf->lbal = in_be32(ioaddr->lbal_addr);
355 tf->lbam = in_be32(ioaddr->lbam_addr);
356 tf->lbah = in_be32(ioaddr->lbah_addr);
357 tf->device = in_be32(ioaddr->device_addr);
358
359 if (tf->flags & ATA_TFLAG_LBA48) {
360 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
361 tf->hob_feature = in_be32(ioaddr->error_addr);
362 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
363 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
364 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
365 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
366 out_be32(ioaddr->ctl_addr, tf->ctl);
367 ap->last_ctl = tf->ctl;
368 }
369 }
370
371 /**
372 * scc_exec_command - issue ATA command to host controller
373 * @ap: port to which command is being issued
374 * @tf: ATA taskfile register set
375 *
376 * Note: Original code is ata_exec_command().
377 */
378
379 static void scc_exec_command (struct ata_port *ap,
380 const struct ata_taskfile *tf)
381 {
382 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
383
384 out_be32(ap->ioaddr.command_addr, tf->command);
385 ata_pause(ap);
386 }
387
388 /**
389 * scc_check_altstatus - Read device alternate status reg
390 * @ap: port where the device is
391 */
392
393 static u8 scc_check_altstatus (struct ata_port *ap)
394 {
395 return in_be32(ap->ioaddr.altstatus_addr);
396 }
397
398 /**
399 * scc_std_dev_select - Select device 0/1 on ATA bus
400 * @ap: ATA channel to manipulate
401 * @device: ATA device (numbered from zero) to select
402 *
403 * Note: Original code is ata_std_dev_select().
404 */
405
406 static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
407 {
408 u8 tmp;
409
410 if (device == 0)
411 tmp = ATA_DEVICE_OBS;
412 else
413 tmp = ATA_DEVICE_OBS | ATA_DEV1;
414
415 out_be32(ap->ioaddr.device_addr, tmp);
416 ata_pause(ap);
417 }
418
419 /**
420 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
421 * @qc: Info associated with this ATA transaction.
422 *
423 * Note: Original code is ata_bmdma_setup().
424 */
425
426 static void scc_bmdma_setup (struct ata_queued_cmd *qc)
427 {
428 struct ata_port *ap = qc->ap;
429 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
430 u8 dmactl;
431 void __iomem *mmio = ap->ioaddr.bmdma_addr;
432
433 /* load PRD table addr */
434 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
435
436 /* specify data direction, triple-check start bit is clear */
437 dmactl = in_be32(mmio + SCC_DMA_CMD);
438 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
439 if (!rw)
440 dmactl |= ATA_DMA_WR;
441 out_be32(mmio + SCC_DMA_CMD, dmactl);
442
443 /* issue r/w command */
444 ap->ops->exec_command(ap, &qc->tf);
445 }
446
447 /**
448 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
449 * @qc: Info associated with this ATA transaction.
450 *
451 * Note: Original code is ata_bmdma_start().
452 */
453
454 static void scc_bmdma_start (struct ata_queued_cmd *qc)
455 {
456 struct ata_port *ap = qc->ap;
457 u8 dmactl;
458 void __iomem *mmio = ap->ioaddr.bmdma_addr;
459
460 /* start host DMA transaction */
461 dmactl = in_be32(mmio + SCC_DMA_CMD);
462 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
463 }
464
465 /**
466 * scc_devchk - PATA device presence detection
467 * @ap: ATA channel to examine
468 * @device: Device to examine (starting at zero)
469 *
470 * Note: Original code is ata_devchk().
471 */
472
473 static unsigned int scc_devchk (struct ata_port *ap,
474 unsigned int device)
475 {
476 struct ata_ioports *ioaddr = &ap->ioaddr;
477 u8 nsect, lbal;
478
479 ap->ops->dev_select(ap, device);
480
481 out_be32(ioaddr->nsect_addr, 0x55);
482 out_be32(ioaddr->lbal_addr, 0xaa);
483
484 out_be32(ioaddr->nsect_addr, 0xaa);
485 out_be32(ioaddr->lbal_addr, 0x55);
486
487 out_be32(ioaddr->nsect_addr, 0x55);
488 out_be32(ioaddr->lbal_addr, 0xaa);
489
490 nsect = in_be32(ioaddr->nsect_addr);
491 lbal = in_be32(ioaddr->lbal_addr);
492
493 if ((nsect == 0x55) && (lbal == 0xaa))
494 return 1; /* we found a device */
495
496 return 0; /* nothing found */
497 }
498
499 /**
500 * scc_bus_post_reset - PATA device post reset
501 *
502 * Note: Original code is ata_bus_post_reset().
503 */
504
505 static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
506 unsigned long deadline)
507 {
508 struct ata_ioports *ioaddr = &ap->ioaddr;
509 unsigned int dev0 = devmask & (1 << 0);
510 unsigned int dev1 = devmask & (1 << 1);
511 int rc;
512
513 /* if device 0 was found in ata_devchk, wait for its
514 * BSY bit to clear
515 */
516 if (dev0) {
517 rc = ata_wait_ready(ap, deadline);
518 if (rc && rc != -ENODEV)
519 return rc;
520 }
521
522 /* if device 1 was found in ata_devchk, wait for
523 * register access, then wait for BSY to clear
524 */
525 while (dev1) {
526 u8 nsect, lbal;
527
528 ap->ops->dev_select(ap, 1);
529 nsect = in_be32(ioaddr->nsect_addr);
530 lbal = in_be32(ioaddr->lbal_addr);
531 if ((nsect == 1) && (lbal == 1))
532 break;
533 if (time_after(jiffies, deadline))
534 return -EBUSY;
535 msleep(50); /* give drive a breather */
536 }
537 if (dev1) {
538 rc = ata_wait_ready(ap, deadline);
539 if (rc && rc != -ENODEV)
540 return rc;
541 }
542
543 /* is all this really necessary? */
544 ap->ops->dev_select(ap, 0);
545 if (dev1)
546 ap->ops->dev_select(ap, 1);
547 if (dev0)
548 ap->ops->dev_select(ap, 0);
549
550 return 0;
551 }
552
553 /**
554 * scc_bus_softreset - PATA device software reset
555 *
556 * Note: Original code is ata_bus_softreset().
557 */
558
559 static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
560 unsigned long deadline)
561 {
562 struct ata_ioports *ioaddr = &ap->ioaddr;
563
564 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
565
566 /* software reset. causes dev0 to be selected */
567 out_be32(ioaddr->ctl_addr, ap->ctl);
568 udelay(20);
569 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
570 udelay(20);
571 out_be32(ioaddr->ctl_addr, ap->ctl);
572
573 /* spec mandates ">= 2ms" before checking status.
574 * We wait 150ms, because that was the magic delay used for
575 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
576 * between when the ATA command register is written, and then
577 * status is checked. Because waiting for "a while" before
578 * checking status is fine, post SRST, we perform this magic
579 * delay here as well.
580 *
581 * Old drivers/ide uses the 2mS rule and then waits for ready
582 */
583 msleep(150);
584
585 /* Before we perform post reset processing we want to see if
586 * the bus shows 0xFF because the odd clown forgets the D7
587 * pulldown resistor.
588 */
589 if (scc_check_status(ap) == 0xFF)
590 return 0;
591
592 scc_bus_post_reset(ap, devmask, deadline);
593
594 return 0;
595 }
596
597 /**
598 * scc_std_softreset - reset host port via ATA SRST
599 * @ap: port to reset
600 * @classes: resulting classes of attached devices
601 * @deadline: deadline jiffies for the operation
602 *
603 * Note: Original code is ata_std_softreset().
604 */
605
606 static int scc_std_softreset(struct ata_link *link, unsigned int *classes,
607 unsigned long deadline)
608 {
609 struct ata_port *ap = link->ap;
610 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
611 unsigned int devmask = 0, err_mask;
612 u8 err;
613
614 DPRINTK("ENTER\n");
615
616 if (ata_link_offline(link)) {
617 classes[0] = ATA_DEV_NONE;
618 goto out;
619 }
620
621 /* determine if device 0/1 are present */
622 if (scc_devchk(ap, 0))
623 devmask |= (1 << 0);
624 if (slave_possible && scc_devchk(ap, 1))
625 devmask |= (1 << 1);
626
627 /* select device 0 again */
628 ap->ops->dev_select(ap, 0);
629
630 /* issue bus reset */
631 DPRINTK("about to softreset, devmask=%x\n", devmask);
632 err_mask = scc_bus_softreset(ap, devmask, deadline);
633 if (err_mask) {
634 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
635 err_mask);
636 return -EIO;
637 }
638
639 /* determine by signature whether we have ATA or ATAPI devices */
640 classes[0] = ata_dev_try_classify(&ap->link.device[0],
641 devmask & (1 << 0), &err);
642 if (slave_possible && err != 0x81)
643 classes[1] = ata_dev_try_classify(&ap->link.device[1],
644 devmask & (1 << 1), &err);
645
646 out:
647 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
648 return 0;
649 }
650
651 /**
652 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
653 * @qc: Command we are ending DMA for
654 */
655
656 static void scc_bmdma_stop (struct ata_queued_cmd *qc)
657 {
658 struct ata_port *ap = qc->ap;
659 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
660 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
661 u32 reg;
662
663 while (1) {
664 reg = in_be32(bmid_base + SCC_DMA_INTST);
665
666 if (reg & INTSTS_SERROR) {
667 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
668 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
669 out_be32(bmid_base + SCC_DMA_CMD,
670 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
671 continue;
672 }
673
674 if (reg & INTSTS_PRERR) {
675 u32 maea0, maec0;
676 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
677 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
678 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
679 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
680 out_be32(bmid_base + SCC_DMA_CMD,
681 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
682 continue;
683 }
684
685 if (reg & INTSTS_RERR) {
686 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
687 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
688 out_be32(bmid_base + SCC_DMA_CMD,
689 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
690 continue;
691 }
692
693 if (reg & INTSTS_ICERR) {
694 out_be32(bmid_base + SCC_DMA_CMD,
695 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
696 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
697 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
698 continue;
699 }
700
701 if (reg & INTSTS_BMSINT) {
702 unsigned int classes;
703 unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
704 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
705 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
706 /* TBD: SW reset */
707 scc_std_softreset(&ap->link, &classes, deadline);
708 continue;
709 }
710
711 if (reg & INTSTS_BMHE) {
712 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
713 continue;
714 }
715
716 if (reg & INTSTS_ACTEINT) {
717 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
718 continue;
719 }
720
721 if (reg & INTSTS_IOIRQS) {
722 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
723 continue;
724 }
725 break;
726 }
727
728 /* clear start/stop bit */
729 out_be32(bmid_base + SCC_DMA_CMD,
730 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
731
732 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
733 ata_altstatus(ap); /* dummy read */
734 }
735
736 /**
737 * scc_bmdma_status - Read PCI IDE BMDMA status
738 * @ap: Port associated with this ATA transaction.
739 */
740
741 static u8 scc_bmdma_status (struct ata_port *ap)
742 {
743 void __iomem *mmio = ap->ioaddr.bmdma_addr;
744 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
745 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
746 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
747 static int retry = 0;
748
749 /* return if IOS_SS is cleared */
750 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
751 return host_stat;
752
753 /* errata A252,A308 workaround: Step4 */
754 if ((ata_altstatus(ap) & ATA_ERR) && (int_status & INTSTS_INTRQ))
755 return (host_stat | ATA_DMA_INTR);
756
757 /* errata A308 workaround Step5 */
758 if (int_status & INTSTS_IOIRQS) {
759 host_stat |= ATA_DMA_INTR;
760
761 /* We don't check ATAPI DMA because it is limited to UDMA4 */
762 if ((qc->tf.protocol == ATA_PROT_DMA &&
763 qc->dev->xfer_mode > XFER_UDMA_4)) {
764 if (!(int_status & INTSTS_ACTEINT)) {
765 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
766 ap->print_id);
767 host_stat |= ATA_DMA_ERR;
768 if (retry++)
769 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
770 } else
771 retry = 0;
772 }
773 }
774
775 return host_stat;
776 }
777
778 /**
779 * scc_data_xfer - Transfer data by PIO
780 * @adev: device for this I/O
781 * @buf: data buffer
782 * @buflen: buffer length
783 * @write_data: read/write
784 *
785 * Note: Original code is ata_data_xfer().
786 */
787
788 static void scc_data_xfer (struct ata_device *adev, unsigned char *buf,
789 unsigned int buflen, int write_data)
790 {
791 struct ata_port *ap = adev->link->ap;
792 unsigned int words = buflen >> 1;
793 unsigned int i;
794 u16 *buf16 = (u16 *) buf;
795 void __iomem *mmio = ap->ioaddr.data_addr;
796
797 /* Transfer multiple of 2 bytes */
798 if (write_data) {
799 for (i = 0; i < words; i++)
800 out_be32(mmio, cpu_to_le16(buf16[i]));
801 } else {
802 for (i = 0; i < words; i++)
803 buf16[i] = le16_to_cpu(in_be32(mmio));
804 }
805
806 /* Transfer trailing 1 byte, if any. */
807 if (unlikely(buflen & 0x01)) {
808 u16 align_buf[1] = { 0 };
809 unsigned char *trailing_buf = buf + buflen - 1;
810
811 if (write_data) {
812 memcpy(align_buf, trailing_buf, 1);
813 out_be32(mmio, cpu_to_le16(align_buf[0]));
814 } else {
815 align_buf[0] = le16_to_cpu(in_be32(mmio));
816 memcpy(trailing_buf, align_buf, 1);
817 }
818 }
819 }
820
821 /**
822 * scc_irq_on - Enable interrupts on a port.
823 * @ap: Port on which interrupts are enabled.
824 *
825 * Note: Original code is ata_irq_on().
826 */
827
828 static u8 scc_irq_on (struct ata_port *ap)
829 {
830 struct ata_ioports *ioaddr = &ap->ioaddr;
831 u8 tmp;
832
833 ap->ctl &= ~ATA_NIEN;
834 ap->last_ctl = ap->ctl;
835
836 out_be32(ioaddr->ctl_addr, ap->ctl);
837 tmp = ata_wait_idle(ap);
838
839 ap->ops->irq_clear(ap);
840
841 return tmp;
842 }
843
844 /**
845 * scc_bmdma_freeze - Freeze BMDMA controller port
846 * @ap: port to freeze
847 *
848 * Note: Original code is ata_bmdma_freeze().
849 */
850
851 static void scc_bmdma_freeze (struct ata_port *ap)
852 {
853 struct ata_ioports *ioaddr = &ap->ioaddr;
854
855 ap->ctl |= ATA_NIEN;
856 ap->last_ctl = ap->ctl;
857
858 out_be32(ioaddr->ctl_addr, ap->ctl);
859
860 /* Under certain circumstances, some controllers raise IRQ on
861 * ATA_NIEN manipulation. Also, many controllers fail to mask
862 * previously pending IRQ on ATA_NIEN assertion. Clear it.
863 */
864 ata_chk_status(ap);
865
866 ap->ops->irq_clear(ap);
867 }
868
869 /**
870 * scc_pata_prereset - prepare for reset
871 * @ap: ATA port to be reset
872 * @deadline: deadline jiffies for the operation
873 */
874
875 static int scc_pata_prereset(struct ata_link *link, unsigned long deadline)
876 {
877 link->ap->cbl = ATA_CBL_PATA80;
878 return ata_std_prereset(link, deadline);
879 }
880
881 /**
882 * scc_std_postreset - standard postreset callback
883 * @ap: the target ata_port
884 * @classes: classes of attached devices
885 *
886 * Note: Original code is ata_std_postreset().
887 */
888
889 static void scc_std_postreset(struct ata_link *link, unsigned int *classes)
890 {
891 struct ata_port *ap = link->ap;
892
893 DPRINTK("ENTER\n");
894
895 /* is double-select really necessary? */
896 if (classes[0] != ATA_DEV_NONE)
897 ap->ops->dev_select(ap, 1);
898 if (classes[1] != ATA_DEV_NONE)
899 ap->ops->dev_select(ap, 0);
900
901 /* bail out if no device is present */
902 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
903 DPRINTK("EXIT, no device\n");
904 return;
905 }
906
907 /* set up device control */
908 if (ap->ioaddr.ctl_addr)
909 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
910
911 DPRINTK("EXIT\n");
912 }
913
914 /**
915 * scc_error_handler - Stock error handler for BMDMA controller
916 * @ap: port to handle error for
917 */
918
919 static void scc_error_handler (struct ata_port *ap)
920 {
921 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
922 scc_std_postreset);
923 }
924
925 /**
926 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
927 * @ap: Port associated with this ATA transaction.
928 *
929 * Note: Original code is ata_bmdma_irq_clear().
930 */
931
932 static void scc_bmdma_irq_clear (struct ata_port *ap)
933 {
934 void __iomem *mmio = ap->ioaddr.bmdma_addr;
935
936 if (!mmio)
937 return;
938
939 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
940 }
941
942 /**
943 * scc_port_start - Set port up for dma.
944 * @ap: Port to initialize
945 *
946 * Allocate space for PRD table using ata_port_start().
947 * Set PRD table address for PTERADD. (PRD Transfer End Read)
948 */
949
950 static int scc_port_start (struct ata_port *ap)
951 {
952 void __iomem *mmio = ap->ioaddr.bmdma_addr;
953 int rc;
954
955 rc = ata_port_start(ap);
956 if (rc)
957 return rc;
958
959 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
960 return 0;
961 }
962
963 /**
964 * scc_port_stop - Undo scc_port_start()
965 * @ap: Port to shut down
966 *
967 * Reset PTERADD.
968 */
969
970 static void scc_port_stop (struct ata_port *ap)
971 {
972 void __iomem *mmio = ap->ioaddr.bmdma_addr;
973
974 out_be32(mmio + SCC_DMA_PTERADD, 0);
975 }
976
977 static struct scsi_host_template scc_sht = {
978 .module = THIS_MODULE,
979 .name = DRV_NAME,
980 .ioctl = ata_scsi_ioctl,
981 .queuecommand = ata_scsi_queuecmd,
982 .can_queue = ATA_DEF_QUEUE,
983 .this_id = ATA_SHT_THIS_ID,
984 .sg_tablesize = LIBATA_MAX_PRD,
985 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
986 .emulated = ATA_SHT_EMULATED,
987 .use_clustering = ATA_SHT_USE_CLUSTERING,
988 .proc_name = DRV_NAME,
989 .dma_boundary = ATA_DMA_BOUNDARY,
990 .slave_configure = ata_scsi_slave_config,
991 .slave_destroy = ata_scsi_slave_destroy,
992 .bios_param = ata_std_bios_param,
993 };
994
995 static const struct ata_port_operations scc_pata_ops = {
996 .set_piomode = scc_set_piomode,
997 .set_dmamode = scc_set_dmamode,
998 .mode_filter = scc_mode_filter,
999
1000 .tf_load = scc_tf_load,
1001 .tf_read = scc_tf_read,
1002 .exec_command = scc_exec_command,
1003 .check_status = scc_check_status,
1004 .check_altstatus = scc_check_altstatus,
1005 .dev_select = scc_std_dev_select,
1006
1007 .bmdma_setup = scc_bmdma_setup,
1008 .bmdma_start = scc_bmdma_start,
1009 .bmdma_stop = scc_bmdma_stop,
1010 .bmdma_status = scc_bmdma_status,
1011 .data_xfer = scc_data_xfer,
1012
1013 .qc_prep = ata_qc_prep,
1014 .qc_issue = ata_qc_issue_prot,
1015
1016 .freeze = scc_bmdma_freeze,
1017 .error_handler = scc_error_handler,
1018 .post_internal_cmd = scc_bmdma_stop,
1019
1020 .irq_clear = scc_bmdma_irq_clear,
1021 .irq_on = scc_irq_on,
1022
1023 .port_start = scc_port_start,
1024 .port_stop = scc_port_stop,
1025 };
1026
1027 static struct ata_port_info scc_port_info[] = {
1028 {
1029 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1030 .pio_mask = 0x1f, /* pio0-4 */
1031 .mwdma_mask = 0x00,
1032 .udma_mask = ATA_UDMA6,
1033 .port_ops = &scc_pata_ops,
1034 },
1035 };
1036
1037 /**
1038 * scc_reset_controller - initialize SCC PATA controller.
1039 */
1040
1041 static int scc_reset_controller(struct ata_host *host)
1042 {
1043 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1044 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
1045 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1046 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1047 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1048 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1049 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1050 u32 reg = 0;
1051
1052 out_be32(cckctrl_port, reg);
1053 reg |= CCKCTRL_ATACLKOEN;
1054 out_be32(cckctrl_port, reg);
1055 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1056 out_be32(cckctrl_port, reg);
1057 reg |= CCKCTRL_CRST;
1058 out_be32(cckctrl_port, reg);
1059
1060 for (;;) {
1061 reg = in_be32(cckctrl_port);
1062 if (reg & CCKCTRL_CRST)
1063 break;
1064 udelay(5000);
1065 }
1066
1067 reg |= CCKCTRL_ATARESET;
1068 out_be32(cckctrl_port, reg);
1069 out_be32(ecmode_port, ECMODE_VALUE);
1070 out_be32(mode_port, MODE_JCUSFEN);
1071 out_be32(intmask_port, INTMASK_MSK);
1072
1073 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1074 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1075 return -EIO;
1076 }
1077
1078 return 0;
1079 }
1080
1081 /**
1082 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1083 * @ioaddr: IO address structure to be initialized
1084 * @base: base address of BMID region
1085 */
1086
1087 static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1088 {
1089 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1090 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1091 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1092 ioaddr->bmdma_addr = base;
1093 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1094 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1095 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1096 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1097 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1098 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1099 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1100 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1101 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1102 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1103 }
1104
1105 static int scc_host_init(struct ata_host *host)
1106 {
1107 struct pci_dev *pdev = to_pci_dev(host->dev);
1108 int rc;
1109
1110 rc = scc_reset_controller(host);
1111 if (rc)
1112 return rc;
1113
1114 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1115 if (rc)
1116 return rc;
1117 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1118 if (rc)
1119 return rc;
1120
1121 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1122
1123 pci_set_master(pdev);
1124
1125 return 0;
1126 }
1127
1128 /**
1129 * scc_init_one - Register SCC PATA device with kernel services
1130 * @pdev: PCI device to register
1131 * @ent: Entry in scc_pci_tbl matching with @pdev
1132 *
1133 * LOCKING:
1134 * Inherited from PCI layer (may sleep).
1135 *
1136 * RETURNS:
1137 * Zero on success, or -ERRNO value.
1138 */
1139
1140 static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1141 {
1142 static int printed_version;
1143 unsigned int board_idx = (unsigned int) ent->driver_data;
1144 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1145 struct ata_host *host;
1146 int rc;
1147
1148 if (!printed_version++)
1149 dev_printk(KERN_DEBUG, &pdev->dev,
1150 "version " DRV_VERSION "\n");
1151
1152 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1153 if (!host)
1154 return -ENOMEM;
1155
1156 rc = pcim_enable_device(pdev);
1157 if (rc)
1158 return rc;
1159
1160 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1161 if (rc == -EBUSY)
1162 pcim_pin_device(pdev);
1163 if (rc)
1164 return rc;
1165 host->iomap = pcim_iomap_table(pdev);
1166
1167 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1168 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1169
1170 rc = scc_host_init(host);
1171 if (rc)
1172 return rc;
1173
1174 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1175 &scc_sht);
1176 }
1177
1178 static struct pci_driver scc_pci_driver = {
1179 .name = DRV_NAME,
1180 .id_table = scc_pci_tbl,
1181 .probe = scc_init_one,
1182 .remove = ata_pci_remove_one,
1183 #ifdef CONFIG_PM
1184 .suspend = ata_pci_device_suspend,
1185 .resume = ata_pci_device_resume,
1186 #endif
1187 };
1188
1189 static int __init scc_init (void)
1190 {
1191 int rc;
1192
1193 DPRINTK("pci_register_driver\n");
1194 rc = pci_register_driver(&scc_pci_driver);
1195 if (rc)
1196 return rc;
1197
1198 DPRINTK("done\n");
1199 return 0;
1200 }
1201
1202 static void __exit scc_exit (void)
1203 {
1204 pci_unregister_driver(&scc_pci_driver);
1205 }
1206
1207 module_init(scc_init);
1208 module_exit(scc_exit);
1209
1210 MODULE_AUTHOR("Toshiba corp");
1211 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1212 MODULE_LICENSE("GPL");
1213 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1214 MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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