drivers/ata/pdc_adma.c

   1 /*
   2  *  pdc_adma.c - Pacific Digital Corporation ADMA
   3  *
   4  *  Maintained by:  Mark Lord <mlord@pobox.com>
   5  *
   6  *  Copyright 2005 Mark Lord
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2, or (at your option)
  11  *  any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; see the file COPYING.  If not, write to
  20  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  *
  23  *  libata documentation is available via 'make {ps|pdf}docs',
  24  *  as Documentation/DocBook/libata.*
  25  *
  26  *
  27  *  Supports ATA disks in single-packet ADMA mode.
  28  *  Uses PIO for everything else.
  29  *
  30  *  TODO:  Use ADMA transfers for ATAPI devices, when possible.
  31  *  This requires careful attention to a number of quirks of the chip.
  32  *
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/init.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/delay.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sched.h>
  43 #include <linux/device.h>
  44 #include <scsi/scsi_host.h>
  45 #include <linux/libata.h>
  46
  47 #define DRV_NAME        "pdc_adma"
  48 #define DRV_VERSION     "0.04"
  49
  50 /* macro to calculate base address for ATA regs */
  51 #define ADMA_ATA_REGS(base,port_no)     ((base) + ((port_no) * 0x40))
  52
  53 /* macro to calculate base address for ADMA regs */
  54 #define ADMA_REGS(base,port_no)         ((base) + 0x80 + ((port_no) * 0x20))
  55
  56 /* macro to obtain addresses from ata_host */
  57 #define ADMA_HOST_REGS(host,port_no) \
  58         ADMA_REGS((host)->iomap[ADMA_MMIO_BAR], port_no)
  59
  60 enum {
  61         ADMA_MMIO_BAR           = 4,
  62
  63         ADMA_PORTS              = 2,
  64         ADMA_CPB_BYTES          = 40,
  65         ADMA_PRD_BYTES          = LIBATA_MAX_PRD * 16,
  66         ADMA_PKT_BYTES          = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
  67
  68         ADMA_DMA_BOUNDARY       = 0xffffffff,
  69
  70         /* global register offsets */
  71         ADMA_MODE_LOCK          = 0x00c7,
  72
  73         /* per-channel register offsets */
  74         ADMA_CONTROL            = 0x0000, /* ADMA control */
  75         ADMA_STATUS             = 0x0002, /* ADMA status */
  76         ADMA_CPB_COUNT          = 0x0004, /* CPB count */
  77         ADMA_CPB_CURRENT        = 0x000c, /* current CPB address */
  78         ADMA_CPB_NEXT           = 0x000c, /* next CPB address */
  79         ADMA_CPB_LOOKUP         = 0x0010, /* CPB lookup table */
  80         ADMA_FIFO_IN            = 0x0014, /* input FIFO threshold */
  81         ADMA_FIFO_OUT           = 0x0016, /* output FIFO threshold */
  82
  83         /* ADMA_CONTROL register bits */
  84         aNIEN                   = (1 << 8), /* irq mask: 1==masked */
  85         aGO                     = (1 << 7), /* packet trigger ("Go!") */
  86         aRSTADM                 = (1 << 5), /* ADMA logic reset */
  87         aPIOMD4                 = 0x0003,   /* PIO mode 4 */
  88
  89         /* ADMA_STATUS register bits */
  90         aPSD                    = (1 << 6),
  91         aUIRQ                   = (1 << 4),
  92         aPERR                   = (1 << 0),
  93
  94         /* CPB bits */
  95         cDONE                   = (1 << 0),
  96         cVLD                    = (1 << 0),
  97         cDAT                    = (1 << 2),
  98         cIEN                    = (1 << 3),
  99
 100         /* PRD bits */
 101         pORD                    = (1 << 4),
 102         pDIRO                   = (1 << 5),
 103         pEND                    = (1 << 7),
 104
 105         /* ATA register flags */
 106         rIGN                    = (1 << 5),
 107         rEND                    = (1 << 7),
 108
 109         /* ATA register addresses */
 110         ADMA_REGS_CONTROL       = 0x0e,
 111         ADMA_REGS_SECTOR_COUNT  = 0x12,
 112         ADMA_REGS_LBA_LOW       = 0x13,
 113         ADMA_REGS_LBA_MID       = 0x14,
 114         ADMA_REGS_LBA_HIGH      = 0x15,
 115         ADMA_REGS_DEVICE        = 0x16,
 116         ADMA_REGS_COMMAND       = 0x17,
 117
 118         /* PCI device IDs */
 119         board_1841_idx          = 0,    /* ADMA 2-port controller */
 120 };
 121
 122 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
 123
 124 struct adma_port_priv {
 125         u8                      *pkt;
 126         dma_addr_t              pkt_dma;
 127         adma_state_t            state;
 128 };
 129
 130 static int adma_ata_init_one (struct pci_dev *pdev,
 131                                 const struct pci_device_id *ent);
 132 static irqreturn_t adma_intr (int irq, void *dev_instance);
 133 static int adma_port_start(struct ata_port *ap);
 134 static void adma_host_stop(struct ata_host *host);
 135 static void adma_port_stop(struct ata_port *ap);
 136 static void adma_phy_reset(struct ata_port *ap);
 137 static void adma_qc_prep(struct ata_queued_cmd *qc);
 138 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
 139 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
 140 static void adma_bmdma_stop(struct ata_queued_cmd *qc);
 141 static u8 adma_bmdma_status(struct ata_port *ap);
 142 static void adma_irq_clear(struct ata_port *ap);
 143 static void adma_eng_timeout(struct ata_port *ap);
 144
 145 static struct scsi_host_template adma_ata_sht = {
 146         .module                 = THIS_MODULE,
 147         .name                   = DRV_NAME,
 148         .ioctl                  = ata_scsi_ioctl,
 149         .queuecommand           = ata_scsi_queuecmd,
 150         .can_queue              = ATA_DEF_QUEUE,
 151         .this_id                = ATA_SHT_THIS_ID,
 152         .sg_tablesize           = LIBATA_MAX_PRD,
 153         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 154         .emulated               = ATA_SHT_EMULATED,
 155         .use_clustering         = ENABLE_CLUSTERING,
 156         .proc_name              = DRV_NAME,
 157         .dma_boundary           = ADMA_DMA_BOUNDARY,
 158         .slave_configure        = ata_scsi_slave_config,
 159         .slave_destroy          = ata_scsi_slave_destroy,
 160         .bios_param             = ata_std_bios_param,
 161 };
 162
 163 static const struct ata_port_operations adma_ata_ops = {
 164         .port_disable           = ata_port_disable,
 165         .tf_load                = ata_tf_load,
 166         .tf_read                = ata_tf_read,
 167         .check_status           = ata_check_status,
 168         .check_atapi_dma        = adma_check_atapi_dma,
 169         .exec_command           = ata_exec_command,
 170         .dev_select             = ata_std_dev_select,
 171         .phy_reset              = adma_phy_reset,
 172         .qc_prep                = adma_qc_prep,
 173         .qc_issue               = adma_qc_issue,
 174         .eng_timeout            = adma_eng_timeout,
 175         .data_xfer              = ata_data_xfer,
 176         .irq_handler            = adma_intr,
 177         .irq_clear              = adma_irq_clear,
 178         .irq_on                 = ata_irq_on,
 179         .irq_ack                = ata_irq_ack,
 180         .port_start             = adma_port_start,
 181         .port_stop              = adma_port_stop,
 182         .host_stop              = adma_host_stop,
 183         .bmdma_stop             = adma_bmdma_stop,
 184         .bmdma_status           = adma_bmdma_status,
 185 };
 186
 187 static struct ata_port_info adma_port_info[] = {
 188         /* board_1841_idx */
 189         {
 190                 .sht            = &adma_ata_sht,
 191                 .flags          = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
 192                                   ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
 193                                   ATA_FLAG_PIO_POLLING,
 194                 .pio_mask       = 0x10, /* pio4 */
 195                 .udma_mask      = 0x1f, /* udma0-4 */
 196                 .port_ops       = &adma_ata_ops,
 197         },
 198 };
 199
 200 static const struct pci_device_id adma_ata_pci_tbl[] = {
 201         { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
 202
 203         { }     /* terminate list */
 204 };
 205
 206 static struct pci_driver adma_ata_pci_driver = {
 207         .name                   = DRV_NAME,
 208         .id_table               = adma_ata_pci_tbl,
 209         .probe                  = adma_ata_init_one,
 210         .remove                 = ata_pci_remove_one,
 211 };
 212
 213 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
 214 {
 215         return 1;       /* ATAPI DMA not yet supported */
 216 }
 217
 218 static void adma_bmdma_stop(struct ata_queued_cmd *qc)
 219 {
 220         /* nothing */
 221 }
 222
 223 static u8 adma_bmdma_status(struct ata_port *ap)
 224 {
 225         return 0;
 226 }
 227
 228 static void adma_irq_clear(struct ata_port *ap)
 229 {
 230         /* nothing */
 231 }
 232
 233 static void adma_reset_engine(void __iomem *chan)
 234 {
 235         /* reset ADMA to idle state */
 236         writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
 237         udelay(2);
 238         writew(aPIOMD4, chan + ADMA_CONTROL);
 239         udelay(2);
 240 }
 241
 242 static void adma_reinit_engine(struct ata_port *ap)
 243 {
 244         struct adma_port_priv *pp = ap->private_data;
 245         void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no);
 246
 247         /* mask/clear ATA interrupts */
 248         writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
 249         ata_check_status(ap);
 250
 251         /* reset the ADMA engine */
 252         adma_reset_engine(chan);
 253
 254         /* set in-FIFO threshold to 0x100 */
 255         writew(0x100, chan + ADMA_FIFO_IN);
 256
 257         /* set CPB pointer */
 258         writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
 259
 260         /* set out-FIFO threshold to 0x100 */
 261         writew(0x100, chan + ADMA_FIFO_OUT);
 262
 263         /* set CPB count */
 264         writew(1, chan + ADMA_CPB_COUNT);
 265
 266         /* read/discard ADMA status */
 267         readb(chan + ADMA_STATUS);
 268 }
 269
 270 static inline void adma_enter_reg_mode(struct ata_port *ap)
 271 {
 272         void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no);
 273
 274         writew(aPIOMD4, chan + ADMA_CONTROL);
 275         readb(chan + ADMA_STATUS);      /* flush */
 276 }
 277
 278 static void adma_phy_reset(struct ata_port *ap)
 279 {
 280         struct adma_port_priv *pp = ap->private_data;
 281
 282         pp->state = adma_state_idle;
 283         adma_reinit_engine(ap);
 284         ata_port_probe(ap);
 285         ata_bus_reset(ap);
 286 }
 287
 288 static void adma_eng_timeout(struct ata_port *ap)
 289 {
 290         struct adma_port_priv *pp = ap->private_data;
 291
 292         if (pp->state != adma_state_idle) /* healthy paranoia */
 293                 pp->state = adma_state_mmio;
 294         adma_reinit_engine(ap);
 295         ata_eng_timeout(ap);
 296 }
 297
 298 static int adma_fill_sg(struct ata_queued_cmd *qc)
 299 {
 300         struct scatterlist *sg;
 301         struct ata_port *ap = qc->ap;
 302         struct adma_port_priv *pp = ap->private_data;
 303         u8  *buf = pp->pkt;
 304         int i = (2 + buf[3]) * 8;
 305         u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
 306
 307         ata_for_each_sg(sg, qc) {
 308                 u32 addr;
 309                 u32 len;
 310
 311                 addr = (u32)sg_dma_address(sg);
 312                 *(__le32 *)(buf + i) = cpu_to_le32(addr);
 313                 i += 4;
 314
 315                 len = sg_dma_len(sg) >> 3;
 316                 *(__le32 *)(buf + i) = cpu_to_le32(len);
 317                 i += 4;
 318
 319                 if (ata_sg_is_last(sg, qc))
 320                         pFLAGS |= pEND;
 321                 buf[i++] = pFLAGS;
 322                 buf[i++] = qc->dev->dma_mode & 0xf;
 323                 buf[i++] = 0;   /* pPKLW */
 324                 buf[i++] = 0;   /* reserved */
 325
 326                 *(__le32 *)(buf + i)
 327                         = (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
 328                 i += 4;
 329
 330                 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
 331                                         (unsigned long)addr, len);
 332         }
 333         return i;
 334 }
 335
 336 static void adma_qc_prep(struct ata_queued_cmd *qc)
 337 {
 338         struct adma_port_priv *pp = qc->ap->private_data;
 339         u8  *buf = pp->pkt;
 340         u32 pkt_dma = (u32)pp->pkt_dma;
 341         int i = 0;
 342
 343         VPRINTK("ENTER\n");
 344
 345         adma_enter_reg_mode(qc->ap);
 346         if (qc->tf.protocol != ATA_PROT_DMA) {
 347                 ata_qc_prep(qc);
 348                 return;
 349         }
 350
 351         buf[i++] = 0;   /* Response flags */
 352         buf[i++] = 0;   /* reserved */
 353         buf[i++] = cVLD | cDAT | cIEN;
 354         i++;            /* cLEN, gets filled in below */
 355
 356         *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma);      /* cNCPB */
 357         i += 4;         /* cNCPB */
 358         i += 4;         /* cPRD, gets filled in below */
 359
 360         buf[i++] = 0;   /* reserved */
 361         buf[i++] = 0;   /* reserved */
 362         buf[i++] = 0;   /* reserved */
 363         buf[i++] = 0;   /* reserved */
 364
 365         /* ATA registers; must be a multiple of 4 */
 366         buf[i++] = qc->tf.device;
 367         buf[i++] = ADMA_REGS_DEVICE;
 368         if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
 369                 buf[i++] = qc->tf.hob_nsect;
 370                 buf[i++] = ADMA_REGS_SECTOR_COUNT;
 371                 buf[i++] = qc->tf.hob_lbal;
 372                 buf[i++] = ADMA_REGS_LBA_LOW;
 373                 buf[i++] = qc->tf.hob_lbam;
 374                 buf[i++] = ADMA_REGS_LBA_MID;
 375                 buf[i++] = qc->tf.hob_lbah;
 376                 buf[i++] = ADMA_REGS_LBA_HIGH;
 377         }
 378         buf[i++] = qc->tf.nsect;
 379         buf[i++] = ADMA_REGS_SECTOR_COUNT;
 380         buf[i++] = qc->tf.lbal;
 381         buf[i++] = ADMA_REGS_LBA_LOW;
 382         buf[i++] = qc->tf.lbam;
 383         buf[i++] = ADMA_REGS_LBA_MID;
 384         buf[i++] = qc->tf.lbah;
 385         buf[i++] = ADMA_REGS_LBA_HIGH;
 386         buf[i++] = 0;
 387         buf[i++] = ADMA_REGS_CONTROL;
 388         buf[i++] = rIGN;
 389         buf[i++] = 0;
 390         buf[i++] = qc->tf.command;
 391         buf[i++] = ADMA_REGS_COMMAND | rEND;
 392
 393         buf[3] = (i >> 3) - 2;                          /* cLEN */
 394         *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i);  /* cPRD */
 395
 396         i = adma_fill_sg(qc);
 397         wmb();  /* flush PRDs and pkt to memory */
 398 #if 0
 399         /* dump out CPB + PRDs for debug */
 400         {
 401                 int j, len = 0;
 402                 static char obuf[2048];
 403                 for (j = 0; j < i; ++j) {
 404                         len += sprintf(obuf+len, "%02x ", buf[j]);
 405                         if ((j & 7) == 7) {
 406                                 printk("%s\n", obuf);
 407                                 len = 0;
 408                         }
 409                 }
 410                 if (len)
 411                         printk("%s\n", obuf);
 412         }
 413 #endif
 414 }
 415
 416 static inline void adma_packet_start(struct ata_queued_cmd *qc)
 417 {
 418         struct ata_port *ap = qc->ap;
 419         void __iomem *chan = ADMA_HOST_REGS(ap->host, ap->port_no);
 420
 421         VPRINTK("ENTER, ap %p\n", ap);
 422
 423         /* fire up the ADMA engine */
 424         writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
 425 }
 426
 427 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
 428 {
 429         struct adma_port_priv *pp = qc->ap->private_data;
 430
 431         switch (qc->tf.protocol) {
 432         case ATA_PROT_DMA:
 433                 pp->state = adma_state_pkt;
 434                 adma_packet_start(qc);
 435                 return 0;
 436
 437         case ATA_PROT_ATAPI_DMA:
 438                 BUG();
 439                 break;
 440
 441         default:
 442                 break;
 443         }
 444
 445         pp->state = adma_state_mmio;
 446         return ata_qc_issue_prot(qc);
 447 }
 448
 449 static inline unsigned int adma_intr_pkt(struct ata_host *host)
 450 {
 451         unsigned int handled = 0, port_no;
 452
 453         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 454                 struct ata_port *ap = host->ports[port_no];
 455                 struct adma_port_priv *pp;
 456                 struct ata_queued_cmd *qc;
 457                 void __iomem *chan = ADMA_HOST_REGS(host, port_no);
 458                 u8 status = readb(chan + ADMA_STATUS);
 459
 460                 if (status == 0)
 461                         continue;
 462                 handled = 1;
 463                 adma_enter_reg_mode(ap);
 464                 if (ap->flags & ATA_FLAG_DISABLED)
 465                         continue;
 466                 pp = ap->private_data;
 467                 if (!pp || pp->state != adma_state_pkt)
 468                         continue;
 469                 qc = ata_qc_from_tag(ap, ap->active_tag);
 470                 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 471                         if ((status & (aPERR | aPSD | aUIRQ)))
 472                                 qc->err_mask |= AC_ERR_OTHER;
 473                         else if (pp->pkt[0] != cDONE)
 474                                 qc->err_mask |= AC_ERR_OTHER;
 475
 476                         ata_qc_complete(qc);
 477                 }
 478         }
 479         return handled;
 480 }
 481
 482 static inline unsigned int adma_intr_mmio(struct ata_host *host)
 483 {
 484         unsigned int handled = 0, port_no;
 485
 486         for (port_no = 0; port_no < host->n_ports; ++port_no) {
 487                 struct ata_port *ap;
 488                 ap = host->ports[port_no];
 489                 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
 490                         struct ata_queued_cmd *qc;
 491                         struct adma_port_priv *pp = ap->private_data;
 492                         if (!pp || pp->state != adma_state_mmio)
 493                                 continue;
 494                         qc = ata_qc_from_tag(ap, ap->active_tag);
 495                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
 496
 497                                 /* check main status, clearing INTRQ */
 498                                 u8 status = ata_check_status(ap);
 499                                 if ((status & ATA_BUSY))
 500                                         continue;
 501                                 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
 502                                         ap->id, qc->tf.protocol, status);
 503
 504                                 /* complete taskfile transaction */
 505                                 pp->state = adma_state_idle;
 506                                 qc->err_mask |= ac_err_mask(status);
 507                                 ata_qc_complete(qc);
 508                                 handled = 1;
 509                         }
 510                 }
 511         }
 512         return handled;
 513 }
 514
 515 static irqreturn_t adma_intr(int irq, void *dev_instance)
 516 {
 517         struct ata_host *host = dev_instance;
 518         unsigned int handled = 0;
 519
 520         VPRINTK("ENTER\n");
 521
 522         spin_lock(&host->lock);
 523         handled  = adma_intr_pkt(host) | adma_intr_mmio(host);
 524         spin_unlock(&host->lock);
 525
 526         VPRINTK("EXIT\n");
 527
 528         return IRQ_RETVAL(handled);
 529 }
 530
 531 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
 532 {
 533         port->cmd_addr          =
 534         port->data_addr         = base + 0x000;
 535         port->error_addr        =
 536         port->feature_addr      = base + 0x004;
 537         port->nsect_addr        = base + 0x008;
 538         port->lbal_addr         = base + 0x00c;
 539         port->lbam_addr         = base + 0x010;
 540         port->lbah_addr         = base + 0x014;
 541         port->device_addr       = base + 0x018;
 542         port->status_addr       =
 543         port->command_addr      = base + 0x01c;
 544         port->altstatus_addr    =
 545         port->ctl_addr          = base + 0x038;
 546 }
 547
 548 static int adma_port_start(struct ata_port *ap)
 549 {
 550         struct device *dev = ap->host->dev;
 551         struct adma_port_priv *pp;
 552         int rc;
 553
 554         rc = ata_port_start(ap);
 555         if (rc)
 556                 return rc;
 557         adma_enter_reg_mode(ap);
 558         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
 559         if (!pp)
 560                 return -ENOMEM;
 561         pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
 562                                       GFP_KERNEL);
 563         if (!pp->pkt)
 564                 return -ENOMEM;
 565         /* paranoia? */
 566         if ((pp->pkt_dma & 7) != 0) {
 567                 printk("bad alignment for pp->pkt_dma: %08x\n",
 568                                                 (u32)pp->pkt_dma);
 569                 return -ENOMEM;
 570         }
 571         memset(pp->pkt, 0, ADMA_PKT_BYTES);
 572         ap->private_data = pp;
 573         adma_reinit_engine(ap);
 574         return 0;
 575 }
 576
 577 static void adma_port_stop(struct ata_port *ap)
 578 {
 579         adma_reset_engine(ADMA_HOST_REGS(ap->host, ap->port_no));
 580 }
 581
 582 static void adma_host_stop(struct ata_host *host)
 583 {
 584         unsigned int port_no;
 585
 586         for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
 587                 adma_reset_engine(ADMA_HOST_REGS(host, port_no));
 588 }
 589
 590 static void adma_host_init(unsigned int chip_id,
 591                                 struct ata_probe_ent *probe_ent)
 592 {
 593         unsigned int port_no;
 594         void __iomem *mmio_base = probe_ent->iomap[ADMA_MMIO_BAR];
 595
 596         /* enable/lock aGO operation */
 597         writeb(7, mmio_base + ADMA_MODE_LOCK);
 598
 599         /* reset the ADMA logic */
 600         for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
 601                 adma_reset_engine(ADMA_REGS(mmio_base, port_no));
 602 }
 603
 604 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
 605 {
 606         int rc;
 607
 608         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 609         if (rc) {
 610                 dev_printk(KERN_ERR, &pdev->dev,
 611                         "32-bit DMA enable failed\n");
 612                 return rc;
 613         }
 614         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 615         if (rc) {
 616                 dev_printk(KERN_ERR, &pdev->dev,
 617                         "32-bit consistent DMA enable failed\n");
 618                 return rc;
 619         }
 620         return 0;
 621 }
 622
 623 static int adma_ata_init_one(struct pci_dev *pdev,
 624                              const struct pci_device_id *ent)
 625 {
 626         static int printed_version;
 627         struct ata_probe_ent *probe_ent = NULL;
 628         void __iomem *mmio_base;
 629         unsigned int board_idx = (unsigned int) ent->driver_data;
 630         int rc, port_no;
 631
 632         if (!printed_version++)
 633                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 634
 635         rc = pcim_enable_device(pdev);
 636         if (rc)
 637                 return rc;
 638
 639         if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
 640                 return -ENODEV;
 641
 642         rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
 643         if (rc)
 644                 return rc;
 645         mmio_base = pcim_iomap_table(pdev)[ADMA_MMIO_BAR];
 646
 647         rc = adma_set_dma_masks(pdev, mmio_base);
 648         if (rc)
 649                 return rc;
 650
 651         probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
 652         if (probe_ent == NULL)
 653                 return -ENOMEM;
 654
 655         probe_ent->dev = pci_dev_to_dev(pdev);
 656         INIT_LIST_HEAD(&probe_ent->node);
 657
 658         probe_ent->sht          = adma_port_info[board_idx].sht;
 659         probe_ent->port_flags   = adma_port_info[board_idx].flags;
 660         probe_ent->pio_mask     = adma_port_info[board_idx].pio_mask;
 661         probe_ent->mwdma_mask   = adma_port_info[board_idx].mwdma_mask;
 662         probe_ent->udma_mask    = adma_port_info[board_idx].udma_mask;
 663         probe_ent->port_ops     = adma_port_info[board_idx].port_ops;
 664
 665         probe_ent->irq          = pdev->irq;
 666         probe_ent->irq_flags    = IRQF_SHARED;
 667         probe_ent->n_ports      = ADMA_PORTS;
 668         probe_ent->iomap        = pcim_iomap_table(pdev);
 669
 670         for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
 671                 adma_ata_setup_port(&probe_ent->port[port_no],
 672                                     ADMA_ATA_REGS(mmio_base, port_no));
 673         }
 674
 675         pci_set_master(pdev);
 676
 677         /* initialize adapter */
 678         adma_host_init(board_idx, probe_ent);
 679
 680         if (!ata_device_add(probe_ent))
 681                 return -ENODEV;
 682
 683         devm_kfree(&pdev->dev, probe_ent);
 684         return 0;
 685 }
 686
 687 static int __init adma_ata_init(void)
 688 {
 689         return pci_register_driver(&adma_ata_pci_driver);
 690 }
 691
 692 static void __exit adma_ata_exit(void)
 693 {
 694         pci_unregister_driver(&adma_ata_pci_driver);
 695 }
 696
 697 MODULE_AUTHOR("Mark Lord");
 698 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
 699 MODULE_LICENSE("GPL");
 700 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
 701 MODULE_VERSION(DRV_VERSION);
 702
 703 module_init(adma_ata_init);
 704 module_exit(adma_ata_exit);