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sata_inic162x: kill now unused SFF related stuff
[deliverable/linux.git] / drivers / ata / sata_inic162x.c
1 /*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *
9 * This controller is eccentric and easily locks up if something isn't
10 * right. Documentation is available at initio's website but it only
11 * documents registers (not programming model).
12 *
13 * - ATA disks work.
14 * - Hotplug works.
15 * - ATAPI read works but burning doesn't. This thing is really
16 * peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
17 * ATAPI DMA WRITE should be programmed. If you've got a clue, be
18 * my guest.
19 * - Both STR and STD work.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <scsi/scsi_host.h>
26 #include <linux/libata.h>
27 #include <linux/blkdev.h>
28 #include <scsi/scsi_device.h>
29
30 #define DRV_NAME "sata_inic162x"
31 #define DRV_VERSION "0.3"
32
33 enum {
34 MMIO_BAR = 5,
35
36 NR_PORTS = 2,
37
38 IDMA_CPB_TBL_SIZE = 4 * 32,
39
40 INIC_DMA_BOUNDARY = 0xffffff,
41
42 HOST_ACTRL = 0x08,
43 HOST_CTL = 0x7c,
44 HOST_STAT = 0x7e,
45 HOST_IRQ_STAT = 0xbc,
46 HOST_IRQ_MASK = 0xbe,
47
48 PORT_SIZE = 0x40,
49
50 /* registers for ATA TF operation */
51 PORT_TF_DATA = 0x00,
52 PORT_TF_FEATURE = 0x01,
53 PORT_TF_NSECT = 0x02,
54 PORT_TF_LBAL = 0x03,
55 PORT_TF_LBAM = 0x04,
56 PORT_TF_LBAH = 0x05,
57 PORT_TF_DEVICE = 0x06,
58 PORT_TF_COMMAND = 0x07,
59 PORT_TF_ALT_STAT = 0x08,
60 PORT_IRQ_STAT = 0x09,
61 PORT_IRQ_MASK = 0x0a,
62 PORT_PRD_CTL = 0x0b,
63 PORT_PRD_ADDR = 0x0c,
64 PORT_PRD_XFERLEN = 0x10,
65 PORT_CPB_CPBLAR = 0x18,
66 PORT_CPB_PTQFIFO = 0x1c,
67
68 /* IDMA register */
69 PORT_IDMA_CTL = 0x14,
70 PORT_IDMA_STAT = 0x16,
71
72 PORT_RPQ_FIFO = 0x1e,
73 PORT_RPQ_CNT = 0x1f,
74
75 PORT_SCR = 0x20,
76
77 /* HOST_CTL bits */
78 HCTL_IRQOFF = (1 << 8), /* global IRQ off */
79 HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
80 HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
81 HCTL_PWRDWN = (1 << 12), /* power down PHYs */
82 HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
83 HCTL_RPGSEL = (1 << 15), /* register page select */
84
85 HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
86 HCTL_RPGSEL,
87
88 /* HOST_IRQ_(STAT|MASK) bits */
89 HIRQ_PORT0 = (1 << 0),
90 HIRQ_PORT1 = (1 << 1),
91 HIRQ_SOFT = (1 << 14),
92 HIRQ_GLOBAL = (1 << 15), /* STAT only */
93
94 /* PORT_IRQ_(STAT|MASK) bits */
95 PIRQ_OFFLINE = (1 << 0), /* device unplugged */
96 PIRQ_ONLINE = (1 << 1), /* device plugged */
97 PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
98 PIRQ_FATAL = (1 << 3), /* fatal error */
99 PIRQ_ATA = (1 << 4), /* ATA interrupt */
100 PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
101 PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
102
103 PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
104 PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
105 PIRQ_MASK_FREEZE = 0xff,
106
107 /* PORT_PRD_CTL bits */
108 PRD_CTL_START = (1 << 0),
109 PRD_CTL_WR = (1 << 3),
110 PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
111
112 /* PORT_IDMA_CTL bits */
113 IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
114 IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
115 IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
116 IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
117
118 /* PORT_IDMA_STAT bits */
119 IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
120 IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
121 IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
122 IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
123 IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
124 IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
125 IDMA_STAT_DONE = (1 << 7), /* ADMA done */
126
127 IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
128
129 /* CPB Control Flags*/
130 CPB_CTL_VALID = (1 << 0), /* CPB valid */
131 CPB_CTL_QUEUED = (1 << 1), /* queued command */
132 CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
133 CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
134 CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
135
136 /* CPB Response Flags */
137 CPB_RESP_DONE = (1 << 0), /* ATA command complete */
138 CPB_RESP_REL = (1 << 1), /* ATA release */
139 CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
140 CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
141 CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
142 CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
143 CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
144 CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
145
146 /* PRD Control Flags */
147 PRD_DRAIN = (1 << 1), /* ignore data excess */
148 PRD_CDB = (1 << 2), /* atapi packet command pointer */
149 PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
150 PRD_DMA = (1 << 4), /* data transfer method */
151 PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
152 PRD_IOM = (1 << 6), /* io/memory transfer */
153 PRD_END = (1 << 7), /* APRD chain end */
154 };
155
156 /* Comman Parameter Block */
157 struct inic_cpb {
158 u8 resp_flags; /* Response Flags */
159 u8 error; /* ATA Error */
160 u8 status; /* ATA Status */
161 u8 ctl_flags; /* Control Flags */
162 __le32 len; /* Total Transfer Length */
163 __le32 prd; /* First PRD pointer */
164 u8 rsvd[4];
165 /* 16 bytes */
166 u8 feature; /* ATA Feature */
167 u8 hob_feature; /* ATA Ex. Feature */
168 u8 device; /* ATA Device/Head */
169 u8 mirctl; /* Mirror Control */
170 u8 nsect; /* ATA Sector Count */
171 u8 hob_nsect; /* ATA Ex. Sector Count */
172 u8 lbal; /* ATA Sector Number */
173 u8 hob_lbal; /* ATA Ex. Sector Number */
174 u8 lbam; /* ATA Cylinder Low */
175 u8 hob_lbam; /* ATA Ex. Cylinder Low */
176 u8 lbah; /* ATA Cylinder High */
177 u8 hob_lbah; /* ATA Ex. Cylinder High */
178 u8 command; /* ATA Command */
179 u8 ctl; /* ATA Control */
180 u8 slave_error; /* Slave ATA Error */
181 u8 slave_status; /* Slave ATA Status */
182 /* 32 bytes */
183 } __packed;
184
185 /* Physical Region Descriptor */
186 struct inic_prd {
187 __le32 mad; /* Physical Memory Address */
188 __le16 len; /* Transfer Length */
189 u8 rsvd;
190 u8 flags; /* Control Flags */
191 } __packed;
192
193 struct inic_pkt {
194 struct inic_cpb cpb;
195 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
196 u8 cdb[ATAPI_CDB_LEN];
197 } __packed;
198
199 struct inic_host_priv {
200 u16 cached_hctl;
201 };
202
203 struct inic_port_priv {
204 struct inic_pkt *pkt;
205 dma_addr_t pkt_dma;
206 u32 *cpb_tbl;
207 dma_addr_t cpb_tbl_dma;
208 };
209
210 static struct scsi_host_template inic_sht = {
211 ATA_BASE_SHT(DRV_NAME),
212 .sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
213 .dma_boundary = INIC_DMA_BOUNDARY,
214 };
215
216 static const int scr_map[] = {
217 [SCR_STATUS] = 0,
218 [SCR_ERROR] = 1,
219 [SCR_CONTROL] = 2,
220 };
221
222 static void __iomem *inic_port_base(struct ata_port *ap)
223 {
224 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
225 }
226
227 static void inic_reset_port(void __iomem *port_base)
228 {
229 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
230
231 /* stop IDMA engine */
232 readw(idma_ctl); /* flush */
233 msleep(1);
234
235 /* mask IRQ and assert reset */
236 writew(IDMA_CTL_RST_IDMA, idma_ctl);
237 readw(idma_ctl); /* flush */
238 msleep(1);
239
240 /* release reset */
241 writew(0, idma_ctl);
242
243 /* clear irq */
244 writeb(0xff, port_base + PORT_IRQ_STAT);
245 }
246
247 static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
248 {
249 void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
250 void __iomem *addr;
251
252 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
253 return -EINVAL;
254
255 addr = scr_addr + scr_map[sc_reg] * 4;
256 *val = readl(scr_addr + scr_map[sc_reg] * 4);
257
258 /* this controller has stuck DIAG.N, ignore it */
259 if (sc_reg == SCR_ERROR)
260 *val &= ~SERR_PHYRDY_CHG;
261 return 0;
262 }
263
264 static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
265 {
266 void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
267
268 if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
269 return -EINVAL;
270
271 writel(val, scr_addr + scr_map[sc_reg] * 4);
272 return 0;
273 }
274
275 static void inic_stop_idma(struct ata_port *ap)
276 {
277 void __iomem *port_base = inic_port_base(ap);
278
279 readb(port_base + PORT_RPQ_FIFO);
280 readb(port_base + PORT_RPQ_CNT);
281 writew(0, port_base + PORT_IDMA_CTL);
282 }
283
284 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
285 {
286 struct ata_eh_info *ehi = &ap->link.eh_info;
287 struct inic_port_priv *pp = ap->private_data;
288 struct inic_cpb *cpb = &pp->pkt->cpb;
289 bool freeze = false;
290
291 ata_ehi_clear_desc(ehi);
292 ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
293 irq_stat, idma_stat);
294
295 inic_stop_idma(ap);
296
297 if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
298 ata_ehi_push_desc(ehi, "hotplug");
299 ata_ehi_hotplugged(ehi);
300 freeze = true;
301 }
302
303 if (idma_stat & IDMA_STAT_PERR) {
304 ata_ehi_push_desc(ehi, "PCI error");
305 freeze = true;
306 }
307
308 if (idma_stat & IDMA_STAT_CPBERR) {
309 ata_ehi_push_desc(ehi, "CPB error");
310
311 if (cpb->resp_flags & CPB_RESP_IGNORED) {
312 __ata_ehi_push_desc(ehi, " ignored");
313 ehi->err_mask |= AC_ERR_INVALID;
314 freeze = true;
315 }
316
317 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
318 ehi->err_mask |= AC_ERR_DEV;
319
320 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
321 __ata_ehi_push_desc(ehi, " spurious-intr");
322 ehi->err_mask |= AC_ERR_HSM;
323 freeze = true;
324 }
325
326 if (cpb->resp_flags &
327 (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
328 __ata_ehi_push_desc(ehi, " data-over/underflow");
329 ehi->err_mask |= AC_ERR_HSM;
330 freeze = true;
331 }
332 }
333
334 if (freeze)
335 ata_port_freeze(ap);
336 else
337 ata_port_abort(ap);
338 }
339
340 static void inic_host_intr(struct ata_port *ap)
341 {
342 void __iomem *port_base = inic_port_base(ap);
343 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
344 u8 irq_stat;
345 u16 idma_stat;
346
347 /* read and clear IRQ status */
348 irq_stat = readb(port_base + PORT_IRQ_STAT);
349 writeb(irq_stat, port_base + PORT_IRQ_STAT);
350 idma_stat = readw(port_base + PORT_IDMA_STAT);
351
352 if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
353 inic_host_err_intr(ap, irq_stat, idma_stat);
354
355 if (unlikely(!qc))
356 goto spurious;
357
358 if (likely(idma_stat & IDMA_STAT_DONE)) {
359 inic_stop_idma(ap);
360
361 /* Depending on circumstances, device error
362 * isn't reported by IDMA, check it explicitly.
363 */
364 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
365 (ATA_DF | ATA_ERR)))
366 qc->err_mask |= AC_ERR_DEV;
367
368 ata_qc_complete(qc);
369 return;
370 }
371
372 spurious:
373 ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: "
374 "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
375 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
376 }
377
378 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
379 {
380 struct ata_host *host = dev_instance;
381 void __iomem *mmio_base = host->iomap[MMIO_BAR];
382 u16 host_irq_stat;
383 int i, handled = 0;;
384
385 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
386
387 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
388 goto out;
389
390 spin_lock(&host->lock);
391
392 for (i = 0; i < NR_PORTS; i++) {
393 struct ata_port *ap = host->ports[i];
394
395 if (!(host_irq_stat & (HIRQ_PORT0 << i)))
396 continue;
397
398 if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
399 inic_host_intr(ap);
400 handled++;
401 } else {
402 if (ata_ratelimit())
403 dev_printk(KERN_ERR, host->dev, "interrupt "
404 "from disabled port %d (0x%x)\n",
405 i, host_irq_stat);
406 }
407 }
408
409 spin_unlock(&host->lock);
410
411 out:
412 return IRQ_RETVAL(handled);
413 }
414
415 static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
416 {
417 /* For some reason ATAPI_PROT_DMA doesn't work for some
418 * commands including writes and other misc ops. Use PIO
419 * protocol instead, which BTW is driven by the DMA engine
420 * anyway, so it shouldn't make much difference for native
421 * SATA devices.
422 */
423 if (atapi_cmd_type(qc->cdb[0]) == READ)
424 return 0;
425 return 1;
426 }
427
428 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
429 {
430 struct scatterlist *sg;
431 unsigned int si;
432 u8 flags = 0;
433
434 if (qc->tf.flags & ATA_TFLAG_WRITE)
435 flags |= PRD_WRITE;
436
437 if (ata_is_dma(qc->tf.protocol))
438 flags |= PRD_DMA;
439
440 for_each_sg(qc->sg, sg, qc->n_elem, si) {
441 prd->mad = cpu_to_le32(sg_dma_address(sg));
442 prd->len = cpu_to_le16(sg_dma_len(sg));
443 prd->flags = flags;
444 prd++;
445 }
446
447 WARN_ON(!si);
448 prd[-1].flags |= PRD_END;
449 }
450
451 static void inic_qc_prep(struct ata_queued_cmd *qc)
452 {
453 struct inic_port_priv *pp = qc->ap->private_data;
454 struct inic_pkt *pkt = pp->pkt;
455 struct inic_cpb *cpb = &pkt->cpb;
456 struct inic_prd *prd = pkt->prd;
457 bool is_atapi = ata_is_atapi(qc->tf.protocol);
458 bool is_data = ata_is_data(qc->tf.protocol);
459 unsigned int cdb_len = 0;
460
461 VPRINTK("ENTER\n");
462
463 if (is_atapi)
464 cdb_len = qc->dev->cdb_len;
465
466 /* prepare packet, based on initio driver */
467 memset(pkt, 0, sizeof(struct inic_pkt));
468
469 cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
470 if (is_atapi || is_data)
471 cpb->ctl_flags |= CPB_CTL_DATA;
472
473 cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
474 cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
475
476 cpb->device = qc->tf.device;
477 cpb->feature = qc->tf.feature;
478 cpb->nsect = qc->tf.nsect;
479 cpb->lbal = qc->tf.lbal;
480 cpb->lbam = qc->tf.lbam;
481 cpb->lbah = qc->tf.lbah;
482
483 if (qc->tf.flags & ATA_TFLAG_LBA48) {
484 cpb->hob_feature = qc->tf.hob_feature;
485 cpb->hob_nsect = qc->tf.hob_nsect;
486 cpb->hob_lbal = qc->tf.hob_lbal;
487 cpb->hob_lbam = qc->tf.hob_lbam;
488 cpb->hob_lbah = qc->tf.hob_lbah;
489 }
490
491 cpb->command = qc->tf.command;
492 /* don't load ctl - dunno why. it's like that in the initio driver */
493
494 /* setup PRD for CDB */
495 if (is_atapi) {
496 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
497 prd->mad = cpu_to_le32(pp->pkt_dma +
498 offsetof(struct inic_pkt, cdb));
499 prd->len = cpu_to_le16(cdb_len);
500 prd->flags = PRD_CDB | PRD_WRITE;
501 if (!is_data)
502 prd->flags |= PRD_END;
503 prd++;
504 }
505
506 /* setup sg table */
507 if (is_data)
508 inic_fill_sg(prd, qc);
509
510 pp->cpb_tbl[0] = pp->pkt_dma;
511 }
512
513 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
514 {
515 struct ata_port *ap = qc->ap;
516 void __iomem *port_base = inic_port_base(ap);
517
518 /* fire up the ADMA engine */
519 writew(HCTL_FTHD0, port_base + HOST_CTL);
520 writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
521 writeb(0, port_base + PORT_CPB_PTQFIFO);
522
523 return 0;
524 }
525
526 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
527 {
528 void __iomem *port_base = inic_port_base(ap);
529
530 tf->feature = readb(port_base + PORT_TF_FEATURE);
531 tf->nsect = readb(port_base + PORT_TF_NSECT);
532 tf->lbal = readb(port_base + PORT_TF_LBAL);
533 tf->lbam = readb(port_base + PORT_TF_LBAM);
534 tf->lbah = readb(port_base + PORT_TF_LBAH);
535 tf->device = readb(port_base + PORT_TF_DEVICE);
536 tf->command = readb(port_base + PORT_TF_COMMAND);
537 }
538
539 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
540 {
541 struct ata_taskfile *rtf = &qc->result_tf;
542 struct ata_taskfile tf;
543
544 /* FIXME: Except for status and error, result TF access
545 * doesn't work. I tried reading from BAR0/2, CPB and BAR5.
546 * None works regardless of which command interface is used.
547 * For now return true iff status indicates device error.
548 * This means that we're reporting bogus sector for RW
549 * failures. Eeekk....
550 */
551 inic_tf_read(qc->ap, &tf);
552
553 if (!(tf.command & ATA_ERR))
554 return false;
555
556 rtf->command = tf.command;
557 rtf->feature = tf.feature;
558 return true;
559 }
560
561 static void inic_freeze(struct ata_port *ap)
562 {
563 void __iomem *port_base = inic_port_base(ap);
564
565 writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
566 writeb(0xff, port_base + PORT_IRQ_STAT);
567 }
568
569 static void inic_thaw(struct ata_port *ap)
570 {
571 void __iomem *port_base = inic_port_base(ap);
572
573 writeb(0xff, port_base + PORT_IRQ_STAT);
574 writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
575 }
576
577 static int inic_check_ready(struct ata_link *link)
578 {
579 void __iomem *port_base = inic_port_base(link->ap);
580
581 return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
582 }
583
584 /*
585 * SRST and SControl hardreset don't give valid signature on this
586 * controller. Only controller specific hardreset mechanism works.
587 */
588 static int inic_hardreset(struct ata_link *link, unsigned int *class,
589 unsigned long deadline)
590 {
591 struct ata_port *ap = link->ap;
592 void __iomem *port_base = inic_port_base(ap);
593 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
594 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
595 int rc;
596
597 /* hammer it into sane state */
598 inic_reset_port(port_base);
599
600 writew(IDMA_CTL_RST_ATA, idma_ctl);
601 readw(idma_ctl); /* flush */
602 msleep(1);
603 writew(0, idma_ctl);
604
605 rc = sata_link_resume(link, timing, deadline);
606 if (rc) {
607 ata_link_printk(link, KERN_WARNING, "failed to resume "
608 "link after reset (errno=%d)\n", rc);
609 return rc;
610 }
611
612 *class = ATA_DEV_NONE;
613 if (ata_link_online(link)) {
614 struct ata_taskfile tf;
615
616 /* wait for link to become ready */
617 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
618 /* link occupied, -ENODEV too is an error */
619 if (rc) {
620 ata_link_printk(link, KERN_WARNING, "device not ready "
621 "after hardreset (errno=%d)\n", rc);
622 return rc;
623 }
624
625 inic_tf_read(ap, &tf);
626 *class = ata_dev_classify(&tf);
627 }
628
629 return 0;
630 }
631
632 static void inic_error_handler(struct ata_port *ap)
633 {
634 void __iomem *port_base = inic_port_base(ap);
635
636 inic_reset_port(port_base);
637 ata_std_error_handler(ap);
638 }
639
640 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
641 {
642 /* make DMA engine forget about the failed command */
643 if (qc->flags & ATA_QCFLAG_FAILED)
644 inic_reset_port(inic_port_base(qc->ap));
645 }
646
647 static void init_port(struct ata_port *ap)
648 {
649 void __iomem *port_base = inic_port_base(ap);
650 struct inic_port_priv *pp = ap->private_data;
651
652 /* clear packet and CPB table */
653 memset(pp->pkt, 0, sizeof(struct inic_pkt));
654 memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
655
656 /* setup PRD and CPB lookup table addresses */
657 writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
658 writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
659 }
660
661 static int inic_port_resume(struct ata_port *ap)
662 {
663 init_port(ap);
664 return 0;
665 }
666
667 static int inic_port_start(struct ata_port *ap)
668 {
669 struct device *dev = ap->host->dev;
670 struct inic_port_priv *pp;
671 int rc;
672
673 /* alloc and initialize private data */
674 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
675 if (!pp)
676 return -ENOMEM;
677 ap->private_data = pp;
678
679 /* Alloc resources */
680 rc = ata_port_start(ap);
681 if (rc)
682 return rc;
683
684 pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
685 &pp->pkt_dma, GFP_KERNEL);
686 if (!pp->pkt)
687 return -ENOMEM;
688
689 pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
690 &pp->cpb_tbl_dma, GFP_KERNEL);
691 if (!pp->cpb_tbl)
692 return -ENOMEM;
693
694 init_port(ap);
695
696 return 0;
697 }
698
699 static struct ata_port_operations inic_port_ops = {
700 .inherits = &sata_port_ops,
701
702 .check_atapi_dma = inic_check_atapi_dma,
703 .qc_prep = inic_qc_prep,
704 .qc_issue = inic_qc_issue,
705 .qc_fill_rtf = inic_qc_fill_rtf,
706
707 .freeze = inic_freeze,
708 .thaw = inic_thaw,
709 .hardreset = inic_hardreset,
710 .error_handler = inic_error_handler,
711 .post_internal_cmd = inic_post_internal_cmd,
712
713 .scr_read = inic_scr_read,
714 .scr_write = inic_scr_write,
715
716 .port_resume = inic_port_resume,
717 .port_start = inic_port_start,
718 };
719
720 static struct ata_port_info inic_port_info = {
721 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
722 .pio_mask = 0x1f, /* pio0-4 */
723 .mwdma_mask = 0x07, /* mwdma0-2 */
724 .udma_mask = ATA_UDMA6,
725 .port_ops = &inic_port_ops
726 };
727
728 static int init_controller(void __iomem *mmio_base, u16 hctl)
729 {
730 int i;
731 u16 val;
732
733 hctl &= ~HCTL_KNOWN_BITS;
734
735 /* Soft reset whole controller. Spec says reset duration is 3
736 * PCI clocks, be generous and give it 10ms.
737 */
738 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
739 readw(mmio_base + HOST_CTL); /* flush */
740
741 for (i = 0; i < 10; i++) {
742 msleep(1);
743 val = readw(mmio_base + HOST_CTL);
744 if (!(val & HCTL_SOFTRST))
745 break;
746 }
747
748 if (val & HCTL_SOFTRST)
749 return -EIO;
750
751 /* mask all interrupts and reset ports */
752 for (i = 0; i < NR_PORTS; i++) {
753 void __iomem *port_base = mmio_base + i * PORT_SIZE;
754
755 writeb(0xff, port_base + PORT_IRQ_MASK);
756 inic_reset_port(port_base);
757 }
758
759 /* port IRQ is masked now, unmask global IRQ */
760 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
761 val = readw(mmio_base + HOST_IRQ_MASK);
762 val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
763 writew(val, mmio_base + HOST_IRQ_MASK);
764
765 return 0;
766 }
767
768 #ifdef CONFIG_PM
769 static int inic_pci_device_resume(struct pci_dev *pdev)
770 {
771 struct ata_host *host = dev_get_drvdata(&pdev->dev);
772 struct inic_host_priv *hpriv = host->private_data;
773 void __iomem *mmio_base = host->iomap[MMIO_BAR];
774 int rc;
775
776 rc = ata_pci_device_do_resume(pdev);
777 if (rc)
778 return rc;
779
780 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
781 rc = init_controller(mmio_base, hpriv->cached_hctl);
782 if (rc)
783 return rc;
784 }
785
786 ata_host_resume(host);
787
788 return 0;
789 }
790 #endif
791
792 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
793 {
794 static int printed_version;
795 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
796 struct ata_host *host;
797 struct inic_host_priv *hpriv;
798 void __iomem * const *iomap;
799 int i, rc;
800
801 if (!printed_version++)
802 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
803
804 /* alloc host */
805 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
806 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
807 if (!host || !hpriv)
808 return -ENOMEM;
809
810 host->private_data = hpriv;
811
812 /* acquire resources and fill host */
813 rc = pcim_enable_device(pdev);
814 if (rc)
815 return rc;
816
817 rc = pcim_iomap_regions(pdev, 1 << MMIO_BAR, DRV_NAME);
818 if (rc)
819 return rc;
820 host->iomap = iomap = pcim_iomap_table(pdev);
821 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
822
823 for (i = 0; i < NR_PORTS; i++) {
824 struct ata_port *ap = host->ports[i];
825
826 ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
827 ata_port_pbar_desc(ap, MMIO_BAR, i * PORT_SIZE, "port");
828 }
829
830 /* Set dma_mask. This devices doesn't support 64bit addressing. */
831 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
832 if (rc) {
833 dev_printk(KERN_ERR, &pdev->dev,
834 "32-bit DMA enable failed\n");
835 return rc;
836 }
837
838 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
839 if (rc) {
840 dev_printk(KERN_ERR, &pdev->dev,
841 "32-bit consistent DMA enable failed\n");
842 return rc;
843 }
844
845 /*
846 * This controller is braindamaged. dma_boundary is 0xffff
847 * like others but it will lock up the whole machine HARD if
848 * 65536 byte PRD entry is fed. Reduce maximum segment size.
849 */
850 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
851 if (rc) {
852 dev_printk(KERN_ERR, &pdev->dev,
853 "failed to set the maximum segment size.\n");
854 return rc;
855 }
856
857 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
858 if (rc) {
859 dev_printk(KERN_ERR, &pdev->dev,
860 "failed to initialize controller\n");
861 return rc;
862 }
863
864 pci_set_master(pdev);
865 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
866 &inic_sht);
867 }
868
869 static const struct pci_device_id inic_pci_tbl[] = {
870 { PCI_VDEVICE(INIT, 0x1622), },
871 { },
872 };
873
874 static struct pci_driver inic_pci_driver = {
875 .name = DRV_NAME,
876 .id_table = inic_pci_tbl,
877 #ifdef CONFIG_PM
878 .suspend = ata_pci_device_suspend,
879 .resume = inic_pci_device_resume,
880 #endif
881 .probe = inic_init_one,
882 .remove = ata_pci_remove_one,
883 };
884
885 static int __init inic_init(void)
886 {
887 return pci_register_driver(&inic_pci_driver);
888 }
889
890 static void __exit inic_exit(void)
891 {
892 pci_unregister_driver(&inic_pci_driver);
893 }
894
895 MODULE_AUTHOR("Tejun Heo");
896 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
897 MODULE_LICENSE("GPL v2");
898 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
899 MODULE_VERSION(DRV_VERSION);
900
901 module_init(inic_init);
902 module_exit(inic_exit);
Linux kernel - Deliverables
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