projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[deliverable/linux.git] / drivers / ata / sata_mv.c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37
38 #define DRV_NAME "sata_mv"
39 #define DRV_VERSION "0.7"
40
41 enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
44 MV_IO_BAR = 2, /* offset 0x18: IO space */
45 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46
47 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
49
50 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
53 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
54 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
55 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
56 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
57
58 MV_SATAHC0_REG_BASE = 0x20000,
59 MV_FLASH_CTL = 0x1046c,
60 MV_GPIO_PORT_CTL = 0x104f0,
61 MV_RESET_CFG = 0x180d8,
62
63 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
65 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
66 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
67
68 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
69
70 MV_MAX_Q_DEPTH = 32,
71 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
72
73 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
74 * CRPB needs alignment on a 256B boundary. Size == 256B
75 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
76 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
77 */
78 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
79 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
80 MV_MAX_SG_CT = 176,
81 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
82 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
83
84 MV_PORTS_PER_HC = 4,
85 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
86 MV_PORT_HC_SHIFT = 2,
87 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
88 MV_PORT_MASK = 3,
89
90 /* Host Flags */
91 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
92 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
93 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
94 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
95 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
96 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
97
98 CRQB_FLAG_READ = (1 << 0),
99 CRQB_TAG_SHIFT = 1,
100 CRQB_CMD_ADDR_SHIFT = 8,
101 CRQB_CMD_CS = (0x2 << 11),
102 CRQB_CMD_LAST = (1 << 15),
103
104 CRPB_FLAG_STATUS_SHIFT = 8,
105
106 EPRD_FLAG_END_OF_TBL = (1 << 31),
107
108 /* PCI interface registers */
109
110 PCI_COMMAND_OFS = 0xc00,
111
112 PCI_MAIN_CMD_STS_OFS = 0xd30,
113 STOP_PCI_MASTER = (1 << 2),
114 PCI_MASTER_EMPTY = (1 << 3),
115 GLOB_SFT_RST = (1 << 4),
116
117 MV_PCI_MODE = 0xd00,
118 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
119 MV_PCI_DISC_TIMER = 0xd04,
120 MV_PCI_MSI_TRIGGER = 0xc38,
121 MV_PCI_SERR_MASK = 0xc28,
122 MV_PCI_XBAR_TMOUT = 0x1d04,
123 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
124 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
125 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
126 MV_PCI_ERR_COMMAND = 0x1d50,
127
128 PCI_IRQ_CAUSE_OFS = 0x1d58,
129 PCI_IRQ_MASK_OFS = 0x1d5c,
130 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
131
132 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
133 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
134 PORT0_ERR = (1 << 0), /* shift by port # */
135 PORT0_DONE = (1 << 1), /* shift by port # */
136 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
137 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
138 PCI_ERR = (1 << 18),
139 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
140 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
141 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
142 GPIO_INT = (1 << 22),
143 SELF_INT = (1 << 23),
144 TWSI_INT = (1 << 24),
145 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
146 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
147 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
148 HC_MAIN_RSVD),
149
150 /* SATAHC registers */
151 HC_CFG_OFS = 0,
152
153 HC_IRQ_CAUSE_OFS = 0x14,
154 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
155 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
156 DEV_IRQ = (1 << 8), /* shift by port # */
157
158 /* Shadow block registers */
159 SHD_BLK_OFS = 0x100,
160 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
161
162 /* SATA registers */
163 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
164 SATA_ACTIVE_OFS = 0x350,
165 PHY_MODE3 = 0x310,
166 PHY_MODE4 = 0x314,
167 PHY_MODE2 = 0x330,
168 MV5_PHY_MODE = 0x74,
169 MV5_LT_MODE = 0x30,
170 MV5_PHY_CTL = 0x0C,
171 SATA_INTERFACE_CTL = 0x050,
172
173 MV_M2_PREAMP_MASK = 0x7e0,
174
175 /* Port registers */
176 EDMA_CFG_OFS = 0,
177 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
178 EDMA_CFG_NCQ = (1 << 5),
179 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
180 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
181 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
182
183 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
184 EDMA_ERR_IRQ_MASK_OFS = 0xc,
185 EDMA_ERR_D_PAR = (1 << 0),
186 EDMA_ERR_PRD_PAR = (1 << 1),
187 EDMA_ERR_DEV = (1 << 2),
188 EDMA_ERR_DEV_DCON = (1 << 3),
189 EDMA_ERR_DEV_CON = (1 << 4),
190 EDMA_ERR_SERR = (1 << 5),
191 EDMA_ERR_SELF_DIS = (1 << 7),
192 EDMA_ERR_BIST_ASYNC = (1 << 8),
193 EDMA_ERR_CRBQ_PAR = (1 << 9),
194 EDMA_ERR_CRPB_PAR = (1 << 10),
195 EDMA_ERR_INTRL_PAR = (1 << 11),
196 EDMA_ERR_IORDY = (1 << 12),
197 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
198 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
199 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
200 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
201 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
202 EDMA_ERR_TRANS_PROTO = (1 << 31),
203 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
204 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
205 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
206 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
207 EDMA_ERR_LNK_DATA_RX |
208 EDMA_ERR_LNK_DATA_TX |
209 EDMA_ERR_TRANS_PROTO),
210
211 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
212 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
213
214 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
215 EDMA_REQ_Q_PTR_SHIFT = 5,
216
217 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
218 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
219 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
220 EDMA_RSP_Q_PTR_SHIFT = 3,
221
222 EDMA_CMD_OFS = 0x28,
223 EDMA_EN = (1 << 0),
224 EDMA_DS = (1 << 1),
225 ATA_RST = (1 << 2),
226
227 EDMA_IORDY_TMOUT = 0x34,
228 EDMA_ARB_CFG = 0x38,
229
230 /* Host private flags (hp_flags) */
231 MV_HP_FLAG_MSI = (1 << 0),
232 MV_HP_ERRATA_50XXB0 = (1 << 1),
233 MV_HP_ERRATA_50XXB2 = (1 << 2),
234 MV_HP_ERRATA_60X1B2 = (1 << 3),
235 MV_HP_ERRATA_60X1C0 = (1 << 4),
236 MV_HP_ERRATA_XX42A0 = (1 << 5),
237 MV_HP_50XX = (1 << 6),
238 MV_HP_GEN_IIE = (1 << 7),
239
240 /* Port private flags (pp_flags) */
241 MV_PP_FLAG_EDMA_EN = (1 << 0),
242 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
243 };
244
245 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
246 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
247 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
248 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
249 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
250
251 enum {
252 /* Our DMA boundary is determined by an ePRD being unable to handle
253 * anything larger than 64KB
254 */
255 MV_DMA_BOUNDARY = 0xffffU,
256
257 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
258
259 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
260 };
261
262 enum chip_type {
263 chip_504x,
264 chip_508x,
265 chip_5080,
266 chip_604x,
267 chip_608x,
268 chip_6042,
269 chip_7042,
270 };
271
272 /* Command ReQuest Block: 32B */
273 struct mv_crqb {
274 __le32 sg_addr;
275 __le32 sg_addr_hi;
276 __le16 ctrl_flags;
277 __le16 ata_cmd[11];
278 };
279
280 struct mv_crqb_iie {
281 __le32 addr;
282 __le32 addr_hi;
283 __le32 flags;
284 __le32 len;
285 __le32 ata_cmd[4];
286 };
287
288 /* Command ResPonse Block: 8B */
289 struct mv_crpb {
290 __le16 id;
291 __le16 flags;
292 __le32 tmstmp;
293 };
294
295 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
296 struct mv_sg {
297 __le32 addr;
298 __le32 flags_size;
299 __le32 addr_hi;
300 __le32 reserved;
301 };
302
303 struct mv_port_priv {
304 struct mv_crqb *crqb;
305 dma_addr_t crqb_dma;
306 struct mv_crpb *crpb;
307 dma_addr_t crpb_dma;
308 struct mv_sg *sg_tbl;
309 dma_addr_t sg_tbl_dma;
310 u32 pp_flags;
311 };
312
313 struct mv_port_signal {
314 u32 amps;
315 u32 pre;
316 };
317
318 struct mv_host_priv;
319 struct mv_hw_ops {
320 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
321 unsigned int port);
322 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
323 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
324 void __iomem *mmio);
325 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
326 unsigned int n_hc);
327 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
328 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
329 };
330
331 struct mv_host_priv {
332 u32 hp_flags;
333 struct mv_port_signal signal[8];
334 const struct mv_hw_ops *ops;
335 };
336
337 static void mv_irq_clear(struct ata_port *ap);
338 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
339 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
340 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
341 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
342 static void mv_phy_reset(struct ata_port *ap);
343 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
344 static int mv_port_start(struct ata_port *ap);
345 static void mv_port_stop(struct ata_port *ap);
346 static void mv_qc_prep(struct ata_queued_cmd *qc);
347 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
348 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
349 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
350 static void mv_eng_timeout(struct ata_port *ap);
351 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
352
353 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
354 unsigned int port);
355 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
356 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
357 void __iomem *mmio);
358 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
359 unsigned int n_hc);
360 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
361 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
362
363 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
364 unsigned int port);
365 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
366 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
367 void __iomem *mmio);
368 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
369 unsigned int n_hc);
370 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
371 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
372 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
373 unsigned int port_no);
374 static void mv_stop_and_reset(struct ata_port *ap);
375
376 static struct scsi_host_template mv_sht = {
377 .module = THIS_MODULE,
378 .name = DRV_NAME,
379 .ioctl = ata_scsi_ioctl,
380 .queuecommand = ata_scsi_queuecmd,
381 .can_queue = MV_USE_Q_DEPTH,
382 .this_id = ATA_SHT_THIS_ID,
383 .sg_tablesize = MV_MAX_SG_CT / 2,
384 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
385 .emulated = ATA_SHT_EMULATED,
386 .use_clustering = ATA_SHT_USE_CLUSTERING,
387 .proc_name = DRV_NAME,
388 .dma_boundary = MV_DMA_BOUNDARY,
389 .slave_configure = ata_scsi_slave_config,
390 .slave_destroy = ata_scsi_slave_destroy,
391 .bios_param = ata_std_bios_param,
392 };
393
394 static const struct ata_port_operations mv5_ops = {
395 .port_disable = ata_port_disable,
396
397 .tf_load = ata_tf_load,
398 .tf_read = ata_tf_read,
399 .check_status = ata_check_status,
400 .exec_command = ata_exec_command,
401 .dev_select = ata_std_dev_select,
402
403 .phy_reset = mv_phy_reset,
404
405 .qc_prep = mv_qc_prep,
406 .qc_issue = mv_qc_issue,
407 .data_xfer = ata_data_xfer,
408
409 .eng_timeout = mv_eng_timeout,
410
411 .irq_handler = mv_interrupt,
412 .irq_clear = mv_irq_clear,
413 .irq_on = ata_irq_on,
414 .irq_ack = ata_irq_ack,
415
416 .scr_read = mv5_scr_read,
417 .scr_write = mv5_scr_write,
418
419 .port_start = mv_port_start,
420 .port_stop = mv_port_stop,
421 };
422
423 static const struct ata_port_operations mv6_ops = {
424 .port_disable = ata_port_disable,
425
426 .tf_load = ata_tf_load,
427 .tf_read = ata_tf_read,
428 .check_status = ata_check_status,
429 .exec_command = ata_exec_command,
430 .dev_select = ata_std_dev_select,
431
432 .phy_reset = mv_phy_reset,
433
434 .qc_prep = mv_qc_prep,
435 .qc_issue = mv_qc_issue,
436 .data_xfer = ata_data_xfer,
437
438 .eng_timeout = mv_eng_timeout,
439
440 .irq_handler = mv_interrupt,
441 .irq_clear = mv_irq_clear,
442 .irq_on = ata_irq_on,
443 .irq_ack = ata_irq_ack,
444
445 .scr_read = mv_scr_read,
446 .scr_write = mv_scr_write,
447
448 .port_start = mv_port_start,
449 .port_stop = mv_port_stop,
450 };
451
452 static const struct ata_port_operations mv_iie_ops = {
453 .port_disable = ata_port_disable,
454
455 .tf_load = ata_tf_load,
456 .tf_read = ata_tf_read,
457 .check_status = ata_check_status,
458 .exec_command = ata_exec_command,
459 .dev_select = ata_std_dev_select,
460
461 .phy_reset = mv_phy_reset,
462
463 .qc_prep = mv_qc_prep_iie,
464 .qc_issue = mv_qc_issue,
465 .data_xfer = ata_data_xfer,
466
467 .eng_timeout = mv_eng_timeout,
468
469 .irq_handler = mv_interrupt,
470 .irq_clear = mv_irq_clear,
471 .irq_on = ata_irq_on,
472 .irq_ack = ata_irq_ack,
473
474 .scr_read = mv_scr_read,
475 .scr_write = mv_scr_write,
476
477 .port_start = mv_port_start,
478 .port_stop = mv_port_stop,
479 };
480
481 static const struct ata_port_info mv_port_info[] = {
482 { /* chip_504x */
483 .sht = &mv_sht,
484 .flags = MV_COMMON_FLAGS,
485 .pio_mask = 0x1f, /* pio0-4 */
486 .udma_mask = 0x7f, /* udma0-6 */
487 .port_ops = &mv5_ops,
488 },
489 { /* chip_508x */
490 .sht = &mv_sht,
491 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
492 .pio_mask = 0x1f, /* pio0-4 */
493 .udma_mask = 0x7f, /* udma0-6 */
494 .port_ops = &mv5_ops,
495 },
496 { /* chip_5080 */
497 .sht = &mv_sht,
498 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
499 .pio_mask = 0x1f, /* pio0-4 */
500 .udma_mask = 0x7f, /* udma0-6 */
501 .port_ops = &mv5_ops,
502 },
503 { /* chip_604x */
504 .sht = &mv_sht,
505 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
506 .pio_mask = 0x1f, /* pio0-4 */
507 .udma_mask = 0x7f, /* udma0-6 */
508 .port_ops = &mv6_ops,
509 },
510 { /* chip_608x */
511 .sht = &mv_sht,
512 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
513 MV_FLAG_DUAL_HC),
514 .pio_mask = 0x1f, /* pio0-4 */
515 .udma_mask = 0x7f, /* udma0-6 */
516 .port_ops = &mv6_ops,
517 },
518 { /* chip_6042 */
519 .sht = &mv_sht,
520 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
521 .pio_mask = 0x1f, /* pio0-4 */
522 .udma_mask = 0x7f, /* udma0-6 */
523 .port_ops = &mv_iie_ops,
524 },
525 { /* chip_7042 */
526 .sht = &mv_sht,
527 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
528 .pio_mask = 0x1f, /* pio0-4 */
529 .udma_mask = 0x7f, /* udma0-6 */
530 .port_ops = &mv_iie_ops,
531 },
532 };
533
534 static const struct pci_device_id mv_pci_tbl[] = {
535 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
536 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
537 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
538 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
539
540 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
541 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
542 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
543 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
544 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
545
546 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
547
548 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
549
550 { } /* terminate list */
551 };
552
553 static struct pci_driver mv_pci_driver = {
554 .name = DRV_NAME,
555 .id_table = mv_pci_tbl,
556 .probe = mv_init_one,
557 .remove = ata_pci_remove_one,
558 };
559
560 static const struct mv_hw_ops mv5xxx_ops = {
561 .phy_errata = mv5_phy_errata,
562 .enable_leds = mv5_enable_leds,
563 .read_preamp = mv5_read_preamp,
564 .reset_hc = mv5_reset_hc,
565 .reset_flash = mv5_reset_flash,
566 .reset_bus = mv5_reset_bus,
567 };
568
569 static const struct mv_hw_ops mv6xxx_ops = {
570 .phy_errata = mv6_phy_errata,
571 .enable_leds = mv6_enable_leds,
572 .read_preamp = mv6_read_preamp,
573 .reset_hc = mv6_reset_hc,
574 .reset_flash = mv6_reset_flash,
575 .reset_bus = mv_reset_pci_bus,
576 };
577
578 /*
579 * module options
580 */
581 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
582
583
584 /*
585 * Functions
586 */
587
588 static inline void writelfl(unsigned long data, void __iomem *addr)
589 {
590 writel(data, addr);
591 (void) readl(addr); /* flush to avoid PCI posted write */
592 }
593
594 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
595 {
596 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
597 }
598
599 static inline unsigned int mv_hc_from_port(unsigned int port)
600 {
601 return port >> MV_PORT_HC_SHIFT;
602 }
603
604 static inline unsigned int mv_hardport_from_port(unsigned int port)
605 {
606 return port & MV_PORT_MASK;
607 }
608
609 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
610 unsigned int port)
611 {
612 return mv_hc_base(base, mv_hc_from_port(port));
613 }
614
615 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
616 {
617 return mv_hc_base_from_port(base, port) +
618 MV_SATAHC_ARBTR_REG_SZ +
619 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
620 }
621
622 static inline void __iomem *mv_ap_base(struct ata_port *ap)
623 {
624 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
625 }
626
627 static inline int mv_get_hc_count(unsigned long port_flags)
628 {
629 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
630 }
631
632 static void mv_irq_clear(struct ata_port *ap)
633 {
634 }
635
636 /**
637 * mv_start_dma - Enable eDMA engine
638 * @base: port base address
639 * @pp: port private data
640 *
641 * Verify the local cache of the eDMA state is accurate with a
642 * WARN_ON.
643 *
644 * LOCKING:
645 * Inherited from caller.
646 */
647 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
648 {
649 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
650 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
651 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
652 }
653 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
654 }
655
656 /**
657 * mv_stop_dma - Disable eDMA engine
658 * @ap: ATA channel to manipulate
659 *
660 * Verify the local cache of the eDMA state is accurate with a
661 * WARN_ON.
662 *
663 * LOCKING:
664 * Inherited from caller.
665 */
666 static void mv_stop_dma(struct ata_port *ap)
667 {
668 void __iomem *port_mmio = mv_ap_base(ap);
669 struct mv_port_priv *pp = ap->private_data;
670 u32 reg;
671 int i;
672
673 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
674 /* Disable EDMA if active. The disable bit auto clears.
675 */
676 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
677 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
678 } else {
679 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
680 }
681
682 /* now properly wait for the eDMA to stop */
683 for (i = 1000; i > 0; i--) {
684 reg = readl(port_mmio + EDMA_CMD_OFS);
685 if (!(EDMA_EN & reg)) {
686 break;
687 }
688 udelay(100);
689 }
690
691 if (EDMA_EN & reg) {
692 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
693 /* FIXME: Consider doing a reset here to recover */
694 }
695 }
696
697 #ifdef ATA_DEBUG
698 static void mv_dump_mem(void __iomem *start, unsigned bytes)
699 {
700 int b, w;
701 for (b = 0; b < bytes; ) {
702 DPRINTK("%p: ", start + b);
703 for (w = 0; b < bytes && w < 4; w++) {
704 printk("%08x ",readl(start + b));
705 b += sizeof(u32);
706 }
707 printk("\n");
708 }
709 }
710 #endif
711
712 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
713 {
714 #ifdef ATA_DEBUG
715 int b, w;
716 u32 dw;
717 for (b = 0; b < bytes; ) {
718 DPRINTK("%02x: ", b);
719 for (w = 0; b < bytes && w < 4; w++) {
720 (void) pci_read_config_dword(pdev,b,&dw);
721 printk("%08x ",dw);
722 b += sizeof(u32);
723 }
724 printk("\n");
725 }
726 #endif
727 }
728 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
729 struct pci_dev *pdev)
730 {
731 #ifdef ATA_DEBUG
732 void __iomem *hc_base = mv_hc_base(mmio_base,
733 port >> MV_PORT_HC_SHIFT);
734 void __iomem *port_base;
735 int start_port, num_ports, p, start_hc, num_hcs, hc;
736
737 if (0 > port) {
738 start_hc = start_port = 0;
739 num_ports = 8; /* shld be benign for 4 port devs */
740 num_hcs = 2;
741 } else {
742 start_hc = port >> MV_PORT_HC_SHIFT;
743 start_port = port;
744 num_ports = num_hcs = 1;
745 }
746 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
747 num_ports > 1 ? num_ports - 1 : start_port);
748
749 if (NULL != pdev) {
750 DPRINTK("PCI config space regs:\n");
751 mv_dump_pci_cfg(pdev, 0x68);
752 }
753 DPRINTK("PCI regs:\n");
754 mv_dump_mem(mmio_base+0xc00, 0x3c);
755 mv_dump_mem(mmio_base+0xd00, 0x34);
756 mv_dump_mem(mmio_base+0xf00, 0x4);
757 mv_dump_mem(mmio_base+0x1d00, 0x6c);
758 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
759 hc_base = mv_hc_base(mmio_base, hc);
760 DPRINTK("HC regs (HC %i):\n", hc);
761 mv_dump_mem(hc_base, 0x1c);
762 }
763 for (p = start_port; p < start_port + num_ports; p++) {
764 port_base = mv_port_base(mmio_base, p);
765 DPRINTK("EDMA regs (port %i):\n",p);
766 mv_dump_mem(port_base, 0x54);
767 DPRINTK("SATA regs (port %i):\n",p);
768 mv_dump_mem(port_base+0x300, 0x60);
769 }
770 #endif
771 }
772
773 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
774 {
775 unsigned int ofs;
776
777 switch (sc_reg_in) {
778 case SCR_STATUS:
779 case SCR_CONTROL:
780 case SCR_ERROR:
781 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
782 break;
783 case SCR_ACTIVE:
784 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
785 break;
786 default:
787 ofs = 0xffffffffU;
788 break;
789 }
790 return ofs;
791 }
792
793 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
794 {
795 unsigned int ofs = mv_scr_offset(sc_reg_in);
796
797 if (0xffffffffU != ofs) {
798 return readl(mv_ap_base(ap) + ofs);
799 } else {
800 return (u32) ofs;
801 }
802 }
803
804 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
805 {
806 unsigned int ofs = mv_scr_offset(sc_reg_in);
807
808 if (0xffffffffU != ofs) {
809 writelfl(val, mv_ap_base(ap) + ofs);
810 }
811 }
812
813 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
814 {
815 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
816
817 /* set up non-NCQ EDMA configuration */
818 cfg &= ~0x1f; /* clear queue depth */
819 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
820 cfg &= ~(1 << 9); /* disable equeue */
821
822 if (IS_GEN_I(hpriv))
823 cfg |= (1 << 8); /* enab config burst size mask */
824
825 else if (IS_GEN_II(hpriv))
826 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
827
828 else if (IS_GEN_IIE(hpriv)) {
829 cfg |= (1 << 23); /* dis RX PM port mask */
830 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
831 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
832 cfg |= (1 << 18); /* enab early completion */
833 cfg |= (1 << 17); /* enab host q cache */
834 cfg |= (1 << 22); /* enab cutthrough */
835 }
836
837 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
838 }
839
840 /**
841 * mv_port_start - Port specific init/start routine.
842 * @ap: ATA channel to manipulate
843 *
844 * Allocate and point to DMA memory, init port private memory,
845 * zero indices.
846 *
847 * LOCKING:
848 * Inherited from caller.
849 */
850 static int mv_port_start(struct ata_port *ap)
851 {
852 struct device *dev = ap->host->dev;
853 struct mv_host_priv *hpriv = ap->host->private_data;
854 struct mv_port_priv *pp;
855 void __iomem *port_mmio = mv_ap_base(ap);
856 void *mem;
857 dma_addr_t mem_dma;
858 int rc;
859
860 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
861 if (!pp)
862 return -ENOMEM;
863
864 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
865 GFP_KERNEL);
866 if (!mem)
867 return -ENOMEM;
868 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
869
870 rc = ata_pad_alloc(ap, dev);
871 if (rc)
872 return rc;
873
874 /* First item in chunk of DMA memory:
875 * 32-slot command request table (CRQB), 32 bytes each in size
876 */
877 pp->crqb = mem;
878 pp->crqb_dma = mem_dma;
879 mem += MV_CRQB_Q_SZ;
880 mem_dma += MV_CRQB_Q_SZ;
881
882 /* Second item:
883 * 32-slot command response table (CRPB), 8 bytes each in size
884 */
885 pp->crpb = mem;
886 pp->crpb_dma = mem_dma;
887 mem += MV_CRPB_Q_SZ;
888 mem_dma += MV_CRPB_Q_SZ;
889
890 /* Third item:
891 * Table of scatter-gather descriptors (ePRD), 16 bytes each
892 */
893 pp->sg_tbl = mem;
894 pp->sg_tbl_dma = mem_dma;
895
896 mv_edma_cfg(hpriv, port_mmio);
897
898 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
899 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
900 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
901
902 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
903 writelfl(pp->crqb_dma & 0xffffffff,
904 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
905 else
906 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
907
908 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
909
910 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
911 writelfl(pp->crpb_dma & 0xffffffff,
912 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
913 else
914 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
915
916 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
917 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
918
919 /* Don't turn on EDMA here...do it before DMA commands only. Else
920 * we'll be unable to send non-data, PIO, etc due to restricted access
921 * to shadow regs.
922 */
923 ap->private_data = pp;
924 return 0;
925 }
926
927 /**
928 * mv_port_stop - Port specific cleanup/stop routine.
929 * @ap: ATA channel to manipulate
930 *
931 * Stop DMA, cleanup port memory.
932 *
933 * LOCKING:
934 * This routine uses the host lock to protect the DMA stop.
935 */
936 static void mv_port_stop(struct ata_port *ap)
937 {
938 unsigned long flags;
939
940 spin_lock_irqsave(&ap->host->lock, flags);
941 mv_stop_dma(ap);
942 spin_unlock_irqrestore(&ap->host->lock, flags);
943 }
944
945 /**
946 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
947 * @qc: queued command whose SG list to source from
948 *
949 * Populate the SG list and mark the last entry.
950 *
951 * LOCKING:
952 * Inherited from caller.
953 */
954 static void mv_fill_sg(struct ata_queued_cmd *qc)
955 {
956 struct mv_port_priv *pp = qc->ap->private_data;
957 unsigned int i = 0;
958 struct scatterlist *sg;
959
960 ata_for_each_sg(sg, qc) {
961 dma_addr_t addr;
962 u32 sg_len, len, offset;
963
964 addr = sg_dma_address(sg);
965 sg_len = sg_dma_len(sg);
966
967 while (sg_len) {
968 offset = addr & MV_DMA_BOUNDARY;
969 len = sg_len;
970 if ((offset + sg_len) > 0x10000)
971 len = 0x10000 - offset;
972
973 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
974 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
975 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
976
977 sg_len -= len;
978 addr += len;
979
980 if (!sg_len && ata_sg_is_last(sg, qc))
981 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
982
983 i++;
984 }
985 }
986 }
987
988 static inline unsigned mv_inc_q_index(unsigned index)
989 {
990 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
991 }
992
993 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
994 {
995 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
996 (last ? CRQB_CMD_LAST : 0);
997 *cmdw = cpu_to_le16(tmp);
998 }
999
1000 /**
1001 * mv_qc_prep - Host specific command preparation.
1002 * @qc: queued command to prepare
1003 *
1004 * This routine simply redirects to the general purpose routine
1005 * if command is not DMA. Else, it handles prep of the CRQB
1006 * (command request block), does some sanity checking, and calls
1007 * the SG load routine.
1008 *
1009 * LOCKING:
1010 * Inherited from caller.
1011 */
1012 static void mv_qc_prep(struct ata_queued_cmd *qc)
1013 {
1014 struct ata_port *ap = qc->ap;
1015 struct mv_port_priv *pp = ap->private_data;
1016 __le16 *cw;
1017 struct ata_taskfile *tf;
1018 u16 flags = 0;
1019 unsigned in_index;
1020
1021 if (ATA_PROT_DMA != qc->tf.protocol)
1022 return;
1023
1024 /* Fill in command request block
1025 */
1026 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1027 flags |= CRQB_FLAG_READ;
1028 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1029 flags |= qc->tag << CRQB_TAG_SHIFT;
1030
1031 /* get current queue index from hardware */
1032 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1033 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1034
1035 pp->crqb[in_index].sg_addr =
1036 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1037 pp->crqb[in_index].sg_addr_hi =
1038 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1039 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1040
1041 cw = &pp->crqb[in_index].ata_cmd[0];
1042 tf = &qc->tf;
1043
1044 /* Sadly, the CRQB cannot accomodate all registers--there are
1045 * only 11 bytes...so we must pick and choose required
1046 * registers based on the command. So, we drop feature and
1047 * hob_feature for [RW] DMA commands, but they are needed for
1048 * NCQ. NCQ will drop hob_nsect.
1049 */
1050 switch (tf->command) {
1051 case ATA_CMD_READ:
1052 case ATA_CMD_READ_EXT:
1053 case ATA_CMD_WRITE:
1054 case ATA_CMD_WRITE_EXT:
1055 case ATA_CMD_WRITE_FUA_EXT:
1056 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1057 break;
1058 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1059 case ATA_CMD_FPDMA_READ:
1060 case ATA_CMD_FPDMA_WRITE:
1061 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1062 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1063 break;
1064 #endif /* FIXME: remove this line when NCQ added */
1065 default:
1066 /* The only other commands EDMA supports in non-queued and
1067 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1068 * of which are defined/used by Linux. If we get here, this
1069 * driver needs work.
1070 *
1071 * FIXME: modify libata to give qc_prep a return value and
1072 * return error here.
1073 */
1074 BUG_ON(tf->command);
1075 break;
1076 }
1077 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1078 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1079 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1080 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1081 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1082 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1083 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1084 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1085 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1086
1087 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1088 return;
1089 mv_fill_sg(qc);
1090 }
1091
1092 /**
1093 * mv_qc_prep_iie - Host specific command preparation.
1094 * @qc: queued command to prepare
1095 *
1096 * This routine simply redirects to the general purpose routine
1097 * if command is not DMA. Else, it handles prep of the CRQB
1098 * (command request block), does some sanity checking, and calls
1099 * the SG load routine.
1100 *
1101 * LOCKING:
1102 * Inherited from caller.
1103 */
1104 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1105 {
1106 struct ata_port *ap = qc->ap;
1107 struct mv_port_priv *pp = ap->private_data;
1108 struct mv_crqb_iie *crqb;
1109 struct ata_taskfile *tf;
1110 unsigned in_index;
1111 u32 flags = 0;
1112
1113 if (ATA_PROT_DMA != qc->tf.protocol)
1114 return;
1115
1116 /* Fill in Gen IIE command request block
1117 */
1118 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1119 flags |= CRQB_FLAG_READ;
1120
1121 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1122 flags |= qc->tag << CRQB_TAG_SHIFT;
1123
1124 /* get current queue index from hardware */
1125 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1126 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1127
1128 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1129 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1130 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1131 crqb->flags = cpu_to_le32(flags);
1132
1133 tf = &qc->tf;
1134 crqb->ata_cmd[0] = cpu_to_le32(
1135 (tf->command << 16) |
1136 (tf->feature << 24)
1137 );
1138 crqb->ata_cmd[1] = cpu_to_le32(
1139 (tf->lbal << 0) |
1140 (tf->lbam << 8) |
1141 (tf->lbah << 16) |
1142 (tf->device << 24)
1143 );
1144 crqb->ata_cmd[2] = cpu_to_le32(
1145 (tf->hob_lbal << 0) |
1146 (tf->hob_lbam << 8) |
1147 (tf->hob_lbah << 16) |
1148 (tf->hob_feature << 24)
1149 );
1150 crqb->ata_cmd[3] = cpu_to_le32(
1151 (tf->nsect << 0) |
1152 (tf->hob_nsect << 8)
1153 );
1154
1155 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1156 return;
1157 mv_fill_sg(qc);
1158 }
1159
1160 /**
1161 * mv_qc_issue - Initiate a command to the host
1162 * @qc: queued command to start
1163 *
1164 * This routine simply redirects to the general purpose routine
1165 * if command is not DMA. Else, it sanity checks our local
1166 * caches of the request producer/consumer indices then enables
1167 * DMA and bumps the request producer index.
1168 *
1169 * LOCKING:
1170 * Inherited from caller.
1171 */
1172 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1173 {
1174 void __iomem *port_mmio = mv_ap_base(qc->ap);
1175 struct mv_port_priv *pp = qc->ap->private_data;
1176 unsigned in_index;
1177 u32 in_ptr;
1178
1179 if (ATA_PROT_DMA != qc->tf.protocol) {
1180 /* We're about to send a non-EDMA capable command to the
1181 * port. Turn off EDMA so there won't be problems accessing
1182 * shadow block, etc registers.
1183 */
1184 mv_stop_dma(qc->ap);
1185 return ata_qc_issue_prot(qc);
1186 }
1187
1188 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1189 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1190
1191 /* until we do queuing, the queue should be empty at this point */
1192 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1193 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1194
1195 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1196
1197 mv_start_dma(port_mmio, pp);
1198
1199 /* and write the request in pointer to kick the EDMA to life */
1200 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1201 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1202 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1203
1204 return 0;
1205 }
1206
1207 /**
1208 * mv_get_crpb_status - get status from most recently completed cmd
1209 * @ap: ATA channel to manipulate
1210 *
1211 * This routine is for use when the port is in DMA mode, when it
1212 * will be using the CRPB (command response block) method of
1213 * returning command completion information. We check indices
1214 * are good, grab status, and bump the response consumer index to
1215 * prove that we're up to date.
1216 *
1217 * LOCKING:
1218 * Inherited from caller.
1219 */
1220 static u8 mv_get_crpb_status(struct ata_port *ap)
1221 {
1222 void __iomem *port_mmio = mv_ap_base(ap);
1223 struct mv_port_priv *pp = ap->private_data;
1224 unsigned out_index;
1225 u32 out_ptr;
1226 u8 ata_status;
1227
1228 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1229 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1230
1231 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1232 >> CRPB_FLAG_STATUS_SHIFT;
1233
1234 /* increment our consumer index... */
1235 out_index = mv_inc_q_index(out_index);
1236
1237 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1238 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1239 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1240
1241 /* write out our inc'd consumer index so EDMA knows we're caught up */
1242 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1243 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1244 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1245
1246 /* Return ATA status register for completed CRPB */
1247 return ata_status;
1248 }
1249
1250 /**
1251 * mv_err_intr - Handle error interrupts on the port
1252 * @ap: ATA channel to manipulate
1253 * @reset_allowed: bool: 0 == don't trigger from reset here
1254 *
1255 * In most cases, just clear the interrupt and move on. However,
1256 * some cases require an eDMA reset, which is done right before
1257 * the COMRESET in mv_phy_reset(). The SERR case requires a
1258 * clear of pending errors in the SATA SERROR register. Finally,
1259 * if the port disabled DMA, update our cached copy to match.
1260 *
1261 * LOCKING:
1262 * Inherited from caller.
1263 */
1264 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1265 {
1266 void __iomem *port_mmio = mv_ap_base(ap);
1267 u32 edma_err_cause, serr = 0;
1268
1269 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1270
1271 if (EDMA_ERR_SERR & edma_err_cause) {
1272 sata_scr_read(ap, SCR_ERROR, &serr);
1273 sata_scr_write_flush(ap, SCR_ERROR, serr);
1274 }
1275 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1276 struct mv_port_priv *pp = ap->private_data;
1277 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1278 }
1279 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1280 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1281
1282 /* Clear EDMA now that SERR cleanup done */
1283 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1284
1285 /* check for fatal here and recover if needed */
1286 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1287 mv_stop_and_reset(ap);
1288 }
1289
1290 /**
1291 * mv_host_intr - Handle all interrupts on the given host controller
1292 * @host: host specific structure
1293 * @relevant: port error bits relevant to this host controller
1294 * @hc: which host controller we're to look at
1295 *
1296 * Read then write clear the HC interrupt status then walk each
1297 * port connected to the HC and see if it needs servicing. Port
1298 * success ints are reported in the HC interrupt status reg, the
1299 * port error ints are reported in the higher level main
1300 * interrupt status register and thus are passed in via the
1301 * 'relevant' argument.
1302 *
1303 * LOCKING:
1304 * Inherited from caller.
1305 */
1306 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1307 {
1308 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1309 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1310 struct ata_queued_cmd *qc;
1311 u32 hc_irq_cause;
1312 int shift, port, port0, hard_port, handled;
1313 unsigned int err_mask;
1314
1315 if (hc == 0) {
1316 port0 = 0;
1317 } else {
1318 port0 = MV_PORTS_PER_HC;
1319 }
1320
1321 /* we'll need the HC success int register in most cases */
1322 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1323 if (hc_irq_cause) {
1324 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1325 }
1326
1327 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1328 hc,relevant,hc_irq_cause);
1329
1330 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1331 u8 ata_status = 0;
1332 struct ata_port *ap = host->ports[port];
1333 struct mv_port_priv *pp = ap->private_data;
1334
1335 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1336 handled = 0; /* ensure ata_status is set if handled++ */
1337
1338 /* Note that DEV_IRQ might happen spuriously during EDMA,
1339 * and should be ignored in such cases.
1340 * The cause of this is still under investigation.
1341 */
1342 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1343 /* EDMA: check for response queue interrupt */
1344 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1345 ata_status = mv_get_crpb_status(ap);
1346 handled = 1;
1347 }
1348 } else {
1349 /* PIO: check for device (drive) interrupt */
1350 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1351 ata_status = readb(ap->ioaddr.status_addr);
1352 handled = 1;
1353 /* ignore spurious intr if drive still BUSY */
1354 if (ata_status & ATA_BUSY) {
1355 ata_status = 0;
1356 handled = 0;
1357 }
1358 }
1359 }
1360
1361 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1362 continue;
1363
1364 err_mask = ac_err_mask(ata_status);
1365
1366 shift = port << 1; /* (port * 2) */
1367 if (port >= MV_PORTS_PER_HC) {
1368 shift++; /* skip bit 8 in the HC Main IRQ reg */
1369 }
1370 if ((PORT0_ERR << shift) & relevant) {
1371 mv_err_intr(ap, 1);
1372 err_mask |= AC_ERR_OTHER;
1373 handled = 1;
1374 }
1375
1376 if (handled) {
1377 qc = ata_qc_from_tag(ap, ap->active_tag);
1378 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1379 VPRINTK("port %u IRQ found for qc, "
1380 "ata_status 0x%x\n", port,ata_status);
1381 /* mark qc status appropriately */
1382 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1383 qc->err_mask |= err_mask;
1384 ata_qc_complete(qc);
1385 }
1386 }
1387 }
1388 }
1389 VPRINTK("EXIT\n");
1390 }
1391
1392 /**
1393 * mv_interrupt -
1394 * @irq: unused
1395 * @dev_instance: private data; in this case the host structure
1396 * @regs: unused
1397 *
1398 * Read the read only register to determine if any host
1399 * controllers have pending interrupts. If so, call lower level
1400 * routine to handle. Also check for PCI errors which are only
1401 * reported here.
1402 *
1403 * LOCKING:
1404 * This routine holds the host lock while processing pending
1405 * interrupts.
1406 */
1407 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1408 {
1409 struct ata_host *host = dev_instance;
1410 unsigned int hc, handled = 0, n_hcs;
1411 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1412 struct mv_host_priv *hpriv;
1413 u32 irq_stat;
1414
1415 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1416
1417 /* check the cases where we either have nothing pending or have read
1418 * a bogus register value which can indicate HW removal or PCI fault
1419 */
1420 if (!irq_stat || (0xffffffffU == irq_stat)) {
1421 return IRQ_NONE;
1422 }
1423
1424 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1425 spin_lock(&host->lock);
1426
1427 for (hc = 0; hc < n_hcs; hc++) {
1428 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1429 if (relevant) {
1430 mv_host_intr(host, relevant, hc);
1431 handled++;
1432 }
1433 }
1434
1435 hpriv = host->private_data;
1436 if (IS_60XX(hpriv)) {
1437 /* deal with the interrupt coalescing bits */
1438 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1439 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1440 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1441 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1442 }
1443 }
1444
1445 if (PCI_ERR & irq_stat) {
1446 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1447 readl(mmio + PCI_IRQ_CAUSE_OFS));
1448
1449 DPRINTK("All regs @ PCI error\n");
1450 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1451
1452 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1453 handled++;
1454 }
1455 spin_unlock(&host->lock);
1456
1457 return IRQ_RETVAL(handled);
1458 }
1459
1460 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1461 {
1462 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1463 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1464
1465 return hc_mmio + ofs;
1466 }
1467
1468 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1469 {
1470 unsigned int ofs;
1471
1472 switch (sc_reg_in) {
1473 case SCR_STATUS:
1474 case SCR_ERROR:
1475 case SCR_CONTROL:
1476 ofs = sc_reg_in * sizeof(u32);
1477 break;
1478 default:
1479 ofs = 0xffffffffU;
1480 break;
1481 }
1482 return ofs;
1483 }
1484
1485 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1486 {
1487 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1488 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1489 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1490
1491 if (ofs != 0xffffffffU)
1492 return readl(addr + ofs);
1493 else
1494 return (u32) ofs;
1495 }
1496
1497 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1498 {
1499 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1500 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1501 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1502
1503 if (ofs != 0xffffffffU)
1504 writelfl(val, addr + ofs);
1505 }
1506
1507 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1508 {
1509 u8 rev_id;
1510 int early_5080;
1511
1512 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1513
1514 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1515
1516 if (!early_5080) {
1517 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1518 tmp |= (1 << 0);
1519 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1520 }
1521
1522 mv_reset_pci_bus(pdev, mmio);
1523 }
1524
1525 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1526 {
1527 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1528 }
1529
1530 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1531 void __iomem *mmio)
1532 {
1533 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1534 u32 tmp;
1535
1536 tmp = readl(phy_mmio + MV5_PHY_MODE);
1537
1538 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1539 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1540 }
1541
1542 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1543 {
1544 u32 tmp;
1545
1546 writel(0, mmio + MV_GPIO_PORT_CTL);
1547
1548 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1549
1550 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1551 tmp |= ~(1 << 0);
1552 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1553 }
1554
1555 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1556 unsigned int port)
1557 {
1558 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1559 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1560 u32 tmp;
1561 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1562
1563 if (fix_apm_sq) {
1564 tmp = readl(phy_mmio + MV5_LT_MODE);
1565 tmp |= (1 << 19);
1566 writel(tmp, phy_mmio + MV5_LT_MODE);
1567
1568 tmp = readl(phy_mmio + MV5_PHY_CTL);
1569 tmp &= ~0x3;
1570 tmp |= 0x1;
1571 writel(tmp, phy_mmio + MV5_PHY_CTL);
1572 }
1573
1574 tmp = readl(phy_mmio + MV5_PHY_MODE);
1575 tmp &= ~mask;
1576 tmp |= hpriv->signal[port].pre;
1577 tmp |= hpriv->signal[port].amps;
1578 writel(tmp, phy_mmio + MV5_PHY_MODE);
1579 }
1580
1581
1582 #undef ZERO
1583 #define ZERO(reg) writel(0, port_mmio + (reg))
1584 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1585 unsigned int port)
1586 {
1587 void __iomem *port_mmio = mv_port_base(mmio, port);
1588
1589 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1590
1591 mv_channel_reset(hpriv, mmio, port);
1592
1593 ZERO(0x028); /* command */
1594 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1595 ZERO(0x004); /* timer */
1596 ZERO(0x008); /* irq err cause */
1597 ZERO(0x00c); /* irq err mask */
1598 ZERO(0x010); /* rq bah */
1599 ZERO(0x014); /* rq inp */
1600 ZERO(0x018); /* rq outp */
1601 ZERO(0x01c); /* respq bah */
1602 ZERO(0x024); /* respq outp */
1603 ZERO(0x020); /* respq inp */
1604 ZERO(0x02c); /* test control */
1605 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1606 }
1607 #undef ZERO
1608
1609 #define ZERO(reg) writel(0, hc_mmio + (reg))
1610 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1611 unsigned int hc)
1612 {
1613 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1614 u32 tmp;
1615
1616 ZERO(0x00c);
1617 ZERO(0x010);
1618 ZERO(0x014);
1619 ZERO(0x018);
1620
1621 tmp = readl(hc_mmio + 0x20);
1622 tmp &= 0x1c1c1c1c;
1623 tmp |= 0x03030303;
1624 writel(tmp, hc_mmio + 0x20);
1625 }
1626 #undef ZERO
1627
1628 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1629 unsigned int n_hc)
1630 {
1631 unsigned int hc, port;
1632
1633 for (hc = 0; hc < n_hc; hc++) {
1634 for (port = 0; port < MV_PORTS_PER_HC; port++)
1635 mv5_reset_hc_port(hpriv, mmio,
1636 (hc * MV_PORTS_PER_HC) + port);
1637
1638 mv5_reset_one_hc(hpriv, mmio, hc);
1639 }
1640
1641 return 0;
1642 }
1643
1644 #undef ZERO
1645 #define ZERO(reg) writel(0, mmio + (reg))
1646 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1647 {
1648 u32 tmp;
1649
1650 tmp = readl(mmio + MV_PCI_MODE);
1651 tmp &= 0xff00ffff;
1652 writel(tmp, mmio + MV_PCI_MODE);
1653
1654 ZERO(MV_PCI_DISC_TIMER);
1655 ZERO(MV_PCI_MSI_TRIGGER);
1656 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1657 ZERO(HC_MAIN_IRQ_MASK_OFS);
1658 ZERO(MV_PCI_SERR_MASK);
1659 ZERO(PCI_IRQ_CAUSE_OFS);
1660 ZERO(PCI_IRQ_MASK_OFS);
1661 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1662 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1663 ZERO(MV_PCI_ERR_ATTRIBUTE);
1664 ZERO(MV_PCI_ERR_COMMAND);
1665 }
1666 #undef ZERO
1667
1668 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1669 {
1670 u32 tmp;
1671
1672 mv5_reset_flash(hpriv, mmio);
1673
1674 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1675 tmp &= 0x3;
1676 tmp |= (1 << 5) | (1 << 6);
1677 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1678 }
1679
1680 /**
1681 * mv6_reset_hc - Perform the 6xxx global soft reset
1682 * @mmio: base address of the HBA
1683 *
1684 * This routine only applies to 6xxx parts.
1685 *
1686 * LOCKING:
1687 * Inherited from caller.
1688 */
1689 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1690 unsigned int n_hc)
1691 {
1692 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1693 int i, rc = 0;
1694 u32 t;
1695
1696 /* Following procedure defined in PCI "main command and status
1697 * register" table.
1698 */
1699 t = readl(reg);
1700 writel(t | STOP_PCI_MASTER, reg);
1701
1702 for (i = 0; i < 1000; i++) {
1703 udelay(1);
1704 t = readl(reg);
1705 if (PCI_MASTER_EMPTY & t) {
1706 break;
1707 }
1708 }
1709 if (!(PCI_MASTER_EMPTY & t)) {
1710 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1711 rc = 1;
1712 goto done;
1713 }
1714
1715 /* set reset */
1716 i = 5;
1717 do {
1718 writel(t | GLOB_SFT_RST, reg);
1719 t = readl(reg);
1720 udelay(1);
1721 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1722
1723 if (!(GLOB_SFT_RST & t)) {
1724 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1725 rc = 1;
1726 goto done;
1727 }
1728
1729 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1730 i = 5;
1731 do {
1732 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1733 t = readl(reg);
1734 udelay(1);
1735 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1736
1737 if (GLOB_SFT_RST & t) {
1738 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1739 rc = 1;
1740 }
1741 done:
1742 return rc;
1743 }
1744
1745 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1746 void __iomem *mmio)
1747 {
1748 void __iomem *port_mmio;
1749 u32 tmp;
1750
1751 tmp = readl(mmio + MV_RESET_CFG);
1752 if ((tmp & (1 << 0)) == 0) {
1753 hpriv->signal[idx].amps = 0x7 << 8;
1754 hpriv->signal[idx].pre = 0x1 << 5;
1755 return;
1756 }
1757
1758 port_mmio = mv_port_base(mmio, idx);
1759 tmp = readl(port_mmio + PHY_MODE2);
1760
1761 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1762 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1763 }
1764
1765 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1766 {
1767 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1768 }
1769
1770 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1771 unsigned int port)
1772 {
1773 void __iomem *port_mmio = mv_port_base(mmio, port);
1774
1775 u32 hp_flags = hpriv->hp_flags;
1776 int fix_phy_mode2 =
1777 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1778 int fix_phy_mode4 =
1779 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1780 u32 m2, tmp;
1781
1782 if (fix_phy_mode2) {
1783 m2 = readl(port_mmio + PHY_MODE2);
1784 m2 &= ~(1 << 16);
1785 m2 |= (1 << 31);
1786 writel(m2, port_mmio + PHY_MODE2);
1787
1788 udelay(200);
1789
1790 m2 = readl(port_mmio + PHY_MODE2);
1791 m2 &= ~((1 << 16) | (1 << 31));
1792 writel(m2, port_mmio + PHY_MODE2);
1793
1794 udelay(200);
1795 }
1796
1797 /* who knows what this magic does */
1798 tmp = readl(port_mmio + PHY_MODE3);
1799 tmp &= ~0x7F800000;
1800 tmp |= 0x2A800000;
1801 writel(tmp, port_mmio + PHY_MODE3);
1802
1803 if (fix_phy_mode4) {
1804 u32 m4;
1805
1806 m4 = readl(port_mmio + PHY_MODE4);
1807
1808 if (hp_flags & MV_HP_ERRATA_60X1B2)
1809 tmp = readl(port_mmio + 0x310);
1810
1811 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1812
1813 writel(m4, port_mmio + PHY_MODE4);
1814
1815 if (hp_flags & MV_HP_ERRATA_60X1B2)
1816 writel(tmp, port_mmio + 0x310);
1817 }
1818
1819 /* Revert values of pre-emphasis and signal amps to the saved ones */
1820 m2 = readl(port_mmio + PHY_MODE2);
1821
1822 m2 &= ~MV_M2_PREAMP_MASK;
1823 m2 |= hpriv->signal[port].amps;
1824 m2 |= hpriv->signal[port].pre;
1825 m2 &= ~(1 << 16);
1826
1827 /* according to mvSata 3.6.1, some IIE values are fixed */
1828 if (IS_GEN_IIE(hpriv)) {
1829 m2 &= ~0xC30FF01F;
1830 m2 |= 0x0000900F;
1831 }
1832
1833 writel(m2, port_mmio + PHY_MODE2);
1834 }
1835
1836 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1837 unsigned int port_no)
1838 {
1839 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1840
1841 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1842
1843 if (IS_60XX(hpriv)) {
1844 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1845 ifctl |= (1 << 7); /* enable gen2i speed */
1846 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1847 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1848 }
1849
1850 udelay(25); /* allow reset propagation */
1851
1852 /* Spec never mentions clearing the bit. Marvell's driver does
1853 * clear the bit, however.
1854 */
1855 writelfl(0, port_mmio + EDMA_CMD_OFS);
1856
1857 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1858
1859 if (IS_50XX(hpriv))
1860 mdelay(1);
1861 }
1862
1863 static void mv_stop_and_reset(struct ata_port *ap)
1864 {
1865 struct mv_host_priv *hpriv = ap->host->private_data;
1866 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1867
1868 mv_stop_dma(ap);
1869
1870 mv_channel_reset(hpriv, mmio, ap->port_no);
1871
1872 __mv_phy_reset(ap, 0);
1873 }
1874
1875 static inline void __msleep(unsigned int msec, int can_sleep)
1876 {
1877 if (can_sleep)
1878 msleep(msec);
1879 else
1880 mdelay(msec);
1881 }
1882
1883 /**
1884 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1885 * @ap: ATA channel to manipulate
1886 *
1887 * Part of this is taken from __sata_phy_reset and modified to
1888 * not sleep since this routine gets called from interrupt level.
1889 *
1890 * LOCKING:
1891 * Inherited from caller. This is coded to safe to call at
1892 * interrupt level, i.e. it does not sleep.
1893 */
1894 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1895 {
1896 struct mv_port_priv *pp = ap->private_data;
1897 struct mv_host_priv *hpriv = ap->host->private_data;
1898 void __iomem *port_mmio = mv_ap_base(ap);
1899 struct ata_taskfile tf;
1900 struct ata_device *dev = &ap->device[0];
1901 unsigned long timeout;
1902 int retry = 5;
1903 u32 sstatus;
1904
1905 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1906
1907 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1908 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1909 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1910
1911 /* Issue COMRESET via SControl */
1912 comreset_retry:
1913 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1914 __msleep(1, can_sleep);
1915
1916 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1917 __msleep(20, can_sleep);
1918
1919 timeout = jiffies + msecs_to_jiffies(200);
1920 do {
1921 sata_scr_read(ap, SCR_STATUS, &sstatus);
1922 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1923 break;
1924
1925 __msleep(1, can_sleep);
1926 } while (time_before(jiffies, timeout));
1927
1928 /* work around errata */
1929 if (IS_60XX(hpriv) &&
1930 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1931 (retry-- > 0))
1932 goto comreset_retry;
1933
1934 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1935 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1936 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1937
1938 if (ata_port_online(ap)) {
1939 ata_port_probe(ap);
1940 } else {
1941 sata_scr_read(ap, SCR_STATUS, &sstatus);
1942 ata_port_printk(ap, KERN_INFO,
1943 "no device found (phy stat %08x)\n", sstatus);
1944 ata_port_disable(ap);
1945 return;
1946 }
1947 ap->cbl = ATA_CBL_SATA;
1948
1949 /* even after SStatus reflects that device is ready,
1950 * it seems to take a while for link to be fully
1951 * established (and thus Status no longer 0x80/0x7F),
1952 * so we poll a bit for that, here.
1953 */
1954 retry = 20;
1955 while (1) {
1956 u8 drv_stat = ata_check_status(ap);
1957 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1958 break;
1959 __msleep(500, can_sleep);
1960 if (retry-- <= 0)
1961 break;
1962 }
1963
1964 tf.lbah = readb(ap->ioaddr.lbah_addr);
1965 tf.lbam = readb(ap->ioaddr.lbam_addr);
1966 tf.lbal = readb(ap->ioaddr.lbal_addr);
1967 tf.nsect = readb(ap->ioaddr.nsect_addr);
1968
1969 dev->class = ata_dev_classify(&tf);
1970 if (!ata_dev_enabled(dev)) {
1971 VPRINTK("Port disabled post-sig: No device present.\n");
1972 ata_port_disable(ap);
1973 }
1974
1975 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1976
1977 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1978
1979 VPRINTK("EXIT\n");
1980 }
1981
1982 static void mv_phy_reset(struct ata_port *ap)
1983 {
1984 __mv_phy_reset(ap, 1);
1985 }
1986
1987 /**
1988 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1989 * @ap: ATA channel to manipulate
1990 *
1991 * Intent is to clear all pending error conditions, reset the
1992 * chip/bus, fail the command, and move on.
1993 *
1994 * LOCKING:
1995 * This routine holds the host lock while failing the command.
1996 */
1997 static void mv_eng_timeout(struct ata_port *ap)
1998 {
1999 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2000 struct ata_queued_cmd *qc;
2001 unsigned long flags;
2002
2003 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2004 DPRINTK("All regs @ start of eng_timeout\n");
2005 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2006
2007 qc = ata_qc_from_tag(ap, ap->active_tag);
2008 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2009 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2010
2011 spin_lock_irqsave(&ap->host->lock, flags);
2012 mv_err_intr(ap, 0);
2013 mv_stop_and_reset(ap);
2014 spin_unlock_irqrestore(&ap->host->lock, flags);
2015
2016 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2017 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2018 qc->err_mask |= AC_ERR_TIMEOUT;
2019 ata_eh_qc_complete(qc);
2020 }
2021 }
2022
2023 /**
2024 * mv_port_init - Perform some early initialization on a single port.
2025 * @port: libata data structure storing shadow register addresses
2026 * @port_mmio: base address of the port
2027 *
2028 * Initialize shadow register mmio addresses, clear outstanding
2029 * interrupts on the port, and unmask interrupts for the future
2030 * start of the port.
2031 *
2032 * LOCKING:
2033 * Inherited from caller.
2034 */
2035 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2036 {
2037 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2038 unsigned serr_ofs;
2039
2040 /* PIO related setup
2041 */
2042 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2043 port->error_addr =
2044 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2045 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2046 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2047 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2048 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2049 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2050 port->status_addr =
2051 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2052 /* special case: control/altstatus doesn't have ATA_REG_ address */
2053 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2054
2055 /* unused: */
2056 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2057
2058 /* Clear any currently outstanding port interrupt conditions */
2059 serr_ofs = mv_scr_offset(SCR_ERROR);
2060 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2061 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2062
2063 /* unmask all EDMA error interrupts */
2064 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2065
2066 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2067 readl(port_mmio + EDMA_CFG_OFS),
2068 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2069 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2070 }
2071
2072 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2073 unsigned int board_idx)
2074 {
2075 u8 rev_id;
2076 u32 hp_flags = hpriv->hp_flags;
2077
2078 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2079
2080 switch(board_idx) {
2081 case chip_5080:
2082 hpriv->ops = &mv5xxx_ops;
2083 hp_flags |= MV_HP_50XX;
2084
2085 switch (rev_id) {
2086 case 0x1:
2087 hp_flags |= MV_HP_ERRATA_50XXB0;
2088 break;
2089 case 0x3:
2090 hp_flags |= MV_HP_ERRATA_50XXB2;
2091 break;
2092 default:
2093 dev_printk(KERN_WARNING, &pdev->dev,
2094 "Applying 50XXB2 workarounds to unknown rev\n");
2095 hp_flags |= MV_HP_ERRATA_50XXB2;
2096 break;
2097 }
2098 break;
2099
2100 case chip_504x:
2101 case chip_508x:
2102 hpriv->ops = &mv5xxx_ops;
2103 hp_flags |= MV_HP_50XX;
2104
2105 switch (rev_id) {
2106 case 0x0:
2107 hp_flags |= MV_HP_ERRATA_50XXB0;
2108 break;
2109 case 0x3:
2110 hp_flags |= MV_HP_ERRATA_50XXB2;
2111 break;
2112 default:
2113 dev_printk(KERN_WARNING, &pdev->dev,
2114 "Applying B2 workarounds to unknown rev\n");
2115 hp_flags |= MV_HP_ERRATA_50XXB2;
2116 break;
2117 }
2118 break;
2119
2120 case chip_604x:
2121 case chip_608x:
2122 hpriv->ops = &mv6xxx_ops;
2123
2124 switch (rev_id) {
2125 case 0x7:
2126 hp_flags |= MV_HP_ERRATA_60X1B2;
2127 break;
2128 case 0x9:
2129 hp_flags |= MV_HP_ERRATA_60X1C0;
2130 break;
2131 default:
2132 dev_printk(KERN_WARNING, &pdev->dev,
2133 "Applying B2 workarounds to unknown rev\n");
2134 hp_flags |= MV_HP_ERRATA_60X1B2;
2135 break;
2136 }
2137 break;
2138
2139 case chip_7042:
2140 case chip_6042:
2141 hpriv->ops = &mv6xxx_ops;
2142
2143 hp_flags |= MV_HP_GEN_IIE;
2144
2145 switch (rev_id) {
2146 case 0x0:
2147 hp_flags |= MV_HP_ERRATA_XX42A0;
2148 break;
2149 case 0x1:
2150 hp_flags |= MV_HP_ERRATA_60X1C0;
2151 break;
2152 default:
2153 dev_printk(KERN_WARNING, &pdev->dev,
2154 "Applying 60X1C0 workarounds to unknown rev\n");
2155 hp_flags |= MV_HP_ERRATA_60X1C0;
2156 break;
2157 }
2158 break;
2159
2160 default:
2161 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2162 return 1;
2163 }
2164
2165 hpriv->hp_flags = hp_flags;
2166
2167 return 0;
2168 }
2169
2170 /**
2171 * mv_init_host - Perform some early initialization of the host.
2172 * @pdev: host PCI device
2173 * @probe_ent: early data struct representing the host
2174 *
2175 * If possible, do an early global reset of the host. Then do
2176 * our port init and clear/unmask all/relevant host interrupts.
2177 *
2178 * LOCKING:
2179 * Inherited from caller.
2180 */
2181 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2182 unsigned int board_idx)
2183 {
2184 int rc = 0, n_hc, port, hc;
2185 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
2186 struct mv_host_priv *hpriv = probe_ent->private_data;
2187
2188 /* global interrupt mask */
2189 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2190
2191 rc = mv_chip_id(pdev, hpriv, board_idx);
2192 if (rc)
2193 goto done;
2194
2195 n_hc = mv_get_hc_count(probe_ent->port_flags);
2196 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2197
2198 for (port = 0; port < probe_ent->n_ports; port++)
2199 hpriv->ops->read_preamp(hpriv, port, mmio);
2200
2201 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2202 if (rc)
2203 goto done;
2204
2205 hpriv->ops->reset_flash(hpriv, mmio);
2206 hpriv->ops->reset_bus(pdev, mmio);
2207 hpriv->ops->enable_leds(hpriv, mmio);
2208
2209 for (port = 0; port < probe_ent->n_ports; port++) {
2210 if (IS_60XX(hpriv)) {
2211 void __iomem *port_mmio = mv_port_base(mmio, port);
2212
2213 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2214 ifctl |= (1 << 7); /* enable gen2i speed */
2215 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2216 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2217 }
2218
2219 hpriv->ops->phy_errata(hpriv, mmio, port);
2220 }
2221
2222 for (port = 0; port < probe_ent->n_ports; port++) {
2223 void __iomem *port_mmio = mv_port_base(mmio, port);
2224 mv_port_init(&probe_ent->port[port], port_mmio);
2225 }
2226
2227 for (hc = 0; hc < n_hc; hc++) {
2228 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2229
2230 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2231 "(before clear)=0x%08x\n", hc,
2232 readl(hc_mmio + HC_CFG_OFS),
2233 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2234
2235 /* Clear any currently outstanding hc interrupt conditions */
2236 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2237 }
2238
2239 /* Clear any currently outstanding host interrupt conditions */
2240 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2241
2242 /* and unmask interrupt generation for host regs */
2243 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2244 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2245
2246 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2247 "PCI int cause/mask=0x%08x/0x%08x\n",
2248 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2249 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2250 readl(mmio + PCI_IRQ_CAUSE_OFS),
2251 readl(mmio + PCI_IRQ_MASK_OFS));
2252
2253 done:
2254 return rc;
2255 }
2256
2257 /**
2258 * mv_print_info - Dump key info to kernel log for perusal.
2259 * @probe_ent: early data struct representing the host
2260 *
2261 * FIXME: complete this.
2262 *
2263 * LOCKING:
2264 * Inherited from caller.
2265 */
2266 static void mv_print_info(struct ata_probe_ent *probe_ent)
2267 {
2268 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2269 struct mv_host_priv *hpriv = probe_ent->private_data;
2270 u8 rev_id, scc;
2271 const char *scc_s;
2272
2273 /* Use this to determine the HW stepping of the chip so we know
2274 * what errata to workaround
2275 */
2276 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2277
2278 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2279 if (scc == 0)
2280 scc_s = "SCSI";
2281 else if (scc == 0x01)
2282 scc_s = "RAID";
2283 else
2284 scc_s = "unknown";
2285
2286 dev_printk(KERN_INFO, &pdev->dev,
2287 "%u slots %u ports %s mode IRQ via %s\n",
2288 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2289 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2290 }
2291
2292 /**
2293 * mv_init_one - handle a positive probe of a Marvell host
2294 * @pdev: PCI device found
2295 * @ent: PCI device ID entry for the matched host
2296 *
2297 * LOCKING:
2298 * Inherited from caller.
2299 */
2300 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2301 {
2302 static int printed_version = 0;
2303 struct device *dev = &pdev->dev;
2304 struct ata_probe_ent *probe_ent;
2305 struct mv_host_priv *hpriv;
2306 unsigned int board_idx = (unsigned int)ent->driver_data;
2307 int rc;
2308
2309 if (!printed_version++)
2310 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2311
2312 rc = pcim_enable_device(pdev);
2313 if (rc)
2314 return rc;
2315 pci_set_master(pdev);
2316
2317 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2318 if (rc == -EBUSY)
2319 pcim_pin_device(pdev);
2320 if (rc)
2321 return rc;
2322
2323 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2324 if (probe_ent == NULL)
2325 return -ENOMEM;
2326
2327 probe_ent->dev = pci_dev_to_dev(pdev);
2328 INIT_LIST_HEAD(&probe_ent->node);
2329
2330 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2331 if (!hpriv)
2332 return -ENOMEM;
2333
2334 probe_ent->sht = mv_port_info[board_idx].sht;
2335 probe_ent->port_flags = mv_port_info[board_idx].flags;
2336 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2337 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2338 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2339
2340 probe_ent->irq = pdev->irq;
2341 probe_ent->irq_flags = IRQF_SHARED;
2342 probe_ent->iomap = pcim_iomap_table(pdev);
2343 probe_ent->private_data = hpriv;
2344
2345 /* initialize adapter */
2346 rc = mv_init_host(pdev, probe_ent, board_idx);
2347 if (rc)
2348 return rc;
2349
2350 /* Enable interrupts */
2351 if (msi && !pci_enable_msi(pdev))
2352 pci_intx(pdev, 1);
2353
2354 mv_dump_pci_cfg(pdev, 0x68);
2355 mv_print_info(probe_ent);
2356
2357 if (ata_device_add(probe_ent) == 0)
2358 return -ENODEV;
2359
2360 devm_kfree(dev, probe_ent);
2361 return 0;
2362 }
2363
2364 static int __init mv_init(void)
2365 {
2366 return pci_register_driver(&mv_pci_driver);
2367 }
2368
2369 static void __exit mv_exit(void)
2370 {
2371 pci_unregister_driver(&mv_pci_driver);
2372 }
2373
2374 MODULE_AUTHOR("Brett Russ");
2375 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2376 MODULE_LICENSE("GPL");
2377 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2378 MODULE_VERSION(DRV_VERSION);
2379
2380 module_param(msi, int, 0444);
2381 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2382
2383 module_init(mv_init);
2384 module_exit(mv_exit);
Linux kernel - Deliverables
This page took 0.091498 seconds and 6 git commands to generate.