2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <scsi/scsi_host.h>
69 #include <scsi/scsi_cmnd.h>
70 #include <scsi/scsi_device.h>
71 #include <linux/libata.h>
73 #define DRV_NAME "sata_mv"
74 #define DRV_VERSION "1.20"
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR
= 0, /* offset 0x10: memory space */
79 MV_IO_BAR
= 2, /* offset 0x18: IO space */
80 MV_MISC_BAR
= 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82 MV_MAJOR_REG_AREA_SZ
= 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ
= 0x2000, /* 8KB */
86 MV_IRQ_COAL_REG_BASE
= 0x18000, /* 6xxx part only */
87 MV_IRQ_COAL_CAUSE
= (MV_IRQ_COAL_REG_BASE
+ 0x08),
88 MV_IRQ_COAL_CAUSE_LO
= (MV_IRQ_COAL_REG_BASE
+ 0x88),
89 MV_IRQ_COAL_CAUSE_HI
= (MV_IRQ_COAL_REG_BASE
+ 0x8c),
90 MV_IRQ_COAL_THRESHOLD
= (MV_IRQ_COAL_REG_BASE
+ 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD
= (MV_IRQ_COAL_REG_BASE
+ 0xd0),
93 MV_SATAHC0_REG_BASE
= 0x20000,
94 MV_FLASH_CTL
= 0x1046c,
95 MV_GPIO_PORT_CTL
= 0x104f0,
96 MV_RESET_CFG
= 0x180d8,
98 MV_PCI_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
99 MV_SATAHC_REG_SZ
= MV_MAJOR_REG_AREA_SZ
,
100 MV_SATAHC_ARBTR_REG_SZ
= MV_MINOR_REG_AREA_SZ
, /* arbiter */
101 MV_PORT_REG_SZ
= MV_MINOR_REG_AREA_SZ
,
104 MV_MAX_Q_DEPTH_MASK
= MV_MAX_Q_DEPTH
- 1,
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 MV_CRQB_Q_SZ
= (32 * MV_MAX_Q_DEPTH
),
111 MV_CRPB_Q_SZ
= (8 * MV_MAX_Q_DEPTH
),
113 MV_SG_TBL_SZ
= (16 * MV_MAX_SG_CT
),
115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
116 MV_PORT_HC_SHIFT
= 2,
117 MV_PORTS_PER_HC
= (1 << MV_PORT_HC_SHIFT
), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK
= (MV_PORTS_PER_HC
- 1), /* 3 */
122 MV_FLAG_DUAL_HC
= (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE
= (1 << 29), /* IRQ coalescing capability */
124 /* SoC integrated controllers, no PCI interface */
125 MV_FLAG_SOC
= (1 << 28),
127 MV_COMMON_FLAGS
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
128 ATA_FLAG_MMIO
| ATA_FLAG_NO_ATAPI
|
129 ATA_FLAG_PIO_POLLING
,
130 MV_6XXX_FLAGS
= MV_FLAG_IRQ_COALESCE
,
132 CRQB_FLAG_READ
= (1 << 0),
134 CRQB_IOID_SHIFT
= 6, /* CRQB Gen-II/IIE IO Id shift */
135 CRQB_PMP_SHIFT
= 12, /* CRQB Gen-II/IIE PMP shift */
136 CRQB_HOSTQ_SHIFT
= 17, /* CRQB Gen-II/IIE HostQueTag shift */
137 CRQB_CMD_ADDR_SHIFT
= 8,
138 CRQB_CMD_CS
= (0x2 << 11),
139 CRQB_CMD_LAST
= (1 << 15),
141 CRPB_FLAG_STATUS_SHIFT
= 8,
142 CRPB_IOID_SHIFT_6
= 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7
= 7, /* CRPB Gen-IIE IO Id shift */
145 EPRD_FLAG_END_OF_TBL
= (1 << 31),
147 /* PCI interface registers */
149 PCI_COMMAND_OFS
= 0xc00,
151 PCI_MAIN_CMD_STS_OFS
= 0xd30,
152 STOP_PCI_MASTER
= (1 << 2),
153 PCI_MASTER_EMPTY
= (1 << 3),
154 GLOB_SFT_RST
= (1 << 4),
157 MV_PCI_EXP_ROM_BAR_CTL
= 0xd2c,
158 MV_PCI_DISC_TIMER
= 0xd04,
159 MV_PCI_MSI_TRIGGER
= 0xc38,
160 MV_PCI_SERR_MASK
= 0xc28,
161 MV_PCI_XBAR_TMOUT
= 0x1d04,
162 MV_PCI_ERR_LOW_ADDRESS
= 0x1d40,
163 MV_PCI_ERR_HIGH_ADDRESS
= 0x1d44,
164 MV_PCI_ERR_ATTRIBUTE
= 0x1d48,
165 MV_PCI_ERR_COMMAND
= 0x1d50,
167 PCI_IRQ_CAUSE_OFS
= 0x1d58,
168 PCI_IRQ_MASK_OFS
= 0x1d5c,
169 PCI_UNMASK_ALL_IRQS
= 0x7fffff, /* bits 22-0 */
171 PCIE_IRQ_CAUSE_OFS
= 0x1900,
172 PCIE_IRQ_MASK_OFS
= 0x1910,
173 PCIE_UNMASK_ALL_IRQS
= 0x40a, /* assorted bits */
175 HC_MAIN_IRQ_CAUSE_OFS
= 0x1d60,
176 HC_MAIN_IRQ_MASK_OFS
= 0x1d64,
177 HC_SOC_MAIN_IRQ_CAUSE_OFS
= 0x20020,
178 HC_SOC_MAIN_IRQ_MASK_OFS
= 0x20024,
179 ERR_IRQ
= (1 << 0), /* shift by port # */
180 DONE_IRQ
= (1 << 1), /* shift by port # */
181 HC0_IRQ_PEND
= 0x1ff, /* bits 0-8 = HC0's ports */
182 HC_SHIFT
= 9, /* bits 9-17 = HC1's ports */
184 TRAN_LO_DONE
= (1 << 19), /* 6xxx: IRQ coalescing */
185 TRAN_HI_DONE
= (1 << 20), /* 6xxx: IRQ coalescing */
186 PORTS_0_3_COAL_DONE
= (1 << 8),
187 PORTS_4_7_COAL_DONE
= (1 << 17),
188 PORTS_0_7_COAL_DONE
= (1 << 21), /* 6xxx: IRQ coalescing */
189 GPIO_INT
= (1 << 22),
190 SELF_INT
= (1 << 23),
191 TWSI_INT
= (1 << 24),
192 HC_MAIN_RSVD
= (0x7f << 25), /* bits 31-25 */
193 HC_MAIN_RSVD_5
= (0x1fff << 19), /* bits 31-19 */
194 HC_MAIN_RSVD_SOC
= (0x3fffffb << 6), /* bits 31-9, 7-6 */
195 HC_MAIN_MASKED_IRQS
= (TRAN_LO_DONE
| TRAN_HI_DONE
|
196 PORTS_0_3_COAL_DONE
| PORTS_4_7_COAL_DONE
|
197 PORTS_0_7_COAL_DONE
| GPIO_INT
| TWSI_INT
|
199 HC_MAIN_MASKED_IRQS_5
= (PORTS_0_3_COAL_DONE
| PORTS_4_7_COAL_DONE
|
201 HC_MAIN_MASKED_IRQS_SOC
= (PORTS_0_3_COAL_DONE
| HC_MAIN_RSVD_SOC
),
203 /* SATAHC registers */
206 HC_IRQ_CAUSE_OFS
= 0x14,
207 DMA_IRQ
= (1 << 0), /* shift by port # */
208 HC_COAL_IRQ
= (1 << 4), /* IRQ coalescing */
209 DEV_IRQ
= (1 << 8), /* shift by port # */
211 /* Shadow block registers */
213 SHD_CTL_AST_OFS
= 0x20, /* ofs from SHD_BLK_OFS */
216 SATA_STATUS_OFS
= 0x300, /* ctrl, err regs follow status */
217 SATA_ACTIVE_OFS
= 0x350,
218 SATA_FIS_IRQ_CAUSE_OFS
= 0x364,
221 LTMODE_BIT8
= (1 << 8), /* unknown, but necessary */
226 SATA_IFCTL_OFS
= 0x344,
227 SATA_IFSTAT_OFS
= 0x34c,
228 VENDOR_UNIQUE_FIS_OFS
= 0x35c,
231 FIS_CFG_SINGLE_SYNC
= (1 << 16), /* SYNC on DMA activation */
236 SATA_INTERFACE_CFG
= 0x050,
238 MV_M2_PREAMP_MASK
= 0x7e0,
242 EDMA_CFG_Q_DEPTH
= 0x1f, /* max device queue depth */
243 EDMA_CFG_NCQ
= (1 << 5), /* for R/W FPDMA queued */
244 EDMA_CFG_NCQ_GO_ON_ERR
= (1 << 14), /* continue on error */
245 EDMA_CFG_RD_BRST_EXT
= (1 << 11), /* read burst 512B */
246 EDMA_CFG_WR_BUFF_LEN
= (1 << 13), /* write buffer 512B */
247 EDMA_CFG_EDMA_FBS
= (1 << 16), /* EDMA FIS-Based Switching */
248 EDMA_CFG_FBS
= (1 << 26), /* FIS-Based Switching */
250 EDMA_ERR_IRQ_CAUSE_OFS
= 0x8,
251 EDMA_ERR_IRQ_MASK_OFS
= 0xc,
252 EDMA_ERR_D_PAR
= (1 << 0), /* UDMA data parity err */
253 EDMA_ERR_PRD_PAR
= (1 << 1), /* UDMA PRD parity err */
254 EDMA_ERR_DEV
= (1 << 2), /* device error */
255 EDMA_ERR_DEV_DCON
= (1 << 3), /* device disconnect */
256 EDMA_ERR_DEV_CON
= (1 << 4), /* device connected */
257 EDMA_ERR_SERR
= (1 << 5), /* SError bits [WBDST] raised */
258 EDMA_ERR_SELF_DIS
= (1 << 7), /* Gen II/IIE self-disable */
259 EDMA_ERR_SELF_DIS_5
= (1 << 8), /* Gen I self-disable */
260 EDMA_ERR_BIST_ASYNC
= (1 << 8), /* BIST FIS or Async Notify */
261 EDMA_ERR_TRANS_IRQ_7
= (1 << 8), /* Gen IIE transprt layer irq */
262 EDMA_ERR_CRQB_PAR
= (1 << 9), /* CRQB parity error */
263 EDMA_ERR_CRPB_PAR
= (1 << 10), /* CRPB parity error */
264 EDMA_ERR_INTRL_PAR
= (1 << 11), /* internal parity error */
265 EDMA_ERR_IORDY
= (1 << 12), /* IORdy timeout */
267 EDMA_ERR_LNK_CTRL_RX
= (0xf << 13), /* link ctrl rx error */
268 EDMA_ERR_LNK_CTRL_RX_0
= (1 << 13), /* transient: CRC err */
269 EDMA_ERR_LNK_CTRL_RX_1
= (1 << 14), /* transient: FIFO err */
270 EDMA_ERR_LNK_CTRL_RX_2
= (1 << 15), /* fatal: caught SYNC */
271 EDMA_ERR_LNK_CTRL_RX_3
= (1 << 16), /* transient: FIS rx err */
273 EDMA_ERR_LNK_DATA_RX
= (0xf << 17), /* link data rx error */
275 EDMA_ERR_LNK_CTRL_TX
= (0x1f << 21), /* link ctrl tx error */
276 EDMA_ERR_LNK_CTRL_TX_0
= (1 << 21), /* transient: CRC err */
277 EDMA_ERR_LNK_CTRL_TX_1
= (1 << 22), /* transient: FIFO err */
278 EDMA_ERR_LNK_CTRL_TX_2
= (1 << 23), /* transient: caught SYNC */
279 EDMA_ERR_LNK_CTRL_TX_3
= (1 << 24), /* transient: caught DMAT */
280 EDMA_ERR_LNK_CTRL_TX_4
= (1 << 25), /* transient: FIS collision */
282 EDMA_ERR_LNK_DATA_TX
= (0x1f << 26), /* link data tx error */
284 EDMA_ERR_TRANS_PROTO
= (1 << 31), /* transport protocol error */
285 EDMA_ERR_OVERRUN_5
= (1 << 5),
286 EDMA_ERR_UNDERRUN_5
= (1 << 6),
288 EDMA_ERR_IRQ_TRANSIENT
= EDMA_ERR_LNK_CTRL_RX_0
|
289 EDMA_ERR_LNK_CTRL_RX_1
|
290 EDMA_ERR_LNK_CTRL_RX_3
|
291 EDMA_ERR_LNK_CTRL_TX
,
293 EDMA_EH_FREEZE
= EDMA_ERR_D_PAR
|
303 EDMA_ERR_LNK_CTRL_RX_2
|
304 EDMA_ERR_LNK_DATA_RX
|
305 EDMA_ERR_LNK_DATA_TX
|
306 EDMA_ERR_TRANS_PROTO
,
308 EDMA_EH_FREEZE_5
= EDMA_ERR_D_PAR
|
313 EDMA_ERR_UNDERRUN_5
|
314 EDMA_ERR_SELF_DIS_5
|
320 EDMA_REQ_Q_BASE_HI_OFS
= 0x10,
321 EDMA_REQ_Q_IN_PTR_OFS
= 0x14, /* also contains BASE_LO */
323 EDMA_REQ_Q_OUT_PTR_OFS
= 0x18,
324 EDMA_REQ_Q_PTR_SHIFT
= 5,
326 EDMA_RSP_Q_BASE_HI_OFS
= 0x1c,
327 EDMA_RSP_Q_IN_PTR_OFS
= 0x20,
328 EDMA_RSP_Q_OUT_PTR_OFS
= 0x24, /* also contains BASE_LO */
329 EDMA_RSP_Q_PTR_SHIFT
= 3,
331 EDMA_CMD_OFS
= 0x28, /* EDMA command register */
332 EDMA_EN
= (1 << 0), /* enable EDMA */
333 EDMA_DS
= (1 << 1), /* disable EDMA; self-negated */
334 ATA_RST
= (1 << 2), /* reset trans/link/phy */
336 EDMA_IORDY_TMOUT
= 0x34,
339 GEN_II_NCQ_MAX_SECTORS
= 256, /* max sects/io on Gen2 w/NCQ */
341 /* Host private flags (hp_flags) */
342 MV_HP_FLAG_MSI
= (1 << 0),
343 MV_HP_ERRATA_50XXB0
= (1 << 1),
344 MV_HP_ERRATA_50XXB2
= (1 << 2),
345 MV_HP_ERRATA_60X1B2
= (1 << 3),
346 MV_HP_ERRATA_60X1C0
= (1 << 4),
347 MV_HP_ERRATA_XX42A0
= (1 << 5),
348 MV_HP_GEN_I
= (1 << 6), /* Generation I: 50xx */
349 MV_HP_GEN_II
= (1 << 7), /* Generation II: 60xx */
350 MV_HP_GEN_IIE
= (1 << 8), /* Generation IIE: 6042/7042 */
351 MV_HP_PCIE
= (1 << 9), /* PCIe bus/regs: 7042 */
353 /* Port private flags (pp_flags) */
354 MV_PP_FLAG_EDMA_EN
= (1 << 0), /* is EDMA engine enabled? */
355 MV_PP_FLAG_NCQ_EN
= (1 << 1), /* is EDMA set up for NCQ? */
358 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
359 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
360 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
361 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
363 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
364 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
367 /* DMA boundary 0xffff is required by the s/g splitting
368 * we need on /length/ in mv_fill-sg().
370 MV_DMA_BOUNDARY
= 0xffffU
,
372 /* mask of register bits containing lower 32 bits
373 * of EDMA request queue DMA address
375 EDMA_REQ_Q_BASE_LO_MASK
= 0xfffffc00U
,
377 /* ditto, for response queue */
378 EDMA_RSP_Q_BASE_LO_MASK
= 0xffffff00U
,
392 /* Command ReQuest Block: 32B */
408 /* Command ResPonse Block: 8B */
415 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
423 struct mv_port_priv
{
424 struct mv_crqb
*crqb
;
426 struct mv_crpb
*crpb
;
428 struct mv_sg
*sg_tbl
[MV_MAX_Q_DEPTH
];
429 dma_addr_t sg_tbl_dma
[MV_MAX_Q_DEPTH
];
431 unsigned int req_idx
;
432 unsigned int resp_idx
;
437 struct mv_port_signal
{
442 struct mv_host_priv
{
444 struct mv_port_signal signal
[8];
445 const struct mv_hw_ops
*ops
;
448 void __iomem
*main_cause_reg_addr
;
449 void __iomem
*main_mask_reg_addr
;
454 * These consistent DMA memory pools give us guaranteed
455 * alignment for hardware-accessed data structures,
456 * and less memory waste in accomplishing the alignment.
458 struct dma_pool
*crqb_pool
;
459 struct dma_pool
*crpb_pool
;
460 struct dma_pool
*sg_tbl_pool
;
464 void (*phy_errata
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
466 void (*enable_leds
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
467 void (*read_preamp
)(struct mv_host_priv
*hpriv
, int idx
,
469 int (*reset_hc
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
471 void (*reset_flash
)(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
472 void (*reset_bus
)(struct ata_host
*host
, void __iomem
*mmio
);
475 static int mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
);
476 static int mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
477 static int mv5_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
);
478 static int mv5_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
);
479 static int mv_port_start(struct ata_port
*ap
);
480 static void mv_port_stop(struct ata_port
*ap
);
481 static void mv_qc_prep(struct ata_queued_cmd
*qc
);
482 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
);
483 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
);
484 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
485 unsigned long deadline
);
486 static void mv_eh_freeze(struct ata_port
*ap
);
487 static void mv_eh_thaw(struct ata_port
*ap
);
488 static void mv6_dev_config(struct ata_device
*dev
);
490 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
492 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
493 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
495 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
497 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
498 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
500 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
502 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
503 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
505 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
507 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
);
508 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
510 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
512 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
513 void __iomem
*mmio
, unsigned int n_hc
);
514 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
516 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
);
517 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
);
518 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
519 unsigned int port_no
);
520 static int mv_stop_edma(struct ata_port
*ap
);
521 static int mv_stop_edma_engine(void __iomem
*port_mmio
);
522 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
);
524 static void mv_pmp_select(struct ata_port
*ap
, int pmp
);
525 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
526 unsigned long deadline
);
527 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
528 unsigned long deadline
);
530 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
531 * because we have to allow room for worst case splitting of
532 * PRDs for 64K boundaries in mv_fill_sg().
534 static struct scsi_host_template mv5_sht
= {
535 ATA_BASE_SHT(DRV_NAME
),
536 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
537 .dma_boundary
= MV_DMA_BOUNDARY
,
540 static struct scsi_host_template mv6_sht
= {
541 ATA_NCQ_SHT(DRV_NAME
),
542 .can_queue
= MV_MAX_Q_DEPTH
- 1,
543 .sg_tablesize
= MV_MAX_SG_CT
/ 2,
544 .dma_boundary
= MV_DMA_BOUNDARY
,
547 static struct ata_port_operations mv5_ops
= {
548 .inherits
= &ata_sff_port_ops
,
550 .qc_prep
= mv_qc_prep
,
551 .qc_issue
= mv_qc_issue
,
553 .freeze
= mv_eh_freeze
,
555 .hardreset
= mv_hardreset
,
556 .error_handler
= ata_std_error_handler
, /* avoid SFF EH */
557 .post_internal_cmd
= ATA_OP_NULL
,
559 .scr_read
= mv5_scr_read
,
560 .scr_write
= mv5_scr_write
,
562 .port_start
= mv_port_start
,
563 .port_stop
= mv_port_stop
,
566 static struct ata_port_operations mv6_ops
= {
567 .inherits
= &mv5_ops
,
568 .qc_defer
= sata_pmp_qc_defer_cmd_switch
,
569 .dev_config
= mv6_dev_config
,
570 .scr_read
= mv_scr_read
,
571 .scr_write
= mv_scr_write
,
573 .pmp_hardreset
= mv_pmp_hardreset
,
574 .pmp_softreset
= mv_softreset
,
575 .softreset
= mv_softreset
,
576 .error_handler
= sata_pmp_error_handler
,
579 static struct ata_port_operations mv_iie_ops
= {
580 .inherits
= &mv6_ops
,
581 .qc_defer
= ata_std_qc_defer
, /* FIS-based switching */
582 .dev_config
= ATA_OP_NULL
,
583 .qc_prep
= mv_qc_prep_iie
,
586 static const struct ata_port_info mv_port_info
[] = {
588 .flags
= MV_COMMON_FLAGS
,
589 .pio_mask
= 0x1f, /* pio0-4 */
590 .udma_mask
= ATA_UDMA6
,
591 .port_ops
= &mv5_ops
,
594 .flags
= MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
,
595 .pio_mask
= 0x1f, /* pio0-4 */
596 .udma_mask
= ATA_UDMA6
,
597 .port_ops
= &mv5_ops
,
600 .flags
= MV_COMMON_FLAGS
| MV_FLAG_DUAL_HC
,
601 .pio_mask
= 0x1f, /* pio0-4 */
602 .udma_mask
= ATA_UDMA6
,
603 .port_ops
= &mv5_ops
,
606 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
607 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
609 .pio_mask
= 0x1f, /* pio0-4 */
610 .udma_mask
= ATA_UDMA6
,
611 .port_ops
= &mv6_ops
,
614 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
615 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
616 ATA_FLAG_NCQ
| MV_FLAG_DUAL_HC
,
617 .pio_mask
= 0x1f, /* pio0-4 */
618 .udma_mask
= ATA_UDMA6
,
619 .port_ops
= &mv6_ops
,
622 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
623 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
625 .pio_mask
= 0x1f, /* pio0-4 */
626 .udma_mask
= ATA_UDMA6
,
627 .port_ops
= &mv_iie_ops
,
630 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
631 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
633 .pio_mask
= 0x1f, /* pio0-4 */
634 .udma_mask
= ATA_UDMA6
,
635 .port_ops
= &mv_iie_ops
,
638 .flags
= MV_COMMON_FLAGS
| MV_6XXX_FLAGS
|
639 ATA_FLAG_PMP
| ATA_FLAG_ACPI_SATA
|
640 ATA_FLAG_NCQ
| MV_FLAG_SOC
,
641 .pio_mask
= 0x1f, /* pio0-4 */
642 .udma_mask
= ATA_UDMA6
,
643 .port_ops
= &mv_iie_ops
,
647 static const struct pci_device_id mv_pci_tbl
[] = {
648 { PCI_VDEVICE(MARVELL
, 0x5040), chip_504x
},
649 { PCI_VDEVICE(MARVELL
, 0x5041), chip_504x
},
650 { PCI_VDEVICE(MARVELL
, 0x5080), chip_5080
},
651 { PCI_VDEVICE(MARVELL
, 0x5081), chip_508x
},
652 /* RocketRAID 1740/174x have different identifiers */
653 { PCI_VDEVICE(TTI
, 0x1740), chip_508x
},
654 { PCI_VDEVICE(TTI
, 0x1742), chip_508x
},
656 { PCI_VDEVICE(MARVELL
, 0x6040), chip_604x
},
657 { PCI_VDEVICE(MARVELL
, 0x6041), chip_604x
},
658 { PCI_VDEVICE(MARVELL
, 0x6042), chip_6042
},
659 { PCI_VDEVICE(MARVELL
, 0x6080), chip_608x
},
660 { PCI_VDEVICE(MARVELL
, 0x6081), chip_608x
},
662 { PCI_VDEVICE(ADAPTEC2
, 0x0241), chip_604x
},
665 { PCI_VDEVICE(ADAPTEC2
, 0x0243), chip_7042
},
667 /* Marvell 7042 support */
668 { PCI_VDEVICE(MARVELL
, 0x7042), chip_7042
},
670 /* Highpoint RocketRAID PCIe series */
671 { PCI_VDEVICE(TTI
, 0x2300), chip_7042
},
672 { PCI_VDEVICE(TTI
, 0x2310), chip_7042
},
674 { } /* terminate list */
677 static const struct mv_hw_ops mv5xxx_ops
= {
678 .phy_errata
= mv5_phy_errata
,
679 .enable_leds
= mv5_enable_leds
,
680 .read_preamp
= mv5_read_preamp
,
681 .reset_hc
= mv5_reset_hc
,
682 .reset_flash
= mv5_reset_flash
,
683 .reset_bus
= mv5_reset_bus
,
686 static const struct mv_hw_ops mv6xxx_ops
= {
687 .phy_errata
= mv6_phy_errata
,
688 .enable_leds
= mv6_enable_leds
,
689 .read_preamp
= mv6_read_preamp
,
690 .reset_hc
= mv6_reset_hc
,
691 .reset_flash
= mv6_reset_flash
,
692 .reset_bus
= mv_reset_pci_bus
,
695 static const struct mv_hw_ops mv_soc_ops
= {
696 .phy_errata
= mv6_phy_errata
,
697 .enable_leds
= mv_soc_enable_leds
,
698 .read_preamp
= mv_soc_read_preamp
,
699 .reset_hc
= mv_soc_reset_hc
,
700 .reset_flash
= mv_soc_reset_flash
,
701 .reset_bus
= mv_soc_reset_bus
,
708 static inline void writelfl(unsigned long data
, void __iomem
*addr
)
711 (void) readl(addr
); /* flush to avoid PCI posted write */
714 static inline unsigned int mv_hc_from_port(unsigned int port
)
716 return port
>> MV_PORT_HC_SHIFT
;
719 static inline unsigned int mv_hardport_from_port(unsigned int port
)
721 return port
& MV_PORT_MASK
;
725 * Consolidate some rather tricky bit shift calculations.
726 * This is hot-path stuff, so not a function.
727 * Simple code, with two return values, so macro rather than inline.
729 * port is the sole input, in range 0..7.
730 * shift is one output, for use with the main_cause and main_mask registers.
731 * hardport is the other output, in range 0..3
733 * Note that port and hardport may be the same variable in some cases.
735 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
737 shift = mv_hc_from_port(port) * HC_SHIFT; \
738 hardport = mv_hardport_from_port(port); \
739 shift += hardport * 2; \
742 static inline void __iomem
*mv_hc_base(void __iomem
*base
, unsigned int hc
)
744 return (base
+ MV_SATAHC0_REG_BASE
+ (hc
* MV_SATAHC_REG_SZ
));
747 static inline void __iomem
*mv_hc_base_from_port(void __iomem
*base
,
750 return mv_hc_base(base
, mv_hc_from_port(port
));
753 static inline void __iomem
*mv_port_base(void __iomem
*base
, unsigned int port
)
755 return mv_hc_base_from_port(base
, port
) +
756 MV_SATAHC_ARBTR_REG_SZ
+
757 (mv_hardport_from_port(port
) * MV_PORT_REG_SZ
);
760 static void __iomem
*mv5_phy_base(void __iomem
*mmio
, unsigned int port
)
762 void __iomem
*hc_mmio
= mv_hc_base_from_port(mmio
, port
);
763 unsigned long ofs
= (mv_hardport_from_port(port
) + 1) * 0x100UL
;
765 return hc_mmio
+ ofs
;
768 static inline void __iomem
*mv_host_base(struct ata_host
*host
)
770 struct mv_host_priv
*hpriv
= host
->private_data
;
774 static inline void __iomem
*mv_ap_base(struct ata_port
*ap
)
776 return mv_port_base(mv_host_base(ap
->host
), ap
->port_no
);
779 static inline int mv_get_hc_count(unsigned long port_flags
)
781 return ((port_flags
& MV_FLAG_DUAL_HC
) ? 2 : 1);
784 static void mv_set_edma_ptrs(void __iomem
*port_mmio
,
785 struct mv_host_priv
*hpriv
,
786 struct mv_port_priv
*pp
)
791 * initialize request queue
793 pp
->req_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
794 index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
796 WARN_ON(pp
->crqb_dma
& 0x3ff);
797 writel((pp
->crqb_dma
>> 16) >> 16, port_mmio
+ EDMA_REQ_Q_BASE_HI_OFS
);
798 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | index
,
799 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
801 if (hpriv
->hp_flags
& MV_HP_ERRATA_XX42A0
)
802 writelfl((pp
->crqb_dma
& 0xffffffff) | index
,
803 port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
);
805 writelfl(index
, port_mmio
+ EDMA_REQ_Q_OUT_PTR_OFS
);
808 * initialize response queue
810 pp
->resp_idx
&= MV_MAX_Q_DEPTH_MASK
; /* paranoia */
811 index
= pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
;
813 WARN_ON(pp
->crpb_dma
& 0xff);
814 writel((pp
->crpb_dma
>> 16) >> 16, port_mmio
+ EDMA_RSP_Q_BASE_HI_OFS
);
816 if (hpriv
->hp_flags
& MV_HP_ERRATA_XX42A0
)
817 writelfl((pp
->crpb_dma
& 0xffffffff) | index
,
818 port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
);
820 writelfl(index
, port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
);
822 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) | index
,
823 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
827 * mv_start_dma - Enable eDMA engine
828 * @base: port base address
829 * @pp: port private data
831 * Verify the local cache of the eDMA state is accurate with a
835 * Inherited from caller.
837 static void mv_start_dma(struct ata_port
*ap
, void __iomem
*port_mmio
,
838 struct mv_port_priv
*pp
, u8 protocol
)
840 int want_ncq
= (protocol
== ATA_PROT_NCQ
);
842 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) {
843 int using_ncq
= ((pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
) != 0);
844 if (want_ncq
!= using_ncq
)
847 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
)) {
848 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
849 int hardport
= mv_hardport_from_port(ap
->port_no
);
850 void __iomem
*hc_mmio
= mv_hc_base_from_port(
851 mv_host_base(ap
->host
), hardport
);
852 u32 hc_irq_cause
, ipending
;
854 /* clear EDMA event indicators, if any */
855 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
857 /* clear EDMA interrupt indicator, if any */
858 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
859 ipending
= (DEV_IRQ
| DMA_IRQ
) << hardport
;
860 if (hc_irq_cause
& ipending
) {
861 writelfl(hc_irq_cause
& ~ipending
,
862 hc_mmio
+ HC_IRQ_CAUSE_OFS
);
865 mv_edma_cfg(ap
, want_ncq
);
867 /* clear FIS IRQ Cause */
868 writelfl(0, port_mmio
+ SATA_FIS_IRQ_CAUSE_OFS
);
870 mv_set_edma_ptrs(port_mmio
, hpriv
, pp
);
872 writelfl(EDMA_EN
, port_mmio
+ EDMA_CMD_OFS
);
873 pp
->pp_flags
|= MV_PP_FLAG_EDMA_EN
;
878 * mv_stop_edma_engine - Disable eDMA engine
879 * @port_mmio: io base address
882 * Inherited from caller.
884 static int mv_stop_edma_engine(void __iomem
*port_mmio
)
888 /* Disable eDMA. The disable bit auto clears. */
889 writelfl(EDMA_DS
, port_mmio
+ EDMA_CMD_OFS
);
891 /* Wait for the chip to confirm eDMA is off. */
892 for (i
= 10000; i
> 0; i
--) {
893 u32 reg
= readl(port_mmio
+ EDMA_CMD_OFS
);
894 if (!(reg
& EDMA_EN
))
901 static int mv_stop_edma(struct ata_port
*ap
)
903 void __iomem
*port_mmio
= mv_ap_base(ap
);
904 struct mv_port_priv
*pp
= ap
->private_data
;
906 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
))
908 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
909 if (mv_stop_edma_engine(port_mmio
)) {
910 ata_port_printk(ap
, KERN_ERR
, "Unable to stop eDMA\n");
917 static void mv_dump_mem(void __iomem
*start
, unsigned bytes
)
920 for (b
= 0; b
< bytes
; ) {
921 DPRINTK("%p: ", start
+ b
);
922 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
923 printk("%08x ", readl(start
+ b
));
931 static void mv_dump_pci_cfg(struct pci_dev
*pdev
, unsigned bytes
)
936 for (b
= 0; b
< bytes
; ) {
937 DPRINTK("%02x: ", b
);
938 for (w
= 0; b
< bytes
&& w
< 4; w
++) {
939 (void) pci_read_config_dword(pdev
, b
, &dw
);
947 static void mv_dump_all_regs(void __iomem
*mmio_base
, int port
,
948 struct pci_dev
*pdev
)
951 void __iomem
*hc_base
= mv_hc_base(mmio_base
,
952 port
>> MV_PORT_HC_SHIFT
);
953 void __iomem
*port_base
;
954 int start_port
, num_ports
, p
, start_hc
, num_hcs
, hc
;
957 start_hc
= start_port
= 0;
958 num_ports
= 8; /* shld be benign for 4 port devs */
961 start_hc
= port
>> MV_PORT_HC_SHIFT
;
963 num_ports
= num_hcs
= 1;
965 DPRINTK("All registers for port(s) %u-%u:\n", start_port
,
966 num_ports
> 1 ? num_ports
- 1 : start_port
);
969 DPRINTK("PCI config space regs:\n");
970 mv_dump_pci_cfg(pdev
, 0x68);
972 DPRINTK("PCI regs:\n");
973 mv_dump_mem(mmio_base
+0xc00, 0x3c);
974 mv_dump_mem(mmio_base
+0xd00, 0x34);
975 mv_dump_mem(mmio_base
+0xf00, 0x4);
976 mv_dump_mem(mmio_base
+0x1d00, 0x6c);
977 for (hc
= start_hc
; hc
< start_hc
+ num_hcs
; hc
++) {
978 hc_base
= mv_hc_base(mmio_base
, hc
);
979 DPRINTK("HC regs (HC %i):\n", hc
);
980 mv_dump_mem(hc_base
, 0x1c);
982 for (p
= start_port
; p
< start_port
+ num_ports
; p
++) {
983 port_base
= mv_port_base(mmio_base
, p
);
984 DPRINTK("EDMA regs (port %i):\n", p
);
985 mv_dump_mem(port_base
, 0x54);
986 DPRINTK("SATA regs (port %i):\n", p
);
987 mv_dump_mem(port_base
+0x300, 0x60);
992 static unsigned int mv_scr_offset(unsigned int sc_reg_in
)
1000 ofs
= SATA_STATUS_OFS
+ (sc_reg_in
* sizeof(u32
));
1003 ofs
= SATA_ACTIVE_OFS
; /* active is not with the others */
1012 static int mv_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
)
1014 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1016 if (ofs
!= 0xffffffffU
) {
1017 *val
= readl(mv_ap_base(ap
) + ofs
);
1023 static int mv_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
1025 unsigned int ofs
= mv_scr_offset(sc_reg_in
);
1027 if (ofs
!= 0xffffffffU
) {
1028 writelfl(val
, mv_ap_base(ap
) + ofs
);
1034 static void mv6_dev_config(struct ata_device
*adev
)
1037 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1039 * Gen-II does not support NCQ over a port multiplier
1040 * (no FIS-based switching).
1042 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1043 * See mv_qc_prep() for more info.
1045 if (adev
->flags
& ATA_DFLAG_NCQ
) {
1046 if (sata_pmp_attached(adev
->link
->ap
)) {
1047 adev
->flags
&= ~ATA_DFLAG_NCQ
;
1048 ata_dev_printk(adev
, KERN_INFO
,
1049 "NCQ disabled for command-based switching\n");
1050 } else if (adev
->max_sectors
> GEN_II_NCQ_MAX_SECTORS
) {
1051 adev
->max_sectors
= GEN_II_NCQ_MAX_SECTORS
;
1052 ata_dev_printk(adev
, KERN_INFO
,
1053 "max_sectors limited to %u for NCQ\n",
1059 static void mv_config_fbs(void __iomem
*port_mmio
, int enable_fbs
)
1061 u32 old_fcfg
, new_fcfg
, old_ltmode
, new_ltmode
;
1063 * Various bit settings required for operation
1064 * in FIS-based switching (fbs) mode on GenIIe:
1066 old_fcfg
= readl(port_mmio
+ FIS_CFG_OFS
);
1067 old_ltmode
= readl(port_mmio
+ LTMODE_OFS
);
1069 new_fcfg
= old_fcfg
| FIS_CFG_SINGLE_SYNC
;
1070 new_ltmode
= old_ltmode
| LTMODE_BIT8
;
1071 } else { /* disable fbs */
1072 new_fcfg
= old_fcfg
& ~FIS_CFG_SINGLE_SYNC
;
1073 new_ltmode
= old_ltmode
& ~LTMODE_BIT8
;
1075 if (new_fcfg
!= old_fcfg
)
1076 writelfl(new_fcfg
, port_mmio
+ FIS_CFG_OFS
);
1077 if (new_ltmode
!= old_ltmode
)
1078 writelfl(new_ltmode
, port_mmio
+ LTMODE_OFS
);
1081 static void mv_edma_cfg(struct ata_port
*ap
, int want_ncq
)
1084 struct mv_port_priv
*pp
= ap
->private_data
;
1085 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1086 void __iomem
*port_mmio
= mv_ap_base(ap
);
1088 /* set up non-NCQ EDMA configuration */
1089 cfg
= EDMA_CFG_Q_DEPTH
; /* always 0x1f for *all* chips */
1091 if (IS_GEN_I(hpriv
))
1092 cfg
|= (1 << 8); /* enab config burst size mask */
1094 else if (IS_GEN_II(hpriv
))
1095 cfg
|= EDMA_CFG_RD_BRST_EXT
| EDMA_CFG_WR_BUFF_LEN
;
1097 else if (IS_GEN_IIE(hpriv
)) {
1098 cfg
|= (1 << 23); /* do not mask PM field in rx'd FIS */
1099 cfg
|= (1 << 22); /* enab 4-entry host queue cache */
1100 cfg
|= (1 << 18); /* enab early completion */
1101 cfg
|= (1 << 17); /* enab cut-through (dis stor&forwrd) */
1103 if (want_ncq
&& sata_pmp_attached(ap
)) {
1104 cfg
|= EDMA_CFG_EDMA_FBS
; /* FIS-based switching */
1105 mv_config_fbs(port_mmio
, 1);
1107 mv_config_fbs(port_mmio
, 0);
1112 cfg
|= EDMA_CFG_NCQ
;
1113 pp
->pp_flags
|= MV_PP_FLAG_NCQ_EN
;
1115 pp
->pp_flags
&= ~MV_PP_FLAG_NCQ_EN
;
1117 writelfl(cfg
, port_mmio
+ EDMA_CFG_OFS
);
1120 static void mv_port_free_dma_mem(struct ata_port
*ap
)
1122 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1123 struct mv_port_priv
*pp
= ap
->private_data
;
1127 dma_pool_free(hpriv
->crqb_pool
, pp
->crqb
, pp
->crqb_dma
);
1131 dma_pool_free(hpriv
->crpb_pool
, pp
->crpb
, pp
->crpb_dma
);
1135 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1136 * For later hardware, we have one unique sg_tbl per NCQ tag.
1138 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1139 if (pp
->sg_tbl
[tag
]) {
1140 if (tag
== 0 || !IS_GEN_I(hpriv
))
1141 dma_pool_free(hpriv
->sg_tbl_pool
,
1143 pp
->sg_tbl_dma
[tag
]);
1144 pp
->sg_tbl
[tag
] = NULL
;
1150 * mv_port_start - Port specific init/start routine.
1151 * @ap: ATA channel to manipulate
1153 * Allocate and point to DMA memory, init port private memory,
1157 * Inherited from caller.
1159 static int mv_port_start(struct ata_port
*ap
)
1161 struct device
*dev
= ap
->host
->dev
;
1162 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1163 struct mv_port_priv
*pp
;
1166 pp
= devm_kzalloc(dev
, sizeof(*pp
), GFP_KERNEL
);
1169 ap
->private_data
= pp
;
1171 pp
->crqb
= dma_pool_alloc(hpriv
->crqb_pool
, GFP_KERNEL
, &pp
->crqb_dma
);
1174 memset(pp
->crqb
, 0, MV_CRQB_Q_SZ
);
1176 pp
->crpb
= dma_pool_alloc(hpriv
->crpb_pool
, GFP_KERNEL
, &pp
->crpb_dma
);
1178 goto out_port_free_dma_mem
;
1179 memset(pp
->crpb
, 0, MV_CRPB_Q_SZ
);
1182 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1183 * For later hardware, we need one unique sg_tbl per NCQ tag.
1185 for (tag
= 0; tag
< MV_MAX_Q_DEPTH
; ++tag
) {
1186 if (tag
== 0 || !IS_GEN_I(hpriv
)) {
1187 pp
->sg_tbl
[tag
] = dma_pool_alloc(hpriv
->sg_tbl_pool
,
1188 GFP_KERNEL
, &pp
->sg_tbl_dma
[tag
]);
1189 if (!pp
->sg_tbl
[tag
])
1190 goto out_port_free_dma_mem
;
1192 pp
->sg_tbl
[tag
] = pp
->sg_tbl
[0];
1193 pp
->sg_tbl_dma
[tag
] = pp
->sg_tbl_dma
[0];
1198 out_port_free_dma_mem
:
1199 mv_port_free_dma_mem(ap
);
1204 * mv_port_stop - Port specific cleanup/stop routine.
1205 * @ap: ATA channel to manipulate
1207 * Stop DMA, cleanup port memory.
1210 * This routine uses the host lock to protect the DMA stop.
1212 static void mv_port_stop(struct ata_port
*ap
)
1215 mv_port_free_dma_mem(ap
);
1219 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1220 * @qc: queued command whose SG list to source from
1222 * Populate the SG list and mark the last entry.
1225 * Inherited from caller.
1227 static void mv_fill_sg(struct ata_queued_cmd
*qc
)
1229 struct mv_port_priv
*pp
= qc
->ap
->private_data
;
1230 struct scatterlist
*sg
;
1231 struct mv_sg
*mv_sg
, *last_sg
= NULL
;
1234 mv_sg
= pp
->sg_tbl
[qc
->tag
];
1235 for_each_sg(qc
->sg
, sg
, qc
->n_elem
, si
) {
1236 dma_addr_t addr
= sg_dma_address(sg
);
1237 u32 sg_len
= sg_dma_len(sg
);
1240 u32 offset
= addr
& 0xffff;
1243 if ((offset
+ sg_len
> 0x10000))
1244 len
= 0x10000 - offset
;
1246 mv_sg
->addr
= cpu_to_le32(addr
& 0xffffffff);
1247 mv_sg
->addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
1248 mv_sg
->flags_size
= cpu_to_le32(len
& 0xffff);
1258 if (likely(last_sg
))
1259 last_sg
->flags_size
|= cpu_to_le32(EPRD_FLAG_END_OF_TBL
);
1262 static void mv_crqb_pack_cmd(__le16
*cmdw
, u8 data
, u8 addr
, unsigned last
)
1264 u16 tmp
= data
| (addr
<< CRQB_CMD_ADDR_SHIFT
) | CRQB_CMD_CS
|
1265 (last
? CRQB_CMD_LAST
: 0);
1266 *cmdw
= cpu_to_le16(tmp
);
1270 * mv_qc_prep - Host specific command preparation.
1271 * @qc: queued command to prepare
1273 * This routine simply redirects to the general purpose routine
1274 * if command is not DMA. Else, it handles prep of the CRQB
1275 * (command request block), does some sanity checking, and calls
1276 * the SG load routine.
1279 * Inherited from caller.
1281 static void mv_qc_prep(struct ata_queued_cmd
*qc
)
1283 struct ata_port
*ap
= qc
->ap
;
1284 struct mv_port_priv
*pp
= ap
->private_data
;
1286 struct ata_taskfile
*tf
;
1290 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1291 (qc
->tf
.protocol
!= ATA_PROT_NCQ
))
1294 /* Fill in command request block
1296 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
1297 flags
|= CRQB_FLAG_READ
;
1298 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
1299 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
1300 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
1302 /* get current queue index from software */
1303 in_index
= pp
->req_idx
;
1305 pp
->crqb
[in_index
].sg_addr
=
1306 cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
1307 pp
->crqb
[in_index
].sg_addr_hi
=
1308 cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
1309 pp
->crqb
[in_index
].ctrl_flags
= cpu_to_le16(flags
);
1311 cw
= &pp
->crqb
[in_index
].ata_cmd
[0];
1314 /* Sadly, the CRQB cannot accomodate all registers--there are
1315 * only 11 bytes...so we must pick and choose required
1316 * registers based on the command. So, we drop feature and
1317 * hob_feature for [RW] DMA commands, but they are needed for
1318 * NCQ. NCQ will drop hob_nsect.
1320 switch (tf
->command
) {
1322 case ATA_CMD_READ_EXT
:
1324 case ATA_CMD_WRITE_EXT
:
1325 case ATA_CMD_WRITE_FUA_EXT
:
1326 mv_crqb_pack_cmd(cw
++, tf
->hob_nsect
, ATA_REG_NSECT
, 0);
1328 case ATA_CMD_FPDMA_READ
:
1329 case ATA_CMD_FPDMA_WRITE
:
1330 mv_crqb_pack_cmd(cw
++, tf
->hob_feature
, ATA_REG_FEATURE
, 0);
1331 mv_crqb_pack_cmd(cw
++, tf
->feature
, ATA_REG_FEATURE
, 0);
1334 /* The only other commands EDMA supports in non-queued and
1335 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1336 * of which are defined/used by Linux. If we get here, this
1337 * driver needs work.
1339 * FIXME: modify libata to give qc_prep a return value and
1340 * return error here.
1342 BUG_ON(tf
->command
);
1345 mv_crqb_pack_cmd(cw
++, tf
->nsect
, ATA_REG_NSECT
, 0);
1346 mv_crqb_pack_cmd(cw
++, tf
->hob_lbal
, ATA_REG_LBAL
, 0);
1347 mv_crqb_pack_cmd(cw
++, tf
->lbal
, ATA_REG_LBAL
, 0);
1348 mv_crqb_pack_cmd(cw
++, tf
->hob_lbam
, ATA_REG_LBAM
, 0);
1349 mv_crqb_pack_cmd(cw
++, tf
->lbam
, ATA_REG_LBAM
, 0);
1350 mv_crqb_pack_cmd(cw
++, tf
->hob_lbah
, ATA_REG_LBAH
, 0);
1351 mv_crqb_pack_cmd(cw
++, tf
->lbah
, ATA_REG_LBAH
, 0);
1352 mv_crqb_pack_cmd(cw
++, tf
->device
, ATA_REG_DEVICE
, 0);
1353 mv_crqb_pack_cmd(cw
++, tf
->command
, ATA_REG_CMD
, 1); /* last */
1355 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
1361 * mv_qc_prep_iie - Host specific command preparation.
1362 * @qc: queued command to prepare
1364 * This routine simply redirects to the general purpose routine
1365 * if command is not DMA. Else, it handles prep of the CRQB
1366 * (command request block), does some sanity checking, and calls
1367 * the SG load routine.
1370 * Inherited from caller.
1372 static void mv_qc_prep_iie(struct ata_queued_cmd
*qc
)
1374 struct ata_port
*ap
= qc
->ap
;
1375 struct mv_port_priv
*pp
= ap
->private_data
;
1376 struct mv_crqb_iie
*crqb
;
1377 struct ata_taskfile
*tf
;
1381 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1382 (qc
->tf
.protocol
!= ATA_PROT_NCQ
))
1385 /* Fill in Gen IIE command request block */
1386 if (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))
1387 flags
|= CRQB_FLAG_READ
;
1389 WARN_ON(MV_MAX_Q_DEPTH
<= qc
->tag
);
1390 flags
|= qc
->tag
<< CRQB_TAG_SHIFT
;
1391 flags
|= qc
->tag
<< CRQB_HOSTQ_SHIFT
;
1392 flags
|= (qc
->dev
->link
->pmp
& 0xf) << CRQB_PMP_SHIFT
;
1394 /* get current queue index from software */
1395 in_index
= pp
->req_idx
;
1397 crqb
= (struct mv_crqb_iie
*) &pp
->crqb
[in_index
];
1398 crqb
->addr
= cpu_to_le32(pp
->sg_tbl_dma
[qc
->tag
] & 0xffffffff);
1399 crqb
->addr_hi
= cpu_to_le32((pp
->sg_tbl_dma
[qc
->tag
] >> 16) >> 16);
1400 crqb
->flags
= cpu_to_le32(flags
);
1403 crqb
->ata_cmd
[0] = cpu_to_le32(
1404 (tf
->command
<< 16) |
1407 crqb
->ata_cmd
[1] = cpu_to_le32(
1413 crqb
->ata_cmd
[2] = cpu_to_le32(
1414 (tf
->hob_lbal
<< 0) |
1415 (tf
->hob_lbam
<< 8) |
1416 (tf
->hob_lbah
<< 16) |
1417 (tf
->hob_feature
<< 24)
1419 crqb
->ata_cmd
[3] = cpu_to_le32(
1421 (tf
->hob_nsect
<< 8)
1424 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
1430 * mv_qc_issue - Initiate a command to the host
1431 * @qc: queued command to start
1433 * This routine simply redirects to the general purpose routine
1434 * if command is not DMA. Else, it sanity checks our local
1435 * caches of the request producer/consumer indices then enables
1436 * DMA and bumps the request producer index.
1439 * Inherited from caller.
1441 static unsigned int mv_qc_issue(struct ata_queued_cmd
*qc
)
1443 struct ata_port
*ap
= qc
->ap
;
1444 void __iomem
*port_mmio
= mv_ap_base(ap
);
1445 struct mv_port_priv
*pp
= ap
->private_data
;
1448 if ((qc
->tf
.protocol
!= ATA_PROT_DMA
) &&
1449 (qc
->tf
.protocol
!= ATA_PROT_NCQ
)) {
1451 * We're about to send a non-EDMA capable command to the
1452 * port. Turn off EDMA so there won't be problems accessing
1453 * shadow block, etc registers.
1456 mv_pmp_select(ap
, qc
->dev
->link
->pmp
);
1457 return ata_sff_qc_issue(qc
);
1460 mv_start_dma(ap
, port_mmio
, pp
, qc
->tf
.protocol
);
1462 pp
->req_idx
= (pp
->req_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
1463 in_index
= pp
->req_idx
<< EDMA_REQ_Q_PTR_SHIFT
;
1465 /* and write the request in pointer to kick the EDMA to life */
1466 writelfl((pp
->crqb_dma
& EDMA_REQ_Q_BASE_LO_MASK
) | in_index
,
1467 port_mmio
+ EDMA_REQ_Q_IN_PTR_OFS
);
1472 static struct ata_queued_cmd
*mv_get_active_qc(struct ata_port
*ap
)
1474 struct mv_port_priv
*pp
= ap
->private_data
;
1475 struct ata_queued_cmd
*qc
;
1477 if (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
)
1479 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1480 if (qc
&& (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1485 static void mv_unexpected_intr(struct ata_port
*ap
)
1487 struct mv_port_priv
*pp
= ap
->private_data
;
1488 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1492 * We got a device interrupt from something that
1493 * was supposed to be using EDMA or polling.
1495 ata_ehi_clear_desc(ehi
);
1496 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
) {
1497 when
= " while EDMA enabled";
1499 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1500 if (qc
&& (qc
->tf
.flags
& ATA_TFLAG_POLLING
))
1501 when
= " while polling";
1503 ata_ehi_push_desc(ehi
, "unexpected device interrupt%s", when
);
1504 ehi
->err_mask
|= AC_ERR_OTHER
;
1505 ehi
->action
|= ATA_EH_RESET
;
1506 ata_port_freeze(ap
);
1510 * mv_err_intr - Handle error interrupts on the port
1511 * @ap: ATA channel to manipulate
1512 * @qc: affected command (non-NCQ), or NULL
1514 * Most cases require a full reset of the chip's state machine,
1515 * which also performs a COMRESET.
1516 * Also, if the port disabled DMA, update our cached copy to match.
1519 * Inherited from caller.
1521 static void mv_err_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
1523 void __iomem
*port_mmio
= mv_ap_base(ap
);
1524 u32 edma_err_cause
, eh_freeze_mask
, serr
= 0;
1525 struct mv_port_priv
*pp
= ap
->private_data
;
1526 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1527 unsigned int action
= 0, err_mask
= 0;
1528 struct ata_eh_info
*ehi
= &ap
->link
.eh_info
;
1530 ata_ehi_clear_desc(ehi
);
1533 * Read and clear the err_cause bits. This won't actually
1534 * clear for some errors (eg. SError), but we will be doing
1535 * a hard reset in those cases regardless, which *will* clear it.
1537 edma_err_cause
= readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1538 writelfl(~edma_err_cause
, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
1540 ata_ehi_push_desc(ehi
, "edma_err_cause=%08x", edma_err_cause
);
1543 * All generations share these EDMA error cause bits:
1545 if (edma_err_cause
& EDMA_ERR_DEV
)
1546 err_mask
|= AC_ERR_DEV
;
1547 if (edma_err_cause
& (EDMA_ERR_D_PAR
| EDMA_ERR_PRD_PAR
|
1548 EDMA_ERR_CRQB_PAR
| EDMA_ERR_CRPB_PAR
|
1549 EDMA_ERR_INTRL_PAR
)) {
1550 err_mask
|= AC_ERR_ATA_BUS
;
1551 action
|= ATA_EH_RESET
;
1552 ata_ehi_push_desc(ehi
, "parity error");
1554 if (edma_err_cause
& (EDMA_ERR_DEV_DCON
| EDMA_ERR_DEV_CON
)) {
1555 ata_ehi_hotplugged(ehi
);
1556 ata_ehi_push_desc(ehi
, edma_err_cause
& EDMA_ERR_DEV_DCON
?
1557 "dev disconnect" : "dev connect");
1558 action
|= ATA_EH_RESET
;
1562 * Gen-I has a different SELF_DIS bit,
1563 * different FREEZE bits, and no SERR bit:
1565 if (IS_GEN_I(hpriv
)) {
1566 eh_freeze_mask
= EDMA_EH_FREEZE_5
;
1567 if (edma_err_cause
& EDMA_ERR_SELF_DIS_5
) {
1568 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1569 ata_ehi_push_desc(ehi
, "EDMA self-disable");
1572 eh_freeze_mask
= EDMA_EH_FREEZE
;
1573 if (edma_err_cause
& EDMA_ERR_SELF_DIS
) {
1574 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
1575 ata_ehi_push_desc(ehi
, "EDMA self-disable");
1577 if (edma_err_cause
& EDMA_ERR_SERR
) {
1579 * Ensure that we read our own SCR, not a pmp link SCR:
1581 ap
->ops
->scr_read(ap
, SCR_ERROR
, &serr
);
1583 * Don't clear SError here; leave it for libata-eh:
1585 ata_ehi_push_desc(ehi
, "SError=%08x", serr
);
1586 err_mask
|= AC_ERR_ATA_BUS
;
1587 action
|= ATA_EH_RESET
;
1592 err_mask
= AC_ERR_OTHER
;
1593 action
|= ATA_EH_RESET
;
1596 ehi
->serror
|= serr
;
1597 ehi
->action
|= action
;
1600 qc
->err_mask
|= err_mask
;
1602 ehi
->err_mask
|= err_mask
;
1604 if (edma_err_cause
& eh_freeze_mask
)
1605 ata_port_freeze(ap
);
1610 static void mv_process_crpb_response(struct ata_port
*ap
,
1611 struct mv_crpb
*response
, unsigned int tag
, int ncq_enabled
)
1613 struct ata_queued_cmd
*qc
= ata_qc_from_tag(ap
, tag
);
1617 u16 edma_status
= le16_to_cpu(response
->flags
);
1619 * edma_status from a response queue entry:
1620 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1621 * MSB is saved ATA status from command completion.
1624 u8 err_cause
= edma_status
& 0xff & ~EDMA_ERR_DEV
;
1627 * Error will be seen/handled by mv_err_intr().
1628 * So do nothing at all here.
1633 ata_status
= edma_status
>> CRPB_FLAG_STATUS_SHIFT
;
1634 qc
->err_mask
|= ac_err_mask(ata_status
);
1635 ata_qc_complete(qc
);
1637 ata_port_printk(ap
, KERN_ERR
, "%s: no qc for tag=%d\n",
1642 static void mv_process_crpb_entries(struct ata_port
*ap
, struct mv_port_priv
*pp
)
1644 void __iomem
*port_mmio
= mv_ap_base(ap
);
1645 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1647 bool work_done
= false;
1648 int ncq_enabled
= (pp
->pp_flags
& MV_PP_FLAG_NCQ_EN
);
1650 /* Get the hardware queue position index */
1651 in_index
= (readl(port_mmio
+ EDMA_RSP_Q_IN_PTR_OFS
)
1652 >> EDMA_RSP_Q_PTR_SHIFT
) & MV_MAX_Q_DEPTH_MASK
;
1654 /* Process new responses from since the last time we looked */
1655 while (in_index
!= pp
->resp_idx
) {
1657 struct mv_crpb
*response
= &pp
->crpb
[pp
->resp_idx
];
1659 pp
->resp_idx
= (pp
->resp_idx
+ 1) & MV_MAX_Q_DEPTH_MASK
;
1661 if (IS_GEN_I(hpriv
)) {
1662 /* 50xx: no NCQ, only one command active at a time */
1663 tag
= ap
->link
.active_tag
;
1665 /* Gen II/IIE: get command tag from CRPB entry */
1666 tag
= le16_to_cpu(response
->id
) & 0x1f;
1668 mv_process_crpb_response(ap
, response
, tag
, ncq_enabled
);
1672 /* Update the software queue position index in hardware */
1674 writelfl((pp
->crpb_dma
& EDMA_RSP_Q_BASE_LO_MASK
) |
1675 (pp
->resp_idx
<< EDMA_RSP_Q_PTR_SHIFT
),
1676 port_mmio
+ EDMA_RSP_Q_OUT_PTR_OFS
);
1680 * mv_host_intr - Handle all interrupts on the given host controller
1681 * @host: host specific structure
1682 * @main_cause: Main interrupt cause register for the chip.
1685 * Inherited from caller.
1687 static int mv_host_intr(struct ata_host
*host
, u32 main_cause
)
1689 struct mv_host_priv
*hpriv
= host
->private_data
;
1690 void __iomem
*mmio
= hpriv
->base
, *hc_mmio
= NULL
;
1691 u32 hc_irq_cause
= 0;
1692 unsigned int handled
= 0, port
;
1694 for (port
= 0; port
< hpriv
->n_ports
; port
++) {
1695 struct ata_port
*ap
= host
->ports
[port
];
1696 struct mv_port_priv
*pp
;
1697 unsigned int shift
, hardport
, port_cause
;
1699 * When we move to the second hc, flag our cached
1700 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1702 if (port
== MV_PORTS_PER_HC
)
1705 * Do nothing if port is not interrupting or is disabled:
1707 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
1708 port_cause
= (main_cause
>> shift
) & (DONE_IRQ
| ERR_IRQ
);
1709 if (!port_cause
|| !ap
|| (ap
->flags
& ATA_FLAG_DISABLED
))
1712 * Each hc within the host has its own hc_irq_cause register.
1713 * We defer reading it until we know we need it, right now:
1715 * FIXME later: we don't really need to read this register
1716 * (some logic changes required below if we go that way),
1717 * because it doesn't tell us anything new. But we do need
1718 * to write to it, outside the top of this loop,
1719 * to reset the interrupt triggers for next time.
1722 hc_mmio
= mv_hc_base_from_port(mmio
, port
);
1723 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1724 writelfl(~hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
1728 * Process completed CRPB response(s) before other events.
1730 pp
= ap
->private_data
;
1731 if (hc_irq_cause
& (DMA_IRQ
<< hardport
)) {
1732 if (pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
)
1733 mv_process_crpb_entries(ap
, pp
);
1736 * Handle chip-reported errors, or continue on to handle PIO.
1738 if (unlikely(port_cause
& ERR_IRQ
)) {
1739 mv_err_intr(ap
, mv_get_active_qc(ap
));
1740 } else if (hc_irq_cause
& (DEV_IRQ
<< hardport
)) {
1741 if (!(pp
->pp_flags
& MV_PP_FLAG_EDMA_EN
)) {
1742 struct ata_queued_cmd
*qc
= mv_get_active_qc(ap
);
1744 ata_sff_host_intr(ap
, qc
);
1748 mv_unexpected_intr(ap
);
1754 static int mv_pci_error(struct ata_host
*host
, void __iomem
*mmio
)
1756 struct mv_host_priv
*hpriv
= host
->private_data
;
1757 struct ata_port
*ap
;
1758 struct ata_queued_cmd
*qc
;
1759 struct ata_eh_info
*ehi
;
1760 unsigned int i
, err_mask
, printed
= 0;
1763 err_cause
= readl(mmio
+ hpriv
->irq_cause_ofs
);
1765 dev_printk(KERN_ERR
, host
->dev
, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1768 DPRINTK("All regs @ PCI error\n");
1769 mv_dump_all_regs(mmio
, -1, to_pci_dev(host
->dev
));
1771 writelfl(0, mmio
+ hpriv
->irq_cause_ofs
);
1773 for (i
= 0; i
< host
->n_ports
; i
++) {
1774 ap
= host
->ports
[i
];
1775 if (!ata_link_offline(&ap
->link
)) {
1776 ehi
= &ap
->link
.eh_info
;
1777 ata_ehi_clear_desc(ehi
);
1779 ata_ehi_push_desc(ehi
,
1780 "PCI err cause 0x%08x", err_cause
);
1781 err_mask
= AC_ERR_HOST_BUS
;
1782 ehi
->action
= ATA_EH_RESET
;
1783 qc
= ata_qc_from_tag(ap
, ap
->link
.active_tag
);
1785 qc
->err_mask
|= err_mask
;
1787 ehi
->err_mask
|= err_mask
;
1789 ata_port_freeze(ap
);
1792 return 1; /* handled */
1796 * mv_interrupt - Main interrupt event handler
1798 * @dev_instance: private data; in this case the host structure
1800 * Read the read only register to determine if any host
1801 * controllers have pending interrupts. If so, call lower level
1802 * routine to handle. Also check for PCI errors which are only
1806 * This routine holds the host lock while processing pending
1809 static irqreturn_t
mv_interrupt(int irq
, void *dev_instance
)
1811 struct ata_host
*host
= dev_instance
;
1812 struct mv_host_priv
*hpriv
= host
->private_data
;
1813 unsigned int handled
= 0;
1814 u32 main_cause
, main_mask
;
1816 spin_lock(&host
->lock
);
1817 main_cause
= readl(hpriv
->main_cause_reg_addr
);
1818 main_mask
= readl(hpriv
->main_mask_reg_addr
);
1820 * Deal with cases where we either have nothing pending, or have read
1821 * a bogus register value which can indicate HW removal or PCI fault.
1823 if ((main_cause
& main_mask
) && (main_cause
!= 0xffffffffU
)) {
1824 if (unlikely((main_cause
& PCI_ERR
) && HAS_PCI(host
)))
1825 handled
= mv_pci_error(host
, hpriv
->base
);
1827 handled
= mv_host_intr(host
, main_cause
);
1829 spin_unlock(&host
->lock
);
1830 return IRQ_RETVAL(handled
);
1833 static unsigned int mv5_scr_offset(unsigned int sc_reg_in
)
1837 switch (sc_reg_in
) {
1841 ofs
= sc_reg_in
* sizeof(u32
);
1850 static int mv5_scr_read(struct ata_port
*ap
, unsigned int sc_reg_in
, u32
*val
)
1852 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1853 void __iomem
*mmio
= hpriv
->base
;
1854 void __iomem
*addr
= mv5_phy_base(mmio
, ap
->port_no
);
1855 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
1857 if (ofs
!= 0xffffffffU
) {
1858 *val
= readl(addr
+ ofs
);
1864 static int mv5_scr_write(struct ata_port
*ap
, unsigned int sc_reg_in
, u32 val
)
1866 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
1867 void __iomem
*mmio
= hpriv
->base
;
1868 void __iomem
*addr
= mv5_phy_base(mmio
, ap
->port_no
);
1869 unsigned int ofs
= mv5_scr_offset(sc_reg_in
);
1871 if (ofs
!= 0xffffffffU
) {
1872 writelfl(val
, addr
+ ofs
);
1878 static void mv5_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
1880 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
1883 early_5080
= (pdev
->device
== 0x5080) && (pdev
->revision
== 0);
1886 u32 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1888 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1891 mv_reset_pci_bus(host
, mmio
);
1894 static void mv5_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1896 writel(0x0fcfffff, mmio
+ MV_FLASH_CTL
);
1899 static void mv5_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
1902 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, idx
);
1905 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
1907 hpriv
->signal
[idx
].pre
= tmp
& 0x1800; /* bits 12:11 */
1908 hpriv
->signal
[idx
].amps
= tmp
& 0xe0; /* bits 7:5 */
1911 static void mv5_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
1915 writel(0, mmio
+ MV_GPIO_PORT_CTL
);
1917 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1919 tmp
= readl(mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1921 writel(tmp
, mmio
+ MV_PCI_EXP_ROM_BAR_CTL
);
1924 static void mv5_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
1927 void __iomem
*phy_mmio
= mv5_phy_base(mmio
, port
);
1928 const u32 mask
= (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1930 int fix_apm_sq
= (hpriv
->hp_flags
& MV_HP_ERRATA_50XXB0
);
1933 tmp
= readl(phy_mmio
+ MV5_LT_MODE
);
1935 writel(tmp
, phy_mmio
+ MV5_LT_MODE
);
1937 tmp
= readl(phy_mmio
+ MV5_PHY_CTL
);
1940 writel(tmp
, phy_mmio
+ MV5_PHY_CTL
);
1943 tmp
= readl(phy_mmio
+ MV5_PHY_MODE
);
1945 tmp
|= hpriv
->signal
[port
].pre
;
1946 tmp
|= hpriv
->signal
[port
].amps
;
1947 writel(tmp
, phy_mmio
+ MV5_PHY_MODE
);
1952 #define ZERO(reg) writel(0, port_mmio + (reg))
1953 static void mv5_reset_hc_port(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
1956 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
1959 * The datasheet warns against setting ATA_RST when EDMA is active
1960 * (but doesn't say what the problem might be). So we first try
1961 * to disable the EDMA engine before doing the ATA_RST operation.
1963 mv_reset_channel(hpriv
, mmio
, port
);
1965 ZERO(0x028); /* command */
1966 writel(0x11f, port_mmio
+ EDMA_CFG_OFS
);
1967 ZERO(0x004); /* timer */
1968 ZERO(0x008); /* irq err cause */
1969 ZERO(0x00c); /* irq err mask */
1970 ZERO(0x010); /* rq bah */
1971 ZERO(0x014); /* rq inp */
1972 ZERO(0x018); /* rq outp */
1973 ZERO(0x01c); /* respq bah */
1974 ZERO(0x024); /* respq outp */
1975 ZERO(0x020); /* respq inp */
1976 ZERO(0x02c); /* test control */
1977 writel(0xbc, port_mmio
+ EDMA_IORDY_TMOUT
);
1981 #define ZERO(reg) writel(0, hc_mmio + (reg))
1982 static void mv5_reset_one_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
1985 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
1993 tmp
= readl(hc_mmio
+ 0x20);
1996 writel(tmp
, hc_mmio
+ 0x20);
2000 static int mv5_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2003 unsigned int hc
, port
;
2005 for (hc
= 0; hc
< n_hc
; hc
++) {
2006 for (port
= 0; port
< MV_PORTS_PER_HC
; port
++)
2007 mv5_reset_hc_port(hpriv
, mmio
,
2008 (hc
* MV_PORTS_PER_HC
) + port
);
2010 mv5_reset_one_hc(hpriv
, mmio
, hc
);
2017 #define ZERO(reg) writel(0, mmio + (reg))
2018 static void mv_reset_pci_bus(struct ata_host
*host
, void __iomem
*mmio
)
2020 struct mv_host_priv
*hpriv
= host
->private_data
;
2023 tmp
= readl(mmio
+ MV_PCI_MODE
);
2025 writel(tmp
, mmio
+ MV_PCI_MODE
);
2027 ZERO(MV_PCI_DISC_TIMER
);
2028 ZERO(MV_PCI_MSI_TRIGGER
);
2029 writel(0x000100ff, mmio
+ MV_PCI_XBAR_TMOUT
);
2030 ZERO(HC_MAIN_IRQ_MASK_OFS
);
2031 ZERO(MV_PCI_SERR_MASK
);
2032 ZERO(hpriv
->irq_cause_ofs
);
2033 ZERO(hpriv
->irq_mask_ofs
);
2034 ZERO(MV_PCI_ERR_LOW_ADDRESS
);
2035 ZERO(MV_PCI_ERR_HIGH_ADDRESS
);
2036 ZERO(MV_PCI_ERR_ATTRIBUTE
);
2037 ZERO(MV_PCI_ERR_COMMAND
);
2041 static void mv6_reset_flash(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2045 mv5_reset_flash(hpriv
, mmio
);
2047 tmp
= readl(mmio
+ MV_GPIO_PORT_CTL
);
2049 tmp
|= (1 << 5) | (1 << 6);
2050 writel(tmp
, mmio
+ MV_GPIO_PORT_CTL
);
2054 * mv6_reset_hc - Perform the 6xxx global soft reset
2055 * @mmio: base address of the HBA
2057 * This routine only applies to 6xxx parts.
2060 * Inherited from caller.
2062 static int mv6_reset_hc(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2065 void __iomem
*reg
= mmio
+ PCI_MAIN_CMD_STS_OFS
;
2069 /* Following procedure defined in PCI "main command and status
2073 writel(t
| STOP_PCI_MASTER
, reg
);
2075 for (i
= 0; i
< 1000; i
++) {
2078 if (PCI_MASTER_EMPTY
& t
)
2081 if (!(PCI_MASTER_EMPTY
& t
)) {
2082 printk(KERN_ERR DRV_NAME
": PCI master won't flush\n");
2090 writel(t
| GLOB_SFT_RST
, reg
);
2093 } while (!(GLOB_SFT_RST
& t
) && (i
-- > 0));
2095 if (!(GLOB_SFT_RST
& t
)) {
2096 printk(KERN_ERR DRV_NAME
": can't set global reset\n");
2101 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2104 writel(t
& ~(GLOB_SFT_RST
| STOP_PCI_MASTER
), reg
);
2107 } while ((GLOB_SFT_RST
& t
) && (i
-- > 0));
2109 if (GLOB_SFT_RST
& t
) {
2110 printk(KERN_ERR DRV_NAME
": can't clear global reset\n");
2117 static void mv6_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
2120 void __iomem
*port_mmio
;
2123 tmp
= readl(mmio
+ MV_RESET_CFG
);
2124 if ((tmp
& (1 << 0)) == 0) {
2125 hpriv
->signal
[idx
].amps
= 0x7 << 8;
2126 hpriv
->signal
[idx
].pre
= 0x1 << 5;
2130 port_mmio
= mv_port_base(mmio
, idx
);
2131 tmp
= readl(port_mmio
+ PHY_MODE2
);
2133 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
2134 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
2137 static void mv6_enable_leds(struct mv_host_priv
*hpriv
, void __iomem
*mmio
)
2139 writel(0x00000060, mmio
+ MV_GPIO_PORT_CTL
);
2142 static void mv6_phy_errata(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2145 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2147 u32 hp_flags
= hpriv
->hp_flags
;
2149 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
2151 hp_flags
& (MV_HP_ERRATA_60X1B2
| MV_HP_ERRATA_60X1C0
);
2154 if (fix_phy_mode2
) {
2155 m2
= readl(port_mmio
+ PHY_MODE2
);
2158 writel(m2
, port_mmio
+ PHY_MODE2
);
2162 m2
= readl(port_mmio
+ PHY_MODE2
);
2163 m2
&= ~((1 << 16) | (1 << 31));
2164 writel(m2
, port_mmio
+ PHY_MODE2
);
2169 /* who knows what this magic does */
2170 tmp
= readl(port_mmio
+ PHY_MODE3
);
2173 writel(tmp
, port_mmio
+ PHY_MODE3
);
2175 if (fix_phy_mode4
) {
2178 m4
= readl(port_mmio
+ PHY_MODE4
);
2180 if (hp_flags
& MV_HP_ERRATA_60X1B2
)
2181 tmp
= readl(port_mmio
+ PHY_MODE3
);
2183 /* workaround for errata FEr SATA#10 (part 1) */
2184 m4
= (m4
& ~(1 << 1)) | (1 << 0);
2186 writel(m4
, port_mmio
+ PHY_MODE4
);
2188 if (hp_flags
& MV_HP_ERRATA_60X1B2
)
2189 writel(tmp
, port_mmio
+ PHY_MODE3
);
2192 /* Revert values of pre-emphasis and signal amps to the saved ones */
2193 m2
= readl(port_mmio
+ PHY_MODE2
);
2195 m2
&= ~MV_M2_PREAMP_MASK
;
2196 m2
|= hpriv
->signal
[port
].amps
;
2197 m2
|= hpriv
->signal
[port
].pre
;
2200 /* according to mvSata 3.6.1, some IIE values are fixed */
2201 if (IS_GEN_IIE(hpriv
)) {
2206 writel(m2
, port_mmio
+ PHY_MODE2
);
2209 /* TODO: use the generic LED interface to configure the SATA Presence */
2210 /* & Acitivy LEDs on the board */
2211 static void mv_soc_enable_leds(struct mv_host_priv
*hpriv
,
2217 static void mv_soc_read_preamp(struct mv_host_priv
*hpriv
, int idx
,
2220 void __iomem
*port_mmio
;
2223 port_mmio
= mv_port_base(mmio
, idx
);
2224 tmp
= readl(port_mmio
+ PHY_MODE2
);
2226 hpriv
->signal
[idx
].amps
= tmp
& 0x700; /* bits 10:8 */
2227 hpriv
->signal
[idx
].pre
= tmp
& 0xe0; /* bits 7:5 */
2231 #define ZERO(reg) writel(0, port_mmio + (reg))
2232 static void mv_soc_reset_hc_port(struct mv_host_priv
*hpriv
,
2233 void __iomem
*mmio
, unsigned int port
)
2235 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2238 * The datasheet warns against setting ATA_RST when EDMA is active
2239 * (but doesn't say what the problem might be). So we first try
2240 * to disable the EDMA engine before doing the ATA_RST operation.
2242 mv_reset_channel(hpriv
, mmio
, port
);
2244 ZERO(0x028); /* command */
2245 writel(0x101f, port_mmio
+ EDMA_CFG_OFS
);
2246 ZERO(0x004); /* timer */
2247 ZERO(0x008); /* irq err cause */
2248 ZERO(0x00c); /* irq err mask */
2249 ZERO(0x010); /* rq bah */
2250 ZERO(0x014); /* rq inp */
2251 ZERO(0x018); /* rq outp */
2252 ZERO(0x01c); /* respq bah */
2253 ZERO(0x024); /* respq outp */
2254 ZERO(0x020); /* respq inp */
2255 ZERO(0x02c); /* test control */
2256 writel(0xbc, port_mmio
+ EDMA_IORDY_TMOUT
);
2261 #define ZERO(reg) writel(0, hc_mmio + (reg))
2262 static void mv_soc_reset_one_hc(struct mv_host_priv
*hpriv
,
2265 void __iomem
*hc_mmio
= mv_hc_base(mmio
, 0);
2275 static int mv_soc_reset_hc(struct mv_host_priv
*hpriv
,
2276 void __iomem
*mmio
, unsigned int n_hc
)
2280 for (port
= 0; port
< hpriv
->n_ports
; port
++)
2281 mv_soc_reset_hc_port(hpriv
, mmio
, port
);
2283 mv_soc_reset_one_hc(hpriv
, mmio
);
2288 static void mv_soc_reset_flash(struct mv_host_priv
*hpriv
,
2294 static void mv_soc_reset_bus(struct ata_host
*host
, void __iomem
*mmio
)
2299 static void mv_setup_ifctl(void __iomem
*port_mmio
, int want_gen2i
)
2301 u32 ifctl
= readl(port_mmio
+ SATA_INTERFACE_CFG
);
2303 ifctl
= (ifctl
& 0xf7f) | 0x9b1000; /* from chip spec */
2305 ifctl
|= (1 << 7); /* enable gen2i speed */
2306 writelfl(ifctl
, port_mmio
+ SATA_INTERFACE_CFG
);
2310 * Caller must ensure that EDMA is not active,
2311 * by first doing mv_stop_edma() where needed.
2313 static void mv_reset_channel(struct mv_host_priv
*hpriv
, void __iomem
*mmio
,
2314 unsigned int port_no
)
2316 void __iomem
*port_mmio
= mv_port_base(mmio
, port_no
);
2318 mv_stop_edma_engine(port_mmio
);
2319 writelfl(ATA_RST
, port_mmio
+ EDMA_CMD_OFS
);
2321 if (!IS_GEN_I(hpriv
)) {
2322 /* Enable 3.0gb/s link speed */
2323 mv_setup_ifctl(port_mmio
, 1);
2326 * Strobing ATA_RST here causes a hard reset of the SATA transport,
2327 * link, and physical layers. It resets all SATA interface registers
2328 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2330 writelfl(ATA_RST
, port_mmio
+ EDMA_CMD_OFS
);
2331 udelay(25); /* allow reset propagation */
2332 writelfl(0, port_mmio
+ EDMA_CMD_OFS
);
2334 hpriv
->ops
->phy_errata(hpriv
, mmio
, port_no
);
2336 if (IS_GEN_I(hpriv
))
2340 static void mv_pmp_select(struct ata_port
*ap
, int pmp
)
2342 if (sata_pmp_supported(ap
)) {
2343 void __iomem
*port_mmio
= mv_ap_base(ap
);
2344 u32 reg
= readl(port_mmio
+ SATA_IFCTL_OFS
);
2345 int old
= reg
& 0xf;
2348 reg
= (reg
& ~0xf) | pmp
;
2349 writelfl(reg
, port_mmio
+ SATA_IFCTL_OFS
);
2354 static int mv_pmp_hardreset(struct ata_link
*link
, unsigned int *class,
2355 unsigned long deadline
)
2357 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
2358 return sata_std_hardreset(link
, class, deadline
);
2361 static int mv_softreset(struct ata_link
*link
, unsigned int *class,
2362 unsigned long deadline
)
2364 mv_pmp_select(link
->ap
, sata_srst_pmp(link
));
2365 return ata_sff_softreset(link
, class, deadline
);
2368 static int mv_hardreset(struct ata_link
*link
, unsigned int *class,
2369 unsigned long deadline
)
2371 struct ata_port
*ap
= link
->ap
;
2372 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2373 struct mv_port_priv
*pp
= ap
->private_data
;
2374 void __iomem
*mmio
= hpriv
->base
;
2375 int rc
, attempts
= 0, extra
= 0;
2379 mv_reset_channel(hpriv
, mmio
, ap
->port_no
);
2380 pp
->pp_flags
&= ~MV_PP_FLAG_EDMA_EN
;
2382 /* Workaround for errata FEr SATA#10 (part 2) */
2384 const unsigned long *timing
=
2385 sata_ehc_deb_timing(&link
->eh_context
);
2387 rc
= sata_link_hardreset(link
, timing
, deadline
+ extra
,
2391 sata_scr_read(link
, SCR_STATUS
, &sstatus
);
2392 if (!IS_GEN_I(hpriv
) && ++attempts
>= 5 && sstatus
== 0x121) {
2393 /* Force 1.5gb/s link speed and try again */
2394 mv_setup_ifctl(mv_ap_base(ap
), 0);
2395 if (time_after(jiffies
+ HZ
, deadline
))
2396 extra
= HZ
; /* only extend it once, max */
2398 } while (sstatus
!= 0x0 && sstatus
!= 0x113 && sstatus
!= 0x123);
2403 static void mv_eh_freeze(struct ata_port
*ap
)
2405 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2406 unsigned int shift
, hardport
, port
= ap
->port_no
;
2409 /* FIXME: handle coalescing completion events properly */
2412 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
2414 /* disable assertion of portN err, done events */
2415 main_mask
= readl(hpriv
->main_mask_reg_addr
);
2416 main_mask
&= ~((DONE_IRQ
| ERR_IRQ
) << shift
);
2417 writelfl(main_mask
, hpriv
->main_mask_reg_addr
);
2420 static void mv_eh_thaw(struct ata_port
*ap
)
2422 struct mv_host_priv
*hpriv
= ap
->host
->private_data
;
2423 unsigned int shift
, hardport
, port
= ap
->port_no
;
2424 void __iomem
*hc_mmio
= mv_hc_base_from_port(hpriv
->base
, port
);
2425 void __iomem
*port_mmio
= mv_ap_base(ap
);
2426 u32 main_mask
, hc_irq_cause
;
2428 /* FIXME: handle coalescing completion events properly */
2430 MV_PORT_TO_SHIFT_AND_HARDPORT(port
, shift
, hardport
);
2432 /* clear EDMA errors on this port */
2433 writel(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
2435 /* clear pending irq events */
2436 hc_irq_cause
= readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2437 hc_irq_cause
&= ~((DEV_IRQ
| DMA_IRQ
) << hardport
);
2438 writelfl(hc_irq_cause
, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2440 /* enable assertion of portN err, done events */
2441 main_mask
= readl(hpriv
->main_mask_reg_addr
);
2442 main_mask
|= ((DONE_IRQ
| ERR_IRQ
) << shift
);
2443 writelfl(main_mask
, hpriv
->main_mask_reg_addr
);
2447 * mv_port_init - Perform some early initialization on a single port.
2448 * @port: libata data structure storing shadow register addresses
2449 * @port_mmio: base address of the port
2451 * Initialize shadow register mmio addresses, clear outstanding
2452 * interrupts on the port, and unmask interrupts for the future
2453 * start of the port.
2456 * Inherited from caller.
2458 static void mv_port_init(struct ata_ioports
*port
, void __iomem
*port_mmio
)
2460 void __iomem
*shd_base
= port_mmio
+ SHD_BLK_OFS
;
2463 /* PIO related setup
2465 port
->data_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DATA
);
2467 port
->feature_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_ERR
);
2468 port
->nsect_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_NSECT
);
2469 port
->lbal_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAL
);
2470 port
->lbam_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAM
);
2471 port
->lbah_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_LBAH
);
2472 port
->device_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_DEVICE
);
2474 port
->command_addr
= shd_base
+ (sizeof(u32
) * ATA_REG_STATUS
);
2475 /* special case: control/altstatus doesn't have ATA_REG_ address */
2476 port
->altstatus_addr
= port
->ctl_addr
= shd_base
+ SHD_CTL_AST_OFS
;
2479 port
->cmd_addr
= port
->bmdma_addr
= port
->scr_addr
= NULL
;
2481 /* Clear any currently outstanding port interrupt conditions */
2482 serr_ofs
= mv_scr_offset(SCR_ERROR
);
2483 writelfl(readl(port_mmio
+ serr_ofs
), port_mmio
+ serr_ofs
);
2484 writelfl(0, port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
);
2486 /* unmask all non-transient EDMA error interrupts */
2487 writelfl(~EDMA_ERR_IRQ_TRANSIENT
, port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
);
2489 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2490 readl(port_mmio
+ EDMA_CFG_OFS
),
2491 readl(port_mmio
+ EDMA_ERR_IRQ_CAUSE_OFS
),
2492 readl(port_mmio
+ EDMA_ERR_IRQ_MASK_OFS
));
2495 static int mv_chip_id(struct ata_host
*host
, unsigned int board_idx
)
2497 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2498 struct mv_host_priv
*hpriv
= host
->private_data
;
2499 u32 hp_flags
= hpriv
->hp_flags
;
2501 switch (board_idx
) {
2503 hpriv
->ops
= &mv5xxx_ops
;
2504 hp_flags
|= MV_HP_GEN_I
;
2506 switch (pdev
->revision
) {
2508 hp_flags
|= MV_HP_ERRATA_50XXB0
;
2511 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2514 dev_printk(KERN_WARNING
, &pdev
->dev
,
2515 "Applying 50XXB2 workarounds to unknown rev\n");
2516 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2523 hpriv
->ops
= &mv5xxx_ops
;
2524 hp_flags
|= MV_HP_GEN_I
;
2526 switch (pdev
->revision
) {
2528 hp_flags
|= MV_HP_ERRATA_50XXB0
;
2531 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2534 dev_printk(KERN_WARNING
, &pdev
->dev
,
2535 "Applying B2 workarounds to unknown rev\n");
2536 hp_flags
|= MV_HP_ERRATA_50XXB2
;
2543 hpriv
->ops
= &mv6xxx_ops
;
2544 hp_flags
|= MV_HP_GEN_II
;
2546 switch (pdev
->revision
) {
2548 hp_flags
|= MV_HP_ERRATA_60X1B2
;
2551 hp_flags
|= MV_HP_ERRATA_60X1C0
;
2554 dev_printk(KERN_WARNING
, &pdev
->dev
,
2555 "Applying B2 workarounds to unknown rev\n");
2556 hp_flags
|= MV_HP_ERRATA_60X1B2
;
2562 hp_flags
|= MV_HP_PCIE
;
2563 if (pdev
->vendor
== PCI_VENDOR_ID_TTI
&&
2564 (pdev
->device
== 0x2300 || pdev
->device
== 0x2310))
2567 * Highpoint RocketRAID PCIe 23xx series cards:
2569 * Unconfigured drives are treated as "Legacy"
2570 * by the BIOS, and it overwrites sector 8 with
2571 * a "Lgcy" metadata block prior to Linux boot.
2573 * Configured drives (RAID or JBOD) leave sector 8
2574 * alone, but instead overwrite a high numbered
2575 * sector for the RAID metadata. This sector can
2576 * be determined exactly, by truncating the physical
2577 * drive capacity to a nice even GB value.
2579 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2581 * Warn the user, lest they think we're just buggy.
2583 printk(KERN_WARNING DRV_NAME
": Highpoint RocketRAID"
2584 " BIOS CORRUPTS DATA on all attached drives,"
2585 " regardless of if/how they are configured."
2587 printk(KERN_WARNING DRV_NAME
": For data safety, do not"
2588 " use sectors 8-9 on \"Legacy\" drives,"
2589 " and avoid the final two gigabytes on"
2590 " all RocketRAID BIOS initialized drives.\n");
2593 hpriv
->ops
= &mv6xxx_ops
;
2594 hp_flags
|= MV_HP_GEN_IIE
;
2596 switch (pdev
->revision
) {
2598 hp_flags
|= MV_HP_ERRATA_XX42A0
;
2601 hp_flags
|= MV_HP_ERRATA_60X1C0
;
2604 dev_printk(KERN_WARNING
, &pdev
->dev
,
2605 "Applying 60X1C0 workarounds to unknown rev\n");
2606 hp_flags
|= MV_HP_ERRATA_60X1C0
;
2611 hpriv
->ops
= &mv_soc_ops
;
2612 hp_flags
|= MV_HP_ERRATA_60X1C0
;
2616 dev_printk(KERN_ERR
, host
->dev
,
2617 "BUG: invalid board index %u\n", board_idx
);
2621 hpriv
->hp_flags
= hp_flags
;
2622 if (hp_flags
& MV_HP_PCIE
) {
2623 hpriv
->irq_cause_ofs
= PCIE_IRQ_CAUSE_OFS
;
2624 hpriv
->irq_mask_ofs
= PCIE_IRQ_MASK_OFS
;
2625 hpriv
->unmask_all_irqs
= PCIE_UNMASK_ALL_IRQS
;
2627 hpriv
->irq_cause_ofs
= PCI_IRQ_CAUSE_OFS
;
2628 hpriv
->irq_mask_ofs
= PCI_IRQ_MASK_OFS
;
2629 hpriv
->unmask_all_irqs
= PCI_UNMASK_ALL_IRQS
;
2636 * mv_init_host - Perform some early initialization of the host.
2637 * @host: ATA host to initialize
2638 * @board_idx: controller index
2640 * If possible, do an early global reset of the host. Then do
2641 * our port init and clear/unmask all/relevant host interrupts.
2644 * Inherited from caller.
2646 static int mv_init_host(struct ata_host
*host
, unsigned int board_idx
)
2648 int rc
= 0, n_hc
, port
, hc
;
2649 struct mv_host_priv
*hpriv
= host
->private_data
;
2650 void __iomem
*mmio
= hpriv
->base
;
2652 rc
= mv_chip_id(host
, board_idx
);
2656 if (HAS_PCI(host
)) {
2657 hpriv
->main_cause_reg_addr
= mmio
+ HC_MAIN_IRQ_CAUSE_OFS
;
2658 hpriv
->main_mask_reg_addr
= mmio
+ HC_MAIN_IRQ_MASK_OFS
;
2660 hpriv
->main_cause_reg_addr
= mmio
+ HC_SOC_MAIN_IRQ_CAUSE_OFS
;
2661 hpriv
->main_mask_reg_addr
= mmio
+ HC_SOC_MAIN_IRQ_MASK_OFS
;
2664 /* global interrupt mask: 0 == mask everything */
2665 writel(0, hpriv
->main_mask_reg_addr
);
2667 n_hc
= mv_get_hc_count(host
->ports
[0]->flags
);
2669 for (port
= 0; port
< host
->n_ports
; port
++)
2670 hpriv
->ops
->read_preamp(hpriv
, port
, mmio
);
2672 rc
= hpriv
->ops
->reset_hc(hpriv
, mmio
, n_hc
);
2676 hpriv
->ops
->reset_flash(hpriv
, mmio
);
2677 hpriv
->ops
->reset_bus(host
, mmio
);
2678 hpriv
->ops
->enable_leds(hpriv
, mmio
);
2680 for (port
= 0; port
< host
->n_ports
; port
++) {
2681 struct ata_port
*ap
= host
->ports
[port
];
2682 void __iomem
*port_mmio
= mv_port_base(mmio
, port
);
2684 mv_port_init(&ap
->ioaddr
, port_mmio
);
2687 if (HAS_PCI(host
)) {
2688 unsigned int offset
= port_mmio
- mmio
;
2689 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, -1, "mmio");
2690 ata_port_pbar_desc(ap
, MV_PRIMARY_BAR
, offset
, "port");
2695 for (hc
= 0; hc
< n_hc
; hc
++) {
2696 void __iomem
*hc_mmio
= mv_hc_base(mmio
, hc
);
2698 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2699 "(before clear)=0x%08x\n", hc
,
2700 readl(hc_mmio
+ HC_CFG_OFS
),
2701 readl(hc_mmio
+ HC_IRQ_CAUSE_OFS
));
2703 /* Clear any currently outstanding hc interrupt conditions */
2704 writelfl(0, hc_mmio
+ HC_IRQ_CAUSE_OFS
);
2707 if (HAS_PCI(host
)) {
2708 /* Clear any currently outstanding host interrupt conditions */
2709 writelfl(0, mmio
+ hpriv
->irq_cause_ofs
);
2711 /* and unmask interrupt generation for host regs */
2712 writelfl(hpriv
->unmask_all_irqs
, mmio
+ hpriv
->irq_mask_ofs
);
2713 if (IS_GEN_I(hpriv
))
2714 writelfl(~HC_MAIN_MASKED_IRQS_5
,
2715 hpriv
->main_mask_reg_addr
);
2717 writelfl(~HC_MAIN_MASKED_IRQS
,
2718 hpriv
->main_mask_reg_addr
);
2720 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2721 "PCI int cause/mask=0x%08x/0x%08x\n",
2722 readl(hpriv
->main_cause_reg_addr
),
2723 readl(hpriv
->main_mask_reg_addr
),
2724 readl(mmio
+ hpriv
->irq_cause_ofs
),
2725 readl(mmio
+ hpriv
->irq_mask_ofs
));
2727 writelfl(~HC_MAIN_MASKED_IRQS_SOC
,
2728 hpriv
->main_mask_reg_addr
);
2729 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
2730 readl(hpriv
->main_cause_reg_addr
),
2731 readl(hpriv
->main_mask_reg_addr
));
2737 static int mv_create_dma_pools(struct mv_host_priv
*hpriv
, struct device
*dev
)
2739 hpriv
->crqb_pool
= dmam_pool_create("crqb_q", dev
, MV_CRQB_Q_SZ
,
2741 if (!hpriv
->crqb_pool
)
2744 hpriv
->crpb_pool
= dmam_pool_create("crpb_q", dev
, MV_CRPB_Q_SZ
,
2746 if (!hpriv
->crpb_pool
)
2749 hpriv
->sg_tbl_pool
= dmam_pool_create("sg_tbl", dev
, MV_SG_TBL_SZ
,
2751 if (!hpriv
->sg_tbl_pool
)
2757 static void mv_conf_mbus_windows(struct mv_host_priv
*hpriv
,
2758 struct mbus_dram_target_info
*dram
)
2762 for (i
= 0; i
< 4; i
++) {
2763 writel(0, hpriv
->base
+ WINDOW_CTRL(i
));
2764 writel(0, hpriv
->base
+ WINDOW_BASE(i
));
2767 for (i
= 0; i
< dram
->num_cs
; i
++) {
2768 struct mbus_dram_window
*cs
= dram
->cs
+ i
;
2770 writel(((cs
->size
- 1) & 0xffff0000) |
2771 (cs
->mbus_attr
<< 8) |
2772 (dram
->mbus_dram_target_id
<< 4) | 1,
2773 hpriv
->base
+ WINDOW_CTRL(i
));
2774 writel(cs
->base
, hpriv
->base
+ WINDOW_BASE(i
));
2779 * mv_platform_probe - handle a positive probe of an soc Marvell
2781 * @pdev: platform device found
2784 * Inherited from caller.
2786 static int mv_platform_probe(struct platform_device
*pdev
)
2788 static int printed_version
;
2789 const struct mv_sata_platform_data
*mv_platform_data
;
2790 const struct ata_port_info
*ppi
[] =
2791 { &mv_port_info
[chip_soc
], NULL
};
2792 struct ata_host
*host
;
2793 struct mv_host_priv
*hpriv
;
2794 struct resource
*res
;
2797 if (!printed_version
++)
2798 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
2801 * Simple resource validation ..
2803 if (unlikely(pdev
->num_resources
!= 2)) {
2804 dev_err(&pdev
->dev
, "invalid number of resources\n");
2809 * Get the register base first
2811 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2816 mv_platform_data
= pdev
->dev
.platform_data
;
2817 n_ports
= mv_platform_data
->n_ports
;
2819 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
2820 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
2822 if (!host
|| !hpriv
)
2824 host
->private_data
= hpriv
;
2825 hpriv
->n_ports
= n_ports
;
2828 hpriv
->base
= devm_ioremap(&pdev
->dev
, res
->start
,
2829 res
->end
- res
->start
+ 1);
2830 hpriv
->base
-= MV_SATAHC0_REG_BASE
;
2833 * (Re-)program MBUS remapping windows if we are asked to.
2835 if (mv_platform_data
->dram
!= NULL
)
2836 mv_conf_mbus_windows(hpriv
, mv_platform_data
->dram
);
2838 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
2842 /* initialize adapter */
2843 rc
= mv_init_host(host
, chip_soc
);
2847 dev_printk(KERN_INFO
, &pdev
->dev
,
2848 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH
,
2851 return ata_host_activate(host
, platform_get_irq(pdev
, 0), mv_interrupt
,
2852 IRQF_SHARED
, &mv6_sht
);
2857 * mv_platform_remove - unplug a platform interface
2858 * @pdev: platform device
2860 * A platform bus SATA device has been unplugged. Perform the needed
2861 * cleanup. Also called on module unload for any active devices.
2863 static int __devexit
mv_platform_remove(struct platform_device
*pdev
)
2865 struct device
*dev
= &pdev
->dev
;
2866 struct ata_host
*host
= dev_get_drvdata(dev
);
2868 ata_host_detach(host
);
2872 static struct platform_driver mv_platform_driver
= {
2873 .probe
= mv_platform_probe
,
2874 .remove
= __devexit_p(mv_platform_remove
),
2877 .owner
= THIS_MODULE
,
2883 static int mv_pci_init_one(struct pci_dev
*pdev
,
2884 const struct pci_device_id
*ent
);
2887 static struct pci_driver mv_pci_driver
= {
2889 .id_table
= mv_pci_tbl
,
2890 .probe
= mv_pci_init_one
,
2891 .remove
= ata_pci_remove_one
,
2897 static int msi
; /* Use PCI msi; either zero (off, default) or non-zero */
2900 /* move to PCI layer or libata core? */
2901 static int pci_go_64(struct pci_dev
*pdev
)
2905 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
2906 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
2908 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
2910 dev_printk(KERN_ERR
, &pdev
->dev
,
2911 "64-bit DMA enable failed\n");
2916 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2918 dev_printk(KERN_ERR
, &pdev
->dev
,
2919 "32-bit DMA enable failed\n");
2922 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
2924 dev_printk(KERN_ERR
, &pdev
->dev
,
2925 "32-bit consistent DMA enable failed\n");
2934 * mv_print_info - Dump key info to kernel log for perusal.
2935 * @host: ATA host to print info about
2937 * FIXME: complete this.
2940 * Inherited from caller.
2942 static void mv_print_info(struct ata_host
*host
)
2944 struct pci_dev
*pdev
= to_pci_dev(host
->dev
);
2945 struct mv_host_priv
*hpriv
= host
->private_data
;
2947 const char *scc_s
, *gen
;
2949 /* Use this to determine the HW stepping of the chip so we know
2950 * what errata to workaround
2952 pci_read_config_byte(pdev
, PCI_CLASS_DEVICE
, &scc
);
2955 else if (scc
== 0x01)
2960 if (IS_GEN_I(hpriv
))
2962 else if (IS_GEN_II(hpriv
))
2964 else if (IS_GEN_IIE(hpriv
))
2969 dev_printk(KERN_INFO
, &pdev
->dev
,
2970 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
2971 gen
, (unsigned)MV_MAX_Q_DEPTH
, host
->n_ports
,
2972 scc_s
, (MV_HP_FLAG_MSI
& hpriv
->hp_flags
) ? "MSI" : "INTx");
2976 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
2977 * @pdev: PCI device found
2978 * @ent: PCI device ID entry for the matched host
2981 * Inherited from caller.
2983 static int mv_pci_init_one(struct pci_dev
*pdev
,
2984 const struct pci_device_id
*ent
)
2986 static int printed_version
;
2987 unsigned int board_idx
= (unsigned int)ent
->driver_data
;
2988 const struct ata_port_info
*ppi
[] = { &mv_port_info
[board_idx
], NULL
};
2989 struct ata_host
*host
;
2990 struct mv_host_priv
*hpriv
;
2993 if (!printed_version
++)
2994 dev_printk(KERN_INFO
, &pdev
->dev
, "version " DRV_VERSION
"\n");
2997 n_ports
= mv_get_hc_count(ppi
[0]->flags
) * MV_PORTS_PER_HC
;
2999 host
= ata_host_alloc_pinfo(&pdev
->dev
, ppi
, n_ports
);
3000 hpriv
= devm_kzalloc(&pdev
->dev
, sizeof(*hpriv
), GFP_KERNEL
);
3001 if (!host
|| !hpriv
)
3003 host
->private_data
= hpriv
;
3004 hpriv
->n_ports
= n_ports
;
3006 /* acquire resources */
3007 rc
= pcim_enable_device(pdev
);
3011 rc
= pcim_iomap_regions(pdev
, 1 << MV_PRIMARY_BAR
, DRV_NAME
);
3013 pcim_pin_device(pdev
);
3016 host
->iomap
= pcim_iomap_table(pdev
);
3017 hpriv
->base
= host
->iomap
[MV_PRIMARY_BAR
];
3019 rc
= pci_go_64(pdev
);
3023 rc
= mv_create_dma_pools(hpriv
, &pdev
->dev
);
3027 /* initialize adapter */
3028 rc
= mv_init_host(host
, board_idx
);
3032 /* Enable interrupts */
3033 if (msi
&& pci_enable_msi(pdev
))
3036 mv_dump_pci_cfg(pdev
, 0x68);
3037 mv_print_info(host
);
3039 pci_set_master(pdev
);
3040 pci_try_set_mwi(pdev
);
3041 return ata_host_activate(host
, pdev
->irq
, mv_interrupt
, IRQF_SHARED
,
3042 IS_GEN_I(hpriv
) ? &mv5_sht
: &mv6_sht
);
3046 static int mv_platform_probe(struct platform_device
*pdev
);
3047 static int __devexit
mv_platform_remove(struct platform_device
*pdev
);
3049 static int __init
mv_init(void)
3053 rc
= pci_register_driver(&mv_pci_driver
);
3057 rc
= platform_driver_register(&mv_platform_driver
);
3061 pci_unregister_driver(&mv_pci_driver
);
3066 static void __exit
mv_exit(void)
3069 pci_unregister_driver(&mv_pci_driver
);
3071 platform_driver_unregister(&mv_platform_driver
);
3074 MODULE_AUTHOR("Brett Russ");
3075 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3076 MODULE_LICENSE("GPL");
3077 MODULE_DEVICE_TABLE(pci
, mv_pci_tbl
);
3078 MODULE_VERSION(DRV_VERSION
);
3079 MODULE_ALIAS("platform:" DRV_NAME
);
3082 module_param(msi
, int, 0444);
3083 MODULE_PARM_DESC(msi
, "Enable use of PCI MSI (0=off, 1=on)");
3086 module_init(mv_init
);
3087 module_exit(mv_exit
);