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[libata] sata_mv: don't touch reserved bits in EDMA config register
[deliverable/linux.git] / drivers / ata / sata_mv.c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
36
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.7"
39
40 enum {
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
45
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
48
49 MV_PCI_REG_BASE = 0,
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
56
57 MV_SATAHC0_REG_BASE = 0x20000,
58 MV_FLASH_CTL = 0x1046c,
59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
61
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
66
67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
68
69 MV_MAX_Q_DEPTH = 32,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
71
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
76 */
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
79 MV_MAX_SG_CT = 176,
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
82
83 MV_PORTS_PER_HC = 4,
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
85 MV_PORT_HC_SHIFT = 2,
86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
87 MV_PORT_MASK = 3,
88
89 /* Host Flags */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
96
97 CRQB_FLAG_READ = (1 << 0),
98 CRQB_TAG_SHIFT = 1,
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
102
103 CRPB_FLAG_STATUS_SHIFT = 8,
104
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
106
107 /* PCI interface registers */
108
109 PCI_COMMAND_OFS = 0xc00,
110
111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
115
116 MV_PCI_MODE = 0xd00,
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
126
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
130
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
137 PCI_ERR = (1 << 18),
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
140 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
141 GPIO_INT = (1 << 22),
142 SELF_INT = (1 << 23),
143 TWSI_INT = (1 << 24),
144 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
145 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
146 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
147 HC_MAIN_RSVD),
148
149 /* SATAHC registers */
150 HC_CFG_OFS = 0,
151
152 HC_IRQ_CAUSE_OFS = 0x14,
153 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
154 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
155 DEV_IRQ = (1 << 8), /* shift by port # */
156
157 /* Shadow block registers */
158 SHD_BLK_OFS = 0x100,
159 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
160
161 /* SATA registers */
162 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
163 SATA_ACTIVE_OFS = 0x350,
164 PHY_MODE3 = 0x310,
165 PHY_MODE4 = 0x314,
166 PHY_MODE2 = 0x330,
167 MV5_PHY_MODE = 0x74,
168 MV5_LT_MODE = 0x30,
169 MV5_PHY_CTL = 0x0C,
170 SATA_INTERFACE_CTL = 0x050,
171
172 MV_M2_PREAMP_MASK = 0x7e0,
173
174 /* Port registers */
175 EDMA_CFG_OFS = 0,
176 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
177 EDMA_CFG_NCQ = (1 << 5),
178 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
179 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
180 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
181
182 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
183 EDMA_ERR_IRQ_MASK_OFS = 0xc,
184 EDMA_ERR_D_PAR = (1 << 0),
185 EDMA_ERR_PRD_PAR = (1 << 1),
186 EDMA_ERR_DEV = (1 << 2),
187 EDMA_ERR_DEV_DCON = (1 << 3),
188 EDMA_ERR_DEV_CON = (1 << 4),
189 EDMA_ERR_SERR = (1 << 5),
190 EDMA_ERR_SELF_DIS = (1 << 7),
191 EDMA_ERR_BIST_ASYNC = (1 << 8),
192 EDMA_ERR_CRBQ_PAR = (1 << 9),
193 EDMA_ERR_CRPB_PAR = (1 << 10),
194 EDMA_ERR_INTRL_PAR = (1 << 11),
195 EDMA_ERR_IORDY = (1 << 12),
196 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
197 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
198 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
199 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
200 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
201 EDMA_ERR_TRANS_PROTO = (1 << 31),
202 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
203 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
204 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
205 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
206 EDMA_ERR_LNK_DATA_RX |
207 EDMA_ERR_LNK_DATA_TX |
208 EDMA_ERR_TRANS_PROTO),
209
210 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
211 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
212
213 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
214 EDMA_REQ_Q_PTR_SHIFT = 5,
215
216 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
217 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
218 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
219 EDMA_RSP_Q_PTR_SHIFT = 3,
220
221 EDMA_CMD_OFS = 0x28,
222 EDMA_EN = (1 << 0),
223 EDMA_DS = (1 << 1),
224 ATA_RST = (1 << 2),
225
226 EDMA_IORDY_TMOUT = 0x34,
227 EDMA_ARB_CFG = 0x38,
228
229 /* Host private flags (hp_flags) */
230 MV_HP_FLAG_MSI = (1 << 0),
231 MV_HP_ERRATA_50XXB0 = (1 << 1),
232 MV_HP_ERRATA_50XXB2 = (1 << 2),
233 MV_HP_ERRATA_60X1B2 = (1 << 3),
234 MV_HP_ERRATA_60X1C0 = (1 << 4),
235 MV_HP_ERRATA_XX42A0 = (1 << 5),
236 MV_HP_50XX = (1 << 6),
237 MV_HP_GEN_IIE = (1 << 7),
238
239 /* Port private flags (pp_flags) */
240 MV_PP_FLAG_EDMA_EN = (1 << 0),
241 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
242 };
243
244 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
245 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
246 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
247 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
248 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
249
250 enum {
251 /* Our DMA boundary is determined by an ePRD being unable to handle
252 * anything larger than 64KB
253 */
254 MV_DMA_BOUNDARY = 0xffffU,
255
256 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
257
258 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
259 };
260
261 enum chip_type {
262 chip_504x,
263 chip_508x,
264 chip_5080,
265 chip_604x,
266 chip_608x,
267 chip_6042,
268 chip_7042,
269 };
270
271 /* Command ReQuest Block: 32B */
272 struct mv_crqb {
273 __le32 sg_addr;
274 __le32 sg_addr_hi;
275 __le16 ctrl_flags;
276 __le16 ata_cmd[11];
277 };
278
279 struct mv_crqb_iie {
280 __le32 addr;
281 __le32 addr_hi;
282 __le32 flags;
283 __le32 len;
284 __le32 ata_cmd[4];
285 };
286
287 /* Command ResPonse Block: 8B */
288 struct mv_crpb {
289 __le16 id;
290 __le16 flags;
291 __le32 tmstmp;
292 };
293
294 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
295 struct mv_sg {
296 __le32 addr;
297 __le32 flags_size;
298 __le32 addr_hi;
299 __le32 reserved;
300 };
301
302 struct mv_port_priv {
303 struct mv_crqb *crqb;
304 dma_addr_t crqb_dma;
305 struct mv_crpb *crpb;
306 dma_addr_t crpb_dma;
307 struct mv_sg *sg_tbl;
308 dma_addr_t sg_tbl_dma;
309 u32 pp_flags;
310 };
311
312 struct mv_port_signal {
313 u32 amps;
314 u32 pre;
315 };
316
317 struct mv_host_priv;
318 struct mv_hw_ops {
319 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
320 unsigned int port);
321 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
322 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
323 void __iomem *mmio);
324 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
325 unsigned int n_hc);
326 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
327 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
328 };
329
330 struct mv_host_priv {
331 u32 hp_flags;
332 struct mv_port_signal signal[8];
333 const struct mv_hw_ops *ops;
334 };
335
336 static void mv_irq_clear(struct ata_port *ap);
337 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
338 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
339 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static void mv_phy_reset(struct ata_port *ap);
342 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
343 static int mv_port_start(struct ata_port *ap);
344 static void mv_port_stop(struct ata_port *ap);
345 static void mv_qc_prep(struct ata_queued_cmd *qc);
346 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
347 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
348 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
349 static void mv_eng_timeout(struct ata_port *ap);
350 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
351
352 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int port);
354 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
356 void __iomem *mmio);
357 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
358 unsigned int n_hc);
359 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
360 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
361
362 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
363 unsigned int port);
364 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
365 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
366 void __iomem *mmio);
367 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
368 unsigned int n_hc);
369 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
370 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
371 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
372 unsigned int port_no);
373 static void mv_stop_and_reset(struct ata_port *ap);
374
375 static struct scsi_host_template mv_sht = {
376 .module = THIS_MODULE,
377 .name = DRV_NAME,
378 .ioctl = ata_scsi_ioctl,
379 .queuecommand = ata_scsi_queuecmd,
380 .can_queue = MV_USE_Q_DEPTH,
381 .this_id = ATA_SHT_THIS_ID,
382 .sg_tablesize = MV_MAX_SG_CT / 2,
383 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
384 .emulated = ATA_SHT_EMULATED,
385 .use_clustering = ATA_SHT_USE_CLUSTERING,
386 .proc_name = DRV_NAME,
387 .dma_boundary = MV_DMA_BOUNDARY,
388 .slave_configure = ata_scsi_slave_config,
389 .slave_destroy = ata_scsi_slave_destroy,
390 .bios_param = ata_std_bios_param,
391 };
392
393 static const struct ata_port_operations mv5_ops = {
394 .port_disable = ata_port_disable,
395
396 .tf_load = ata_tf_load,
397 .tf_read = ata_tf_read,
398 .check_status = ata_check_status,
399 .exec_command = ata_exec_command,
400 .dev_select = ata_std_dev_select,
401
402 .phy_reset = mv_phy_reset,
403
404 .qc_prep = mv_qc_prep,
405 .qc_issue = mv_qc_issue,
406 .data_xfer = ata_data_xfer,
407
408 .eng_timeout = mv_eng_timeout,
409
410 .irq_handler = mv_interrupt,
411 .irq_clear = mv_irq_clear,
412 .irq_on = ata_irq_on,
413 .irq_ack = ata_irq_ack,
414
415 .scr_read = mv5_scr_read,
416 .scr_write = mv5_scr_write,
417
418 .port_start = mv_port_start,
419 .port_stop = mv_port_stop,
420 };
421
422 static const struct ata_port_operations mv6_ops = {
423 .port_disable = ata_port_disable,
424
425 .tf_load = ata_tf_load,
426 .tf_read = ata_tf_read,
427 .check_status = ata_check_status,
428 .exec_command = ata_exec_command,
429 .dev_select = ata_std_dev_select,
430
431 .phy_reset = mv_phy_reset,
432
433 .qc_prep = mv_qc_prep,
434 .qc_issue = mv_qc_issue,
435 .data_xfer = ata_data_xfer,
436
437 .eng_timeout = mv_eng_timeout,
438
439 .irq_handler = mv_interrupt,
440 .irq_clear = mv_irq_clear,
441 .irq_on = ata_irq_on,
442 .irq_ack = ata_irq_ack,
443
444 .scr_read = mv_scr_read,
445 .scr_write = mv_scr_write,
446
447 .port_start = mv_port_start,
448 .port_stop = mv_port_stop,
449 };
450
451 static const struct ata_port_operations mv_iie_ops = {
452 .port_disable = ata_port_disable,
453
454 .tf_load = ata_tf_load,
455 .tf_read = ata_tf_read,
456 .check_status = ata_check_status,
457 .exec_command = ata_exec_command,
458 .dev_select = ata_std_dev_select,
459
460 .phy_reset = mv_phy_reset,
461
462 .qc_prep = mv_qc_prep_iie,
463 .qc_issue = mv_qc_issue,
464 .data_xfer = ata_data_xfer,
465
466 .eng_timeout = mv_eng_timeout,
467
468 .irq_handler = mv_interrupt,
469 .irq_clear = mv_irq_clear,
470 .irq_on = ata_irq_on,
471 .irq_ack = ata_irq_ack,
472
473 .scr_read = mv_scr_read,
474 .scr_write = mv_scr_write,
475
476 .port_start = mv_port_start,
477 .port_stop = mv_port_stop,
478 };
479
480 static const struct ata_port_info mv_port_info[] = {
481 { /* chip_504x */
482 .sht = &mv_sht,
483 .flags = MV_COMMON_FLAGS,
484 .pio_mask = 0x1f, /* pio0-4 */
485 .udma_mask = 0x7f, /* udma0-6 */
486 .port_ops = &mv5_ops,
487 },
488 { /* chip_508x */
489 .sht = &mv_sht,
490 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
491 .pio_mask = 0x1f, /* pio0-4 */
492 .udma_mask = 0x7f, /* udma0-6 */
493 .port_ops = &mv5_ops,
494 },
495 { /* chip_5080 */
496 .sht = &mv_sht,
497 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
498 .pio_mask = 0x1f, /* pio0-4 */
499 .udma_mask = 0x7f, /* udma0-6 */
500 .port_ops = &mv5_ops,
501 },
502 { /* chip_604x */
503 .sht = &mv_sht,
504 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
505 .pio_mask = 0x1f, /* pio0-4 */
506 .udma_mask = 0x7f, /* udma0-6 */
507 .port_ops = &mv6_ops,
508 },
509 { /* chip_608x */
510 .sht = &mv_sht,
511 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
512 MV_FLAG_DUAL_HC),
513 .pio_mask = 0x1f, /* pio0-4 */
514 .udma_mask = 0x7f, /* udma0-6 */
515 .port_ops = &mv6_ops,
516 },
517 { /* chip_6042 */
518 .sht = &mv_sht,
519 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
520 .pio_mask = 0x1f, /* pio0-4 */
521 .udma_mask = 0x7f, /* udma0-6 */
522 .port_ops = &mv_iie_ops,
523 },
524 { /* chip_7042 */
525 .sht = &mv_sht,
526 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
527 .pio_mask = 0x1f, /* pio0-4 */
528 .udma_mask = 0x7f, /* udma0-6 */
529 .port_ops = &mv_iie_ops,
530 },
531 };
532
533 static const struct pci_device_id mv_pci_tbl[] = {
534 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
535 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
536 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
537 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
538
539 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
540 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
541 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
542 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
543 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
544
545 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
546
547 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
548
549 { } /* terminate list */
550 };
551
552 static struct pci_driver mv_pci_driver = {
553 .name = DRV_NAME,
554 .id_table = mv_pci_tbl,
555 .probe = mv_init_one,
556 .remove = ata_pci_remove_one,
557 };
558
559 static const struct mv_hw_ops mv5xxx_ops = {
560 .phy_errata = mv5_phy_errata,
561 .enable_leds = mv5_enable_leds,
562 .read_preamp = mv5_read_preamp,
563 .reset_hc = mv5_reset_hc,
564 .reset_flash = mv5_reset_flash,
565 .reset_bus = mv5_reset_bus,
566 };
567
568 static const struct mv_hw_ops mv6xxx_ops = {
569 .phy_errata = mv6_phy_errata,
570 .enable_leds = mv6_enable_leds,
571 .read_preamp = mv6_read_preamp,
572 .reset_hc = mv6_reset_hc,
573 .reset_flash = mv6_reset_flash,
574 .reset_bus = mv_reset_pci_bus,
575 };
576
577 /*
578 * module options
579 */
580 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
581
582
583 /*
584 * Functions
585 */
586
587 static inline void writelfl(unsigned long data, void __iomem *addr)
588 {
589 writel(data, addr);
590 (void) readl(addr); /* flush to avoid PCI posted write */
591 }
592
593 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
594 {
595 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
596 }
597
598 static inline unsigned int mv_hc_from_port(unsigned int port)
599 {
600 return port >> MV_PORT_HC_SHIFT;
601 }
602
603 static inline unsigned int mv_hardport_from_port(unsigned int port)
604 {
605 return port & MV_PORT_MASK;
606 }
607
608 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
609 unsigned int port)
610 {
611 return mv_hc_base(base, mv_hc_from_port(port));
612 }
613
614 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
615 {
616 return mv_hc_base_from_port(base, port) +
617 MV_SATAHC_ARBTR_REG_SZ +
618 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
619 }
620
621 static inline void __iomem *mv_ap_base(struct ata_port *ap)
622 {
623 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
624 }
625
626 static inline int mv_get_hc_count(unsigned long port_flags)
627 {
628 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
629 }
630
631 static void mv_irq_clear(struct ata_port *ap)
632 {
633 }
634
635 /**
636 * mv_start_dma - Enable eDMA engine
637 * @base: port base address
638 * @pp: port private data
639 *
640 * Verify the local cache of the eDMA state is accurate with a
641 * WARN_ON.
642 *
643 * LOCKING:
644 * Inherited from caller.
645 */
646 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
647 {
648 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
649 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
650 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
651 }
652 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
653 }
654
655 /**
656 * mv_stop_dma - Disable eDMA engine
657 * @ap: ATA channel to manipulate
658 *
659 * Verify the local cache of the eDMA state is accurate with a
660 * WARN_ON.
661 *
662 * LOCKING:
663 * Inherited from caller.
664 */
665 static void mv_stop_dma(struct ata_port *ap)
666 {
667 void __iomem *port_mmio = mv_ap_base(ap);
668 struct mv_port_priv *pp = ap->private_data;
669 u32 reg;
670 int i;
671
672 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
673 /* Disable EDMA if active. The disable bit auto clears.
674 */
675 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
676 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
677 } else {
678 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
679 }
680
681 /* now properly wait for the eDMA to stop */
682 for (i = 1000; i > 0; i--) {
683 reg = readl(port_mmio + EDMA_CMD_OFS);
684 if (!(EDMA_EN & reg)) {
685 break;
686 }
687 udelay(100);
688 }
689
690 if (EDMA_EN & reg) {
691 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
692 /* FIXME: Consider doing a reset here to recover */
693 }
694 }
695
696 #ifdef ATA_DEBUG
697 static void mv_dump_mem(void __iomem *start, unsigned bytes)
698 {
699 int b, w;
700 for (b = 0; b < bytes; ) {
701 DPRINTK("%p: ", start + b);
702 for (w = 0; b < bytes && w < 4; w++) {
703 printk("%08x ",readl(start + b));
704 b += sizeof(u32);
705 }
706 printk("\n");
707 }
708 }
709 #endif
710
711 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
712 {
713 #ifdef ATA_DEBUG
714 int b, w;
715 u32 dw;
716 for (b = 0; b < bytes; ) {
717 DPRINTK("%02x: ", b);
718 for (w = 0; b < bytes && w < 4; w++) {
719 (void) pci_read_config_dword(pdev,b,&dw);
720 printk("%08x ",dw);
721 b += sizeof(u32);
722 }
723 printk("\n");
724 }
725 #endif
726 }
727 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
728 struct pci_dev *pdev)
729 {
730 #ifdef ATA_DEBUG
731 void __iomem *hc_base = mv_hc_base(mmio_base,
732 port >> MV_PORT_HC_SHIFT);
733 void __iomem *port_base;
734 int start_port, num_ports, p, start_hc, num_hcs, hc;
735
736 if (0 > port) {
737 start_hc = start_port = 0;
738 num_ports = 8; /* shld be benign for 4 port devs */
739 num_hcs = 2;
740 } else {
741 start_hc = port >> MV_PORT_HC_SHIFT;
742 start_port = port;
743 num_ports = num_hcs = 1;
744 }
745 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
746 num_ports > 1 ? num_ports - 1 : start_port);
747
748 if (NULL != pdev) {
749 DPRINTK("PCI config space regs:\n");
750 mv_dump_pci_cfg(pdev, 0x68);
751 }
752 DPRINTK("PCI regs:\n");
753 mv_dump_mem(mmio_base+0xc00, 0x3c);
754 mv_dump_mem(mmio_base+0xd00, 0x34);
755 mv_dump_mem(mmio_base+0xf00, 0x4);
756 mv_dump_mem(mmio_base+0x1d00, 0x6c);
757 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
758 hc_base = mv_hc_base(mmio_base, hc);
759 DPRINTK("HC regs (HC %i):\n", hc);
760 mv_dump_mem(hc_base, 0x1c);
761 }
762 for (p = start_port; p < start_port + num_ports; p++) {
763 port_base = mv_port_base(mmio_base, p);
764 DPRINTK("EDMA regs (port %i):\n",p);
765 mv_dump_mem(port_base, 0x54);
766 DPRINTK("SATA regs (port %i):\n",p);
767 mv_dump_mem(port_base+0x300, 0x60);
768 }
769 #endif
770 }
771
772 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
773 {
774 unsigned int ofs;
775
776 switch (sc_reg_in) {
777 case SCR_STATUS:
778 case SCR_CONTROL:
779 case SCR_ERROR:
780 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
781 break;
782 case SCR_ACTIVE:
783 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
784 break;
785 default:
786 ofs = 0xffffffffU;
787 break;
788 }
789 return ofs;
790 }
791
792 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
793 {
794 unsigned int ofs = mv_scr_offset(sc_reg_in);
795
796 if (0xffffffffU != ofs) {
797 return readl(mv_ap_base(ap) + ofs);
798 } else {
799 return (u32) ofs;
800 }
801 }
802
803 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
804 {
805 unsigned int ofs = mv_scr_offset(sc_reg_in);
806
807 if (0xffffffffU != ofs) {
808 writelfl(val, mv_ap_base(ap) + ofs);
809 }
810 }
811
812 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
813 {
814 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
815
816 /* set up non-NCQ EDMA configuration */
817 cfg &= ~(1 << 9); /* disable equeue */
818
819 if (IS_GEN_I(hpriv)) {
820 cfg &= ~0x1f; /* clear queue depth */
821 cfg |= (1 << 8); /* enab config burst size mask */
822 }
823
824 else if (IS_GEN_II(hpriv)) {
825 cfg &= ~0x1f; /* clear queue depth */
826 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
827 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
828 }
829
830 else if (IS_GEN_IIE(hpriv)) {
831 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
832 cfg |= (1 << 22); /* enab 4-entry host queue cache */
833 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
834 cfg |= (1 << 18); /* enab early completion */
835 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
836 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
837 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
838 }
839
840 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
841 }
842
843 /**
844 * mv_port_start - Port specific init/start routine.
845 * @ap: ATA channel to manipulate
846 *
847 * Allocate and point to DMA memory, init port private memory,
848 * zero indices.
849 *
850 * LOCKING:
851 * Inherited from caller.
852 */
853 static int mv_port_start(struct ata_port *ap)
854 {
855 struct device *dev = ap->host->dev;
856 struct mv_host_priv *hpriv = ap->host->private_data;
857 struct mv_port_priv *pp;
858 void __iomem *port_mmio = mv_ap_base(ap);
859 void *mem;
860 dma_addr_t mem_dma;
861 int rc;
862
863 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
864 if (!pp)
865 return -ENOMEM;
866
867 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
868 GFP_KERNEL);
869 if (!mem)
870 return -ENOMEM;
871 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
872
873 rc = ata_pad_alloc(ap, dev);
874 if (rc)
875 return rc;
876
877 /* First item in chunk of DMA memory:
878 * 32-slot command request table (CRQB), 32 bytes each in size
879 */
880 pp->crqb = mem;
881 pp->crqb_dma = mem_dma;
882 mem += MV_CRQB_Q_SZ;
883 mem_dma += MV_CRQB_Q_SZ;
884
885 /* Second item:
886 * 32-slot command response table (CRPB), 8 bytes each in size
887 */
888 pp->crpb = mem;
889 pp->crpb_dma = mem_dma;
890 mem += MV_CRPB_Q_SZ;
891 mem_dma += MV_CRPB_Q_SZ;
892
893 /* Third item:
894 * Table of scatter-gather descriptors (ePRD), 16 bytes each
895 */
896 pp->sg_tbl = mem;
897 pp->sg_tbl_dma = mem_dma;
898
899 mv_edma_cfg(hpriv, port_mmio);
900
901 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
902 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
903 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
904
905 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
906 writelfl(pp->crqb_dma & 0xffffffff,
907 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
908 else
909 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
910
911 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
912
913 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
914 writelfl(pp->crpb_dma & 0xffffffff,
915 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
916 else
917 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
918
919 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
920 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
921
922 /* Don't turn on EDMA here...do it before DMA commands only. Else
923 * we'll be unable to send non-data, PIO, etc due to restricted access
924 * to shadow regs.
925 */
926 ap->private_data = pp;
927 return 0;
928 }
929
930 /**
931 * mv_port_stop - Port specific cleanup/stop routine.
932 * @ap: ATA channel to manipulate
933 *
934 * Stop DMA, cleanup port memory.
935 *
936 * LOCKING:
937 * This routine uses the host lock to protect the DMA stop.
938 */
939 static void mv_port_stop(struct ata_port *ap)
940 {
941 unsigned long flags;
942
943 spin_lock_irqsave(&ap->host->lock, flags);
944 mv_stop_dma(ap);
945 spin_unlock_irqrestore(&ap->host->lock, flags);
946 }
947
948 /**
949 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
950 * @qc: queued command whose SG list to source from
951 *
952 * Populate the SG list and mark the last entry.
953 *
954 * LOCKING:
955 * Inherited from caller.
956 */
957 static void mv_fill_sg(struct ata_queued_cmd *qc)
958 {
959 struct mv_port_priv *pp = qc->ap->private_data;
960 unsigned int i = 0;
961 struct scatterlist *sg;
962
963 ata_for_each_sg(sg, qc) {
964 dma_addr_t addr;
965 u32 sg_len, len, offset;
966
967 addr = sg_dma_address(sg);
968 sg_len = sg_dma_len(sg);
969
970 while (sg_len) {
971 offset = addr & MV_DMA_BOUNDARY;
972 len = sg_len;
973 if ((offset + sg_len) > 0x10000)
974 len = 0x10000 - offset;
975
976 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
977 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
978 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
979
980 sg_len -= len;
981 addr += len;
982
983 if (!sg_len && ata_sg_is_last(sg, qc))
984 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
985
986 i++;
987 }
988 }
989 }
990
991 static inline unsigned mv_inc_q_index(unsigned index)
992 {
993 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
994 }
995
996 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
997 {
998 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
999 (last ? CRQB_CMD_LAST : 0);
1000 *cmdw = cpu_to_le16(tmp);
1001 }
1002
1003 /**
1004 * mv_qc_prep - Host specific command preparation.
1005 * @qc: queued command to prepare
1006 *
1007 * This routine simply redirects to the general purpose routine
1008 * if command is not DMA. Else, it handles prep of the CRQB
1009 * (command request block), does some sanity checking, and calls
1010 * the SG load routine.
1011 *
1012 * LOCKING:
1013 * Inherited from caller.
1014 */
1015 static void mv_qc_prep(struct ata_queued_cmd *qc)
1016 {
1017 struct ata_port *ap = qc->ap;
1018 struct mv_port_priv *pp = ap->private_data;
1019 __le16 *cw;
1020 struct ata_taskfile *tf;
1021 u16 flags = 0;
1022 unsigned in_index;
1023
1024 if (ATA_PROT_DMA != qc->tf.protocol)
1025 return;
1026
1027 /* Fill in command request block
1028 */
1029 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1030 flags |= CRQB_FLAG_READ;
1031 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1032 flags |= qc->tag << CRQB_TAG_SHIFT;
1033
1034 /* get current queue index from hardware */
1035 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1036 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1037
1038 pp->crqb[in_index].sg_addr =
1039 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1040 pp->crqb[in_index].sg_addr_hi =
1041 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1042 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1043
1044 cw = &pp->crqb[in_index].ata_cmd[0];
1045 tf = &qc->tf;
1046
1047 /* Sadly, the CRQB cannot accomodate all registers--there are
1048 * only 11 bytes...so we must pick and choose required
1049 * registers based on the command. So, we drop feature and
1050 * hob_feature for [RW] DMA commands, but they are needed for
1051 * NCQ. NCQ will drop hob_nsect.
1052 */
1053 switch (tf->command) {
1054 case ATA_CMD_READ:
1055 case ATA_CMD_READ_EXT:
1056 case ATA_CMD_WRITE:
1057 case ATA_CMD_WRITE_EXT:
1058 case ATA_CMD_WRITE_FUA_EXT:
1059 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1060 break;
1061 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1062 case ATA_CMD_FPDMA_READ:
1063 case ATA_CMD_FPDMA_WRITE:
1064 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1065 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1066 break;
1067 #endif /* FIXME: remove this line when NCQ added */
1068 default:
1069 /* The only other commands EDMA supports in non-queued and
1070 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1071 * of which are defined/used by Linux. If we get here, this
1072 * driver needs work.
1073 *
1074 * FIXME: modify libata to give qc_prep a return value and
1075 * return error here.
1076 */
1077 BUG_ON(tf->command);
1078 break;
1079 }
1080 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1081 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1082 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1083 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1084 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1085 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1086 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1087 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1088 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1089
1090 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1091 return;
1092 mv_fill_sg(qc);
1093 }
1094
1095 /**
1096 * mv_qc_prep_iie - Host specific command preparation.
1097 * @qc: queued command to prepare
1098 *
1099 * This routine simply redirects to the general purpose routine
1100 * if command is not DMA. Else, it handles prep of the CRQB
1101 * (command request block), does some sanity checking, and calls
1102 * the SG load routine.
1103 *
1104 * LOCKING:
1105 * Inherited from caller.
1106 */
1107 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1108 {
1109 struct ata_port *ap = qc->ap;
1110 struct mv_port_priv *pp = ap->private_data;
1111 struct mv_crqb_iie *crqb;
1112 struct ata_taskfile *tf;
1113 unsigned in_index;
1114 u32 flags = 0;
1115
1116 if (ATA_PROT_DMA != qc->tf.protocol)
1117 return;
1118
1119 /* Fill in Gen IIE command request block
1120 */
1121 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1122 flags |= CRQB_FLAG_READ;
1123
1124 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1125 flags |= qc->tag << CRQB_TAG_SHIFT;
1126
1127 /* get current queue index from hardware */
1128 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1129 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1130
1131 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1132 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1133 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1134 crqb->flags = cpu_to_le32(flags);
1135
1136 tf = &qc->tf;
1137 crqb->ata_cmd[0] = cpu_to_le32(
1138 (tf->command << 16) |
1139 (tf->feature << 24)
1140 );
1141 crqb->ata_cmd[1] = cpu_to_le32(
1142 (tf->lbal << 0) |
1143 (tf->lbam << 8) |
1144 (tf->lbah << 16) |
1145 (tf->device << 24)
1146 );
1147 crqb->ata_cmd[2] = cpu_to_le32(
1148 (tf->hob_lbal << 0) |
1149 (tf->hob_lbam << 8) |
1150 (tf->hob_lbah << 16) |
1151 (tf->hob_feature << 24)
1152 );
1153 crqb->ata_cmd[3] = cpu_to_le32(
1154 (tf->nsect << 0) |
1155 (tf->hob_nsect << 8)
1156 );
1157
1158 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1159 return;
1160 mv_fill_sg(qc);
1161 }
1162
1163 /**
1164 * mv_qc_issue - Initiate a command to the host
1165 * @qc: queued command to start
1166 *
1167 * This routine simply redirects to the general purpose routine
1168 * if command is not DMA. Else, it sanity checks our local
1169 * caches of the request producer/consumer indices then enables
1170 * DMA and bumps the request producer index.
1171 *
1172 * LOCKING:
1173 * Inherited from caller.
1174 */
1175 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1176 {
1177 void __iomem *port_mmio = mv_ap_base(qc->ap);
1178 struct mv_port_priv *pp = qc->ap->private_data;
1179 unsigned in_index;
1180 u32 in_ptr;
1181
1182 if (ATA_PROT_DMA != qc->tf.protocol) {
1183 /* We're about to send a non-EDMA capable command to the
1184 * port. Turn off EDMA so there won't be problems accessing
1185 * shadow block, etc registers.
1186 */
1187 mv_stop_dma(qc->ap);
1188 return ata_qc_issue_prot(qc);
1189 }
1190
1191 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1192 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1193
1194 /* until we do queuing, the queue should be empty at this point */
1195 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1196 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1197
1198 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1199
1200 mv_start_dma(port_mmio, pp);
1201
1202 /* and write the request in pointer to kick the EDMA to life */
1203 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1204 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1205 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1206
1207 return 0;
1208 }
1209
1210 /**
1211 * mv_get_crpb_status - get status from most recently completed cmd
1212 * @ap: ATA channel to manipulate
1213 *
1214 * This routine is for use when the port is in DMA mode, when it
1215 * will be using the CRPB (command response block) method of
1216 * returning command completion information. We check indices
1217 * are good, grab status, and bump the response consumer index to
1218 * prove that we're up to date.
1219 *
1220 * LOCKING:
1221 * Inherited from caller.
1222 */
1223 static u8 mv_get_crpb_status(struct ata_port *ap)
1224 {
1225 void __iomem *port_mmio = mv_ap_base(ap);
1226 struct mv_port_priv *pp = ap->private_data;
1227 unsigned out_index;
1228 u32 out_ptr;
1229 u8 ata_status;
1230
1231 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1232 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1233
1234 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1235 >> CRPB_FLAG_STATUS_SHIFT;
1236
1237 /* increment our consumer index... */
1238 out_index = mv_inc_q_index(out_index);
1239
1240 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1241 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1242 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1243
1244 /* write out our inc'd consumer index so EDMA knows we're caught up */
1245 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1246 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1247 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1248
1249 /* Return ATA status register for completed CRPB */
1250 return ata_status;
1251 }
1252
1253 /**
1254 * mv_err_intr - Handle error interrupts on the port
1255 * @ap: ATA channel to manipulate
1256 * @reset_allowed: bool: 0 == don't trigger from reset here
1257 *
1258 * In most cases, just clear the interrupt and move on. However,
1259 * some cases require an eDMA reset, which is done right before
1260 * the COMRESET in mv_phy_reset(). The SERR case requires a
1261 * clear of pending errors in the SATA SERROR register. Finally,
1262 * if the port disabled DMA, update our cached copy to match.
1263 *
1264 * LOCKING:
1265 * Inherited from caller.
1266 */
1267 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1268 {
1269 void __iomem *port_mmio = mv_ap_base(ap);
1270 u32 edma_err_cause, serr = 0;
1271
1272 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1273
1274 if (EDMA_ERR_SERR & edma_err_cause) {
1275 sata_scr_read(ap, SCR_ERROR, &serr);
1276 sata_scr_write_flush(ap, SCR_ERROR, serr);
1277 }
1278 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1279 struct mv_port_priv *pp = ap->private_data;
1280 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1281 }
1282 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1283 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
1284
1285 /* Clear EDMA now that SERR cleanup done */
1286 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1287
1288 /* check for fatal here and recover if needed */
1289 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1290 mv_stop_and_reset(ap);
1291 }
1292
1293 /**
1294 * mv_host_intr - Handle all interrupts on the given host controller
1295 * @host: host specific structure
1296 * @relevant: port error bits relevant to this host controller
1297 * @hc: which host controller we're to look at
1298 *
1299 * Read then write clear the HC interrupt status then walk each
1300 * port connected to the HC and see if it needs servicing. Port
1301 * success ints are reported in the HC interrupt status reg, the
1302 * port error ints are reported in the higher level main
1303 * interrupt status register and thus are passed in via the
1304 * 'relevant' argument.
1305 *
1306 * LOCKING:
1307 * Inherited from caller.
1308 */
1309 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1310 {
1311 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1312 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1313 struct ata_queued_cmd *qc;
1314 u32 hc_irq_cause;
1315 int shift, port, port0, hard_port, handled;
1316 unsigned int err_mask;
1317
1318 if (hc == 0) {
1319 port0 = 0;
1320 } else {
1321 port0 = MV_PORTS_PER_HC;
1322 }
1323
1324 /* we'll need the HC success int register in most cases */
1325 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1326 if (hc_irq_cause) {
1327 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1328 }
1329
1330 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1331 hc,relevant,hc_irq_cause);
1332
1333 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1334 u8 ata_status = 0;
1335 struct ata_port *ap = host->ports[port];
1336 struct mv_port_priv *pp = ap->private_data;
1337
1338 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1339 handled = 0; /* ensure ata_status is set if handled++ */
1340
1341 /* Note that DEV_IRQ might happen spuriously during EDMA,
1342 * and should be ignored in such cases.
1343 * The cause of this is still under investigation.
1344 */
1345 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1346 /* EDMA: check for response queue interrupt */
1347 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1348 ata_status = mv_get_crpb_status(ap);
1349 handled = 1;
1350 }
1351 } else {
1352 /* PIO: check for device (drive) interrupt */
1353 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1354 ata_status = readb(ap->ioaddr.status_addr);
1355 handled = 1;
1356 /* ignore spurious intr if drive still BUSY */
1357 if (ata_status & ATA_BUSY) {
1358 ata_status = 0;
1359 handled = 0;
1360 }
1361 }
1362 }
1363
1364 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1365 continue;
1366
1367 err_mask = ac_err_mask(ata_status);
1368
1369 shift = port << 1; /* (port * 2) */
1370 if (port >= MV_PORTS_PER_HC) {
1371 shift++; /* skip bit 8 in the HC Main IRQ reg */
1372 }
1373 if ((PORT0_ERR << shift) & relevant) {
1374 mv_err_intr(ap, 1);
1375 err_mask |= AC_ERR_OTHER;
1376 handled = 1;
1377 }
1378
1379 if (handled) {
1380 qc = ata_qc_from_tag(ap, ap->active_tag);
1381 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1382 VPRINTK("port %u IRQ found for qc, "
1383 "ata_status 0x%x\n", port,ata_status);
1384 /* mark qc status appropriately */
1385 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1386 qc->err_mask |= err_mask;
1387 ata_qc_complete(qc);
1388 }
1389 }
1390 }
1391 }
1392 VPRINTK("EXIT\n");
1393 }
1394
1395 /**
1396 * mv_interrupt -
1397 * @irq: unused
1398 * @dev_instance: private data; in this case the host structure
1399 * @regs: unused
1400 *
1401 * Read the read only register to determine if any host
1402 * controllers have pending interrupts. If so, call lower level
1403 * routine to handle. Also check for PCI errors which are only
1404 * reported here.
1405 *
1406 * LOCKING:
1407 * This routine holds the host lock while processing pending
1408 * interrupts.
1409 */
1410 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1411 {
1412 struct ata_host *host = dev_instance;
1413 unsigned int hc, handled = 0, n_hcs;
1414 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1415 struct mv_host_priv *hpriv;
1416 u32 irq_stat;
1417
1418 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1419
1420 /* check the cases where we either have nothing pending or have read
1421 * a bogus register value which can indicate HW removal or PCI fault
1422 */
1423 if (!irq_stat || (0xffffffffU == irq_stat)) {
1424 return IRQ_NONE;
1425 }
1426
1427 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1428 spin_lock(&host->lock);
1429
1430 for (hc = 0; hc < n_hcs; hc++) {
1431 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1432 if (relevant) {
1433 mv_host_intr(host, relevant, hc);
1434 handled++;
1435 }
1436 }
1437
1438 hpriv = host->private_data;
1439 if (IS_60XX(hpriv)) {
1440 /* deal with the interrupt coalescing bits */
1441 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1442 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1443 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1444 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1445 }
1446 }
1447
1448 if (PCI_ERR & irq_stat) {
1449 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1450 readl(mmio + PCI_IRQ_CAUSE_OFS));
1451
1452 DPRINTK("All regs @ PCI error\n");
1453 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1454
1455 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1456 handled++;
1457 }
1458 spin_unlock(&host->lock);
1459
1460 return IRQ_RETVAL(handled);
1461 }
1462
1463 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1464 {
1465 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1466 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1467
1468 return hc_mmio + ofs;
1469 }
1470
1471 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1472 {
1473 unsigned int ofs;
1474
1475 switch (sc_reg_in) {
1476 case SCR_STATUS:
1477 case SCR_ERROR:
1478 case SCR_CONTROL:
1479 ofs = sc_reg_in * sizeof(u32);
1480 break;
1481 default:
1482 ofs = 0xffffffffU;
1483 break;
1484 }
1485 return ofs;
1486 }
1487
1488 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1489 {
1490 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1491 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1492 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1493
1494 if (ofs != 0xffffffffU)
1495 return readl(addr + ofs);
1496 else
1497 return (u32) ofs;
1498 }
1499
1500 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1501 {
1502 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1503 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1504 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1505
1506 if (ofs != 0xffffffffU)
1507 writelfl(val, addr + ofs);
1508 }
1509
1510 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1511 {
1512 u8 rev_id;
1513 int early_5080;
1514
1515 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1516
1517 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1518
1519 if (!early_5080) {
1520 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1521 tmp |= (1 << 0);
1522 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1523 }
1524
1525 mv_reset_pci_bus(pdev, mmio);
1526 }
1527
1528 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1529 {
1530 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1531 }
1532
1533 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1534 void __iomem *mmio)
1535 {
1536 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1537 u32 tmp;
1538
1539 tmp = readl(phy_mmio + MV5_PHY_MODE);
1540
1541 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1542 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1543 }
1544
1545 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1546 {
1547 u32 tmp;
1548
1549 writel(0, mmio + MV_GPIO_PORT_CTL);
1550
1551 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1552
1553 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1554 tmp |= ~(1 << 0);
1555 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1556 }
1557
1558 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1559 unsigned int port)
1560 {
1561 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1562 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1563 u32 tmp;
1564 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1565
1566 if (fix_apm_sq) {
1567 tmp = readl(phy_mmio + MV5_LT_MODE);
1568 tmp |= (1 << 19);
1569 writel(tmp, phy_mmio + MV5_LT_MODE);
1570
1571 tmp = readl(phy_mmio + MV5_PHY_CTL);
1572 tmp &= ~0x3;
1573 tmp |= 0x1;
1574 writel(tmp, phy_mmio + MV5_PHY_CTL);
1575 }
1576
1577 tmp = readl(phy_mmio + MV5_PHY_MODE);
1578 tmp &= ~mask;
1579 tmp |= hpriv->signal[port].pre;
1580 tmp |= hpriv->signal[port].amps;
1581 writel(tmp, phy_mmio + MV5_PHY_MODE);
1582 }
1583
1584
1585 #undef ZERO
1586 #define ZERO(reg) writel(0, port_mmio + (reg))
1587 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1588 unsigned int port)
1589 {
1590 void __iomem *port_mmio = mv_port_base(mmio, port);
1591
1592 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1593
1594 mv_channel_reset(hpriv, mmio, port);
1595
1596 ZERO(0x028); /* command */
1597 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1598 ZERO(0x004); /* timer */
1599 ZERO(0x008); /* irq err cause */
1600 ZERO(0x00c); /* irq err mask */
1601 ZERO(0x010); /* rq bah */
1602 ZERO(0x014); /* rq inp */
1603 ZERO(0x018); /* rq outp */
1604 ZERO(0x01c); /* respq bah */
1605 ZERO(0x024); /* respq outp */
1606 ZERO(0x020); /* respq inp */
1607 ZERO(0x02c); /* test control */
1608 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1609 }
1610 #undef ZERO
1611
1612 #define ZERO(reg) writel(0, hc_mmio + (reg))
1613 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1614 unsigned int hc)
1615 {
1616 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1617 u32 tmp;
1618
1619 ZERO(0x00c);
1620 ZERO(0x010);
1621 ZERO(0x014);
1622 ZERO(0x018);
1623
1624 tmp = readl(hc_mmio + 0x20);
1625 tmp &= 0x1c1c1c1c;
1626 tmp |= 0x03030303;
1627 writel(tmp, hc_mmio + 0x20);
1628 }
1629 #undef ZERO
1630
1631 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1632 unsigned int n_hc)
1633 {
1634 unsigned int hc, port;
1635
1636 for (hc = 0; hc < n_hc; hc++) {
1637 for (port = 0; port < MV_PORTS_PER_HC; port++)
1638 mv5_reset_hc_port(hpriv, mmio,
1639 (hc * MV_PORTS_PER_HC) + port);
1640
1641 mv5_reset_one_hc(hpriv, mmio, hc);
1642 }
1643
1644 return 0;
1645 }
1646
1647 #undef ZERO
1648 #define ZERO(reg) writel(0, mmio + (reg))
1649 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1650 {
1651 u32 tmp;
1652
1653 tmp = readl(mmio + MV_PCI_MODE);
1654 tmp &= 0xff00ffff;
1655 writel(tmp, mmio + MV_PCI_MODE);
1656
1657 ZERO(MV_PCI_DISC_TIMER);
1658 ZERO(MV_PCI_MSI_TRIGGER);
1659 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1660 ZERO(HC_MAIN_IRQ_MASK_OFS);
1661 ZERO(MV_PCI_SERR_MASK);
1662 ZERO(PCI_IRQ_CAUSE_OFS);
1663 ZERO(PCI_IRQ_MASK_OFS);
1664 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1665 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1666 ZERO(MV_PCI_ERR_ATTRIBUTE);
1667 ZERO(MV_PCI_ERR_COMMAND);
1668 }
1669 #undef ZERO
1670
1671 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1672 {
1673 u32 tmp;
1674
1675 mv5_reset_flash(hpriv, mmio);
1676
1677 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1678 tmp &= 0x3;
1679 tmp |= (1 << 5) | (1 << 6);
1680 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1681 }
1682
1683 /**
1684 * mv6_reset_hc - Perform the 6xxx global soft reset
1685 * @mmio: base address of the HBA
1686 *
1687 * This routine only applies to 6xxx parts.
1688 *
1689 * LOCKING:
1690 * Inherited from caller.
1691 */
1692 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1693 unsigned int n_hc)
1694 {
1695 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1696 int i, rc = 0;
1697 u32 t;
1698
1699 /* Following procedure defined in PCI "main command and status
1700 * register" table.
1701 */
1702 t = readl(reg);
1703 writel(t | STOP_PCI_MASTER, reg);
1704
1705 for (i = 0; i < 1000; i++) {
1706 udelay(1);
1707 t = readl(reg);
1708 if (PCI_MASTER_EMPTY & t) {
1709 break;
1710 }
1711 }
1712 if (!(PCI_MASTER_EMPTY & t)) {
1713 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1714 rc = 1;
1715 goto done;
1716 }
1717
1718 /* set reset */
1719 i = 5;
1720 do {
1721 writel(t | GLOB_SFT_RST, reg);
1722 t = readl(reg);
1723 udelay(1);
1724 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1725
1726 if (!(GLOB_SFT_RST & t)) {
1727 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1728 rc = 1;
1729 goto done;
1730 }
1731
1732 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1733 i = 5;
1734 do {
1735 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1736 t = readl(reg);
1737 udelay(1);
1738 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1739
1740 if (GLOB_SFT_RST & t) {
1741 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1742 rc = 1;
1743 }
1744 done:
1745 return rc;
1746 }
1747
1748 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1749 void __iomem *mmio)
1750 {
1751 void __iomem *port_mmio;
1752 u32 tmp;
1753
1754 tmp = readl(mmio + MV_RESET_CFG);
1755 if ((tmp & (1 << 0)) == 0) {
1756 hpriv->signal[idx].amps = 0x7 << 8;
1757 hpriv->signal[idx].pre = 0x1 << 5;
1758 return;
1759 }
1760
1761 port_mmio = mv_port_base(mmio, idx);
1762 tmp = readl(port_mmio + PHY_MODE2);
1763
1764 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1765 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1766 }
1767
1768 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1769 {
1770 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1771 }
1772
1773 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1774 unsigned int port)
1775 {
1776 void __iomem *port_mmio = mv_port_base(mmio, port);
1777
1778 u32 hp_flags = hpriv->hp_flags;
1779 int fix_phy_mode2 =
1780 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1781 int fix_phy_mode4 =
1782 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1783 u32 m2, tmp;
1784
1785 if (fix_phy_mode2) {
1786 m2 = readl(port_mmio + PHY_MODE2);
1787 m2 &= ~(1 << 16);
1788 m2 |= (1 << 31);
1789 writel(m2, port_mmio + PHY_MODE2);
1790
1791 udelay(200);
1792
1793 m2 = readl(port_mmio + PHY_MODE2);
1794 m2 &= ~((1 << 16) | (1 << 31));
1795 writel(m2, port_mmio + PHY_MODE2);
1796
1797 udelay(200);
1798 }
1799
1800 /* who knows what this magic does */
1801 tmp = readl(port_mmio + PHY_MODE3);
1802 tmp &= ~0x7F800000;
1803 tmp |= 0x2A800000;
1804 writel(tmp, port_mmio + PHY_MODE3);
1805
1806 if (fix_phy_mode4) {
1807 u32 m4;
1808
1809 m4 = readl(port_mmio + PHY_MODE4);
1810
1811 if (hp_flags & MV_HP_ERRATA_60X1B2)
1812 tmp = readl(port_mmio + 0x310);
1813
1814 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1815
1816 writel(m4, port_mmio + PHY_MODE4);
1817
1818 if (hp_flags & MV_HP_ERRATA_60X1B2)
1819 writel(tmp, port_mmio + 0x310);
1820 }
1821
1822 /* Revert values of pre-emphasis and signal amps to the saved ones */
1823 m2 = readl(port_mmio + PHY_MODE2);
1824
1825 m2 &= ~MV_M2_PREAMP_MASK;
1826 m2 |= hpriv->signal[port].amps;
1827 m2 |= hpriv->signal[port].pre;
1828 m2 &= ~(1 << 16);
1829
1830 /* according to mvSata 3.6.1, some IIE values are fixed */
1831 if (IS_GEN_IIE(hpriv)) {
1832 m2 &= ~0xC30FF01F;
1833 m2 |= 0x0000900F;
1834 }
1835
1836 writel(m2, port_mmio + PHY_MODE2);
1837 }
1838
1839 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1840 unsigned int port_no)
1841 {
1842 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1843
1844 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1845
1846 if (IS_60XX(hpriv)) {
1847 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1848 ifctl |= (1 << 7); /* enable gen2i speed */
1849 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1850 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1851 }
1852
1853 udelay(25); /* allow reset propagation */
1854
1855 /* Spec never mentions clearing the bit. Marvell's driver does
1856 * clear the bit, however.
1857 */
1858 writelfl(0, port_mmio + EDMA_CMD_OFS);
1859
1860 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1861
1862 if (IS_50XX(hpriv))
1863 mdelay(1);
1864 }
1865
1866 static void mv_stop_and_reset(struct ata_port *ap)
1867 {
1868 struct mv_host_priv *hpriv = ap->host->private_data;
1869 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1870
1871 mv_stop_dma(ap);
1872
1873 mv_channel_reset(hpriv, mmio, ap->port_no);
1874
1875 __mv_phy_reset(ap, 0);
1876 }
1877
1878 static inline void __msleep(unsigned int msec, int can_sleep)
1879 {
1880 if (can_sleep)
1881 msleep(msec);
1882 else
1883 mdelay(msec);
1884 }
1885
1886 /**
1887 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1888 * @ap: ATA channel to manipulate
1889 *
1890 * Part of this is taken from __sata_phy_reset and modified to
1891 * not sleep since this routine gets called from interrupt level.
1892 *
1893 * LOCKING:
1894 * Inherited from caller. This is coded to safe to call at
1895 * interrupt level, i.e. it does not sleep.
1896 */
1897 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1898 {
1899 struct mv_port_priv *pp = ap->private_data;
1900 struct mv_host_priv *hpriv = ap->host->private_data;
1901 void __iomem *port_mmio = mv_ap_base(ap);
1902 struct ata_taskfile tf;
1903 struct ata_device *dev = &ap->device[0];
1904 unsigned long timeout;
1905 int retry = 5;
1906 u32 sstatus;
1907
1908 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1909
1910 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1911 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1912 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1913
1914 /* Issue COMRESET via SControl */
1915 comreset_retry:
1916 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1917 __msleep(1, can_sleep);
1918
1919 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1920 __msleep(20, can_sleep);
1921
1922 timeout = jiffies + msecs_to_jiffies(200);
1923 do {
1924 sata_scr_read(ap, SCR_STATUS, &sstatus);
1925 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1926 break;
1927
1928 __msleep(1, can_sleep);
1929 } while (time_before(jiffies, timeout));
1930
1931 /* work around errata */
1932 if (IS_60XX(hpriv) &&
1933 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1934 (retry-- > 0))
1935 goto comreset_retry;
1936
1937 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1938 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1939 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1940
1941 if (ata_port_online(ap)) {
1942 ata_port_probe(ap);
1943 } else {
1944 sata_scr_read(ap, SCR_STATUS, &sstatus);
1945 ata_port_printk(ap, KERN_INFO,
1946 "no device found (phy stat %08x)\n", sstatus);
1947 ata_port_disable(ap);
1948 return;
1949 }
1950 ap->cbl = ATA_CBL_SATA;
1951
1952 /* even after SStatus reflects that device is ready,
1953 * it seems to take a while for link to be fully
1954 * established (and thus Status no longer 0x80/0x7F),
1955 * so we poll a bit for that, here.
1956 */
1957 retry = 20;
1958 while (1) {
1959 u8 drv_stat = ata_check_status(ap);
1960 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1961 break;
1962 __msleep(500, can_sleep);
1963 if (retry-- <= 0)
1964 break;
1965 }
1966
1967 tf.lbah = readb(ap->ioaddr.lbah_addr);
1968 tf.lbam = readb(ap->ioaddr.lbam_addr);
1969 tf.lbal = readb(ap->ioaddr.lbal_addr);
1970 tf.nsect = readb(ap->ioaddr.nsect_addr);
1971
1972 dev->class = ata_dev_classify(&tf);
1973 if (!ata_dev_enabled(dev)) {
1974 VPRINTK("Port disabled post-sig: No device present.\n");
1975 ata_port_disable(ap);
1976 }
1977
1978 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1979
1980 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1981
1982 VPRINTK("EXIT\n");
1983 }
1984
1985 static void mv_phy_reset(struct ata_port *ap)
1986 {
1987 __mv_phy_reset(ap, 1);
1988 }
1989
1990 /**
1991 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1992 * @ap: ATA channel to manipulate
1993 *
1994 * Intent is to clear all pending error conditions, reset the
1995 * chip/bus, fail the command, and move on.
1996 *
1997 * LOCKING:
1998 * This routine holds the host lock while failing the command.
1999 */
2000 static void mv_eng_timeout(struct ata_port *ap)
2001 {
2002 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2003 struct ata_queued_cmd *qc;
2004 unsigned long flags;
2005
2006 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2007 DPRINTK("All regs @ start of eng_timeout\n");
2008 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2009
2010 qc = ata_qc_from_tag(ap, ap->active_tag);
2011 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2012 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2013
2014 spin_lock_irqsave(&ap->host->lock, flags);
2015 mv_err_intr(ap, 0);
2016 mv_stop_and_reset(ap);
2017 spin_unlock_irqrestore(&ap->host->lock, flags);
2018
2019 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2020 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2021 qc->err_mask |= AC_ERR_TIMEOUT;
2022 ata_eh_qc_complete(qc);
2023 }
2024 }
2025
2026 /**
2027 * mv_port_init - Perform some early initialization on a single port.
2028 * @port: libata data structure storing shadow register addresses
2029 * @port_mmio: base address of the port
2030 *
2031 * Initialize shadow register mmio addresses, clear outstanding
2032 * interrupts on the port, and unmask interrupts for the future
2033 * start of the port.
2034 *
2035 * LOCKING:
2036 * Inherited from caller.
2037 */
2038 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2039 {
2040 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2041 unsigned serr_ofs;
2042
2043 /* PIO related setup
2044 */
2045 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2046 port->error_addr =
2047 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2048 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2049 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2050 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2051 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2052 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2053 port->status_addr =
2054 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2055 /* special case: control/altstatus doesn't have ATA_REG_ address */
2056 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2057
2058 /* unused: */
2059 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2060
2061 /* Clear any currently outstanding port interrupt conditions */
2062 serr_ofs = mv_scr_offset(SCR_ERROR);
2063 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2064 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2065
2066 /* unmask all EDMA error interrupts */
2067 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2068
2069 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2070 readl(port_mmio + EDMA_CFG_OFS),
2071 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2072 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2073 }
2074
2075 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2076 unsigned int board_idx)
2077 {
2078 u8 rev_id;
2079 u32 hp_flags = hpriv->hp_flags;
2080
2081 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2082
2083 switch(board_idx) {
2084 case chip_5080:
2085 hpriv->ops = &mv5xxx_ops;
2086 hp_flags |= MV_HP_50XX;
2087
2088 switch (rev_id) {
2089 case 0x1:
2090 hp_flags |= MV_HP_ERRATA_50XXB0;
2091 break;
2092 case 0x3:
2093 hp_flags |= MV_HP_ERRATA_50XXB2;
2094 break;
2095 default:
2096 dev_printk(KERN_WARNING, &pdev->dev,
2097 "Applying 50XXB2 workarounds to unknown rev\n");
2098 hp_flags |= MV_HP_ERRATA_50XXB2;
2099 break;
2100 }
2101 break;
2102
2103 case chip_504x:
2104 case chip_508x:
2105 hpriv->ops = &mv5xxx_ops;
2106 hp_flags |= MV_HP_50XX;
2107
2108 switch (rev_id) {
2109 case 0x0:
2110 hp_flags |= MV_HP_ERRATA_50XXB0;
2111 break;
2112 case 0x3:
2113 hp_flags |= MV_HP_ERRATA_50XXB2;
2114 break;
2115 default:
2116 dev_printk(KERN_WARNING, &pdev->dev,
2117 "Applying B2 workarounds to unknown rev\n");
2118 hp_flags |= MV_HP_ERRATA_50XXB2;
2119 break;
2120 }
2121 break;
2122
2123 case chip_604x:
2124 case chip_608x:
2125 hpriv->ops = &mv6xxx_ops;
2126
2127 switch (rev_id) {
2128 case 0x7:
2129 hp_flags |= MV_HP_ERRATA_60X1B2;
2130 break;
2131 case 0x9:
2132 hp_flags |= MV_HP_ERRATA_60X1C0;
2133 break;
2134 default:
2135 dev_printk(KERN_WARNING, &pdev->dev,
2136 "Applying B2 workarounds to unknown rev\n");
2137 hp_flags |= MV_HP_ERRATA_60X1B2;
2138 break;
2139 }
2140 break;
2141
2142 case chip_7042:
2143 case chip_6042:
2144 hpriv->ops = &mv6xxx_ops;
2145
2146 hp_flags |= MV_HP_GEN_IIE;
2147
2148 switch (rev_id) {
2149 case 0x0:
2150 hp_flags |= MV_HP_ERRATA_XX42A0;
2151 break;
2152 case 0x1:
2153 hp_flags |= MV_HP_ERRATA_60X1C0;
2154 break;
2155 default:
2156 dev_printk(KERN_WARNING, &pdev->dev,
2157 "Applying 60X1C0 workarounds to unknown rev\n");
2158 hp_flags |= MV_HP_ERRATA_60X1C0;
2159 break;
2160 }
2161 break;
2162
2163 default:
2164 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2165 return 1;
2166 }
2167
2168 hpriv->hp_flags = hp_flags;
2169
2170 return 0;
2171 }
2172
2173 /**
2174 * mv_init_host - Perform some early initialization of the host.
2175 * @pdev: host PCI device
2176 * @probe_ent: early data struct representing the host
2177 *
2178 * If possible, do an early global reset of the host. Then do
2179 * our port init and clear/unmask all/relevant host interrupts.
2180 *
2181 * LOCKING:
2182 * Inherited from caller.
2183 */
2184 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2185 unsigned int board_idx)
2186 {
2187 int rc = 0, n_hc, port, hc;
2188 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
2189 struct mv_host_priv *hpriv = probe_ent->private_data;
2190
2191 /* global interrupt mask */
2192 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2193
2194 rc = mv_chip_id(pdev, hpriv, board_idx);
2195 if (rc)
2196 goto done;
2197
2198 n_hc = mv_get_hc_count(probe_ent->port_flags);
2199 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2200
2201 for (port = 0; port < probe_ent->n_ports; port++)
2202 hpriv->ops->read_preamp(hpriv, port, mmio);
2203
2204 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2205 if (rc)
2206 goto done;
2207
2208 hpriv->ops->reset_flash(hpriv, mmio);
2209 hpriv->ops->reset_bus(pdev, mmio);
2210 hpriv->ops->enable_leds(hpriv, mmio);
2211
2212 for (port = 0; port < probe_ent->n_ports; port++) {
2213 if (IS_60XX(hpriv)) {
2214 void __iomem *port_mmio = mv_port_base(mmio, port);
2215
2216 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2217 ifctl |= (1 << 7); /* enable gen2i speed */
2218 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2219 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2220 }
2221
2222 hpriv->ops->phy_errata(hpriv, mmio, port);
2223 }
2224
2225 for (port = 0; port < probe_ent->n_ports; port++) {
2226 void __iomem *port_mmio = mv_port_base(mmio, port);
2227 mv_port_init(&probe_ent->port[port], port_mmio);
2228 }
2229
2230 for (hc = 0; hc < n_hc; hc++) {
2231 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2232
2233 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2234 "(before clear)=0x%08x\n", hc,
2235 readl(hc_mmio + HC_CFG_OFS),
2236 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2237
2238 /* Clear any currently outstanding hc interrupt conditions */
2239 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2240 }
2241
2242 /* Clear any currently outstanding host interrupt conditions */
2243 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2244
2245 /* and unmask interrupt generation for host regs */
2246 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2247 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2248
2249 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2250 "PCI int cause/mask=0x%08x/0x%08x\n",
2251 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2252 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2253 readl(mmio + PCI_IRQ_CAUSE_OFS),
2254 readl(mmio + PCI_IRQ_MASK_OFS));
2255
2256 done:
2257 return rc;
2258 }
2259
2260 /**
2261 * mv_print_info - Dump key info to kernel log for perusal.
2262 * @probe_ent: early data struct representing the host
2263 *
2264 * FIXME: complete this.
2265 *
2266 * LOCKING:
2267 * Inherited from caller.
2268 */
2269 static void mv_print_info(struct ata_probe_ent *probe_ent)
2270 {
2271 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2272 struct mv_host_priv *hpriv = probe_ent->private_data;
2273 u8 rev_id, scc;
2274 const char *scc_s;
2275
2276 /* Use this to determine the HW stepping of the chip so we know
2277 * what errata to workaround
2278 */
2279 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2280
2281 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2282 if (scc == 0)
2283 scc_s = "SCSI";
2284 else if (scc == 0x01)
2285 scc_s = "RAID";
2286 else
2287 scc_s = "unknown";
2288
2289 dev_printk(KERN_INFO, &pdev->dev,
2290 "%u slots %u ports %s mode IRQ via %s\n",
2291 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2292 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2293 }
2294
2295 /**
2296 * mv_init_one - handle a positive probe of a Marvell host
2297 * @pdev: PCI device found
2298 * @ent: PCI device ID entry for the matched host
2299 *
2300 * LOCKING:
2301 * Inherited from caller.
2302 */
2303 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2304 {
2305 static int printed_version = 0;
2306 struct device *dev = &pdev->dev;
2307 struct ata_probe_ent *probe_ent;
2308 struct mv_host_priv *hpriv;
2309 unsigned int board_idx = (unsigned int)ent->driver_data;
2310 int rc;
2311
2312 if (!printed_version++)
2313 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2314
2315 rc = pcim_enable_device(pdev);
2316 if (rc)
2317 return rc;
2318 pci_set_master(pdev);
2319
2320 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2321 if (rc == -EBUSY)
2322 pcim_pin_device(pdev);
2323 if (rc)
2324 return rc;
2325
2326 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2327 if (probe_ent == NULL)
2328 return -ENOMEM;
2329
2330 probe_ent->dev = pci_dev_to_dev(pdev);
2331 INIT_LIST_HEAD(&probe_ent->node);
2332
2333 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2334 if (!hpriv)
2335 return -ENOMEM;
2336
2337 probe_ent->sht = mv_port_info[board_idx].sht;
2338 probe_ent->port_flags = mv_port_info[board_idx].flags;
2339 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2340 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2341 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2342
2343 probe_ent->irq = pdev->irq;
2344 probe_ent->irq_flags = IRQF_SHARED;
2345 probe_ent->iomap = pcim_iomap_table(pdev);
2346 probe_ent->private_data = hpriv;
2347
2348 /* initialize adapter */
2349 rc = mv_init_host(pdev, probe_ent, board_idx);
2350 if (rc)
2351 return rc;
2352
2353 /* Enable interrupts */
2354 if (msi && pci_enable_msi(pdev))
2355 pci_intx(pdev, 1);
2356
2357 mv_dump_pci_cfg(pdev, 0x68);
2358 mv_print_info(probe_ent);
2359
2360 if (ata_device_add(probe_ent) == 0)
2361 return -ENODEV;
2362
2363 devm_kfree(dev, probe_ent);
2364 return 0;
2365 }
2366
2367 static int __init mv_init(void)
2368 {
2369 return pci_register_driver(&mv_pci_driver);
2370 }
2371
2372 static void __exit mv_exit(void)
2373 {
2374 pci_unregister_driver(&mv_pci_driver);
2375 }
2376
2377 MODULE_AUTHOR("Brett Russ");
2378 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2379 MODULE_LICENSE("GPL");
2380 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2381 MODULE_VERSION(DRV_VERSION);
2382
2383 module_param(msi, int, 0444);
2384 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2385
2386 module_init(mv_init);
2387 module_exit(mv_exit);
Linux kernel - Deliverables
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