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sata_nv: cleanup CPB and APRD initialization
[deliverable/linux.git] / drivers / ata / sata_nv.c
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 * CK804/MCP04 controllers support an alternate programming interface
33 * similar to the ADMA specification (with some modifications).
34 * This allows the use of NCQ. Non-DMA-mapped ATA commands are still
35 * sent through the legacy interface.
36 *
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/device.h>
47 #include <scsi/scsi_host.h>
48 #include <scsi/scsi_device.h>
49 #include <linux/libata.h>
50
51 #define DRV_NAME "sata_nv"
52 #define DRV_VERSION "3.3"
53
54 #define NV_ADMA_DMA_BOUNDARY 0xffffffffUL
55
56 enum {
57 NV_MMIO_BAR = 5,
58
59 NV_PORTS = 2,
60 NV_PIO_MASK = 0x1f,
61 NV_MWDMA_MASK = 0x07,
62 NV_UDMA_MASK = 0x7f,
63 NV_PORT0_SCR_REG_OFFSET = 0x00,
64 NV_PORT1_SCR_REG_OFFSET = 0x40,
65
66 /* INT_STATUS/ENABLE */
67 NV_INT_STATUS = 0x10,
68 NV_INT_ENABLE = 0x11,
69 NV_INT_STATUS_CK804 = 0x440,
70 NV_INT_ENABLE_CK804 = 0x441,
71
72 /* INT_STATUS/ENABLE bits */
73 NV_INT_DEV = 0x01,
74 NV_INT_PM = 0x02,
75 NV_INT_ADDED = 0x04,
76 NV_INT_REMOVED = 0x08,
77
78 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
79
80 NV_INT_ALL = 0x0f,
81 NV_INT_MASK = NV_INT_DEV |
82 NV_INT_ADDED | NV_INT_REMOVED,
83
84 /* INT_CONFIG */
85 NV_INT_CONFIG = 0x12,
86 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
87
88 // For PCI config register 20
89 NV_MCP_SATA_CFG_20 = 0x50,
90 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
91 NV_MCP_SATA_CFG_20_PORT0_EN = (1 << 17),
92 NV_MCP_SATA_CFG_20_PORT1_EN = (1 << 16),
93 NV_MCP_SATA_CFG_20_PORT0_PWB_EN = (1 << 14),
94 NV_MCP_SATA_CFG_20_PORT1_PWB_EN = (1 << 12),
95
96 NV_ADMA_MAX_CPBS = 32,
97 NV_ADMA_CPB_SZ = 128,
98 NV_ADMA_APRD_SZ = 16,
99 NV_ADMA_SGTBL_LEN = (1024 - NV_ADMA_CPB_SZ) /
100 NV_ADMA_APRD_SZ,
101 NV_ADMA_SGTBL_TOTAL_LEN = NV_ADMA_SGTBL_LEN + 5,
102 NV_ADMA_SGTBL_SZ = NV_ADMA_SGTBL_LEN * NV_ADMA_APRD_SZ,
103 NV_ADMA_PORT_PRIV_DMA_SZ = NV_ADMA_MAX_CPBS *
104 (NV_ADMA_CPB_SZ + NV_ADMA_SGTBL_SZ),
105
106 /* BAR5 offset to ADMA general registers */
107 NV_ADMA_GEN = 0x400,
108 NV_ADMA_GEN_CTL = 0x00,
109 NV_ADMA_NOTIFIER_CLEAR = 0x30,
110
111 /* BAR5 offset to ADMA ports */
112 NV_ADMA_PORT = 0x480,
113
114 /* size of ADMA port register space */
115 NV_ADMA_PORT_SIZE = 0x100,
116
117 /* ADMA port registers */
118 NV_ADMA_CTL = 0x40,
119 NV_ADMA_CPB_COUNT = 0x42,
120 NV_ADMA_NEXT_CPB_IDX = 0x43,
121 NV_ADMA_STAT = 0x44,
122 NV_ADMA_CPB_BASE_LOW = 0x48,
123 NV_ADMA_CPB_BASE_HIGH = 0x4C,
124 NV_ADMA_APPEND = 0x50,
125 NV_ADMA_NOTIFIER = 0x68,
126 NV_ADMA_NOTIFIER_ERROR = 0x6C,
127
128 /* NV_ADMA_CTL register bits */
129 NV_ADMA_CTL_HOTPLUG_IEN = (1 << 0),
130 NV_ADMA_CTL_CHANNEL_RESET = (1 << 5),
131 NV_ADMA_CTL_GO = (1 << 7),
132 NV_ADMA_CTL_AIEN = (1 << 8),
133 NV_ADMA_CTL_READ_NON_COHERENT = (1 << 11),
134 NV_ADMA_CTL_WRITE_NON_COHERENT = (1 << 12),
135
136 /* CPB response flag bits */
137 NV_CPB_RESP_DONE = (1 << 0),
138 NV_CPB_RESP_ATA_ERR = (1 << 3),
139 NV_CPB_RESP_CMD_ERR = (1 << 4),
140 NV_CPB_RESP_CPB_ERR = (1 << 7),
141
142 /* CPB control flag bits */
143 NV_CPB_CTL_CPB_VALID = (1 << 0),
144 NV_CPB_CTL_QUEUE = (1 << 1),
145 NV_CPB_CTL_APRD_VALID = (1 << 2),
146 NV_CPB_CTL_IEN = (1 << 3),
147 NV_CPB_CTL_FPDMA = (1 << 4),
148
149 /* APRD flags */
150 NV_APRD_WRITE = (1 << 1),
151 NV_APRD_END = (1 << 2),
152 NV_APRD_CONT = (1 << 3),
153
154 /* NV_ADMA_STAT flags */
155 NV_ADMA_STAT_TIMEOUT = (1 << 0),
156 NV_ADMA_STAT_HOTUNPLUG = (1 << 1),
157 NV_ADMA_STAT_HOTPLUG = (1 << 2),
158 NV_ADMA_STAT_CPBERR = (1 << 4),
159 NV_ADMA_STAT_SERROR = (1 << 5),
160 NV_ADMA_STAT_CMD_COMPLETE = (1 << 6),
161 NV_ADMA_STAT_IDLE = (1 << 8),
162 NV_ADMA_STAT_LEGACY = (1 << 9),
163 NV_ADMA_STAT_STOPPED = (1 << 10),
164 NV_ADMA_STAT_DONE = (1 << 12),
165 NV_ADMA_STAT_ERR = NV_ADMA_STAT_CPBERR |
166 NV_ADMA_STAT_TIMEOUT,
167
168 /* port flags */
169 NV_ADMA_PORT_REGISTER_MODE = (1 << 0),
170 NV_ADMA_ATAPI_SETUP_COMPLETE = (1 << 1),
171
172 };
173
174 /* ADMA Physical Region Descriptor - one SG segment */
175 struct nv_adma_prd {
176 __le64 addr;
177 __le32 len;
178 u8 flags;
179 u8 packet_len;
180 __le16 reserved;
181 };
182
183 enum nv_adma_regbits {
184 CMDEND = (1 << 15), /* end of command list */
185 WNB = (1 << 14), /* wait-not-BSY */
186 IGN = (1 << 13), /* ignore this entry */
187 CS1n = (1 << (4 + 8)), /* std. PATA signals follow... */
188 DA2 = (1 << (2 + 8)),
189 DA1 = (1 << (1 + 8)),
190 DA0 = (1 << (0 + 8)),
191 };
192
193 /* ADMA Command Parameter Block
194 The first 5 SG segments are stored inside the Command Parameter Block itself.
195 If there are more than 5 segments the remainder are stored in a separate
196 memory area indicated by next_aprd. */
197 struct nv_adma_cpb {
198 u8 resp_flags; /* 0 */
199 u8 reserved1; /* 1 */
200 u8 ctl_flags; /* 2 */
201 /* len is length of taskfile in 64 bit words */
202 u8 len; /* 3 */
203 u8 tag; /* 4 */
204 u8 next_cpb_idx; /* 5 */
205 __le16 reserved2; /* 6-7 */
206 __le16 tf[12]; /* 8-31 */
207 struct nv_adma_prd aprd[5]; /* 32-111 */
208 __le64 next_aprd; /* 112-119 */
209 __le64 reserved3; /* 120-127 */
210 };
211
212
213 struct nv_adma_port_priv {
214 struct nv_adma_cpb *cpb;
215 dma_addr_t cpb_dma;
216 struct nv_adma_prd *aprd;
217 dma_addr_t aprd_dma;
218 void __iomem * ctl_block;
219 void __iomem * gen_block;
220 void __iomem * notifier_clear_block;
221 u8 flags;
222 int last_issue_ncq;
223 };
224
225 struct nv_host_priv {
226 unsigned long type;
227 };
228
229 #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & ( 1 << (19 + (12 * (PORT)))))
230
231 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
232 static void nv_remove_one (struct pci_dev *pdev);
233 static int nv_pci_device_resume(struct pci_dev *pdev);
234 static void nv_ck804_host_stop(struct ata_host *host);
235 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance);
236 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance);
237 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance);
238 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
239 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
240
241 static void nv_nf2_freeze(struct ata_port *ap);
242 static void nv_nf2_thaw(struct ata_port *ap);
243 static void nv_ck804_freeze(struct ata_port *ap);
244 static void nv_ck804_thaw(struct ata_port *ap);
245 static void nv_error_handler(struct ata_port *ap);
246 static int nv_adma_slave_config(struct scsi_device *sdev);
247 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc);
248 static void nv_adma_qc_prep(struct ata_queued_cmd *qc);
249 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc);
250 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance);
251 static void nv_adma_irq_clear(struct ata_port *ap);
252 static int nv_adma_port_start(struct ata_port *ap);
253 static void nv_adma_port_stop(struct ata_port *ap);
254 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg);
255 static int nv_adma_port_resume(struct ata_port *ap);
256 static void nv_adma_error_handler(struct ata_port *ap);
257 static void nv_adma_host_stop(struct ata_host *host);
258 static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc);
259 static void nv_adma_bmdma_start(struct ata_queued_cmd *qc);
260 static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc);
261 static u8 nv_adma_bmdma_status(struct ata_port *ap);
262
263 enum nv_host_type
264 {
265 GENERIC,
266 NFORCE2,
267 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
268 CK804,
269 ADMA
270 };
271
272 static const struct pci_device_id nv_pci_tbl[] = {
273 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 },
274 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 },
275 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 },
276 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 },
277 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 },
278 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 },
279 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 },
280 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC },
281 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC },
282 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC },
283 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC },
284 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC },
285 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC },
286 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC },
287 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
288 PCI_ANY_ID, PCI_ANY_ID,
289 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
290 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
291 PCI_ANY_ID, PCI_ANY_ID,
292 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
293
294 { } /* terminate list */
295 };
296
297 static struct pci_driver nv_pci_driver = {
298 .name = DRV_NAME,
299 .id_table = nv_pci_tbl,
300 .probe = nv_init_one,
301 .suspend = ata_pci_device_suspend,
302 .resume = nv_pci_device_resume,
303 .remove = nv_remove_one,
304 };
305
306 static struct scsi_host_template nv_sht = {
307 .module = THIS_MODULE,
308 .name = DRV_NAME,
309 .ioctl = ata_scsi_ioctl,
310 .queuecommand = ata_scsi_queuecmd,
311 .can_queue = ATA_DEF_QUEUE,
312 .this_id = ATA_SHT_THIS_ID,
313 .sg_tablesize = LIBATA_MAX_PRD,
314 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
315 .emulated = ATA_SHT_EMULATED,
316 .use_clustering = ATA_SHT_USE_CLUSTERING,
317 .proc_name = DRV_NAME,
318 .dma_boundary = ATA_DMA_BOUNDARY,
319 .slave_configure = ata_scsi_slave_config,
320 .slave_destroy = ata_scsi_slave_destroy,
321 .bios_param = ata_std_bios_param,
322 .suspend = ata_scsi_device_suspend,
323 .resume = ata_scsi_device_resume,
324 };
325
326 static struct scsi_host_template nv_adma_sht = {
327 .module = THIS_MODULE,
328 .name = DRV_NAME,
329 .ioctl = ata_scsi_ioctl,
330 .queuecommand = ata_scsi_queuecmd,
331 .can_queue = NV_ADMA_MAX_CPBS,
332 .this_id = ATA_SHT_THIS_ID,
333 .sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN,
334 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
335 .emulated = ATA_SHT_EMULATED,
336 .use_clustering = ATA_SHT_USE_CLUSTERING,
337 .proc_name = DRV_NAME,
338 .dma_boundary = NV_ADMA_DMA_BOUNDARY,
339 .slave_configure = nv_adma_slave_config,
340 .slave_destroy = ata_scsi_slave_destroy,
341 .bios_param = ata_std_bios_param,
342 .suspend = ata_scsi_device_suspend,
343 .resume = ata_scsi_device_resume,
344 };
345
346 static const struct ata_port_operations nv_generic_ops = {
347 .port_disable = ata_port_disable,
348 .tf_load = ata_tf_load,
349 .tf_read = ata_tf_read,
350 .exec_command = ata_exec_command,
351 .check_status = ata_check_status,
352 .dev_select = ata_std_dev_select,
353 .bmdma_setup = ata_bmdma_setup,
354 .bmdma_start = ata_bmdma_start,
355 .bmdma_stop = ata_bmdma_stop,
356 .bmdma_status = ata_bmdma_status,
357 .qc_prep = ata_qc_prep,
358 .qc_issue = ata_qc_issue_prot,
359 .freeze = ata_bmdma_freeze,
360 .thaw = ata_bmdma_thaw,
361 .error_handler = nv_error_handler,
362 .post_internal_cmd = ata_bmdma_post_internal_cmd,
363 .data_xfer = ata_data_xfer,
364 .irq_handler = nv_generic_interrupt,
365 .irq_clear = ata_bmdma_irq_clear,
366 .irq_on = ata_irq_on,
367 .irq_ack = ata_irq_ack,
368 .scr_read = nv_scr_read,
369 .scr_write = nv_scr_write,
370 .port_start = ata_port_start,
371 };
372
373 static const struct ata_port_operations nv_nf2_ops = {
374 .port_disable = ata_port_disable,
375 .tf_load = ata_tf_load,
376 .tf_read = ata_tf_read,
377 .exec_command = ata_exec_command,
378 .check_status = ata_check_status,
379 .dev_select = ata_std_dev_select,
380 .bmdma_setup = ata_bmdma_setup,
381 .bmdma_start = ata_bmdma_start,
382 .bmdma_stop = ata_bmdma_stop,
383 .bmdma_status = ata_bmdma_status,
384 .qc_prep = ata_qc_prep,
385 .qc_issue = ata_qc_issue_prot,
386 .freeze = nv_nf2_freeze,
387 .thaw = nv_nf2_thaw,
388 .error_handler = nv_error_handler,
389 .post_internal_cmd = ata_bmdma_post_internal_cmd,
390 .data_xfer = ata_data_xfer,
391 .irq_handler = nv_nf2_interrupt,
392 .irq_clear = ata_bmdma_irq_clear,
393 .irq_on = ata_irq_on,
394 .irq_ack = ata_irq_ack,
395 .scr_read = nv_scr_read,
396 .scr_write = nv_scr_write,
397 .port_start = ata_port_start,
398 };
399
400 static const struct ata_port_operations nv_ck804_ops = {
401 .port_disable = ata_port_disable,
402 .tf_load = ata_tf_load,
403 .tf_read = ata_tf_read,
404 .exec_command = ata_exec_command,
405 .check_status = ata_check_status,
406 .dev_select = ata_std_dev_select,
407 .bmdma_setup = ata_bmdma_setup,
408 .bmdma_start = ata_bmdma_start,
409 .bmdma_stop = ata_bmdma_stop,
410 .bmdma_status = ata_bmdma_status,
411 .qc_prep = ata_qc_prep,
412 .qc_issue = ata_qc_issue_prot,
413 .freeze = nv_ck804_freeze,
414 .thaw = nv_ck804_thaw,
415 .error_handler = nv_error_handler,
416 .post_internal_cmd = ata_bmdma_post_internal_cmd,
417 .data_xfer = ata_data_xfer,
418 .irq_handler = nv_ck804_interrupt,
419 .irq_clear = ata_bmdma_irq_clear,
420 .irq_on = ata_irq_on,
421 .irq_ack = ata_irq_ack,
422 .scr_read = nv_scr_read,
423 .scr_write = nv_scr_write,
424 .port_start = ata_port_start,
425 .host_stop = nv_ck804_host_stop,
426 };
427
428 static const struct ata_port_operations nv_adma_ops = {
429 .port_disable = ata_port_disable,
430 .tf_load = ata_tf_load,
431 .tf_read = ata_tf_read,
432 .check_atapi_dma = nv_adma_check_atapi_dma,
433 .exec_command = ata_exec_command,
434 .check_status = ata_check_status,
435 .dev_select = ata_std_dev_select,
436 .bmdma_setup = nv_adma_bmdma_setup,
437 .bmdma_start = nv_adma_bmdma_start,
438 .bmdma_stop = nv_adma_bmdma_stop,
439 .bmdma_status = nv_adma_bmdma_status,
440 .qc_prep = nv_adma_qc_prep,
441 .qc_issue = nv_adma_qc_issue,
442 .freeze = nv_ck804_freeze,
443 .thaw = nv_ck804_thaw,
444 .error_handler = nv_adma_error_handler,
445 .post_internal_cmd = nv_adma_bmdma_stop,
446 .data_xfer = ata_data_xfer,
447 .irq_handler = nv_adma_interrupt,
448 .irq_clear = nv_adma_irq_clear,
449 .irq_on = ata_irq_on,
450 .irq_ack = ata_irq_ack,
451 .scr_read = nv_scr_read,
452 .scr_write = nv_scr_write,
453 .port_start = nv_adma_port_start,
454 .port_stop = nv_adma_port_stop,
455 .port_suspend = nv_adma_port_suspend,
456 .port_resume = nv_adma_port_resume,
457 .host_stop = nv_adma_host_stop,
458 };
459
460 static struct ata_port_info nv_port_info[] = {
461 /* generic */
462 {
463 .sht = &nv_sht,
464 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
465 ATA_FLAG_HRST_TO_RESUME,
466 .pio_mask = NV_PIO_MASK,
467 .mwdma_mask = NV_MWDMA_MASK,
468 .udma_mask = NV_UDMA_MASK,
469 .port_ops = &nv_generic_ops,
470 },
471 /* nforce2/3 */
472 {
473 .sht = &nv_sht,
474 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
475 ATA_FLAG_HRST_TO_RESUME,
476 .pio_mask = NV_PIO_MASK,
477 .mwdma_mask = NV_MWDMA_MASK,
478 .udma_mask = NV_UDMA_MASK,
479 .port_ops = &nv_nf2_ops,
480 },
481 /* ck804 */
482 {
483 .sht = &nv_sht,
484 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
485 ATA_FLAG_HRST_TO_RESUME,
486 .pio_mask = NV_PIO_MASK,
487 .mwdma_mask = NV_MWDMA_MASK,
488 .udma_mask = NV_UDMA_MASK,
489 .port_ops = &nv_ck804_ops,
490 },
491 /* ADMA */
492 {
493 .sht = &nv_adma_sht,
494 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
495 ATA_FLAG_HRST_TO_RESUME |
496 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
497 .pio_mask = NV_PIO_MASK,
498 .mwdma_mask = NV_MWDMA_MASK,
499 .udma_mask = NV_UDMA_MASK,
500 .port_ops = &nv_adma_ops,
501 },
502 };
503
504 MODULE_AUTHOR("NVIDIA");
505 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
506 MODULE_LICENSE("GPL");
507 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
508 MODULE_VERSION(DRV_VERSION);
509
510 static int adma_enabled = 1;
511
512 static void nv_adma_register_mode(struct ata_port *ap)
513 {
514 struct nv_adma_port_priv *pp = ap->private_data;
515 void __iomem *mmio = pp->ctl_block;
516 u16 tmp, status;
517 int count = 0;
518
519 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE)
520 return;
521
522 status = readw(mmio + NV_ADMA_STAT);
523 while(!(status & NV_ADMA_STAT_IDLE) && count < 20) {
524 ndelay(50);
525 status = readw(mmio + NV_ADMA_STAT);
526 count++;
527 }
528 if(count == 20)
529 ata_port_printk(ap, KERN_WARNING,
530 "timeout waiting for ADMA IDLE, stat=0x%hx\n",
531 status);
532
533 tmp = readw(mmio + NV_ADMA_CTL);
534 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
535
536 count = 0;
537 status = readw(mmio + NV_ADMA_STAT);
538 while(!(status & NV_ADMA_STAT_LEGACY) && count < 20) {
539 ndelay(50);
540 status = readw(mmio + NV_ADMA_STAT);
541 count++;
542 }
543 if(count == 20)
544 ata_port_printk(ap, KERN_WARNING,
545 "timeout waiting for ADMA LEGACY, stat=0x%hx\n",
546 status);
547
548 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
549 }
550
551 static void nv_adma_mode(struct ata_port *ap)
552 {
553 struct nv_adma_port_priv *pp = ap->private_data;
554 void __iomem *mmio = pp->ctl_block;
555 u16 tmp, status;
556 int count = 0;
557
558 if (!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
559 return;
560
561 WARN_ON(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
562
563 tmp = readw(mmio + NV_ADMA_CTL);
564 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
565
566 status = readw(mmio + NV_ADMA_STAT);
567 while(((status & NV_ADMA_STAT_LEGACY) ||
568 !(status & NV_ADMA_STAT_IDLE)) && count < 20) {
569 ndelay(50);
570 status = readw(mmio + NV_ADMA_STAT);
571 count++;
572 }
573 if(count == 20)
574 ata_port_printk(ap, KERN_WARNING,
575 "timeout waiting for ADMA LEGACY clear and IDLE, stat=0x%hx\n",
576 status);
577
578 pp->flags &= ~NV_ADMA_PORT_REGISTER_MODE;
579 }
580
581 static int nv_adma_slave_config(struct scsi_device *sdev)
582 {
583 struct ata_port *ap = ata_shost_to_port(sdev->host);
584 struct nv_adma_port_priv *pp = ap->private_data;
585 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
586 u64 bounce_limit;
587 unsigned long segment_boundary;
588 unsigned short sg_tablesize;
589 int rc;
590 int adma_enable;
591 u32 current_reg, new_reg, config_mask;
592
593 rc = ata_scsi_slave_config(sdev);
594
595 if (sdev->id >= ATA_MAX_DEVICES || sdev->channel || sdev->lun)
596 /* Not a proper libata device, ignore */
597 return rc;
598
599 if (ap->device[sdev->id].class == ATA_DEV_ATAPI) {
600 /*
601 * NVIDIA reports that ADMA mode does not support ATAPI commands.
602 * Therefore ATAPI commands are sent through the legacy interface.
603 * However, the legacy interface only supports 32-bit DMA.
604 * Restrict DMA parameters as required by the legacy interface
605 * when an ATAPI device is connected.
606 */
607 bounce_limit = ATA_DMA_MASK;
608 segment_boundary = ATA_DMA_BOUNDARY;
609 /* Subtract 1 since an extra entry may be needed for padding, see
610 libata-scsi.c */
611 sg_tablesize = LIBATA_MAX_PRD - 1;
612
613 /* Since the legacy DMA engine is in use, we need to disable ADMA
614 on the port. */
615 adma_enable = 0;
616 nv_adma_register_mode(ap);
617 }
618 else {
619 bounce_limit = *ap->dev->dma_mask;
620 segment_boundary = NV_ADMA_DMA_BOUNDARY;
621 sg_tablesize = NV_ADMA_SGTBL_TOTAL_LEN;
622 adma_enable = 1;
623 }
624
625 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &current_reg);
626
627 if(ap->port_no == 1)
628 config_mask = NV_MCP_SATA_CFG_20_PORT1_EN |
629 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
630 else
631 config_mask = NV_MCP_SATA_CFG_20_PORT0_EN |
632 NV_MCP_SATA_CFG_20_PORT0_PWB_EN;
633
634 if(adma_enable) {
635 new_reg = current_reg | config_mask;
636 pp->flags &= ~NV_ADMA_ATAPI_SETUP_COMPLETE;
637 }
638 else {
639 new_reg = current_reg & ~config_mask;
640 pp->flags |= NV_ADMA_ATAPI_SETUP_COMPLETE;
641 }
642
643 if(current_reg != new_reg)
644 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, new_reg);
645
646 blk_queue_bounce_limit(sdev->request_queue, bounce_limit);
647 blk_queue_segment_boundary(sdev->request_queue, segment_boundary);
648 blk_queue_max_hw_segments(sdev->request_queue, sg_tablesize);
649 ata_port_printk(ap, KERN_INFO,
650 "bounce limit 0x%llX, segment boundary 0x%lX, hw segs %hu\n",
651 (unsigned long long)bounce_limit, segment_boundary, sg_tablesize);
652 return rc;
653 }
654
655 static int nv_adma_check_atapi_dma(struct ata_queued_cmd *qc)
656 {
657 struct nv_adma_port_priv *pp = qc->ap->private_data;
658 return !(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE);
659 }
660
661 static unsigned int nv_adma_tf_to_cpb(struct ata_taskfile *tf, __le16 *cpb)
662 {
663 unsigned int idx = 0;
664
665 cpb[idx++] = cpu_to_le16((ATA_REG_DEVICE << 8) | tf->device | WNB);
666
667 if ((tf->flags & ATA_TFLAG_LBA48) == 0) {
668 cpb[idx++] = cpu_to_le16(IGN);
669 cpb[idx++] = cpu_to_le16(IGN);
670 cpb[idx++] = cpu_to_le16(IGN);
671 cpb[idx++] = cpu_to_le16(IGN);
672 cpb[idx++] = cpu_to_le16(IGN);
673 }
674 else {
675 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->hob_feature);
676 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->hob_nsect);
677 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->hob_lbal);
678 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->hob_lbam);
679 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->hob_lbah);
680 }
681 cpb[idx++] = cpu_to_le16((ATA_REG_ERR << 8) | tf->feature);
682 cpb[idx++] = cpu_to_le16((ATA_REG_NSECT << 8) | tf->nsect);
683 cpb[idx++] = cpu_to_le16((ATA_REG_LBAL << 8) | tf->lbal);
684 cpb[idx++] = cpu_to_le16((ATA_REG_LBAM << 8) | tf->lbam);
685 cpb[idx++] = cpu_to_le16((ATA_REG_LBAH << 8) | tf->lbah);
686
687 cpb[idx++] = cpu_to_le16((ATA_REG_CMD << 8) | tf->command | CMDEND);
688
689 return idx;
690 }
691
692 static int nv_adma_check_cpb(struct ata_port *ap, int cpb_num, int force_err)
693 {
694 struct nv_adma_port_priv *pp = ap->private_data;
695 u8 flags = pp->cpb[cpb_num].resp_flags;
696
697 VPRINTK("CPB %d, flags=0x%x\n", cpb_num, flags);
698
699 if (unlikely((force_err ||
700 flags & (NV_CPB_RESP_ATA_ERR |
701 NV_CPB_RESP_CMD_ERR |
702 NV_CPB_RESP_CPB_ERR)))) {
703 struct ata_eh_info *ehi = &ap->eh_info;
704 int freeze = 0;
705
706 ata_ehi_clear_desc(ehi);
707 ata_ehi_push_desc(ehi, "CPB resp_flags 0x%x", flags );
708 if (flags & NV_CPB_RESP_ATA_ERR) {
709 ata_ehi_push_desc(ehi, ": ATA error");
710 ehi->err_mask |= AC_ERR_DEV;
711 } else if (flags & NV_CPB_RESP_CMD_ERR) {
712 ata_ehi_push_desc(ehi, ": CMD error");
713 ehi->err_mask |= AC_ERR_DEV;
714 } else if (flags & NV_CPB_RESP_CPB_ERR) {
715 ata_ehi_push_desc(ehi, ": CPB error");
716 ehi->err_mask |= AC_ERR_SYSTEM;
717 freeze = 1;
718 } else {
719 /* notifier error, but no error in CPB flags? */
720 ehi->err_mask |= AC_ERR_OTHER;
721 freeze = 1;
722 }
723 /* Kill all commands. EH will determine what actually failed. */
724 if (freeze)
725 ata_port_freeze(ap);
726 else
727 ata_port_abort(ap);
728 return 1;
729 }
730
731 if (flags & NV_CPB_RESP_DONE) {
732 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, cpb_num);
733 VPRINTK("CPB flags done, flags=0x%x\n", flags);
734 if (likely(qc)) {
735 /* Grab the ATA port status for non-NCQ commands.
736 For NCQ commands the current status may have nothing to do with
737 the command just completed. */
738 if (qc->tf.protocol != ATA_PROT_NCQ) {
739 u8 ata_status = readb(pp->ctl_block + (ATA_REG_STATUS * 4));
740 qc->err_mask |= ac_err_mask(ata_status);
741 }
742 DPRINTK("Completing qc from tag %d with err_mask %u\n",cpb_num,
743 qc->err_mask);
744 ata_qc_complete(qc);
745 }
746 }
747 return 0;
748 }
749
750 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
751 {
752 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
753
754 /* freeze if hotplugged */
755 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
756 ata_port_freeze(ap);
757 return 1;
758 }
759
760 /* bail out if not our interrupt */
761 if (!(irq_stat & NV_INT_DEV))
762 return 0;
763
764 /* DEV interrupt w/ no active qc? */
765 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
766 ata_check_status(ap);
767 return 1;
768 }
769
770 /* handle interrupt */
771 return ata_host_intr(ap, qc);
772 }
773
774 static irqreturn_t nv_adma_interrupt(int irq, void *dev_instance)
775 {
776 struct ata_host *host = dev_instance;
777 int i, handled = 0;
778 u32 notifier_clears[2];
779
780 spin_lock(&host->lock);
781
782 for (i = 0; i < host->n_ports; i++) {
783 struct ata_port *ap = host->ports[i];
784 notifier_clears[i] = 0;
785
786 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
787 struct nv_adma_port_priv *pp = ap->private_data;
788 void __iomem *mmio = pp->ctl_block;
789 u16 status;
790 u32 gen_ctl;
791 u32 notifier, notifier_error;
792
793 /* if in ATA register mode, use standard ata interrupt handler */
794 if (pp->flags & NV_ADMA_PORT_REGISTER_MODE) {
795 u8 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804)
796 >> (NV_INT_PORT_SHIFT * i);
797 if(ata_tag_valid(ap->active_tag))
798 /** NV_INT_DEV indication seems unreliable at times
799 at least in ADMA mode. Force it on always when a
800 command is active, to prevent losing interrupts. */
801 irq_stat |= NV_INT_DEV;
802 handled += nv_host_intr(ap, irq_stat);
803 continue;
804 }
805
806 notifier = readl(mmio + NV_ADMA_NOTIFIER);
807 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
808 notifier_clears[i] = notifier | notifier_error;
809
810 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
811
812 if( !NV_ADMA_CHECK_INTR(gen_ctl, ap->port_no) && !notifier &&
813 !notifier_error)
814 /* Nothing to do */
815 continue;
816
817 status = readw(mmio + NV_ADMA_STAT);
818
819 /* Clear status. Ensure the controller sees the clearing before we start
820 looking at any of the CPB statuses, so that any CPB completions after
821 this point in the handler will raise another interrupt. */
822 writew(status, mmio + NV_ADMA_STAT);
823 readw(mmio + NV_ADMA_STAT); /* flush posted write */
824 rmb();
825
826 handled++; /* irq handled if we got here */
827
828 /* freeze if hotplugged or controller error */
829 if (unlikely(status & (NV_ADMA_STAT_HOTPLUG |
830 NV_ADMA_STAT_HOTUNPLUG |
831 NV_ADMA_STAT_TIMEOUT |
832 NV_ADMA_STAT_SERROR))) {
833 struct ata_eh_info *ehi = &ap->eh_info;
834
835 ata_ehi_clear_desc(ehi);
836 ata_ehi_push_desc(ehi, "ADMA status 0x%08x", status );
837 if (status & NV_ADMA_STAT_TIMEOUT) {
838 ehi->err_mask |= AC_ERR_SYSTEM;
839 ata_ehi_push_desc(ehi, ": timeout");
840 } else if (status & NV_ADMA_STAT_HOTPLUG) {
841 ata_ehi_hotplugged(ehi);
842 ata_ehi_push_desc(ehi, ": hotplug");
843 } else if (status & NV_ADMA_STAT_HOTUNPLUG) {
844 ata_ehi_hotplugged(ehi);
845 ata_ehi_push_desc(ehi, ": hot unplug");
846 } else if (status & NV_ADMA_STAT_SERROR) {
847 /* let libata analyze SError and figure out the cause */
848 ata_ehi_push_desc(ehi, ": SError");
849 }
850 ata_port_freeze(ap);
851 continue;
852 }
853
854 if (status & (NV_ADMA_STAT_DONE |
855 NV_ADMA_STAT_CPBERR)) {
856 /** Check CPBs for completed commands */
857
858 if (ata_tag_valid(ap->active_tag)) {
859 /* Non-NCQ command */
860 nv_adma_check_cpb(ap, ap->active_tag,
861 notifier_error & (1 << ap->active_tag));
862 } else {
863 int pos, error = 0;
864 u32 active = ap->sactive;
865
866 while ((pos = ffs(active)) && !error) {
867 pos--;
868 error = nv_adma_check_cpb(ap, pos,
869 notifier_error & (1 << pos) );
870 active &= ~(1 << pos );
871 }
872 }
873 }
874 }
875 }
876
877 if(notifier_clears[0] || notifier_clears[1]) {
878 /* Note: Both notifier clear registers must be written
879 if either is set, even if one is zero, according to NVIDIA. */
880 struct nv_adma_port_priv *pp = host->ports[0]->private_data;
881 writel(notifier_clears[0], pp->notifier_clear_block);
882 pp = host->ports[1]->private_data;
883 writel(notifier_clears[1], pp->notifier_clear_block);
884 }
885
886 spin_unlock(&host->lock);
887
888 return IRQ_RETVAL(handled);
889 }
890
891 static void nv_adma_irq_clear(struct ata_port *ap)
892 {
893 struct nv_adma_port_priv *pp = ap->private_data;
894 void __iomem *mmio = pp->ctl_block;
895 u16 status = readw(mmio + NV_ADMA_STAT);
896 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
897 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
898 void __iomem *dma_stat_addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
899
900 /* clear ADMA status */
901 writew(status, mmio + NV_ADMA_STAT);
902 writel(notifier | notifier_error,
903 pp->notifier_clear_block);
904
905 /** clear legacy status */
906 iowrite8(ioread8(dma_stat_addr), dma_stat_addr);
907 }
908
909 static void nv_adma_bmdma_setup(struct ata_queued_cmd *qc)
910 {
911 struct ata_port *ap = qc->ap;
912 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
913 struct nv_adma_port_priv *pp = ap->private_data;
914 u8 dmactl;
915
916 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
917 WARN_ON(1);
918 return;
919 }
920
921 /* load PRD table addr. */
922 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
923
924 /* specify data direction, triple-check start bit is clear */
925 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
926 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
927 if (!rw)
928 dmactl |= ATA_DMA_WR;
929
930 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
931
932 /* issue r/w command */
933 ata_exec_command(ap, &qc->tf);
934 }
935
936 static void nv_adma_bmdma_start(struct ata_queued_cmd *qc)
937 {
938 struct ata_port *ap = qc->ap;
939 struct nv_adma_port_priv *pp = ap->private_data;
940 u8 dmactl;
941
942 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
943 WARN_ON(1);
944 return;
945 }
946
947 /* start host DMA transaction */
948 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
949 iowrite8(dmactl | ATA_DMA_START,
950 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
951 }
952
953 static void nv_adma_bmdma_stop(struct ata_queued_cmd *qc)
954 {
955 struct ata_port *ap = qc->ap;
956 struct nv_adma_port_priv *pp = ap->private_data;
957
958 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE))
959 return;
960
961 /* clear start/stop bit */
962 iowrite8(ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
963 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
964
965 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
966 ata_altstatus(ap); /* dummy read */
967 }
968
969 static u8 nv_adma_bmdma_status(struct ata_port *ap)
970 {
971 struct nv_adma_port_priv *pp = ap->private_data;
972
973 WARN_ON(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE));
974
975 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
976 }
977
978 static int nv_adma_port_start(struct ata_port *ap)
979 {
980 struct device *dev = ap->host->dev;
981 struct nv_adma_port_priv *pp;
982 int rc;
983 void *mem;
984 dma_addr_t mem_dma;
985 void __iomem *mmio;
986 u16 tmp;
987
988 VPRINTK("ENTER\n");
989
990 rc = ata_port_start(ap);
991 if (rc)
992 return rc;
993
994 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
995 if (!pp)
996 return -ENOMEM;
997
998 mmio = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_PORT +
999 ap->port_no * NV_ADMA_PORT_SIZE;
1000 pp->ctl_block = mmio;
1001 pp->gen_block = ap->host->iomap[NV_MMIO_BAR] + NV_ADMA_GEN;
1002 pp->notifier_clear_block = pp->gen_block +
1003 NV_ADMA_NOTIFIER_CLEAR + (4 * ap->port_no);
1004
1005 mem = dmam_alloc_coherent(dev, NV_ADMA_PORT_PRIV_DMA_SZ,
1006 &mem_dma, GFP_KERNEL);
1007 if (!mem)
1008 return -ENOMEM;
1009 memset(mem, 0, NV_ADMA_PORT_PRIV_DMA_SZ);
1010
1011 /*
1012 * First item in chunk of DMA memory:
1013 * 128-byte command parameter block (CPB)
1014 * one for each command tag
1015 */
1016 pp->cpb = mem;
1017 pp->cpb_dma = mem_dma;
1018
1019 writel(mem_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1020 writel((mem_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1021
1022 mem += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1023 mem_dma += NV_ADMA_MAX_CPBS * NV_ADMA_CPB_SZ;
1024
1025 /*
1026 * Second item: block of ADMA_SGTBL_LEN s/g entries
1027 */
1028 pp->aprd = mem;
1029 pp->aprd_dma = mem_dma;
1030
1031 ap->private_data = pp;
1032
1033 /* clear any outstanding interrupt conditions */
1034 writew(0xffff, mmio + NV_ADMA_STAT);
1035
1036 /* initialize port variables */
1037 pp->flags = NV_ADMA_PORT_REGISTER_MODE;
1038
1039 /* clear CPB fetch count */
1040 writew(0, mmio + NV_ADMA_CPB_COUNT);
1041
1042 /* clear GO for register mode, enable interrupt */
1043 tmp = readw(mmio + NV_ADMA_CTL);
1044 writew( (tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
1045
1046 tmp = readw(mmio + NV_ADMA_CTL);
1047 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1048 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1049 udelay(1);
1050 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1051 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1052
1053 return 0;
1054 }
1055
1056 static void nv_adma_port_stop(struct ata_port *ap)
1057 {
1058 struct nv_adma_port_priv *pp = ap->private_data;
1059 void __iomem *mmio = pp->ctl_block;
1060
1061 VPRINTK("ENTER\n");
1062 writew(0, mmio + NV_ADMA_CTL);
1063 }
1064
1065 static int nv_adma_port_suspend(struct ata_port *ap, pm_message_t mesg)
1066 {
1067 struct nv_adma_port_priv *pp = ap->private_data;
1068 void __iomem *mmio = pp->ctl_block;
1069
1070 /* Go to register mode - clears GO */
1071 nv_adma_register_mode(ap);
1072
1073 /* clear CPB fetch count */
1074 writew(0, mmio + NV_ADMA_CPB_COUNT);
1075
1076 /* disable interrupt, shut down port */
1077 writew(0, mmio + NV_ADMA_CTL);
1078
1079 return 0;
1080 }
1081
1082 static int nv_adma_port_resume(struct ata_port *ap)
1083 {
1084 struct nv_adma_port_priv *pp = ap->private_data;
1085 void __iomem *mmio = pp->ctl_block;
1086 u16 tmp;
1087
1088 /* set CPB block location */
1089 writel(pp->cpb_dma & 0xFFFFFFFF, mmio + NV_ADMA_CPB_BASE_LOW);
1090 writel((pp->cpb_dma >> 16 ) >> 16, mmio + NV_ADMA_CPB_BASE_HIGH);
1091
1092 /* clear any outstanding interrupt conditions */
1093 writew(0xffff, mmio + NV_ADMA_STAT);
1094
1095 /* initialize port variables */
1096 pp->flags |= NV_ADMA_PORT_REGISTER_MODE;
1097
1098 /* clear CPB fetch count */
1099 writew(0, mmio + NV_ADMA_CPB_COUNT);
1100
1101 /* clear GO for register mode, enable interrupt */
1102 tmp = readw(mmio + NV_ADMA_CTL);
1103 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN, mmio + NV_ADMA_CTL);
1104
1105 tmp = readw(mmio + NV_ADMA_CTL);
1106 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1107 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1108 udelay(1);
1109 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1110 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1111
1112 return 0;
1113 }
1114
1115 static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port)
1116 {
1117 void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR];
1118 struct ata_ioports *ioport = &probe_ent->port[port];
1119
1120 VPRINTK("ENTER\n");
1121
1122 mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE;
1123
1124 ioport->cmd_addr = mmio;
1125 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
1126 ioport->error_addr =
1127 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1128 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1129 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1130 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1131 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1132 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
1133 ioport->status_addr =
1134 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
1135 ioport->altstatus_addr =
1136 ioport->ctl_addr = mmio + 0x20;
1137 }
1138
1139 static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
1140 {
1141 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1142 unsigned int i;
1143 u32 tmp32;
1144
1145 VPRINTK("ENTER\n");
1146
1147 /* enable ADMA on the ports */
1148 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1149 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1150 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1151 NV_MCP_SATA_CFG_20_PORT1_EN |
1152 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1153
1154 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1155
1156 for (i = 0; i < probe_ent->n_ports; i++)
1157 nv_adma_setup_port(probe_ent, i);
1158
1159 return 0;
1160 }
1161
1162 static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1163 struct scatterlist *sg,
1164 int idx,
1165 struct nv_adma_prd *aprd)
1166 {
1167 u8 flags = 0;
1168 if (qc->tf.flags & ATA_TFLAG_WRITE)
1169 flags |= NV_APRD_WRITE;
1170 if (idx == qc->n_elem - 1)
1171 flags |= NV_APRD_END;
1172 else if (idx != 4)
1173 flags |= NV_APRD_CONT;
1174
1175 aprd->addr = cpu_to_le64(((u64)sg_dma_address(sg)));
1176 aprd->len = cpu_to_le32(((u32)sg_dma_len(sg))); /* len in bytes */
1177 aprd->flags = flags;
1178 aprd->packet_len = 0;
1179 }
1180
1181 static void nv_adma_fill_sg(struct ata_queued_cmd *qc, struct nv_adma_cpb *cpb)
1182 {
1183 struct nv_adma_port_priv *pp = qc->ap->private_data;
1184 unsigned int idx;
1185 struct nv_adma_prd *aprd;
1186 struct scatterlist *sg;
1187
1188 VPRINTK("ENTER\n");
1189
1190 idx = 0;
1191
1192 ata_for_each_sg(sg, qc) {
1193 aprd = (idx < 5) ? &cpb->aprd[idx] : &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (idx-5)];
1194 nv_adma_fill_aprd(qc, sg, idx, aprd);
1195 idx++;
1196 }
1197 if (idx > 5)
1198 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1199 else
1200 cpb->next_aprd = cpu_to_le64(0);
1201 }
1202
1203 static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1204 {
1205 struct nv_adma_port_priv *pp = qc->ap->private_data;
1206
1207 /* ADMA engine can only be used for non-ATAPI DMA commands,
1208 or interrupt-driven no-data commands. */
1209 if((pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) ||
1210 (qc->tf.flags & ATA_TFLAG_POLLING))
1211 return 1;
1212
1213 if((qc->flags & ATA_QCFLAG_DMAMAP) ||
1214 (qc->tf.protocol == ATA_PROT_NODATA))
1215 return 0;
1216
1217 return 1;
1218 }
1219
1220 static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1221 {
1222 struct nv_adma_port_priv *pp = qc->ap->private_data;
1223 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1224 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1225 NV_CPB_CTL_IEN;
1226
1227 if (nv_adma_use_reg_mode(qc)) {
1228 nv_adma_register_mode(qc->ap);
1229 ata_qc_prep(qc);
1230 return;
1231 }
1232
1233 cpb->resp_flags = NV_CPB_RESP_DONE;
1234 wmb();
1235 cpb->ctl_flags = 0;
1236 wmb();
1237
1238 cpb->len = 3;
1239 cpb->tag = qc->tag;
1240 cpb->next_cpb_idx = 0;
1241
1242 /* turn on NCQ flags for NCQ commands */
1243 if (qc->tf.protocol == ATA_PROT_NCQ)
1244 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1245
1246 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1247
1248 nv_adma_tf_to_cpb(&qc->tf, cpb->tf);
1249
1250 if(qc->flags & ATA_QCFLAG_DMAMAP) {
1251 nv_adma_fill_sg(qc, cpb);
1252 ctl_flags |= NV_CPB_CTL_APRD_VALID;
1253 } else
1254 memset(&cpb->aprd[0], 0, sizeof(struct nv_adma_prd) * 5);
1255
1256 /* Be paranoid and don't let the device see NV_CPB_CTL_CPB_VALID until we are
1257 finished filling in all of the contents */
1258 wmb();
1259 cpb->ctl_flags = ctl_flags;
1260 wmb();
1261 cpb->resp_flags = 0;
1262 }
1263
1264 static unsigned int nv_adma_qc_issue(struct ata_queued_cmd *qc)
1265 {
1266 struct nv_adma_port_priv *pp = qc->ap->private_data;
1267 void __iomem *mmio = pp->ctl_block;
1268 int curr_ncq = (qc->tf.protocol == ATA_PROT_NCQ);
1269
1270 VPRINTK("ENTER\n");
1271
1272 if (nv_adma_use_reg_mode(qc)) {
1273 /* use ATA register mode */
1274 VPRINTK("using ATA register mode: 0x%lx\n", qc->flags);
1275 nv_adma_register_mode(qc->ap);
1276 return ata_qc_issue_prot(qc);
1277 } else
1278 nv_adma_mode(qc->ap);
1279
1280 /* write append register, command tag in lower 8 bits
1281 and (number of cpbs to append -1) in top 8 bits */
1282 wmb();
1283
1284 if(curr_ncq != pp->last_issue_ncq) {
1285 /* Seems to need some delay before switching between NCQ and non-NCQ
1286 commands, else we get command timeouts and such. */
1287 udelay(20);
1288 pp->last_issue_ncq = curr_ncq;
1289 }
1290
1291 writew(qc->tag, mmio + NV_ADMA_APPEND);
1292
1293 DPRINTK("Issued tag %u\n",qc->tag);
1294
1295 return 0;
1296 }
1297
1298 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1299 {
1300 struct ata_host *host = dev_instance;
1301 unsigned int i;
1302 unsigned int handled = 0;
1303 unsigned long flags;
1304
1305 spin_lock_irqsave(&host->lock, flags);
1306
1307 for (i = 0; i < host->n_ports; i++) {
1308 struct ata_port *ap;
1309
1310 ap = host->ports[i];
1311 if (ap &&
1312 !(ap->flags & ATA_FLAG_DISABLED)) {
1313 struct ata_queued_cmd *qc;
1314
1315 qc = ata_qc_from_tag(ap, ap->active_tag);
1316 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1317 handled += ata_host_intr(ap, qc);
1318 else
1319 // No request pending? Clear interrupt status
1320 // anyway, in case there's one pending.
1321 ap->ops->check_status(ap);
1322 }
1323
1324 }
1325
1326 spin_unlock_irqrestore(&host->lock, flags);
1327
1328 return IRQ_RETVAL(handled);
1329 }
1330
1331 static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat)
1332 {
1333 int i, handled = 0;
1334
1335 for (i = 0; i < host->n_ports; i++) {
1336 struct ata_port *ap = host->ports[i];
1337
1338 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
1339 handled += nv_host_intr(ap, irq_stat);
1340
1341 irq_stat >>= NV_INT_PORT_SHIFT;
1342 }
1343
1344 return IRQ_RETVAL(handled);
1345 }
1346
1347 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance)
1348 {
1349 struct ata_host *host = dev_instance;
1350 u8 irq_stat;
1351 irqreturn_t ret;
1352
1353 spin_lock(&host->lock);
1354 irq_stat = ioread8(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
1355 ret = nv_do_interrupt(host, irq_stat);
1356 spin_unlock(&host->lock);
1357
1358 return ret;
1359 }
1360
1361 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance)
1362 {
1363 struct ata_host *host = dev_instance;
1364 u8 irq_stat;
1365 irqreturn_t ret;
1366
1367 spin_lock(&host->lock);
1368 irq_stat = readb(host->iomap[NV_MMIO_BAR] + NV_INT_STATUS_CK804);
1369 ret = nv_do_interrupt(host, irq_stat);
1370 spin_unlock(&host->lock);
1371
1372 return ret;
1373 }
1374
1375 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
1376 {
1377 if (sc_reg > SCR_CONTROL)
1378 return 0xffffffffU;
1379
1380 return ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
1381 }
1382
1383 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
1384 {
1385 if (sc_reg > SCR_CONTROL)
1386 return;
1387
1388 iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
1389 }
1390
1391 static void nv_nf2_freeze(struct ata_port *ap)
1392 {
1393 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1394 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1395 u8 mask;
1396
1397 mask = ioread8(scr_addr + NV_INT_ENABLE);
1398 mask &= ~(NV_INT_ALL << shift);
1399 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1400 }
1401
1402 static void nv_nf2_thaw(struct ata_port *ap)
1403 {
1404 void __iomem *scr_addr = ap->host->ports[0]->ioaddr.scr_addr;
1405 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1406 u8 mask;
1407
1408 iowrite8(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
1409
1410 mask = ioread8(scr_addr + NV_INT_ENABLE);
1411 mask |= (NV_INT_MASK << shift);
1412 iowrite8(mask, scr_addr + NV_INT_ENABLE);
1413 }
1414
1415 static void nv_ck804_freeze(struct ata_port *ap)
1416 {
1417 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1418 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1419 u8 mask;
1420
1421 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1422 mask &= ~(NV_INT_ALL << shift);
1423 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1424 }
1425
1426 static void nv_ck804_thaw(struct ata_port *ap)
1427 {
1428 void __iomem *mmio_base = ap->host->iomap[NV_MMIO_BAR];
1429 int shift = ap->port_no * NV_INT_PORT_SHIFT;
1430 u8 mask;
1431
1432 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
1433
1434 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
1435 mask |= (NV_INT_MASK << shift);
1436 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
1437 }
1438
1439 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
1440 {
1441 unsigned int dummy;
1442
1443 /* SATA hardreset fails to retrieve proper device signature on
1444 * some controllers. Don't classify on hardreset. For more
1445 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
1446 */
1447 return sata_std_hardreset(ap, &dummy);
1448 }
1449
1450 static void nv_error_handler(struct ata_port *ap)
1451 {
1452 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1453 nv_hardreset, ata_std_postreset);
1454 }
1455
1456 static void nv_adma_error_handler(struct ata_port *ap)
1457 {
1458 struct nv_adma_port_priv *pp = ap->private_data;
1459 if(!(pp->flags & NV_ADMA_PORT_REGISTER_MODE)) {
1460 void __iomem *mmio = pp->ctl_block;
1461 int i;
1462 u16 tmp;
1463
1464 if(ata_tag_valid(ap->active_tag) || ap->sactive) {
1465 u32 notifier = readl(mmio + NV_ADMA_NOTIFIER);
1466 u32 notifier_error = readl(mmio + NV_ADMA_NOTIFIER_ERROR);
1467 u32 gen_ctl = readl(pp->gen_block + NV_ADMA_GEN_CTL);
1468 u32 status = readw(mmio + NV_ADMA_STAT);
1469 u8 cpb_count = readb(mmio + NV_ADMA_CPB_COUNT);
1470 u8 next_cpb_idx = readb(mmio + NV_ADMA_NEXT_CPB_IDX);
1471
1472 ata_port_printk(ap, KERN_ERR, "EH in ADMA mode, notifier 0x%X "
1473 "notifier_error 0x%X gen_ctl 0x%X status 0x%X "
1474 "next cpb count 0x%X next cpb idx 0x%x\n",
1475 notifier, notifier_error, gen_ctl, status,
1476 cpb_count, next_cpb_idx);
1477
1478 for( i=0;i<NV_ADMA_MAX_CPBS;i++) {
1479 struct nv_adma_cpb *cpb = &pp->cpb[i];
1480 if( (ata_tag_valid(ap->active_tag) && i == ap->active_tag) ||
1481 ap->sactive & (1 << i) )
1482 ata_port_printk(ap, KERN_ERR,
1483 "CPB %d: ctl_flags 0x%x, resp_flags 0x%x\n",
1484 i, cpb->ctl_flags, cpb->resp_flags);
1485 }
1486 }
1487
1488 /* Push us back into port register mode for error handling. */
1489 nv_adma_register_mode(ap);
1490
1491 /* Mark all of the CPBs as invalid to prevent them from being executed */
1492 for( i=0;i<NV_ADMA_MAX_CPBS;i++)
1493 pp->cpb[i].ctl_flags &= ~NV_CPB_CTL_CPB_VALID;
1494
1495 /* clear CPB fetch count */
1496 writew(0, mmio + NV_ADMA_CPB_COUNT);
1497
1498 /* Reset channel */
1499 tmp = readw(mmio + NV_ADMA_CTL);
1500 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1501 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1502 udelay(1);
1503 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1504 readl( mmio + NV_ADMA_CTL ); /* flush posted write */
1505 }
1506
1507 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1508 nv_hardreset, ata_std_postreset);
1509 }
1510
1511 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1512 {
1513 static int printed_version = 0;
1514 struct ata_port_info *ppi[2];
1515 struct ata_probe_ent *probe_ent;
1516 struct nv_host_priv *hpriv;
1517 int rc;
1518 u32 bar;
1519 void __iomem *base;
1520 unsigned long type = ent->driver_data;
1521 int mask_set = 0;
1522
1523 // Make sure this is a SATA controller by counting the number of bars
1524 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1525 // it's an IDE controller and we ignore it.
1526 for (bar=0; bar<6; bar++)
1527 if (pci_resource_start(pdev, bar) == 0)
1528 return -ENODEV;
1529
1530 if (!printed_version++)
1531 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1532
1533 rc = pcim_enable_device(pdev);
1534 if (rc)
1535 return rc;
1536
1537 rc = pci_request_regions(pdev, DRV_NAME);
1538 if (rc) {
1539 pcim_pin_device(pdev);
1540 return rc;
1541 }
1542
1543 if(type >= CK804 && adma_enabled) {
1544 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1545 type = ADMA;
1546 if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
1547 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1548 mask_set = 1;
1549 }
1550
1551 if(!mask_set) {
1552 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1553 if (rc)
1554 return rc;
1555 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1556 if (rc)
1557 return rc;
1558 }
1559
1560 rc = -ENOMEM;
1561
1562 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1563 if (!hpriv)
1564 return -ENOMEM;
1565
1566 ppi[0] = ppi[1] = &nv_port_info[type];
1567 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
1568 if (!probe_ent)
1569 return -ENOMEM;
1570
1571 if (!pcim_iomap(pdev, NV_MMIO_BAR, 0))
1572 return -EIO;
1573 probe_ent->iomap = pcim_iomap_table(pdev);
1574
1575 probe_ent->private_data = hpriv;
1576 hpriv->type = type;
1577
1578 base = probe_ent->iomap[NV_MMIO_BAR];
1579 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1580 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1581
1582 /* enable SATA space for CK804 */
1583 if (type >= CK804) {
1584 u8 regval;
1585
1586 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1587 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1588 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1589 }
1590
1591 pci_set_master(pdev);
1592
1593 if (type == ADMA) {
1594 rc = nv_adma_host_init(probe_ent);
1595 if (rc)
1596 return rc;
1597 }
1598
1599 rc = ata_device_add(probe_ent);
1600 if (rc != NV_PORTS)
1601 return -ENODEV;
1602
1603 devm_kfree(&pdev->dev, probe_ent);
1604 return 0;
1605 }
1606
1607 static void nv_remove_one (struct pci_dev *pdev)
1608 {
1609 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1610 struct nv_host_priv *hpriv = host->private_data;
1611
1612 ata_pci_remove_one(pdev);
1613 kfree(hpriv);
1614 }
1615
1616 static int nv_pci_device_resume(struct pci_dev *pdev)
1617 {
1618 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1619 struct nv_host_priv *hpriv = host->private_data;
1620 int rc;
1621
1622 rc = ata_pci_device_do_resume(pdev);
1623 if(rc)
1624 return rc;
1625
1626 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1627 if(hpriv->type >= CK804) {
1628 u8 regval;
1629
1630 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1631 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1632 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1633 }
1634 if(hpriv->type == ADMA) {
1635 u32 tmp32;
1636 struct nv_adma_port_priv *pp;
1637 /* enable/disable ADMA on the ports appropriately */
1638 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1639
1640 pp = host->ports[0]->private_data;
1641 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1642 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1643 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1644 else
1645 tmp32 |= (NV_MCP_SATA_CFG_20_PORT0_EN |
1646 NV_MCP_SATA_CFG_20_PORT0_PWB_EN);
1647 pp = host->ports[1]->private_data;
1648 if(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE)
1649 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT1_EN |
1650 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1651 else
1652 tmp32 |= (NV_MCP_SATA_CFG_20_PORT1_EN |
1653 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1654
1655 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1656 }
1657 }
1658
1659 ata_host_resume(host);
1660
1661 return 0;
1662 }
1663
1664 static void nv_ck804_host_stop(struct ata_host *host)
1665 {
1666 struct pci_dev *pdev = to_pci_dev(host->dev);
1667 u8 regval;
1668
1669 /* disable SATA space for CK804 */
1670 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1671 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1672 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1673 }
1674
1675 static void nv_adma_host_stop(struct ata_host *host)
1676 {
1677 struct pci_dev *pdev = to_pci_dev(host->dev);
1678 u32 tmp32;
1679
1680 /* disable ADMA on the ports */
1681 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1682 tmp32 &= ~(NV_MCP_SATA_CFG_20_PORT0_EN |
1683 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1684 NV_MCP_SATA_CFG_20_PORT1_EN |
1685 NV_MCP_SATA_CFG_20_PORT1_PWB_EN);
1686
1687 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1688
1689 nv_ck804_host_stop(host);
1690 }
1691
1692 static int __init nv_init(void)
1693 {
1694 return pci_register_driver(&nv_pci_driver);
1695 }
1696
1697 static void __exit nv_exit(void)
1698 {
1699 pci_unregister_driver(&nv_pci_driver);
1700 }
1701
1702 module_init(nv_init);
1703 module_exit(nv_exit);
1704 module_param_named(adma, adma_enabled, bool, 0444);
1705 MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)");
Linux kernel - Deliverables
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