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libata: implement and use SHT initializers
[deliverable/linux.git] / drivers / ata / sata_promise.c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.12"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
94
95 board_2037x = 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319 = 2, /* FastTrak S150 TX4 */
98 board_20619 = 3, /* FastTrak TX4000 */
99 board_2057x = 4, /* SATAII150 Tx2plus */
100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
101 board_40518 = 6, /* SATAII150 Tx4 */
102
103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
104
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111
112 /* Device/Head register values */
113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
118 PDC_RESET = (1 << 11), /* HDMA reset */
119
120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO |
122 ATA_FLAG_PIO_POLLING,
123
124 /* ap->flags bits */
125 PDC_FLAG_GEN_II = (1 << 24),
126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
128 };
129
130 struct pdc_port_priv {
131 u8 *pkt;
132 dma_addr_t pkt_dma;
133 };
134
135 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
137 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
138 static int pdc_common_port_start(struct ata_port *ap);
139 static int pdc_sata_port_start(struct ata_port *ap);
140 static void pdc_qc_prep(struct ata_queued_cmd *qc);
141 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
143 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
145 static void pdc_irq_clear(struct ata_port *ap);
146 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
147 static void pdc_freeze(struct ata_port *ap);
148 static void pdc_sata_freeze(struct ata_port *ap);
149 static void pdc_thaw(struct ata_port *ap);
150 static void pdc_sata_thaw(struct ata_port *ap);
151 static void pdc_pata_error_handler(struct ata_port *ap);
152 static void pdc_sata_error_handler(struct ata_port *ap);
153 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
154 static int pdc_pata_cable_detect(struct ata_port *ap);
155 static int pdc_sata_cable_detect(struct ata_port *ap);
156
157 static struct scsi_host_template pdc_ata_sht = {
158 ATA_BASE_SHT(DRV_NAME),
159 .sg_tablesize = PDC_MAX_PRD,
160 .dma_boundary = ATA_DMA_BOUNDARY,
161 };
162
163 static const struct ata_port_operations pdc_sata_ops = {
164 .tf_load = pdc_tf_load_mmio,
165 .tf_read = ata_tf_read,
166 .check_status = ata_check_status,
167 .exec_command = pdc_exec_command_mmio,
168 .dev_select = ata_std_dev_select,
169 .check_atapi_dma = pdc_check_atapi_dma,
170
171 .qc_prep = pdc_qc_prep,
172 .qc_issue = pdc_qc_issue_prot,
173 .freeze = pdc_sata_freeze,
174 .thaw = pdc_sata_thaw,
175 .error_handler = pdc_sata_error_handler,
176 .post_internal_cmd = pdc_post_internal_cmd,
177 .cable_detect = pdc_sata_cable_detect,
178 .data_xfer = ata_data_xfer,
179 .irq_clear = pdc_irq_clear,
180 .irq_on = ata_irq_on,
181
182 .scr_read = pdc_sata_scr_read,
183 .scr_write = pdc_sata_scr_write,
184 .port_start = pdc_sata_port_start,
185 };
186
187 /* First-generation chips need a more restrictive ->check_atapi_dma op */
188 static const struct ata_port_operations pdc_old_sata_ops = {
189 .tf_load = pdc_tf_load_mmio,
190 .tf_read = ata_tf_read,
191 .check_status = ata_check_status,
192 .exec_command = pdc_exec_command_mmio,
193 .dev_select = ata_std_dev_select,
194 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
195
196 .qc_prep = pdc_qc_prep,
197 .qc_issue = pdc_qc_issue_prot,
198 .freeze = pdc_sata_freeze,
199 .thaw = pdc_sata_thaw,
200 .error_handler = pdc_sata_error_handler,
201 .post_internal_cmd = pdc_post_internal_cmd,
202 .cable_detect = pdc_sata_cable_detect,
203 .data_xfer = ata_data_xfer,
204 .irq_clear = pdc_irq_clear,
205 .irq_on = ata_irq_on,
206
207 .scr_read = pdc_sata_scr_read,
208 .scr_write = pdc_sata_scr_write,
209 .port_start = pdc_sata_port_start,
210 };
211
212 static const struct ata_port_operations pdc_pata_ops = {
213 .tf_load = pdc_tf_load_mmio,
214 .tf_read = ata_tf_read,
215 .check_status = ata_check_status,
216 .exec_command = pdc_exec_command_mmio,
217 .dev_select = ata_std_dev_select,
218 .check_atapi_dma = pdc_check_atapi_dma,
219
220 .qc_prep = pdc_qc_prep,
221 .qc_issue = pdc_qc_issue_prot,
222 .freeze = pdc_freeze,
223 .thaw = pdc_thaw,
224 .error_handler = pdc_pata_error_handler,
225 .post_internal_cmd = pdc_post_internal_cmd,
226 .cable_detect = pdc_pata_cable_detect,
227 .data_xfer = ata_data_xfer,
228 .irq_clear = pdc_irq_clear,
229 .irq_on = ata_irq_on,
230
231 .port_start = pdc_common_port_start,
232 };
233
234 static const struct ata_port_info pdc_port_info[] = {
235 [board_2037x] =
236 {
237 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
238 PDC_FLAG_SATA_PATA,
239 .pio_mask = 0x1f, /* pio0-4 */
240 .mwdma_mask = 0x07, /* mwdma0-2 */
241 .udma_mask = ATA_UDMA6,
242 .port_ops = &pdc_old_sata_ops,
243 },
244
245 [board_2037x_pata] =
246 {
247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
250 .udma_mask = ATA_UDMA6,
251 .port_ops = &pdc_pata_ops,
252 },
253
254 [board_20319] =
255 {
256 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
257 PDC_FLAG_4_PORTS,
258 .pio_mask = 0x1f, /* pio0-4 */
259 .mwdma_mask = 0x07, /* mwdma0-2 */
260 .udma_mask = ATA_UDMA6,
261 .port_ops = &pdc_old_sata_ops,
262 },
263
264 [board_20619] =
265 {
266 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
267 PDC_FLAG_4_PORTS,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .mwdma_mask = 0x07, /* mwdma0-2 */
270 .udma_mask = ATA_UDMA6,
271 .port_ops = &pdc_pata_ops,
272 },
273
274 [board_2057x] =
275 {
276 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
277 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
278 .pio_mask = 0x1f, /* pio0-4 */
279 .mwdma_mask = 0x07, /* mwdma0-2 */
280 .udma_mask = ATA_UDMA6,
281 .port_ops = &pdc_sata_ops,
282 },
283
284 [board_2057x_pata] =
285 {
286 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
287 PDC_FLAG_GEN_II,
288 .pio_mask = 0x1f, /* pio0-4 */
289 .mwdma_mask = 0x07, /* mwdma0-2 */
290 .udma_mask = ATA_UDMA6,
291 .port_ops = &pdc_pata_ops,
292 },
293
294 [board_40518] =
295 {
296 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
297 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
298 .pio_mask = 0x1f, /* pio0-4 */
299 .mwdma_mask = 0x07, /* mwdma0-2 */
300 .udma_mask = ATA_UDMA6,
301 .port_ops = &pdc_sata_ops,
302 },
303 };
304
305 static const struct pci_device_id pdc_ata_pci_tbl[] = {
306 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
307 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
308 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
309 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
310 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
311 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
312 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
313 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
314 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
315 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
316
317 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
318 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
319 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
320 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
321 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
322 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
323
324 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
325
326 { } /* terminate list */
327 };
328
329 static struct pci_driver pdc_ata_pci_driver = {
330 .name = DRV_NAME,
331 .id_table = pdc_ata_pci_tbl,
332 .probe = pdc_ata_init_one,
333 .remove = ata_pci_remove_one,
334 };
335
336 static int pdc_common_port_start(struct ata_port *ap)
337 {
338 struct device *dev = ap->host->dev;
339 struct pdc_port_priv *pp;
340 int rc;
341
342 rc = ata_port_start(ap);
343 if (rc)
344 return rc;
345
346 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
347 if (!pp)
348 return -ENOMEM;
349
350 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
351 if (!pp->pkt)
352 return -ENOMEM;
353
354 ap->private_data = pp;
355
356 return 0;
357 }
358
359 static int pdc_sata_port_start(struct ata_port *ap)
360 {
361 int rc;
362
363 rc = pdc_common_port_start(ap);
364 if (rc)
365 return rc;
366
367 /* fix up PHYMODE4 align timing */
368 if (ap->flags & PDC_FLAG_GEN_II) {
369 void __iomem *mmio = ap->ioaddr.scr_addr;
370 unsigned int tmp;
371
372 tmp = readl(mmio + 0x014);
373 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
374 writel(tmp, mmio + 0x014);
375 }
376
377 return 0;
378 }
379
380 static void pdc_reset_port(struct ata_port *ap)
381 {
382 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
383 unsigned int i;
384 u32 tmp;
385
386 for (i = 11; i > 0; i--) {
387 tmp = readl(mmio);
388 if (tmp & PDC_RESET)
389 break;
390
391 udelay(100);
392
393 tmp |= PDC_RESET;
394 writel(tmp, mmio);
395 }
396
397 tmp &= ~PDC_RESET;
398 writel(tmp, mmio);
399 readl(mmio); /* flush */
400 }
401
402 static int pdc_pata_cable_detect(struct ata_port *ap)
403 {
404 u8 tmp;
405 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
406
407 tmp = readb(mmio);
408 if (tmp & 0x01)
409 return ATA_CBL_PATA40;
410 return ATA_CBL_PATA80;
411 }
412
413 static int pdc_sata_cable_detect(struct ata_port *ap)
414 {
415 return ATA_CBL_SATA;
416 }
417
418 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
419 {
420 if (sc_reg > SCR_CONTROL)
421 return -EINVAL;
422 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
423 return 0;
424 }
425
426 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
427 {
428 if (sc_reg > SCR_CONTROL)
429 return -EINVAL;
430 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
431 return 0;
432 }
433
434 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
435 {
436 struct ata_port *ap = qc->ap;
437 dma_addr_t sg_table = ap->prd_dma;
438 unsigned int cdb_len = qc->dev->cdb_len;
439 u8 *cdb = qc->cdb;
440 struct pdc_port_priv *pp = ap->private_data;
441 u8 *buf = pp->pkt;
442 u32 *buf32 = (u32 *) buf;
443 unsigned int dev_sel, feature;
444
445 /* set control bits (byte 0), zero delay seq id (byte 3),
446 * and seq id (byte 2)
447 */
448 switch (qc->tf.protocol) {
449 case ATAPI_PROT_DMA:
450 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
451 buf32[0] = cpu_to_le32(PDC_PKT_READ);
452 else
453 buf32[0] = 0;
454 break;
455 case ATAPI_PROT_NODATA:
456 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
457 break;
458 default:
459 BUG();
460 break;
461 }
462 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
463 buf32[2] = 0; /* no next-packet */
464
465 /* select drive */
466 if (sata_scr_valid(&ap->link))
467 dev_sel = PDC_DEVICE_SATA;
468 else
469 dev_sel = qc->tf.device;
470
471 buf[12] = (1 << 5) | ATA_REG_DEVICE;
472 buf[13] = dev_sel;
473 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
474 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
475
476 buf[16] = (1 << 5) | ATA_REG_NSECT;
477 buf[17] = qc->tf.nsect;
478 buf[18] = (1 << 5) | ATA_REG_LBAL;
479 buf[19] = qc->tf.lbal;
480
481 /* set feature and byte counter registers */
482 if (qc->tf.protocol != ATAPI_PROT_DMA)
483 feature = PDC_FEATURE_ATAPI_PIO;
484 else
485 feature = PDC_FEATURE_ATAPI_DMA;
486
487 buf[20] = (1 << 5) | ATA_REG_FEATURE;
488 buf[21] = feature;
489 buf[22] = (1 << 5) | ATA_REG_BYTEL;
490 buf[23] = qc->tf.lbam;
491 buf[24] = (1 << 5) | ATA_REG_BYTEH;
492 buf[25] = qc->tf.lbah;
493
494 /* send ATAPI packet command 0xA0 */
495 buf[26] = (1 << 5) | ATA_REG_CMD;
496 buf[27] = qc->tf.command;
497
498 /* select drive and check DRQ */
499 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
500 buf[29] = dev_sel;
501
502 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
503 BUG_ON(cdb_len & ~0x1E);
504
505 /* append the CDB as the final part */
506 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
507 memcpy(buf+31, cdb, cdb_len);
508 }
509
510 /**
511 * pdc_fill_sg - Fill PCI IDE PRD table
512 * @qc: Metadata associated with taskfile to be transferred
513 *
514 * Fill PCI IDE PRD (scatter-gather) table with segments
515 * associated with the current disk command.
516 * Make sure hardware does not choke on it.
517 *
518 * LOCKING:
519 * spin_lock_irqsave(host lock)
520 *
521 */
522 static void pdc_fill_sg(struct ata_queued_cmd *qc)
523 {
524 struct ata_port *ap = qc->ap;
525 struct scatterlist *sg;
526 const u32 SG_COUNT_ASIC_BUG = 41*4;
527 unsigned int si, idx;
528 u32 len;
529
530 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
531 return;
532
533 idx = 0;
534 for_each_sg(qc->sg, sg, qc->n_elem, si) {
535 u32 addr, offset;
536 u32 sg_len;
537
538 /* determine if physical DMA addr spans 64K boundary.
539 * Note h/w doesn't support 64-bit, so we unconditionally
540 * truncate dma_addr_t to u32.
541 */
542 addr = (u32) sg_dma_address(sg);
543 sg_len = sg_dma_len(sg);
544
545 while (sg_len) {
546 offset = addr & 0xffff;
547 len = sg_len;
548 if ((offset + sg_len) > 0x10000)
549 len = 0x10000 - offset;
550
551 ap->prd[idx].addr = cpu_to_le32(addr);
552 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
553 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
554
555 idx++;
556 sg_len -= len;
557 addr += len;
558 }
559 }
560
561 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
562
563 if (len > SG_COUNT_ASIC_BUG) {
564 u32 addr;
565
566 VPRINTK("Splitting last PRD.\n");
567
568 addr = le32_to_cpu(ap->prd[idx - 1].addr);
569 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
570 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
571
572 addr = addr + len - SG_COUNT_ASIC_BUG;
573 len = SG_COUNT_ASIC_BUG;
574 ap->prd[idx].addr = cpu_to_le32(addr);
575 ap->prd[idx].flags_len = cpu_to_le32(len);
576 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
577
578 idx++;
579 }
580
581 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
582 }
583
584 static void pdc_qc_prep(struct ata_queued_cmd *qc)
585 {
586 struct pdc_port_priv *pp = qc->ap->private_data;
587 unsigned int i;
588
589 VPRINTK("ENTER\n");
590
591 switch (qc->tf.protocol) {
592 case ATA_PROT_DMA:
593 pdc_fill_sg(qc);
594 /* fall through */
595
596 case ATA_PROT_NODATA:
597 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
598 qc->dev->devno, pp->pkt);
599
600 if (qc->tf.flags & ATA_TFLAG_LBA48)
601 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
602 else
603 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
604
605 pdc_pkt_footer(&qc->tf, pp->pkt, i);
606 break;
607
608 case ATAPI_PROT_PIO:
609 pdc_fill_sg(qc);
610 break;
611
612 case ATAPI_PROT_DMA:
613 pdc_fill_sg(qc);
614 /*FALLTHROUGH*/
615 case ATAPI_PROT_NODATA:
616 pdc_atapi_pkt(qc);
617 break;
618
619 default:
620 break;
621 }
622 }
623
624 static int pdc_is_sataii_tx4(unsigned long flags)
625 {
626 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
627 return (flags & mask) == mask;
628 }
629
630 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
631 int is_sataii_tx4)
632 {
633 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
634 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
635 }
636
637 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
638 {
639 return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
640 }
641
642 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
643 {
644 const struct ata_host *host = ap->host;
645 unsigned int nr_ports = pdc_sata_nr_ports(ap);
646 unsigned int i;
647
648 for(i = 0; i < nr_ports && host->ports[i] != ap; ++i)
649 ;
650 BUG_ON(i >= nr_ports);
651 return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
652 }
653
654 static unsigned int pdc_sata_hotplug_offset(const struct ata_port *ap)
655 {
656 return (ap->flags & PDC_FLAG_GEN_II) ? PDC2_SATA_PLUG_CSR : PDC_SATA_PLUG_CSR;
657 }
658
659 static void pdc_freeze(struct ata_port *ap)
660 {
661 void __iomem *mmio = ap->ioaddr.cmd_addr;
662 u32 tmp;
663
664 tmp = readl(mmio + PDC_CTLSTAT);
665 tmp |= PDC_IRQ_DISABLE;
666 tmp &= ~PDC_DMA_ENABLE;
667 writel(tmp, mmio + PDC_CTLSTAT);
668 readl(mmio + PDC_CTLSTAT); /* flush */
669 }
670
671 static void pdc_sata_freeze(struct ata_port *ap)
672 {
673 struct ata_host *host = ap->host;
674 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
675 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
676 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
677 u32 hotplug_status;
678
679 /* Disable hotplug events on this port.
680 *
681 * Locking:
682 * 1) hotplug register accesses must be serialised via host->lock
683 * 2) ap->lock == &ap->host->lock
684 * 3) ->freeze() and ->thaw() are called with ap->lock held
685 */
686 hotplug_status = readl(host_mmio + hotplug_offset);
687 hotplug_status |= 0x11 << (ata_no + 16);
688 writel(hotplug_status, host_mmio + hotplug_offset);
689 readl(host_mmio + hotplug_offset); /* flush */
690
691 pdc_freeze(ap);
692 }
693
694 static void pdc_thaw(struct ata_port *ap)
695 {
696 void __iomem *mmio = ap->ioaddr.cmd_addr;
697 u32 tmp;
698
699 /* clear IRQ */
700 readl(mmio + PDC_INT_SEQMASK);
701
702 /* turn IRQ back on */
703 tmp = readl(mmio + PDC_CTLSTAT);
704 tmp &= ~PDC_IRQ_DISABLE;
705 writel(tmp, mmio + PDC_CTLSTAT);
706 readl(mmio + PDC_CTLSTAT); /* flush */
707 }
708
709 static void pdc_sata_thaw(struct ata_port *ap)
710 {
711 struct ata_host *host = ap->host;
712 void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
713 unsigned int hotplug_offset = pdc_sata_hotplug_offset(ap);
714 unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
715 u32 hotplug_status;
716
717 pdc_thaw(ap);
718
719 /* Enable hotplug events on this port.
720 * Locking: see pdc_sata_freeze().
721 */
722 hotplug_status = readl(host_mmio + hotplug_offset);
723 hotplug_status |= 0x11 << ata_no;
724 hotplug_status &= ~(0x11 << (ata_no + 16));
725 writel(hotplug_status, host_mmio + hotplug_offset);
726 readl(host_mmio + hotplug_offset); /* flush */
727 }
728
729 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
730 {
731 if (!(ap->pflags & ATA_PFLAG_FROZEN))
732 pdc_reset_port(ap);
733
734 /* perform recovery */
735 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
736 ata_std_postreset);
737 }
738
739 static void pdc_pata_error_handler(struct ata_port *ap)
740 {
741 pdc_common_error_handler(ap, NULL);
742 }
743
744 static void pdc_sata_error_handler(struct ata_port *ap)
745 {
746 pdc_common_error_handler(ap, sata_std_hardreset);
747 }
748
749 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
750 {
751 struct ata_port *ap = qc->ap;
752
753 /* make DMA engine forget about the failed command */
754 if (qc->flags & ATA_QCFLAG_FAILED)
755 pdc_reset_port(ap);
756 }
757
758 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
759 u32 port_status, u32 err_mask)
760 {
761 struct ata_eh_info *ehi = &ap->link.eh_info;
762 unsigned int ac_err_mask = 0;
763
764 ata_ehi_clear_desc(ehi);
765 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
766 port_status &= err_mask;
767
768 if (port_status & PDC_DRIVE_ERR)
769 ac_err_mask |= AC_ERR_DEV;
770 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
771 ac_err_mask |= AC_ERR_HSM;
772 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
773 ac_err_mask |= AC_ERR_ATA_BUS;
774 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
775 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
776 ac_err_mask |= AC_ERR_HOST_BUS;
777
778 if (sata_scr_valid(&ap->link)) {
779 u32 serror;
780
781 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
782 ehi->serror |= serror;
783 }
784
785 qc->err_mask |= ac_err_mask;
786
787 pdc_reset_port(ap);
788
789 ata_port_abort(ap);
790 }
791
792 static inline unsigned int pdc_host_intr(struct ata_port *ap,
793 struct ata_queued_cmd *qc)
794 {
795 unsigned int handled = 0;
796 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
797 u32 port_status, err_mask;
798
799 err_mask = PDC_ERR_MASK;
800 if (ap->flags & PDC_FLAG_GEN_II)
801 err_mask &= ~PDC1_ERR_MASK;
802 else
803 err_mask &= ~PDC2_ERR_MASK;
804 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
805 if (unlikely(port_status & err_mask)) {
806 pdc_error_intr(ap, qc, port_status, err_mask);
807 return 1;
808 }
809
810 switch (qc->tf.protocol) {
811 case ATA_PROT_DMA:
812 case ATA_PROT_NODATA:
813 case ATAPI_PROT_DMA:
814 case ATAPI_PROT_NODATA:
815 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
816 ata_qc_complete(qc);
817 handled = 1;
818 break;
819
820 default:
821 ap->stats.idle_irq++;
822 break;
823 }
824
825 return handled;
826 }
827
828 static void pdc_irq_clear(struct ata_port *ap)
829 {
830 struct ata_host *host = ap->host;
831 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
832
833 readl(mmio + PDC_INT_SEQMASK);
834 }
835
836 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
837 {
838 struct ata_host *host = dev_instance;
839 struct ata_port *ap;
840 u32 mask = 0;
841 unsigned int i, tmp;
842 unsigned int handled = 0;
843 void __iomem *mmio_base;
844 unsigned int hotplug_offset, ata_no;
845 u32 hotplug_status;
846 int is_sataii_tx4;
847
848 VPRINTK("ENTER\n");
849
850 if (!host || !host->iomap[PDC_MMIO_BAR]) {
851 VPRINTK("QUICK EXIT\n");
852 return IRQ_NONE;
853 }
854
855 mmio_base = host->iomap[PDC_MMIO_BAR];
856
857 spin_lock(&host->lock);
858
859 /* read and clear hotplug flags for all ports */
860 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
861 hotplug_offset = PDC2_SATA_PLUG_CSR;
862 else
863 hotplug_offset = PDC_SATA_PLUG_CSR;
864 hotplug_status = readl(mmio_base + hotplug_offset);
865 if (hotplug_status & 0xff)
866 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
867 hotplug_status &= 0xff; /* clear uninteresting bits */
868
869 /* reading should also clear interrupts */
870 mask = readl(mmio_base + PDC_INT_SEQMASK);
871
872 if (mask == 0xffffffff && hotplug_status == 0) {
873 VPRINTK("QUICK EXIT 2\n");
874 goto done_irq;
875 }
876
877 mask &= 0xffff; /* only 16 tags possible */
878 if (mask == 0 && hotplug_status == 0) {
879 VPRINTK("QUICK EXIT 3\n");
880 goto done_irq;
881 }
882
883 writel(mask, mmio_base + PDC_INT_SEQMASK);
884
885 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
886
887 for (i = 0; i < host->n_ports; i++) {
888 VPRINTK("port %u\n", i);
889 ap = host->ports[i];
890
891 /* check for a plug or unplug event */
892 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
893 tmp = hotplug_status & (0x11 << ata_no);
894 if (tmp && ap &&
895 !(ap->flags & ATA_FLAG_DISABLED)) {
896 struct ata_eh_info *ehi = &ap->link.eh_info;
897 ata_ehi_clear_desc(ehi);
898 ata_ehi_hotplugged(ehi);
899 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
900 ata_port_freeze(ap);
901 ++handled;
902 continue;
903 }
904
905 /* check for a packet interrupt */
906 tmp = mask & (1 << (i + 1));
907 if (tmp && ap &&
908 !(ap->flags & ATA_FLAG_DISABLED)) {
909 struct ata_queued_cmd *qc;
910
911 qc = ata_qc_from_tag(ap, ap->link.active_tag);
912 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
913 handled += pdc_host_intr(ap, qc);
914 }
915 }
916
917 VPRINTK("EXIT\n");
918
919 done_irq:
920 spin_unlock(&host->lock);
921 return IRQ_RETVAL(handled);
922 }
923
924 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
925 {
926 struct ata_port *ap = qc->ap;
927 struct pdc_port_priv *pp = ap->private_data;
928 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
929 unsigned int port_no = ap->port_no;
930 u8 seq = (u8) (port_no + 1);
931
932 VPRINTK("ENTER, ap %p\n", ap);
933
934 writel(0x00000001, mmio + (seq * 4));
935 readl(mmio + (seq * 4)); /* flush */
936
937 pp->pkt[2] = seq;
938 wmb(); /* flush PRD, pkt writes */
939 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
940 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
941 }
942
943 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
944 {
945 switch (qc->tf.protocol) {
946 case ATAPI_PROT_NODATA:
947 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
948 break;
949 /*FALLTHROUGH*/
950 case ATA_PROT_NODATA:
951 if (qc->tf.flags & ATA_TFLAG_POLLING)
952 break;
953 /*FALLTHROUGH*/
954 case ATAPI_PROT_DMA:
955 case ATA_PROT_DMA:
956 pdc_packet_start(qc);
957 return 0;
958
959 default:
960 break;
961 }
962
963 return ata_qc_issue_prot(qc);
964 }
965
966 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
967 {
968 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
969 ata_tf_load(ap, tf);
970 }
971
972 static void pdc_exec_command_mmio(struct ata_port *ap,
973 const struct ata_taskfile *tf)
974 {
975 WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
976 ata_exec_command(ap, tf);
977 }
978
979 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
980 {
981 u8 *scsicmd = qc->scsicmd->cmnd;
982 int pio = 1; /* atapi dma off by default */
983
984 /* Whitelist commands that may use DMA. */
985 switch (scsicmd[0]) {
986 case WRITE_12:
987 case WRITE_10:
988 case WRITE_6:
989 case READ_12:
990 case READ_10:
991 case READ_6:
992 case 0xad: /* READ_DVD_STRUCTURE */
993 case 0xbe: /* READ_CD */
994 pio = 0;
995 }
996 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
997 if (scsicmd[0] == WRITE_10) {
998 unsigned int lba =
999 (scsicmd[2] << 24) |
1000 (scsicmd[3] << 16) |
1001 (scsicmd[4] << 8) |
1002 scsicmd[5];
1003 if (lba >= 0xFFFF4FA2)
1004 pio = 1;
1005 }
1006 return pio;
1007 }
1008
1009 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1010 {
1011 /* First generation chips cannot use ATAPI DMA on SATA ports */
1012 return 1;
1013 }
1014
1015 static void pdc_ata_setup_port(struct ata_port *ap,
1016 void __iomem *base, void __iomem *scr_addr)
1017 {
1018 ap->ioaddr.cmd_addr = base;
1019 ap->ioaddr.data_addr = base;
1020 ap->ioaddr.feature_addr =
1021 ap->ioaddr.error_addr = base + 0x4;
1022 ap->ioaddr.nsect_addr = base + 0x8;
1023 ap->ioaddr.lbal_addr = base + 0xc;
1024 ap->ioaddr.lbam_addr = base + 0x10;
1025 ap->ioaddr.lbah_addr = base + 0x14;
1026 ap->ioaddr.device_addr = base + 0x18;
1027 ap->ioaddr.command_addr =
1028 ap->ioaddr.status_addr = base + 0x1c;
1029 ap->ioaddr.altstatus_addr =
1030 ap->ioaddr.ctl_addr = base + 0x38;
1031 ap->ioaddr.scr_addr = scr_addr;
1032 }
1033
1034 static void pdc_host_init(struct ata_host *host)
1035 {
1036 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1037 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1038 int hotplug_offset;
1039 u32 tmp;
1040
1041 if (is_gen2)
1042 hotplug_offset = PDC2_SATA_PLUG_CSR;
1043 else
1044 hotplug_offset = PDC_SATA_PLUG_CSR;
1045
1046 /*
1047 * Except for the hotplug stuff, this is voodoo from the
1048 * Promise driver. Label this entire section
1049 * "TODO: figure out why we do this"
1050 */
1051
1052 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1053 tmp = readl(mmio + PDC_FLASH_CTL);
1054 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1055 if (!is_gen2)
1056 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1057 writel(tmp, mmio + PDC_FLASH_CTL);
1058
1059 /* clear plug/unplug flags for all ports */
1060 tmp = readl(mmio + hotplug_offset);
1061 writel(tmp | 0xff, mmio + hotplug_offset);
1062
1063 /* unmask plug/unplug ints */
1064 tmp = readl(mmio + hotplug_offset);
1065 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1066
1067 /* don't initialise TBG or SLEW on 2nd generation chips */
1068 if (is_gen2)
1069 return;
1070
1071 /* reduce TBG clock to 133 Mhz. */
1072 tmp = readl(mmio + PDC_TBG_MODE);
1073 tmp &= ~0x30000; /* clear bit 17, 16*/
1074 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1075 writel(tmp, mmio + PDC_TBG_MODE);
1076
1077 readl(mmio + PDC_TBG_MODE); /* flush */
1078 msleep(10);
1079
1080 /* adjust slew rate control register. */
1081 tmp = readl(mmio + PDC_SLEW_CTL);
1082 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1083 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1084 writel(tmp, mmio + PDC_SLEW_CTL);
1085 }
1086
1087 static int pdc_ata_init_one(struct pci_dev *pdev,
1088 const struct pci_device_id *ent)
1089 {
1090 static int printed_version;
1091 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1092 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1093 struct ata_host *host;
1094 void __iomem *base;
1095 int n_ports, i, rc;
1096 int is_sataii_tx4;
1097
1098 if (!printed_version++)
1099 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1100
1101 /* enable and acquire resources */
1102 rc = pcim_enable_device(pdev);
1103 if (rc)
1104 return rc;
1105
1106 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1107 if (rc == -EBUSY)
1108 pcim_pin_device(pdev);
1109 if (rc)
1110 return rc;
1111 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1112
1113 /* determine port configuration and setup host */
1114 n_ports = 2;
1115 if (pi->flags & PDC_FLAG_4_PORTS)
1116 n_ports = 4;
1117 for (i = 0; i < n_ports; i++)
1118 ppi[i] = pi;
1119
1120 if (pi->flags & PDC_FLAG_SATA_PATA) {
1121 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1122 if (!(tmp & 0x80))
1123 ppi[n_ports++] = pi + 1;
1124 }
1125
1126 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1127 if (!host) {
1128 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1129 return -ENOMEM;
1130 }
1131 host->iomap = pcim_iomap_table(pdev);
1132
1133 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1134 for (i = 0; i < host->n_ports; i++) {
1135 struct ata_port *ap = host->ports[i];
1136 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1137 unsigned int port_offset = 0x200 + ata_no * 0x80;
1138 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1139
1140 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1141
1142 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1143 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1144 }
1145
1146 /* initialize adapter */
1147 pdc_host_init(host);
1148
1149 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1150 if (rc)
1151 return rc;
1152 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1153 if (rc)
1154 return rc;
1155
1156 /* start host, request IRQ and attach */
1157 pci_set_master(pdev);
1158 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1159 &pdc_ata_sht);
1160 }
1161
1162 static int __init pdc_ata_init(void)
1163 {
1164 return pci_register_driver(&pdc_ata_pci_driver);
1165 }
1166
1167 static void __exit pdc_ata_exit(void)
1168 {
1169 pci_unregister_driver(&pdc_ata_pci_driver);
1170 }
1171
1172 MODULE_AUTHOR("Jeff Garzik");
1173 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1174 MODULE_LICENSE("GPL");
1175 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1176 MODULE_VERSION(DRV_VERSION);
1177
1178 module_init(pdc_ata_init);
1179 module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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