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libata: replace tf_read with qc_fill_rtf for non-SFF drivers
[deliverable/linux.git] / drivers / ata / sata_sil24.c
1 /*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
31
32 #define DRV_NAME "sata_sil24"
33 #define DRV_VERSION "1.1"
34
35 /*
36 * Port request block (PRB) 32 bytes
37 */
38 struct sil24_prb {
39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
42 u8 fis[6 * 4];
43 };
44
45 /*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48 struct sil24_sge {
49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
52 };
53
54 /*
55 * Port multiplier
56 */
57 struct sil24_port_multiplier {
58 __le32 diag;
59 __le32 sactive;
60 };
61
62 enum {
63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
113
114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
119
120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
122
123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
128 /* 32 bit regs */
129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
150 PORT_CONTEXT = 0x1e04,
151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
183
184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
187
188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
220
221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
244
245 SIL24_MAX_CMDS = 31,
246
247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
250 BID_SIL3131 = 2,
251
252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
256 ATA_FLAG_AN | ATA_FLAG_PMP,
257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
258
259 IRQ_STAT_4PORTS = 0xf,
260 };
261
262 struct sil24_ata_block {
263 struct sil24_prb prb;
264 struct sil24_sge sge[SIL24_MAX_SGE];
265 };
266
267 struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
270 struct sil24_sge sge[SIL24_MAX_SGE];
271 };
272
273 union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276 };
277
278 static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281 } sil24_cerr_db[] = {
282 [0] = { AC_ERR_DEV, 0,
283 "device error" },
284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
285 "device error via D2H FIS" },
286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
287 "device error via SDB FIS" },
288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
289 "error in data FIS" },
290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
291 "failed to transmit command FIS" },
292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
293 "protocol mismatch" },
294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
295 "data directon mismatch" },
296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
297 "ran out of SGEs while writing" },
298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
299 "ran out of SGEs while reading" },
300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
301 "invalid data directon for ATAPI CDB" },
302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
303 "SGT not on qword boundary" },
304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
305 "PCI target abort while fetching SGT" },
306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
307 "PCI master abort while fetching SGT" },
308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
309 "PCI parity error while fetching SGT" },
310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
311 "PRB not on qword boundary" },
312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
313 "PCI target abort while fetching PRB" },
314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
315 "PCI master abort while fetching PRB" },
316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
317 "PCI parity error while fetching PRB" },
318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
319 "undefined error while transferring data" },
320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
321 "PCI target abort while transferring data" },
322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
323 "PCI master abort while transferring data" },
324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
325 "PCI parity error while transferring data" },
326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
327 "FIS received while sending service FIS" },
328 };
329
330 /*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336 struct sil24_port_priv {
337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
339 struct ata_taskfile tf; /* Cached taskfile registers */
340 int do_port_rst;
341 };
342
343 static void sil24_dev_config(struct ata_device *dev);
344 static u8 sil24_check_status(struct ata_port *ap);
345 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
346 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
347 static int sil24_qc_defer(struct ata_queued_cmd *qc);
348 static void sil24_qc_prep(struct ata_queued_cmd *qc);
349 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
350 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
351 static void sil24_pmp_attach(struct ata_port *ap);
352 static void sil24_pmp_detach(struct ata_port *ap);
353 static void sil24_freeze(struct ata_port *ap);
354 static void sil24_thaw(struct ata_port *ap);
355 static int sil24_softreset(struct ata_link *link, unsigned int *class,
356 unsigned long deadline);
357 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
358 unsigned long deadline);
359 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
360 unsigned long deadline);
361 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
362 unsigned long deadline);
363 static void sil24_error_handler(struct ata_port *ap);
364 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
365 static int sil24_port_start(struct ata_port *ap);
366 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
367 #ifdef CONFIG_PM
368 static int sil24_pci_device_resume(struct pci_dev *pdev);
369 static int sil24_port_resume(struct ata_port *ap);
370 #endif
371
372 static const struct pci_device_id sil24_pci_tbl[] = {
373 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
374 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
375 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
376 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
377 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
378 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
379
380 { } /* terminate list */
381 };
382
383 static struct pci_driver sil24_pci_driver = {
384 .name = DRV_NAME,
385 .id_table = sil24_pci_tbl,
386 .probe = sil24_init_one,
387 .remove = ata_pci_remove_one,
388 #ifdef CONFIG_PM
389 .suspend = ata_pci_device_suspend,
390 .resume = sil24_pci_device_resume,
391 #endif
392 };
393
394 static struct scsi_host_template sil24_sht = {
395 ATA_NCQ_SHT(DRV_NAME),
396 .can_queue = SIL24_MAX_CMDS,
397 .sg_tablesize = SIL24_MAX_SGE,
398 .dma_boundary = ATA_DMA_BOUNDARY,
399 };
400
401 static struct ata_port_operations sil24_ops = {
402 .inherits = &sata_pmp_port_ops,
403
404 .sff_check_status = sil24_check_status,
405 .sff_check_altstatus = sil24_check_status,
406 .qc_defer = sil24_qc_defer,
407 .qc_prep = sil24_qc_prep,
408 .qc_issue = sil24_qc_issue,
409 .qc_fill_rtf = sil24_qc_fill_rtf,
410
411 .freeze = sil24_freeze,
412 .thaw = sil24_thaw,
413 .softreset = sil24_softreset,
414 .hardreset = sil24_hardreset,
415 .pmp_softreset = sil24_pmp_softreset,
416 .pmp_hardreset = sil24_pmp_hardreset,
417 .error_handler = sil24_error_handler,
418 .post_internal_cmd = sil24_post_internal_cmd,
419 .dev_config = sil24_dev_config,
420
421 .scr_read = sil24_scr_read,
422 .scr_write = sil24_scr_write,
423 .pmp_attach = sil24_pmp_attach,
424 .pmp_detach = sil24_pmp_detach,
425
426 .port_start = sil24_port_start,
427 #ifdef CONFIG_PM
428 .port_resume = sil24_port_resume,
429 #endif
430 };
431
432 /*
433 * Use bits 30-31 of port_flags to encode available port numbers.
434 * Current maxium is 4.
435 */
436 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
437 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
438
439 static const struct ata_port_info sil24_port_info[] = {
440 /* sil_3124 */
441 {
442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
443 SIL24_FLAG_PCIX_IRQ_WOC,
444 .pio_mask = 0x1f, /* pio0-4 */
445 .mwdma_mask = 0x07, /* mwdma0-2 */
446 .udma_mask = ATA_UDMA5, /* udma0-5 */
447 .port_ops = &sil24_ops,
448 },
449 /* sil_3132 */
450 {
451 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
452 .pio_mask = 0x1f, /* pio0-4 */
453 .mwdma_mask = 0x07, /* mwdma0-2 */
454 .udma_mask = ATA_UDMA5, /* udma0-5 */
455 .port_ops = &sil24_ops,
456 },
457 /* sil_3131/sil_3531 */
458 {
459 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
460 .pio_mask = 0x1f, /* pio0-4 */
461 .mwdma_mask = 0x07, /* mwdma0-2 */
462 .udma_mask = ATA_UDMA5, /* udma0-5 */
463 .port_ops = &sil24_ops,
464 },
465 };
466
467 static int sil24_tag(int tag)
468 {
469 if (unlikely(ata_tag_internal(tag)))
470 return 0;
471 return tag;
472 }
473
474 static void sil24_dev_config(struct ata_device *dev)
475 {
476 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
477
478 if (dev->cdb_len == 16)
479 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
480 else
481 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
482 }
483
484 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
485 {
486 void __iomem *port = ap->ioaddr.cmd_addr;
487 struct sil24_prb __iomem *prb;
488 u8 fis[6 * 4];
489
490 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
491 memcpy_fromio(fis, prb->fis, sizeof(fis));
492 ata_tf_from_fis(fis, tf);
493 }
494
495 static u8 sil24_check_status(struct ata_port *ap)
496 {
497 struct sil24_port_priv *pp = ap->private_data;
498 return pp->tf.command;
499 }
500
501 static int sil24_scr_map[] = {
502 [SCR_CONTROL] = 0,
503 [SCR_STATUS] = 1,
504 [SCR_ERROR] = 2,
505 [SCR_ACTIVE] = 3,
506 };
507
508 static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
509 {
510 void __iomem *scr_addr = ap->ioaddr.scr_addr;
511
512 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
513 void __iomem *addr;
514 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
515 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
516 return 0;
517 }
518 return -EINVAL;
519 }
520
521 static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
522 {
523 void __iomem *scr_addr = ap->ioaddr.scr_addr;
524
525 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
526 void __iomem *addr;
527 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
528 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
529 return 0;
530 }
531 return -EINVAL;
532 }
533
534 static void sil24_config_port(struct ata_port *ap)
535 {
536 void __iomem *port = ap->ioaddr.cmd_addr;
537
538 /* configure IRQ WoC */
539 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
540 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
541 else
542 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
543
544 /* zero error counters. */
545 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
546 writel(0x8000, port + PORT_CRC_ERR_THRESH);
547 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
548 writel(0x0000, port + PORT_DECODE_ERR_CNT);
549 writel(0x0000, port + PORT_CRC_ERR_CNT);
550 writel(0x0000, port + PORT_HSHK_ERR_CNT);
551
552 /* always use 64bit activation */
553 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
554
555 /* clear port multiplier enable and resume bits */
556 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
557 }
558
559 static void sil24_config_pmp(struct ata_port *ap, int attached)
560 {
561 void __iomem *port = ap->ioaddr.cmd_addr;
562
563 if (attached)
564 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
565 else
566 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
567 }
568
569 static void sil24_clear_pmp(struct ata_port *ap)
570 {
571 void __iomem *port = ap->ioaddr.cmd_addr;
572 int i;
573
574 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
575
576 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
577 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
578
579 writel(0, pmp_base + PORT_PMP_STATUS);
580 writel(0, pmp_base + PORT_PMP_QACTIVE);
581 }
582 }
583
584 static int sil24_init_port(struct ata_port *ap)
585 {
586 void __iomem *port = ap->ioaddr.cmd_addr;
587 struct sil24_port_priv *pp = ap->private_data;
588 u32 tmp;
589
590 /* clear PMP error status */
591 if (ap->nr_pmp_links)
592 sil24_clear_pmp(ap);
593
594 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
595 ata_wait_register(port + PORT_CTRL_STAT,
596 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
597 tmp = ata_wait_register(port + PORT_CTRL_STAT,
598 PORT_CS_RDY, 0, 10, 100);
599
600 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
601 pp->do_port_rst = 1;
602 ap->link.eh_context.i.action |= ATA_EH_RESET;
603 return -EIO;
604 }
605
606 return 0;
607 }
608
609 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
610 const struct ata_taskfile *tf,
611 int is_cmd, u32 ctrl,
612 unsigned long timeout_msec)
613 {
614 void __iomem *port = ap->ioaddr.cmd_addr;
615 struct sil24_port_priv *pp = ap->private_data;
616 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
617 dma_addr_t paddr = pp->cmd_block_dma;
618 u32 irq_enabled, irq_mask, irq_stat;
619 int rc;
620
621 prb->ctrl = cpu_to_le16(ctrl);
622 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
623
624 /* temporarily plug completion and error interrupts */
625 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
626 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
627
628 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
629 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
630
631 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
632 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
633 10, timeout_msec);
634
635 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
636 irq_stat >>= PORT_IRQ_RAW_SHIFT;
637
638 if (irq_stat & PORT_IRQ_COMPLETE)
639 rc = 0;
640 else {
641 /* force port into known state */
642 sil24_init_port(ap);
643
644 if (irq_stat & PORT_IRQ_ERROR)
645 rc = -EIO;
646 else
647 rc = -EBUSY;
648 }
649
650 /* restore IRQ enabled */
651 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
652
653 return rc;
654 }
655
656 static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
657 int pmp, unsigned long deadline)
658 {
659 struct ata_port *ap = link->ap;
660 unsigned long timeout_msec = 0;
661 struct ata_taskfile tf;
662 const char *reason;
663 int rc;
664
665 DPRINTK("ENTER\n");
666
667 if (ata_link_offline(link)) {
668 DPRINTK("PHY reports no device\n");
669 *class = ATA_DEV_NONE;
670 goto out;
671 }
672
673 /* put the port into known state */
674 if (sil24_init_port(ap)) {
675 reason = "port not ready";
676 goto err;
677 }
678
679 /* do SRST */
680 if (time_after(deadline, jiffies))
681 timeout_msec = jiffies_to_msecs(deadline - jiffies);
682
683 ata_tf_init(link->device, &tf); /* doesn't really matter */
684 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
685 timeout_msec);
686 if (rc == -EBUSY) {
687 reason = "timeout";
688 goto err;
689 } else if (rc) {
690 reason = "SRST command error";
691 goto err;
692 }
693
694 sil24_read_tf(ap, 0, &tf);
695 *class = ata_dev_classify(&tf);
696
697 if (*class == ATA_DEV_UNKNOWN)
698 *class = ATA_DEV_NONE;
699
700 out:
701 DPRINTK("EXIT, class=%u\n", *class);
702 return 0;
703
704 err:
705 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
706 return -EIO;
707 }
708
709 static int sil24_softreset(struct ata_link *link, unsigned int *class,
710 unsigned long deadline)
711 {
712 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
713 }
714
715 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
716 unsigned long deadline)
717 {
718 struct ata_port *ap = link->ap;
719 void __iomem *port = ap->ioaddr.cmd_addr;
720 struct sil24_port_priv *pp = ap->private_data;
721 int did_port_rst = 0;
722 const char *reason;
723 int tout_msec, rc;
724 u32 tmp;
725
726 retry:
727 /* Sometimes, DEV_RST is not enough to recover the controller.
728 * This happens often after PM DMA CS errata.
729 */
730 if (pp->do_port_rst) {
731 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
732 "state, performing PORT_RST\n");
733
734 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
735 msleep(10);
736 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
737 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
738 10, 5000);
739
740 /* restore port configuration */
741 sil24_config_port(ap);
742 sil24_config_pmp(ap, ap->nr_pmp_links);
743
744 pp->do_port_rst = 0;
745 did_port_rst = 1;
746 }
747
748 /* sil24 does the right thing(tm) without any protection */
749 sata_set_spd(link);
750
751 tout_msec = 100;
752 if (ata_link_online(link))
753 tout_msec = 5000;
754
755 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
756 tmp = ata_wait_register(port + PORT_CTRL_STAT,
757 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
758 tout_msec);
759
760 /* SStatus oscillates between zero and valid status after
761 * DEV_RST, debounce it.
762 */
763 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
764 if (rc) {
765 reason = "PHY debouncing failed";
766 goto err;
767 }
768
769 if (tmp & PORT_CS_DEV_RST) {
770 if (ata_link_offline(link))
771 return 0;
772 reason = "link not ready";
773 goto err;
774 }
775
776 /* Sil24 doesn't store signature FIS after hardreset, so we
777 * can't wait for BSY to clear. Some devices take a long time
778 * to get ready and those devices will choke if we don't wait
779 * for BSY clearance here. Tell libata to perform follow-up
780 * softreset.
781 */
782 return -EAGAIN;
783
784 err:
785 if (!did_port_rst) {
786 pp->do_port_rst = 1;
787 goto retry;
788 }
789
790 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
791 return -EIO;
792 }
793
794 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
795 struct sil24_sge *sge)
796 {
797 struct scatterlist *sg;
798 struct sil24_sge *last_sge = NULL;
799 unsigned int si;
800
801 for_each_sg(qc->sg, sg, qc->n_elem, si) {
802 sge->addr = cpu_to_le64(sg_dma_address(sg));
803 sge->cnt = cpu_to_le32(sg_dma_len(sg));
804 sge->flags = 0;
805
806 last_sge = sge;
807 sge++;
808 }
809
810 last_sge->flags = cpu_to_le32(SGE_TRM);
811 }
812
813 static int sil24_qc_defer(struct ata_queued_cmd *qc)
814 {
815 struct ata_link *link = qc->dev->link;
816 struct ata_port *ap = link->ap;
817 u8 prot = qc->tf.protocol;
818
819 /*
820 * There is a bug in the chip:
821 * Port LRAM Causes the PRB/SGT Data to be Corrupted
822 * If the host issues a read request for LRAM and SActive registers
823 * while active commands are available in the port, PRB/SGT data in
824 * the LRAM can become corrupted. This issue applies only when
825 * reading from, but not writing to, the LRAM.
826 *
827 * Therefore, reading LRAM when there is no particular error [and
828 * other commands may be outstanding] is prohibited.
829 *
830 * To avoid this bug there are two situations where a command must run
831 * exclusive of any other commands on the port:
832 *
833 * - ATAPI commands which check the sense data
834 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
835 * set.
836 *
837 */
838 int is_excl = (ata_is_atapi(prot) ||
839 (qc->flags & ATA_QCFLAG_RESULT_TF));
840
841 if (unlikely(ap->excl_link)) {
842 if (link == ap->excl_link) {
843 if (ap->nr_active_links)
844 return ATA_DEFER_PORT;
845 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
846 } else
847 return ATA_DEFER_PORT;
848 } else if (unlikely(is_excl)) {
849 ap->excl_link = link;
850 if (ap->nr_active_links)
851 return ATA_DEFER_PORT;
852 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
853 }
854
855 return ata_std_qc_defer(qc);
856 }
857
858 static void sil24_qc_prep(struct ata_queued_cmd *qc)
859 {
860 struct ata_port *ap = qc->ap;
861 struct sil24_port_priv *pp = ap->private_data;
862 union sil24_cmd_block *cb;
863 struct sil24_prb *prb;
864 struct sil24_sge *sge;
865 u16 ctrl = 0;
866
867 cb = &pp->cmd_block[sil24_tag(qc->tag)];
868
869 if (!ata_is_atapi(qc->tf.protocol)) {
870 prb = &cb->ata.prb;
871 sge = cb->ata.sge;
872 } else {
873 prb = &cb->atapi.prb;
874 sge = cb->atapi.sge;
875 memset(cb->atapi.cdb, 0, 32);
876 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
877
878 if (ata_is_data(qc->tf.protocol)) {
879 if (qc->tf.flags & ATA_TFLAG_WRITE)
880 ctrl = PRB_CTRL_PACKET_WRITE;
881 else
882 ctrl = PRB_CTRL_PACKET_READ;
883 }
884 }
885
886 prb->ctrl = cpu_to_le16(ctrl);
887 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
888
889 if (qc->flags & ATA_QCFLAG_DMAMAP)
890 sil24_fill_sg(qc, sge);
891 }
892
893 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
894 {
895 struct ata_port *ap = qc->ap;
896 struct sil24_port_priv *pp = ap->private_data;
897 void __iomem *port = ap->ioaddr.cmd_addr;
898 unsigned int tag = sil24_tag(qc->tag);
899 dma_addr_t paddr;
900 void __iomem *activate;
901
902 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
903 activate = port + PORT_CMD_ACTIVATE + tag * 8;
904
905 writel((u32)paddr, activate);
906 writel((u64)paddr >> 32, activate + 4);
907
908 return 0;
909 }
910
911 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
912 {
913 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
914 return true;
915 }
916
917 static void sil24_pmp_attach(struct ata_port *ap)
918 {
919 sil24_config_pmp(ap, 1);
920 sil24_init_port(ap);
921 }
922
923 static void sil24_pmp_detach(struct ata_port *ap)
924 {
925 sil24_init_port(ap);
926 sil24_config_pmp(ap, 0);
927 }
928
929 static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
930 unsigned long deadline)
931 {
932 return sil24_do_softreset(link, class, link->pmp, deadline);
933 }
934
935 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
936 unsigned long deadline)
937 {
938 int rc;
939
940 rc = sil24_init_port(link->ap);
941 if (rc) {
942 ata_link_printk(link, KERN_ERR,
943 "hardreset failed (port not ready)\n");
944 return rc;
945 }
946
947 return sata_std_hardreset(link, class, deadline);
948 }
949
950 static void sil24_freeze(struct ata_port *ap)
951 {
952 void __iomem *port = ap->ioaddr.cmd_addr;
953
954 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
955 * PORT_IRQ_ENABLE instead.
956 */
957 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
958 }
959
960 static void sil24_thaw(struct ata_port *ap)
961 {
962 void __iomem *port = ap->ioaddr.cmd_addr;
963 u32 tmp;
964
965 /* clear IRQ */
966 tmp = readl(port + PORT_IRQ_STAT);
967 writel(tmp, port + PORT_IRQ_STAT);
968
969 /* turn IRQ back on */
970 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
971 }
972
973 static void sil24_error_intr(struct ata_port *ap)
974 {
975 void __iomem *port = ap->ioaddr.cmd_addr;
976 struct sil24_port_priv *pp = ap->private_data;
977 struct ata_queued_cmd *qc = NULL;
978 struct ata_link *link;
979 struct ata_eh_info *ehi;
980 int abort = 0, freeze = 0;
981 u32 irq_stat;
982
983 /* on error, we need to clear IRQ explicitly */
984 irq_stat = readl(port + PORT_IRQ_STAT);
985 writel(irq_stat, port + PORT_IRQ_STAT);
986
987 /* first, analyze and record host port events */
988 link = &ap->link;
989 ehi = &link->eh_info;
990 ata_ehi_clear_desc(ehi);
991
992 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
993
994 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
995 ata_ehi_push_desc(ehi, "SDB notify");
996 sata_async_notification(ap);
997 }
998
999 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1000 ata_ehi_hotplugged(ehi);
1001 ata_ehi_push_desc(ehi, "%s",
1002 irq_stat & PORT_IRQ_PHYRDY_CHG ?
1003 "PHY RDY changed" : "device exchanged");
1004 freeze = 1;
1005 }
1006
1007 if (irq_stat & PORT_IRQ_UNK_FIS) {
1008 ehi->err_mask |= AC_ERR_HSM;
1009 ehi->action |= ATA_EH_RESET;
1010 ata_ehi_push_desc(ehi, "unknown FIS");
1011 freeze = 1;
1012 }
1013
1014 /* deal with command error */
1015 if (irq_stat & PORT_IRQ_ERROR) {
1016 struct sil24_cerr_info *ci = NULL;
1017 unsigned int err_mask = 0, action = 0;
1018 u32 context, cerr;
1019 int pmp;
1020
1021 abort = 1;
1022
1023 /* DMA Context Switch Failure in Port Multiplier Mode
1024 * errata. If we have active commands to 3 or more
1025 * devices, any error condition on active devices can
1026 * corrupt DMA context switching.
1027 */
1028 if (ap->nr_active_links >= 3) {
1029 ehi->err_mask |= AC_ERR_OTHER;
1030 ehi->action |= ATA_EH_RESET;
1031 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1032 pp->do_port_rst = 1;
1033 freeze = 1;
1034 }
1035
1036 /* find out the offending link and qc */
1037 if (ap->nr_pmp_links) {
1038 context = readl(port + PORT_CONTEXT);
1039 pmp = (context >> 5) & 0xf;
1040
1041 if (pmp < ap->nr_pmp_links) {
1042 link = &ap->pmp_link[pmp];
1043 ehi = &link->eh_info;
1044 qc = ata_qc_from_tag(ap, link->active_tag);
1045
1046 ata_ehi_clear_desc(ehi);
1047 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1048 irq_stat);
1049 } else {
1050 err_mask |= AC_ERR_HSM;
1051 action |= ATA_EH_RESET;
1052 freeze = 1;
1053 }
1054 } else
1055 qc = ata_qc_from_tag(ap, link->active_tag);
1056
1057 /* analyze CMD_ERR */
1058 cerr = readl(port + PORT_CMD_ERR);
1059 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1060 ci = &sil24_cerr_db[cerr];
1061
1062 if (ci && ci->desc) {
1063 err_mask |= ci->err_mask;
1064 action |= ci->action;
1065 if (action & ATA_EH_RESET)
1066 freeze = 1;
1067 ata_ehi_push_desc(ehi, "%s", ci->desc);
1068 } else {
1069 err_mask |= AC_ERR_OTHER;
1070 action |= ATA_EH_RESET;
1071 freeze = 1;
1072 ata_ehi_push_desc(ehi, "unknown command error %d",
1073 cerr);
1074 }
1075
1076 /* record error info */
1077 if (qc) {
1078 sil24_read_tf(ap, qc->tag, &pp->tf);
1079 qc->err_mask |= err_mask;
1080 } else
1081 ehi->err_mask |= err_mask;
1082
1083 ehi->action |= action;
1084
1085 /* if PMP, resume */
1086 if (ap->nr_pmp_links)
1087 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1088 }
1089
1090 /* freeze or abort */
1091 if (freeze)
1092 ata_port_freeze(ap);
1093 else if (abort) {
1094 if (qc)
1095 ata_link_abort(qc->dev->link);
1096 else
1097 ata_port_abort(ap);
1098 }
1099 }
1100
1101 static inline void sil24_host_intr(struct ata_port *ap)
1102 {
1103 void __iomem *port = ap->ioaddr.cmd_addr;
1104 u32 slot_stat, qc_active;
1105 int rc;
1106
1107 /* If PCIX_IRQ_WOC, there's an inherent race window between
1108 * clearing IRQ pending status and reading PORT_SLOT_STAT
1109 * which may cause spurious interrupts afterwards. This is
1110 * unavoidable and much better than losing interrupts which
1111 * happens if IRQ pending is cleared after reading
1112 * PORT_SLOT_STAT.
1113 */
1114 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1115 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1116
1117 slot_stat = readl(port + PORT_SLOT_STAT);
1118
1119 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1120 sil24_error_intr(ap);
1121 return;
1122 }
1123
1124 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1125 rc = ata_qc_complete_multiple(ap, qc_active);
1126 if (rc > 0)
1127 return;
1128 if (rc < 0) {
1129 struct ata_eh_info *ehi = &ap->link.eh_info;
1130 ehi->err_mask |= AC_ERR_HSM;
1131 ehi->action |= ATA_EH_RESET;
1132 ata_port_freeze(ap);
1133 return;
1134 }
1135
1136 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1137 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1138 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1139 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1140 slot_stat, ap->link.active_tag, ap->link.sactive);
1141 }
1142
1143 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1144 {
1145 struct ata_host *host = dev_instance;
1146 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1147 unsigned handled = 0;
1148 u32 status;
1149 int i;
1150
1151 status = readl(host_base + HOST_IRQ_STAT);
1152
1153 if (status == 0xffffffff) {
1154 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1155 "PCI fault or device removal?\n");
1156 goto out;
1157 }
1158
1159 if (!(status & IRQ_STAT_4PORTS))
1160 goto out;
1161
1162 spin_lock(&host->lock);
1163
1164 for (i = 0; i < host->n_ports; i++)
1165 if (status & (1 << i)) {
1166 struct ata_port *ap = host->ports[i];
1167 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
1168 sil24_host_intr(ap);
1169 handled++;
1170 } else
1171 printk(KERN_ERR DRV_NAME
1172 ": interrupt from disabled port %d\n", i);
1173 }
1174
1175 spin_unlock(&host->lock);
1176 out:
1177 return IRQ_RETVAL(handled);
1178 }
1179
1180 static void sil24_error_handler(struct ata_port *ap)
1181 {
1182 struct sil24_port_priv *pp = ap->private_data;
1183
1184 if (sil24_init_port(ap))
1185 ata_eh_freeze_port(ap);
1186
1187 sata_pmp_error_handler(ap);
1188
1189 pp->do_port_rst = 0;
1190 }
1191
1192 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1193 {
1194 struct ata_port *ap = qc->ap;
1195
1196 /* make DMA engine forget about the failed command */
1197 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1198 ata_eh_freeze_port(ap);
1199 }
1200
1201 static int sil24_port_start(struct ata_port *ap)
1202 {
1203 struct device *dev = ap->host->dev;
1204 struct sil24_port_priv *pp;
1205 union sil24_cmd_block *cb;
1206 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1207 dma_addr_t cb_dma;
1208
1209 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1210 if (!pp)
1211 return -ENOMEM;
1212
1213 pp->tf.command = ATA_DRDY;
1214
1215 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1216 if (!cb)
1217 return -ENOMEM;
1218 memset(cb, 0, cb_size);
1219
1220 pp->cmd_block = cb;
1221 pp->cmd_block_dma = cb_dma;
1222
1223 ap->private_data = pp;
1224
1225 return 0;
1226 }
1227
1228 static void sil24_init_controller(struct ata_host *host)
1229 {
1230 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1231 u32 tmp;
1232 int i;
1233
1234 /* GPIO off */
1235 writel(0, host_base + HOST_FLASH_CMD);
1236
1237 /* clear global reset & mask interrupts during initialization */
1238 writel(0, host_base + HOST_CTRL);
1239
1240 /* init ports */
1241 for (i = 0; i < host->n_ports; i++) {
1242 struct ata_port *ap = host->ports[i];
1243 void __iomem *port = ap->ioaddr.cmd_addr;
1244
1245 /* Initial PHY setting */
1246 writel(0x20c, port + PORT_PHY_CFG);
1247
1248 /* Clear port RST */
1249 tmp = readl(port + PORT_CTRL_STAT);
1250 if (tmp & PORT_CS_PORT_RST) {
1251 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1252 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1253 PORT_CS_PORT_RST,
1254 PORT_CS_PORT_RST, 10, 100);
1255 if (tmp & PORT_CS_PORT_RST)
1256 dev_printk(KERN_ERR, host->dev,
1257 "failed to clear port RST\n");
1258 }
1259
1260 /* configure port */
1261 sil24_config_port(ap);
1262 }
1263
1264 /* Turn on interrupts */
1265 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1266 }
1267
1268 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1269 {
1270 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1271 static int printed_version;
1272 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1273 const struct ata_port_info *ppi[] = { &pi, NULL };
1274 void __iomem * const *iomap;
1275 struct ata_host *host;
1276 int i, rc;
1277 u32 tmp;
1278
1279 /* cause link error if sil24_cmd_block is sized wrongly */
1280 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1281 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1282
1283 if (!printed_version++)
1284 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1285
1286 /* acquire resources */
1287 rc = pcim_enable_device(pdev);
1288 if (rc)
1289 return rc;
1290
1291 rc = pcim_iomap_regions(pdev,
1292 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1293 DRV_NAME);
1294 if (rc)
1295 return rc;
1296 iomap = pcim_iomap_table(pdev);
1297
1298 /* apply workaround for completion IRQ loss on PCI-X errata */
1299 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1300 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1301 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1302 dev_printk(KERN_INFO, &pdev->dev,
1303 "Applying completion IRQ loss on PCI-X "
1304 "errata fix\n");
1305 else
1306 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1307 }
1308
1309 /* allocate and fill host */
1310 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1311 SIL24_FLAG2NPORTS(ppi[0]->flags));
1312 if (!host)
1313 return -ENOMEM;
1314 host->iomap = iomap;
1315
1316 for (i = 0; i < host->n_ports; i++) {
1317 struct ata_port *ap = host->ports[i];
1318 size_t offset = ap->port_no * PORT_REGS_SIZE;
1319 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
1320
1321 host->ports[i]->ioaddr.cmd_addr = port;
1322 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1323
1324 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1325 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
1326 }
1327
1328 /* configure and activate the device */
1329 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1330 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1331 if (rc) {
1332 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1333 if (rc) {
1334 dev_printk(KERN_ERR, &pdev->dev,
1335 "64-bit DMA enable failed\n");
1336 return rc;
1337 }
1338 }
1339 } else {
1340 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1341 if (rc) {
1342 dev_printk(KERN_ERR, &pdev->dev,
1343 "32-bit DMA enable failed\n");
1344 return rc;
1345 }
1346 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1347 if (rc) {
1348 dev_printk(KERN_ERR, &pdev->dev,
1349 "32-bit consistent DMA enable failed\n");
1350 return rc;
1351 }
1352 }
1353
1354 sil24_init_controller(host);
1355
1356 pci_set_master(pdev);
1357 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1358 &sil24_sht);
1359 }
1360
1361 #ifdef CONFIG_PM
1362 static int sil24_pci_device_resume(struct pci_dev *pdev)
1363 {
1364 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1365 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1366 int rc;
1367
1368 rc = ata_pci_device_do_resume(pdev);
1369 if (rc)
1370 return rc;
1371
1372 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1373 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1374
1375 sil24_init_controller(host);
1376
1377 ata_host_resume(host);
1378
1379 return 0;
1380 }
1381
1382 static int sil24_port_resume(struct ata_port *ap)
1383 {
1384 sil24_config_pmp(ap, ap->nr_pmp_links);
1385 return 0;
1386 }
1387 #endif
1388
1389 static int __init sil24_init(void)
1390 {
1391 return pci_register_driver(&sil24_pci_driver);
1392 }
1393
1394 static void __exit sil24_exit(void)
1395 {
1396 pci_unregister_driver(&sil24_pci_driver);
1397 }
1398
1399 MODULE_AUTHOR("Tejun Heo");
1400 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1401 MODULE_LICENSE("GPL");
1402 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1403
1404 module_init(sil24_init);
1405 module_exit(sil24_exit);
Linux kernel - Deliverables
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