2 * Broadcom specific AMBA
3 * ChipCommon Power Management Unit driver
5 * Copyright 2009, Michael Buesch <m@bues.ch>
6 * Copyright 2007, 2011, Broadcom Corporation
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/export.h>
14 #include <linux/bcma/bcma.h>
16 static u32
bcma_chipco_pll_read(struct bcma_drv_cc
*cc
, u32 offset
)
18 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
19 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
20 return bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
23 void bcma_chipco_pll_write(struct bcma_drv_cc
*cc
, u32 offset
, u32 value
)
25 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
26 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
27 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, value
);
29 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write
);
31 void bcma_chipco_pll_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
34 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
35 bcma_cc_read32(cc
, BCMA_CC_PLLCTL_ADDR
);
36 bcma_cc_maskset32(cc
, BCMA_CC_PLLCTL_DATA
, mask
, set
);
38 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset
);
40 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc
*cc
,
41 u32 offset
, u32 mask
, u32 set
)
43 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL_ADDR
, offset
);
44 bcma_cc_read32(cc
, BCMA_CC_CHIPCTL_ADDR
);
45 bcma_cc_maskset32(cc
, BCMA_CC_CHIPCTL_DATA
, mask
, set
);
47 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset
);
49 void bcma_chipco_regctl_maskset(struct bcma_drv_cc
*cc
, u32 offset
, u32 mask
,
52 bcma_cc_write32(cc
, BCMA_CC_REGCTL_ADDR
, offset
);
53 bcma_cc_read32(cc
, BCMA_CC_REGCTL_ADDR
);
54 bcma_cc_maskset32(cc
, BCMA_CC_REGCTL_DATA
, mask
, set
);
56 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset
);
58 static void bcma_pmu_resources_init(struct bcma_drv_cc
*cc
)
60 struct bcma_bus
*bus
= cc
->core
->bus
;
61 u32 min_msk
= 0, max_msk
= 0;
63 switch (bus
->chipinfo
.id
) {
64 case BCMA_CHIP_ID_BCM4313
:
69 bcma_debug(bus
, "PMU resource config unknown or not needed for device 0x%04X\n",
73 /* Set the resource masks. */
75 bcma_cc_write32(cc
, BCMA_CC_PMU_MINRES_MSK
, min_msk
);
77 bcma_cc_write32(cc
, BCMA_CC_PMU_MAXRES_MSK
, max_msk
);
79 /* Add some delay; allow resources to come up and settle. */
83 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
84 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc
*cc
, bool enable
)
86 struct bcma_bus
*bus
= cc
->core
->bus
;
89 val
= bcma_cc_read32(cc
, BCMA_CC_CHIPCTL
);
91 val
|= BCMA_CHIPCTL_4331_EXTPA_EN
;
92 if (bus
->chipinfo
.pkg
== 9 || bus
->chipinfo
.pkg
== 11)
93 val
|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
94 else if (bus
->chipinfo
.rev
> 0)
95 val
|= BCMA_CHIPCTL_4331_EXTPA_EN2
;
97 val
&= ~BCMA_CHIPCTL_4331_EXTPA_EN
;
98 val
&= ~BCMA_CHIPCTL_4331_EXTPA_EN2
;
99 val
&= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5
;
101 bcma_cc_write32(cc
, BCMA_CC_CHIPCTL
, val
);
104 void bcma_pmu_workarounds(struct bcma_drv_cc
*cc
)
106 struct bcma_bus
*bus
= cc
->core
->bus
;
108 switch (bus
->chipinfo
.id
) {
109 case BCMA_CHIP_ID_BCM4313
:
110 /* enable 12 mA drive strenth for 4313 and set chipControl
112 bcma_chipco_chipctl_maskset(cc
, 0,
113 ~BCMA_CCTRL_4313_12MA_LED_DRIVE
,
114 BCMA_CCTRL_4313_12MA_LED_DRIVE
);
116 case BCMA_CHIP_ID_BCM4331
:
117 case BCMA_CHIP_ID_BCM43431
:
118 /* Ext PA lines must be enabled for tx on BCM4331 */
119 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc
, true);
121 case BCMA_CHIP_ID_BCM43224
:
122 case BCMA_CHIP_ID_BCM43421
:
123 /* enable 12 mA drive strenth for 43224 and set chipControl
125 if (bus
->chipinfo
.rev
== 0) {
126 bcma_cc_maskset32(cc
, BCMA_CC_CHIPCTL
,
127 ~BCMA_CCTRL_43224_GPIO_TOGGLE
,
128 BCMA_CCTRL_43224_GPIO_TOGGLE
);
129 bcma_chipco_chipctl_maskset(cc
, 0,
130 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE
,
131 BCMA_CCTRL_43224A0_12MA_LED_DRIVE
);
133 bcma_chipco_chipctl_maskset(cc
, 0,
134 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE
,
135 BCMA_CCTRL_43224B0_12MA_LED_DRIVE
);
139 bcma_debug(bus
, "Workarounds unknown or not needed for device 0x%04X\n",
144 void bcma_pmu_init(struct bcma_drv_cc
*cc
)
148 pmucap
= bcma_cc_read32(cc
, BCMA_CC_PMU_CAP
);
149 cc
->pmu
.rev
= (pmucap
& BCMA_CC_PMU_CAP_REVISION
);
151 bcma_debug(cc
->core
->bus
, "Found rev %u PMU (capabilities 0x%08X)\n",
152 cc
->pmu
.rev
, pmucap
);
154 if (cc
->pmu
.rev
== 1)
155 bcma_cc_mask32(cc
, BCMA_CC_PMU_CTL
,
156 ~BCMA_CC_PMU_CTL_NOILPONW
);
158 bcma_cc_set32(cc
, BCMA_CC_PMU_CTL
,
159 BCMA_CC_PMU_CTL_NOILPONW
);
161 bcma_pmu_resources_init(cc
);
162 bcma_pmu_workarounds(cc
);
165 u32
bcma_pmu_alp_clock(struct bcma_drv_cc
*cc
)
167 struct bcma_bus
*bus
= cc
->core
->bus
;
169 switch (bus
->chipinfo
.id
) {
170 case BCMA_CHIP_ID_BCM4716
:
171 case BCMA_CHIP_ID_BCM4748
:
172 case BCMA_CHIP_ID_BCM47162
:
173 case BCMA_CHIP_ID_BCM4313
:
174 case BCMA_CHIP_ID_BCM5357
:
175 case BCMA_CHIP_ID_BCM4749
:
176 case BCMA_CHIP_ID_BCM53572
:
179 case BCMA_CHIP_ID_BCM5356
:
180 case BCMA_CHIP_ID_BCM4706
:
184 bcma_warn(bus
, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
185 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_ALP_CLOCK
);
187 return BCMA_CC_PMU_ALP_CLOCK
;
190 /* Find the output of the "m" pll divider given pll controls that start with
191 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
193 static u32
bcma_pmu_clock(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
195 u32 tmp
, div
, ndiv
, p1
, p2
, fc
;
196 struct bcma_bus
*bus
= cc
->core
->bus
;
198 BUG_ON((pll0
& 3) || (pll0
> BCMA_CC_PMU4716_MAINPLL_PLL0
));
202 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM5357
||
203 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4749
) {
204 /* Detect failure in clock setting */
205 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
207 return 133 * 1000000;
210 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_P1P2_OFF
);
211 p1
= (tmp
& BCMA_CC_PPL_P1_MASK
) >> BCMA_CC_PPL_P1_SHIFT
;
212 p2
= (tmp
& BCMA_CC_PPL_P2_MASK
) >> BCMA_CC_PPL_P2_SHIFT
;
214 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_M14_OFF
);
215 div
= (tmp
>> ((m
- 1) * BCMA_CC_PPL_MDIV_WIDTH
)) &
216 BCMA_CC_PPL_MDIV_MASK
;
218 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PPL_NM5_OFF
);
219 ndiv
= (tmp
& BCMA_CC_PPL_NDIV_MASK
) >> BCMA_CC_PPL_NDIV_SHIFT
;
221 /* Do calculation in Mhz */
222 fc
= bcma_pmu_alp_clock(cc
) / 1000000;
223 fc
= (p1
* ndiv
* fc
) / p2
;
225 /* Return clock in Hertz */
226 return (fc
/ div
) * 1000000;
229 static u32
bcma_pmu_clock_bcm4706(struct bcma_drv_cc
*cc
, u32 pll0
, u32 m
)
231 u32 tmp
, ndiv
, p1div
, p2div
;
236 /* Get N, P1 and P2 dividers to determine CPU clock */
237 tmp
= bcma_chipco_pll_read(cc
, pll0
+ BCMA_CC_PMU6_4706_PROCPLL_OFF
);
238 ndiv
= (tmp
& BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK
)
239 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT
;
240 p1div
= (tmp
& BCMA_CC_PMU6_4706_PROC_P1DIV_MASK
)
241 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT
;
242 p2div
= (tmp
& BCMA_CC_PMU6_4706_PROC_P2DIV_MASK
)
243 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT
;
245 tmp
= bcma_cc_read32(cc
, BCMA_CC_CHIPSTAT
);
246 if (tmp
& BCMA_CC_CHIPST_4706_PKG_OPTION
)
247 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
248 clock
= (25000000 / 4) * ndiv
* p2div
/ p1div
;
250 /* Fixed reference clock 25MHz and m = 2 */
251 clock
= (25000000 / 2) * ndiv
* p2div
/ p1div
;
253 if (m
== BCMA_CC_PMU5_MAINPLL_SSB
)
259 /* query bus clock frequency for PMU-enabled chipcommon */
260 u32
bcma_pmu_get_clockcontrol(struct bcma_drv_cc
*cc
)
262 struct bcma_bus
*bus
= cc
->core
->bus
;
264 switch (bus
->chipinfo
.id
) {
265 case BCMA_CHIP_ID_BCM4716
:
266 case BCMA_CHIP_ID_BCM4748
:
267 case BCMA_CHIP_ID_BCM47162
:
268 return bcma_pmu_clock(cc
, BCMA_CC_PMU4716_MAINPLL_PLL0
,
269 BCMA_CC_PMU5_MAINPLL_SSB
);
270 case BCMA_CHIP_ID_BCM5356
:
271 return bcma_pmu_clock(cc
, BCMA_CC_PMU5356_MAINPLL_PLL0
,
272 BCMA_CC_PMU5_MAINPLL_SSB
);
273 case BCMA_CHIP_ID_BCM5357
:
274 case BCMA_CHIP_ID_BCM4749
:
275 return bcma_pmu_clock(cc
, BCMA_CC_PMU5357_MAINPLL_PLL0
,
276 BCMA_CC_PMU5_MAINPLL_SSB
);
277 case BCMA_CHIP_ID_BCM4706
:
278 return bcma_pmu_clock_bcm4706(cc
, BCMA_CC_PMU4706_MAINPLL_PLL0
,
279 BCMA_CC_PMU5_MAINPLL_SSB
);
280 case BCMA_CHIP_ID_BCM53572
:
283 bcma_warn(bus
, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
284 bus
->chipinfo
.id
, cc
->pmu
.rev
, BCMA_CC_PMU_HT_CLOCK
);
286 return BCMA_CC_PMU_HT_CLOCK
;
289 /* query cpu clock frequency for PMU-enabled chipcommon */
290 u32
bcma_pmu_get_clockcpu(struct bcma_drv_cc
*cc
)
292 struct bcma_bus
*bus
= cc
->core
->bus
;
294 if (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM53572
)
297 if (cc
->pmu
.rev
>= 5) {
299 switch (bus
->chipinfo
.id
) {
300 case BCMA_CHIP_ID_BCM4706
:
301 return bcma_pmu_clock_bcm4706(cc
,
302 BCMA_CC_PMU4706_MAINPLL_PLL0
,
303 BCMA_CC_PMU5_MAINPLL_CPU
);
304 case BCMA_CHIP_ID_BCM5356
:
305 pll
= BCMA_CC_PMU5356_MAINPLL_PLL0
;
307 case BCMA_CHIP_ID_BCM5357
:
308 case BCMA_CHIP_ID_BCM4749
:
309 pll
= BCMA_CC_PMU5357_MAINPLL_PLL0
;
312 pll
= BCMA_CC_PMU4716_MAINPLL_PLL0
;
316 return bcma_pmu_clock(cc
, pll
, BCMA_CC_PMU5_MAINPLL_CPU
);
319 return bcma_pmu_get_clockcontrol(cc
);
322 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc
*cc
, u32 offset
,
325 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
, offset
);
326 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, value
);
329 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc
*cc
, int spuravoid
)
332 u8 phypll_offset
= 0;
333 u8 bcm5357_bcm43236_p1div
[] = {0x1, 0x5, 0x5};
334 u8 bcm5357_bcm43236_ndiv
[] = {0x30, 0xf6, 0xfc};
335 struct bcma_bus
*bus
= cc
->core
->bus
;
337 switch (bus
->chipinfo
.id
) {
338 case BCMA_CHIP_ID_BCM5357
:
339 case BCMA_CHIP_ID_BCM4749
:
340 case BCMA_CHIP_ID_BCM53572
:
341 /* 5357[ab]0, 43236[ab]0, and 6362b0 */
343 /* BCM5357 needs to touch PLL1_PLLCTL[02],
344 so offset PLL0_PLLCTL[02] by 6 */
345 phypll_offset
= (bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM5357
||
346 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM4749
||
347 bus
->chipinfo
.id
== BCMA_CHIP_ID_BCM53572
) ? 6 : 0;
349 /* RMW only the P1 divider */
350 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
,
351 BCMA_CC_PMU_PLL_CTL0
+ phypll_offset
);
352 tmp
= bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
353 tmp
&= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK
));
354 tmp
|= (bcm5357_bcm43236_p1div
[spuravoid
] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT
);
355 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, tmp
);
357 /* RMW only the int feedback divider */
358 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_ADDR
,
359 BCMA_CC_PMU_PLL_CTL2
+ phypll_offset
);
360 tmp
= bcma_cc_read32(cc
, BCMA_CC_PLLCTL_DATA
);
361 tmp
&= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK
);
362 tmp
|= (bcm5357_bcm43236_ndiv
[spuravoid
]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT
;
363 bcma_cc_write32(cc
, BCMA_CC_PLLCTL_DATA
, tmp
);
368 case BCMA_CHIP_ID_BCM4331
:
369 case BCMA_CHIP_ID_BCM43431
:
370 if (spuravoid
== 2) {
371 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
373 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
375 } else if (spuravoid
== 1) {
376 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
378 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
381 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
383 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
389 case BCMA_CHIP_ID_BCM43224
:
390 case BCMA_CHIP_ID_BCM43225
:
391 case BCMA_CHIP_ID_BCM43421
:
392 if (spuravoid
== 1) {
393 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
395 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
397 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
399 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
401 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
403 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
406 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
408 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
410 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
412 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
414 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
416 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
422 case BCMA_CHIP_ID_BCM4716
:
423 case BCMA_CHIP_ID_BCM4748
:
424 case BCMA_CHIP_ID_BCM47162
:
425 if (spuravoid
== 1) {
426 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
428 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
430 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
432 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
434 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
436 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
439 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
441 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
443 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
445 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
447 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
449 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
456 case BCMA_CHIP_ID_BCM43227
:
457 case BCMA_CHIP_ID_BCM43228
:
458 case BCMA_CHIP_ID_BCM43428
:
460 /* PLL Settings for spur avoidance on/off mode,
461 no on2 support for 43228A0 */
462 if (spuravoid
== 1) {
463 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
465 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
467 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
469 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
471 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
473 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
476 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL0
,
478 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL1
,
480 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL2
,
482 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL3
,
484 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL4
,
486 bcma_pmu_spuravoid_pll_write(cc
, BCMA_CC_PMU_PLL_CTL5
,
492 bcma_err(bus
, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
497 tmp
|= bcma_cc_read32(cc
, BCMA_CC_PMU_CTL
);
498 bcma_cc_write32(cc
, BCMA_CC_PMU_CTL
, tmp
);
500 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate
);