2 * Broadcom specific AMBA
5 * Copyright 2014, Broadcom Corporation
6 * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
8 * Licensed under the GNU/GPL. See COPYING for details.
11 #include "bcma_private.h"
12 #include <linux/bcma/bcma.h>
14 /**************************************************
16 **************************************************/
19 static u32
bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2
*pcie2
, u32 addr
)
21 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, addr
);
22 pcie2_read32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
);
23 return pcie2_read32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
);
27 static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2
*pcie2
, u32 addr
,
30 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, addr
);
31 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, val
);
34 /**************************************************
36 **************************************************/
38 static u32
bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2
*pcie2
,
43 /* restore back to default */
44 val
= pcie2_read32(pcie2
, BCMA_CORE_PCIE2_CLK_CONTROL
);
45 val
|= PCIE2_CLKC_DLYPERST
;
46 val
&= ~PCIE2_CLKC_DISSPROMLD
;
48 val
&= ~PCIE2_CLKC_DLYPERST
;
49 val
|= PCIE2_CLKC_DISSPROMLD
;
51 pcie2_write32(pcie2
, (BCMA_CORE_PCIE2_CLK_CONTROL
), val
);
53 return pcie2_read32(pcie2
, BCMA_CORE_PCIE2_CLK_CONTROL
);
56 static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2
*pcie2
)
59 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, 0x844);
60 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, 0x883c883c);
62 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, 0x848);
63 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, 0x88648864);
65 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, 0x84C);
66 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, 0x90039003);
69 static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2
*pcie2
)
71 u8 core_rev
= pcie2
->core
->id
.rev
;
74 if (core_rev
< 2 || core_rev
== 10 || core_rev
> 13)
77 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
,
78 PCIE2_CAP_DEVSTSCTRL2_OFFSET
);
79 devstsctr2
= pcie2_read32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
);
80 if (devstsctr2
& PCIE2_CAP_DEVSTSCTRL2_LTRENAB
) {
81 /* force the right LTR values */
82 bcma_core_pcie2_set_ltr_vals(pcie2
);
85 si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
88 devstsctr2
|= PCIE2_CAP_DEVSTSCTRL2_LTRENAB
;
89 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
,
90 PCIE2_CAP_DEVSTSCTRL2_OFFSET
);
91 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, devstsctr2
);
93 /* set the LTR state to be active */
94 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_LTR_STATE
,
96 usleep_range(1000, 2000);
98 /* set the LTR state to be sleep */
99 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_LTR_STATE
,
101 usleep_range(1000, 2000);
105 static void pciedev_crwlpciegen2(struct bcma_drv_pcie2
*pcie2
)
107 u8 core_rev
= pcie2
->core
->id
.rev
;
108 bool pciewar160
, pciewar162
;
110 pciewar160
= core_rev
== 7 || core_rev
== 9 || core_rev
== 11;
111 pciewar162
= core_rev
== 5 || core_rev
== 7 || core_rev
== 8 ||
112 core_rev
== 9 || core_rev
== 11;
114 if (!pciewar160
&& !pciewar162
)
119 pcie2_set32(pcie2
, BCMA_CORE_PCIE2_CLK_CONTROL
,
120 PCIE_DISABLE_L1CLK_GATING
);
122 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
,
123 PCIEGEN2_COE_PVT_TL_CTRL_0
);
124 pcie2_mask32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
,
125 ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT
));
130 static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2
*pcie2
)
132 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, PCIE2_PMCR_REFUP
);
133 pcie2_set32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, 0x1f);
136 static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2
*pcie2
)
138 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
, PCIE2_SBMBX
);
139 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, 1 << 0);
142 static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2
*pcie2
)
144 struct bcma_drv_cc
*drv_cc
= &pcie2
->core
->bus
->drv_cc
;
145 u8 core_rev
= pcie2
->core
->id
.rev
;
146 u32 alp_khz
, pm_value
;
148 if (core_rev
<= 13) {
149 alp_khz
= bcma_pmu_get_alp_clock(drv_cc
) / 1000;
150 pm_value
= (1000000 * 2) / alp_khz
;
151 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDADDR
,
152 PCIE2_PVT_REG_PM_CLK_PERIOD
);
153 pcie2_write32(pcie2
, BCMA_CORE_PCIE2_CONFIGINDDATA
, pm_value
);
157 void bcma_core_pcie2_init(struct bcma_drv_pcie2
*pcie2
)
159 struct bcma_chipinfo
*ci
= &pcie2
->core
->bus
->chipinfo
;
162 tmp
= pcie2_read32(pcie2
, BCMA_CORE_PCIE2_SPROM(54));
163 if ((tmp
& 0xe) >> 1 == 2)
164 bcma_core_pcie2_cfg_write(pcie2
, 0x4e0, 0x17);
166 /* TODO: Do we need pcie_reqsize? */
168 if (ci
->id
== BCMA_CHIP_ID_BCM4360
&& ci
->rev
> 3)
169 bcma_core_pcie2_war_delay_perst_enab(pcie2
, true);
170 bcma_core_pcie2_hw_ltr_war(pcie2
);
171 pciedev_crwlpciegen2(pcie2
);
172 pciedev_reg_pm_clk_period(pcie2
);
173 pciedev_crwlpciegen2_180(pcie2
);
174 pciedev_crwlpciegen2_182(pcie2
);