2 * Setup routines for AGP 3.5 compliant bridges.
5 #include <linux/list.h>
7 #include <linux/agp_backend.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
13 /* Generic AGP 3.5 enabling routines */
16 struct list_head list
;
22 static void agp_3_5_dev_list_insert(struct list_head
*head
, struct list_head
*new)
24 struct agp_3_5_dev
*cur
, *n
= list_entry(new, struct agp_3_5_dev
, list
);
25 struct list_head
*pos
;
27 list_for_each(pos
, head
) {
28 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
29 if (cur
->maxbw
> n
->maxbw
)
32 list_add_tail(new, pos
);
35 static void agp_3_5_dev_list_sort(struct agp_3_5_dev
*list
, unsigned int ndevs
)
37 struct agp_3_5_dev
*cur
;
39 struct list_head
*pos
, *tmp
, *head
= &list
->list
, *start
= head
->next
;
44 for (pos
=start
; pos
!=head
; ) {
45 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
48 pci_read_config_dword(dev
, cur
->capndx
+AGPNISTAT
, &nistat
);
49 cur
->maxbw
= (nistat
>> 16) & 0xff;
53 agp_3_5_dev_list_insert(head
, tmp
);
58 * Initialize all isochronous transfer parameters for an AGP 3.0
59 * node (i.e. a host bridge in combination with the adapters
63 static int agp_3_5_isochronous_node_enable(struct agp_bridge_data
*bridge
,
64 struct agp_3_5_dev
*dev_list
, unsigned int ndevs
)
67 * Convenience structure to make the calculations clearer
68 * here. The field names come straight from the AGP 3.0 spec.
76 struct agp_3_5_dev
*dev
;
79 struct pci_dev
*td
= bridge
->dev
, *dev
;
80 struct list_head
*head
= &dev_list
->list
, *pos
;
81 struct agp_3_5_dev
*cur
;
82 struct isoch_data
*master
, target
;
83 unsigned int cdev
= 0;
84 u32 mnistat
, tnistat
, tstatus
, mcmd
;
87 u32 tot_bw
= 0, tot_n
= 0, tot_rq
= 0, y_max
, rq_isoch
, rq_async
;
88 u32 step
, rem
, rem_isoch
, rem_async
;
92 * We'll work with an array of isoch_data's (one for each
93 * device in dev_list) throughout this function.
95 if ((master
= kmalloc(ndevs
* sizeof(*master
), GFP_KERNEL
)) == NULL
) {
101 * Sort the device list by maxbw. We need to do this because the
102 * spec suggests that the devices with the smallest requirements
103 * have their resources allocated first, with all remaining resources
104 * falling to the device with the largest requirement.
106 * We don't exactly do this, we divide target resources by ndevs
107 * and split them amongst the AGP 3.0 devices. The remainder of such
108 * division operations are dropped on the last device, sort of like
109 * the spec mentions it should be done.
111 * We can't do this sort when we initially construct the dev_list
112 * because we don't know until this function whether isochronous
113 * transfers are enabled and consequently whether maxbw will mean
116 agp_3_5_dev_list_sort(dev_list
, ndevs
);
118 pci_read_config_dword(td
, bridge
->capndx
+AGPNISTAT
, &tnistat
);
119 pci_read_config_dword(td
, bridge
->capndx
+AGPSTAT
, &tstatus
);
121 /* Extract power-on defaults from the target */
122 target
.maxbw
= (tnistat
>> 16) & 0xff;
123 target
.n
= (tnistat
>> 8) & 0xff;
124 target
.y
= (tnistat
>> 6) & 0x3;
125 target
.l
= (tnistat
>> 3) & 0x7;
126 target
.rq
= (tstatus
>> 24) & 0xff;
131 * Extract power-on defaults for each device in dev_list. Along
132 * the way, calculate the total isochronous bandwidth required
133 * by these devices and the largest requested payload size.
135 list_for_each(pos
, head
) {
136 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
139 mcapndx
= cur
->capndx
;
141 pci_read_config_dword(dev
, cur
->capndx
+AGPNISTAT
, &mnistat
);
143 master
[cdev
].maxbw
= (mnistat
>> 16) & 0xff;
144 master
[cdev
].n
= (mnistat
>> 8) & 0xff;
145 master
[cdev
].y
= (mnistat
>> 6) & 0x3;
146 master
[cdev
].dev
= cur
;
148 tot_bw
+= master
[cdev
].maxbw
;
149 y_max
= max(y_max
, master
[cdev
].y
);
154 /* Check if this configuration has any chance of working */
155 if (tot_bw
> target
.maxbw
) {
156 dev_err(&td
->dev
, "isochronous bandwidth required "
157 "by AGP 3.0 devices exceeds that which is supported by "
158 "the AGP 3.0 bridge!\n");
166 * Write the calculated payload size into the target's NICMD
167 * register. Doing this directly effects the ISOCH_N value
168 * in the target's NISTAT register, so we need to do this now
169 * to get an accurate value for ISOCH_N later.
171 pci_read_config_word(td
, bridge
->capndx
+AGPNICMD
, &tnicmd
);
172 tnicmd
&= ~(0x3 << 6);
173 tnicmd
|= target
.y
<< 6;
174 pci_write_config_word(td
, bridge
->capndx
+AGPNICMD
, tnicmd
);
176 /* Reread the target's ISOCH_N */
177 pci_read_config_dword(td
, bridge
->capndx
+AGPNISTAT
, &tnistat
);
178 target
.n
= (tnistat
>> 8) & 0xff;
180 /* Calculate the minimum ISOCH_N needed by each master */
181 for (cdev
=0; cdev
<ndevs
; cdev
++) {
182 master
[cdev
].y
= target
.y
;
183 master
[cdev
].n
= master
[cdev
].maxbw
/ (master
[cdev
].y
+ 1);
185 tot_n
+= master
[cdev
].n
;
188 /* Exit if the minimal ISOCH_N allocation among the masters is more
189 * than the target can handle. */
190 if (tot_n
> target
.n
) {
191 dev_err(&td
->dev
, "number of isochronous "
192 "transactions per period required by AGP 3.0 devices "
193 "exceeds that which is supported by the AGP 3.0 "
199 /* Calculate left over ISOCH_N capability in the target. We'll give
200 * this to the hungriest device (as per the spec) */
201 rem
= target
.n
- tot_n
;
204 * Calculate the minimum isochronous RQ depth needed by each master.
205 * Along the way, distribute the extra ISOCH_N capability calculated
208 for (cdev
=0; cdev
<ndevs
; cdev
++) {
210 * This is a little subtle. If ISOCH_Y > 64B, then ISOCH_Y
211 * byte isochronous writes will be broken into 64B pieces.
212 * This means we need to budget more RQ depth to account for
213 * these kind of writes (each isochronous write is actually
214 * many writes on the AGP bus).
216 master
[cdev
].rq
= master
[cdev
].n
;
217 if (master
[cdev
].y
> 0x1)
218 master
[cdev
].rq
*= (1 << (master
[cdev
].y
- 1));
220 tot_rq
+= master
[cdev
].rq
;
222 master
[ndevs
-1].n
+= rem
;
224 /* Figure the number of isochronous and asynchronous RQ slots the
225 * target is providing. */
226 rq_isoch
= (target
.y
> 0x1) ? target
.n
* (1 << (target
.y
- 1)) : target
.n
;
227 rq_async
= target
.rq
- rq_isoch
;
229 /* Exit if the minimal RQ needs of the masters exceeds what the target
231 if (tot_rq
> rq_isoch
) {
232 dev_err(&td
->dev
, "number of request queue slots "
233 "required by the isochronous bandwidth requested by "
234 "AGP 3.0 devices exceeds the number provided by the "
235 "AGP 3.0 bridge!\n");
240 /* Calculate asynchronous RQ capability in the target (per master) as
241 * well as the total number of leftover isochronous RQ slots. */
242 step
= rq_async
/ ndevs
;
243 rem_async
= step
+ (rq_async
% ndevs
);
244 rem_isoch
= rq_isoch
- tot_rq
;
246 /* Distribute the extra RQ slots calculated above and write our
247 * isochronous settings out to the actual devices. */
248 for (cdev
=0; cdev
<ndevs
; cdev
++) {
249 cur
= master
[cdev
].dev
;
252 mcapndx
= cur
->capndx
;
254 master
[cdev
].rq
+= (cdev
== ndevs
- 1)
255 ? (rem_async
+ rem_isoch
) : step
;
257 pci_read_config_word(dev
, cur
->capndx
+AGPNICMD
, &mnicmd
);
258 pci_read_config_dword(dev
, cur
->capndx
+AGPCMD
, &mcmd
);
260 mnicmd
&= ~(0xff << 8);
261 mnicmd
&= ~(0x3 << 6);
262 mcmd
&= ~(0xff << 24);
264 mnicmd
|= master
[cdev
].n
<< 8;
265 mnicmd
|= master
[cdev
].y
<< 6;
266 mcmd
|= master
[cdev
].rq
<< 24;
268 pci_write_config_dword(dev
, cur
->capndx
+AGPCMD
, mcmd
);
269 pci_write_config_word(dev
, cur
->capndx
+AGPNICMD
, mnicmd
);
280 * This function basically allocates request queue slots among the
281 * AGP 3.0 systems in nonisochronous nodes. The algorithm is
282 * pretty stupid, divide the total number of RQ slots provided by the
283 * target by ndevs. Distribute this many slots to each AGP 3.0 device,
284 * giving any left over slots to the last device in dev_list.
286 static void agp_3_5_nonisochronous_node_enable(struct agp_bridge_data
*bridge
,
287 struct agp_3_5_dev
*dev_list
, unsigned int ndevs
)
289 struct agp_3_5_dev
*cur
;
290 struct list_head
*head
= &dev_list
->list
, *pos
;
293 unsigned int cdev
= 0;
295 pci_read_config_dword(bridge
->dev
, bridge
->capndx
+AGPSTAT
, &tstatus
);
297 trq
= (tstatus
>> 24) & 0xff;
300 rem
= mrq
+ (trq
% ndevs
);
302 for (pos
=head
->next
; cdev
<ndevs
; cdev
++, pos
=pos
->next
) {
303 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
305 pci_read_config_dword(cur
->dev
, cur
->capndx
+AGPCMD
, &mcmd
);
306 mcmd
&= ~(0xff << 24);
307 mcmd
|= ((cdev
== ndevs
- 1) ? rem
: mrq
) << 24;
308 pci_write_config_dword(cur
->dev
, cur
->capndx
+AGPCMD
, mcmd
);
313 * Fully configure and enable an AGP 3.0 host bridge and all the devices
316 int agp_3_5_enable(struct agp_bridge_data
*bridge
)
318 struct pci_dev
*td
= bridge
->dev
, *dev
= NULL
;
321 u32 tstatus
, mstatus
, ncapid
;
324 struct agp_3_5_dev
*dev_list
, *cur
;
325 struct list_head
*head
, *pos
;
326 unsigned int ndevs
= 0;
329 /* Extract some power-on defaults from the target */
330 pci_read_config_dword(td
, bridge
->capndx
+AGPSTAT
, &tstatus
);
331 isoch
= (tstatus
>> 17) & 0x1;
332 if (isoch
== 0) /* isoch xfers not available, bail out. */
335 arqsz
= (tstatus
>> 13) & 0x7;
338 * Allocate a head for our AGP 3.5 device list
339 * (multiple AGP v3 devices are allowed behind a single bridge).
341 if ((dev_list
= kmalloc(sizeof(*dev_list
), GFP_KERNEL
)) == NULL
) {
345 head
= &dev_list
->list
;
346 INIT_LIST_HEAD(head
);
348 /* Find all AGP devices, and add them to dev_list. */
349 for_each_pci_dev(dev
) {
350 mcapndx
= pci_find_capability(dev
, PCI_CAP_ID_AGP
);
354 switch ((dev
->class >>8) & 0xff00) {
355 case 0x0600: /* Bridge */
356 /* Skip bridges. We should call this function for each one. */
359 case 0x0001: /* Unclassified device */
360 /* Don't know what this is, but log it for investigation. */
362 dev_info(&td
->dev
, "wacky, found unclassified AGP device %s [%04x/%04x]\n",
364 dev
->vendor
, dev
->device
);
368 case 0x0300: /* Display controller */
369 case 0x0400: /* Multimedia controller */
370 if ((cur
= kmalloc(sizeof(*cur
), GFP_KERNEL
)) == NULL
) {
387 * Take an initial pass through the devices lying behind our host
388 * bridge. Make sure each one is actually an AGP 3.0 device, otherwise
389 * exit with an error message. Along the way store the AGP 3.0
390 * cap_ptr for each device
392 list_for_each(pos
, head
) {
393 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
396 pci_read_config_word(dev
, PCI_STATUS
, &mpstat
);
397 if ((mpstat
& PCI_STATUS_CAP_LIST
) == 0)
400 pci_read_config_byte(dev
, PCI_CAPABILITY_LIST
, &mcapndx
);
403 pci_read_config_dword(dev
, mcapndx
, &ncapid
);
404 if ((ncapid
& 0xff) != 2)
405 mcapndx
= (ncapid
>> 8) & 0xff;
407 while (((ncapid
& 0xff) != 2) && (mcapndx
!= 0));
411 dev_err(&td
->dev
, "woah! Non-AGP device %s on "
412 "secondary bus of AGP 3.5 bridge!\n",
418 mmajor
= (ncapid
>> AGP_MAJOR_VERSION_SHIFT
) & 0xf;
420 dev_err(&td
->dev
, "woah! AGP 2.0 device %s on "
421 "secondary bus of AGP 3.5 bridge operating "
422 "with AGP 3.0 electricals!\n", pci_name(dev
));
427 cur
->capndx
= mcapndx
;
429 pci_read_config_dword(dev
, cur
->capndx
+AGPSTAT
, &mstatus
);
431 if (((mstatus
>> 3) & 0x1) == 0) {
432 dev_err(&td
->dev
, "woah! AGP 3.x device %s not "
433 "operating in AGP 3.x mode on secondary bus "
434 "of AGP 3.5 bridge operating with AGP 3.0 "
435 "electricals!\n", pci_name(dev
));
442 * Call functions to divide target resources amongst the AGP 3.0
443 * masters. This process is dramatically different depending on
444 * whether isochronous transfers are supported.
447 ret
= agp_3_5_isochronous_node_enable(bridge
, dev_list
, ndevs
);
449 dev_info(&td
->dev
, "something bad happened setting "
450 "up isochronous xfers; falling back to "
451 "non-isochronous xfer mode\n");
456 agp_3_5_nonisochronous_node_enable(bridge
, dev_list
, ndevs
);
459 /* Be sure to free the dev_list */
460 for (pos
=head
->next
; pos
!=head
; ) {
461 cur
= list_entry(pos
, struct agp_3_5_dev
, list
);
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